diff options
Diffstat (limited to 'gcc/config/pdp11')
| -rwxr-xr-x | gcc/config/pdp11/2bsd.h | 87 | ||||
| -rwxr-xr-x | gcc/config/pdp11/pdp11.c | 1415 | ||||
| -rwxr-xr-x | gcc/config/pdp11/pdp11.h | 1393 | ||||
| -rwxr-xr-x | gcc/config/pdp11/pdp11.md | 1824 | ||||
| -rwxr-xr-x | gcc/config/pdp11/t-pdp11 | 8 | ||||
| -rwxr-xr-x | gcc/config/pdp11/xm-pdp11.h | 27 |
6 files changed, 0 insertions, 4754 deletions
diff --git a/gcc/config/pdp11/2bsd.h b/gcc/config/pdp11/2bsd.h deleted file mode 100755 index 401df17..0000000 --- a/gcc/config/pdp11/2bsd.h +++ /dev/null @@ -1,87 +0,0 @@ -/* Definitions of target machine for GNU compiler, for a PDP with 2BSD - Copyright (C) 1995, 1996 Free Software Foundation, Inc. - Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* This macro generates the assembly code for function entry. */ -#undef FUNCTION_PROLOGUE -#define FUNCTION_PROLOGUE(FILE, SIZE) \ -do { \ -fprintf(FILE, "\tjsr r5, csv\n"); \ -if ((SIZE) != 0) \ - { \ - fprintf(FILE, "\t/*abuse empty parameter slot for locals!*/\n"); \ - if ((SIZE) > 2) \ - fprintf(FILE, "\tsub $%d, sp\n", (SIZE)-2); \ - }; \ -} while (0) - -/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, - the stack pointer does not matter. The value is tested only in - functions that have frame pointers. - No definition is equivalent to always zero. */ - -#undef EXIT_IGNORE_STACK -#define EXIT_IGNORE_STACK 1 - -/* This macro generates the assembly code for function exit, - on machines that need it. If FUNCTION_EPILOGUE is not defined - then individual return instructions are generated for each - return statement. Args are same as for FUNCTION_PROLOGUE. -*/ - -#undef FUNCTION_EPILOGUE -#define FUNCTION_EPILOGUE(FILE, SIZE) \ -do { \ -fprintf(FILE, "\t/* SP ignored by cret? */\n"); \ -fprintf(FILE, "\tjmp cret\n"); \ -} while (0) - -#undef INITIAL_FRAME_POINTER_OFFSET -#define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) \ -{ \ - int offset, regno; \ - offset = get_frame_size(); \ - offset = (offset <= 2)? 0: (offset -2); \ - (DEPTH_VAR) = offset+10; \ -} - -/* Value should be nonzero if functions must have frame pointers. - Zero means the frame pointer need not be set up (and parms - may be accessed via the stack pointer) in functions that seem suitable. - This is computed in `reload', in reload1.c. - */ - -#undef FRAME_POINTER_REQUIRED -#define FRAME_POINTER_REQUIRED 1 - -/* Offset within stack frame to start allocating local variables at. - If FRAME_GROWS_DOWNWARD, this is the offset to the END of the - first local allocated. Otherwise, it is the offset to the BEGINNING - of the first local allocated. */ -#undef STARTING_FRAME_OFFSET -#define STARTING_FRAME_OFFSET -8 - - -#undef ASM_DECLARE_FUNCTION_NAME -#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ -do { \ -ASM_OUTPUT_LABEL (STREAM, NAME); \ -fprintf (STREAM, "~~%s:\n", NAME); \ -} while (0) diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c deleted file mode 100755 index 9bf69dd..0000000 --- a/gcc/config/pdp11/pdp11.c +++ /dev/null @@ -1,1415 +0,0 @@ -/* Subroutines for gcc2 for pdp11. - Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc. - Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#include "config.h" -#include <stdio.h> -#include "rtl.h" -#include "regs.h" -#include "hard-reg-set.h" -#include "real.h" -#include "insn-config.h" -#include "conditions.h" -#include "insn-flags.h" -#include "output.h" -#include "insn-attr.h" -#include "flags.h" - -/* -#define FPU_REG_P(X) ((X)>=8 && (X)<14) -#define CPU_REG_P(X) ((X)>=0 && (X)<8) -*/ - -/* this is the current value returned by the macro FIRST_PARM_OFFSET - defined in tm.h */ -int current_first_parm_offset; - -/* This is where the condition code register lives. */ -/* rtx cc0_reg_rtx; - no longer needed? */ - -static rtx find_addr_reg (); - -/* Nonzero if OP is a valid second operand for an arithmetic insn. */ - -int -arith_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (register_operand (op, mode) || GET_CODE (op) == CONST_INT); -} - -int -const_immediate_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (GET_CODE (op) == CONST_INT); -} - -int -immediate15_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (GET_CODE (op) == CONST_INT && ((INTVAL (op) & 0x8000) == 0x0000)); -} - -int -expand_shift_operand (op, mode) - rtx op; - enum machine_mode mode; -{ - return (GET_CODE (op) == CONST_INT - && abs (INTVAL(op)) > 1 - && abs (INTVAL(op)) <= 4); -} - -/* - stream is a stdio stream to output the code to. - size is an int: how many units of temporary storage to allocate. - Refer to the array `regs_ever_live' to determine which registers - to save; `regs_ever_live[I]' is nonzero if register number I - is ever used in the function. This macro is responsible for - knowing which registers should not be saved even if used. -*/ - -void -output_function_prologue(stream, size) - FILE *stream; - int size; -{ - int fsize = ((size) + 1) & ~1; - int regno, nregs, i; - int offset = 0; - - int via_ac = -1; - - fprintf (stream, "\n\t; /* function prologue %s*/\n", current_function_name); - - /* if we are outputting code for main, - the switch FPU to right mode if TARGET_FPU */ - if ( (strcmp ("main", current_function_name) == 0) - && TARGET_FPU) - { - fprintf(stream, "\t;/* switch cpu to double float, single integer */\n"); - fprintf(stream, "\tsetd\n"); - fprintf(stream, "\tseti\n\n"); - } - - if (frame_pointer_needed) - { - fprintf(stream, "\tmov fp, -(sp)\n"); - fprintf(stream, "\tmov sp, fp\n"); - } - else - { - /* DON'T SAVE FP */ - } - - /* make frame */ - if (fsize) - fprintf (stream, "\tsub $%d, sp\n", fsize); - - /* save CPU registers */ - for (regno = 0; regno < 8; regno++) - if (regs_ever_live[regno] && ! call_used_regs[regno]) - if (! ((regno == FRAME_POINTER_REGNUM) - && frame_pointer_needed)) - fprintf (stream, "\tmov %s, -(sp)\n", reg_names[regno]); - /* fpu regs saving */ - - /* via_ac specifies the ac to use for saving ac4, ac5 */ - via_ac = -1; - - for (regno = 8; regno < FIRST_PSEUDO_REGISTER ; regno++) - { - /* ac0 - ac3 */ - if (LOAD_FPU_REG_P(regno) - && regs_ever_live[regno] - && ! call_used_regs[regno]) - { - fprintf (stream, "\tfstd %s, -(sp)\n", reg_names[regno]); - via_ac = regno; - } - - /* maybe make ac4, ac5 call used regs?? */ - /* ac4 - ac5 */ - if (NO_LOAD_FPU_REG_P(regno) - && regs_ever_live[regno] - && ! call_used_regs[regno]) - { - if (via_ac == -1) - abort(); - - fprintf (stream, "\tfldd %s, %s\n", reg_names[regno], reg_names[via_ac]); - fprintf (stream, "\tfstd %s, -(sp)\n", reg_names[via_ac]); - } - } - - fprintf (stream, "\t;/* end of prologue */\n\n"); -} - -/* - The function epilogue should not depend on the current stack pointer! - It should use the frame pointer only. This is mandatory because - of alloca; we also take advantage of it to omit stack adjustments - before returning. */ - -/* maybe we can make leaf functions faster by switching to the - second register file - this way we don't have to save regs! - leaf functions are ~ 50% of all functions (dynamically!) - - set/clear bit 11 (dec. 2048) of status word for switching register files - - but how can we do this? the pdp11/45 manual says bit may only - be set (p.24), but not cleared! - - switching to kernel is probably more expensive, so we'll leave it - like this and not use the second set of registers... - - maybe as option if you want to generate code for kernel mode? */ - - -void -output_function_epilogue(stream, size) - FILE *stream; - int size; -{ - extern int may_call_alloca; - - int fsize = ((size) + 1) & ~1; - int nregs, regno, i, j, k, adjust_fp; - - int via_ac; - - fprintf (stream, "\n\t; /*function epilogue */\n"); - - if (frame_pointer_needed) - { - /* hope this is safe - m68k does it also .... */ - regs_ever_live[FRAME_POINTER_REGNUM] = 0; - - for (i =7, j = 0 ; i >= 0 ; i--) - if (regs_ever_live[i] && ! call_used_regs[i]) - j++; - - /* remember # of pushed bytes for CPU regs */ - k = 2*j; - - for (i =7 ; i >= 0 ; i--) - if (regs_ever_live[i] && ! call_used_regs[i]) - fprintf(stream, "\tmov %d(fp), %s\n",-fsize-2*j--, reg_names[i]); - - /* get ACs */ - via_ac = FIRST_PSEUDO_REGISTER -1; - - for (i = FIRST_PSEUDO_REGISTER; i > 7; i--) - if (regs_ever_live[i] && ! call_used_regs[i]) - { - via_ac = i; - k += 8; - } - - for (i = FIRST_PSEUDO_REGISTER; i > 7; i--) - { - if (LOAD_FPU_REG_P(i) - && regs_ever_live[i] - && ! call_used_regs[i]) - { - fprintf(stream, "\tfldd %d(fp), %s\n", -fsize-k, reg_names[i]); - k -= 8; - } - - if (NO_LOAD_FPU_REG_P(i) - && regs_ever_live[i] - && ! call_used_regs[i]) - { - if (! LOAD_FPU_REG_P(via_ac)) - abort(); - - fprintf(stream, "\tfldd %d(fp), %s\n", -fsize-k, reg_names[via_ac]); - fprintf(stream, "\tfstd %s, %s\n", reg_names[via_ac], reg_names[i]); - k -= 8; - } - } - - fprintf(stream, "\tmov fp, sp\n"); - fprintf (stream, "\tmov (sp)+, fp\n"); - } - else - { - via_ac = FIRST_PSEUDO_REGISTER -1; - - /* get ACs */ - for (i = FIRST_PSEUDO_REGISTER; i > 7; i--) - if (regs_ever_live[i] && call_used_regs[i]) - via_ac = i; - - for (i = FIRST_PSEUDO_REGISTER; i > 7; i--) - { - if (LOAD_FPU_REG_P(i) - && regs_ever_live[i] - && ! call_used_regs[i]) - fprintf(stream, "\tfldd (sp)+, %s\n", reg_names[i]); - - if (NO_LOAD_FPU_REG_P(i) - && regs_ever_live[i] - && ! call_used_regs[i]) - { - if (! LOAD_FPU_REG_P(via_ac)) - abort(); - - fprintf(stream, "\tfldd (sp)+, %s\n", reg_names[via_ac]); - fprintf(stream, "\tfstd %s, %s\n", reg_names[via_ac], reg_names[i]); - } - } - - for (i=7; i >= 0; i--) - if (regs_ever_live[i] && !call_used_regs[i]) - fprintf(stream, "\tmov (sp)+, %s\n", reg_names[i]); - - if (fsize) - fprintf((stream), "\tadd $%d, sp\n", fsize); - } - - fprintf (stream, "\trts pc\n"); - fprintf (stream, "\t;/* end of epilogue*/\n\n\n"); -} - -/* Return the best assembler insn template - for moving operands[1] into operands[0] as a fullword. */ -static char * -singlemove_string (operands) - rtx *operands; -{ - if (operands[1] != const0_rtx) - return "mov %1,%0"; - - return "clr %0"; -} - - -/* Output assembler code to perform a doubleword move insn - with operands OPERANDS. */ - -char * -output_move_double (operands) - rtx *operands; -{ - enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; - rtx latehalf[2]; - rtx addreg0 = 0, addreg1 = 0; - - /* First classify both operands. */ - - if (REG_P (operands[0])) - optype0 = REGOP; - else if (offsettable_memref_p (operands[0])) - optype0 = OFFSOP; - else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) - optype0 = POPOP; - else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) - optype0 = PUSHOP; - else if (GET_CODE (operands[0]) == MEM) - optype0 = MEMOP; - else - optype0 = RNDOP; - - if (REG_P (operands[1])) - optype1 = REGOP; - else if (CONSTANT_P (operands[1])) -#if 0 - || GET_CODE (operands[1]) == CONST_DOUBLE) -#endif - optype1 = CNSTOP; - else if (offsettable_memref_p (operands[1])) - optype1 = OFFSOP; - else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) - optype1 = POPOP; - else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) - optype1 = PUSHOP; - else if (GET_CODE (operands[1]) == MEM) - optype1 = MEMOP; - else - optype1 = RNDOP; - - /* Check for the cases that the operand constraints are not - supposed to allow to happen. Abort if we get one, - because generating code for these cases is painful. */ - - if (optype0 == RNDOP || optype1 == RNDOP) - abort (); - - /* If one operand is decrementing and one is incrementing - decrement the former register explicitly - and change that operand into ordinary indexing. */ - - if (optype0 == PUSHOP && optype1 == POPOP) - { - operands[0] = XEXP (XEXP (operands[0], 0), 0); - output_asm_insn ("sub $4,%0", operands); - operands[0] = gen_rtx (MEM, SImode, operands[0]); - optype0 = OFFSOP; - } - if (optype0 == POPOP && optype1 == PUSHOP) - { - operands[1] = XEXP (XEXP (operands[1], 0), 0); - output_asm_insn ("sub $4,%1", operands); - operands[1] = gen_rtx (MEM, SImode, operands[1]); - optype1 = OFFSOP; - } - - /* If an operand is an unoffsettable memory ref, find a register - we can increment temporarily to make it refer to the second word. */ - - if (optype0 == MEMOP) - addreg0 = find_addr_reg (XEXP (operands[0], 0)); - - if (optype1 == MEMOP) - addreg1 = find_addr_reg (XEXP (operands[1], 0)); - - /* Ok, we can do one word at a time. - Normally we do the low-numbered word first, - but if either operand is autodecrementing then we - do the high-numbered word first. - - In either case, set up in LATEHALF the operands to use - for the high-numbered word and in some cases alter the - operands in OPERANDS to be suitable for the low-numbered word. */ - - if (optype0 == REGOP) - latehalf[0] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1); - else if (optype0 == OFFSOP) - latehalf[0] = adj_offsettable_operand (operands[0], 2); - else - latehalf[0] = operands[0]; - - if (optype1 == REGOP) - latehalf[1] = gen_rtx (REG, HImode, REGNO (operands[1]) + 1); - else if (optype1 == OFFSOP) - latehalf[1] = adj_offsettable_operand (operands[1], 2); - else if (optype1 == CNSTOP) - { - if (CONSTANT_P (operands[1])) - { - /* now the mess begins, high word is in lower word??? - - that's what ashc makes me think, but I don't remember :-( */ - latehalf[1] = GEN_INT (INTVAL(operands[1])>>16); - operands[1] = GEN_INT (INTVAL(operands[1])&0xff); - } - else if (GET_CODE (operands[1]) == CONST_DOUBLE) - { - /* immediate 32 bit values not allowed */ - abort(); - } - } - else - latehalf[1] = operands[1]; - - /* If insn is effectively movd N(sp),-(sp) then we will do the - high word first. We should use the adjusted operand 1 (which is N+4(sp)) - for the low word as well, to compensate for the first decrement of sp. */ - if (optype0 == PUSHOP - && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM - && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) - operands[1] = latehalf[1]; - - /* If one or both operands autodecrementing, - do the two words, high-numbered first. */ - - /* Likewise, the first move would clobber the source of the second one, - do them in the other order. This happens only for registers; - such overlap can't happen in memory unless the user explicitly - sets it up, and that is an undefined circumstance. */ - - if (optype0 == PUSHOP || optype1 == PUSHOP - || (optype0 == REGOP && optype1 == REGOP - && REGNO (operands[0]) == REGNO (latehalf[1]))) - { - /* Make any unoffsettable addresses point at high-numbered word. */ - if (addreg0) - output_asm_insn ("add $2,%0", &addreg0); - if (addreg1) - output_asm_insn ("add $2,%0", &addreg1); - - /* Do that word. */ - output_asm_insn (singlemove_string (latehalf), latehalf); - - /* Undo the adds we just did. */ - if (addreg0) - output_asm_insn ("sub $2,%0", &addreg0); - if (addreg1) - output_asm_insn ("sub $2,%0", &addreg1); - - /* Do low-numbered word. */ - return singlemove_string (operands); - } - - /* Normal case: do the two words, low-numbered first. */ - - output_asm_insn (singlemove_string (operands), operands); - - /* Make any unoffsettable addresses point at high-numbered word. */ - if (addreg0) - output_asm_insn ("add $2,%0", &addreg0); - if (addreg1) - output_asm_insn ("add $2,%0", &addreg1); - - /* Do that word. */ - output_asm_insn (singlemove_string (latehalf), latehalf); - - /* Undo the adds we just did. */ - if (addreg0) - output_asm_insn ("sub $2,%0", &addreg0); - if (addreg1) - output_asm_insn ("sub $2,%0", &addreg1); - - return ""; -} -/* Output assembler code to perform a quadword move insn - with operands OPERANDS. */ - -char * -output_move_quad (operands) - rtx *operands; -{ - enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; - rtx latehalf[2]; - rtx addreg0 = 0, addreg1 = 0; - - output_asm_insn(";; movdi/df: %1 -> %0", operands); - - if (REG_P (operands[0])) - optype0 = REGOP; - else if (offsettable_memref_p (operands[0])) - optype0 = OFFSOP; - else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) - optype0 = POPOP; - else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) - optype0 = PUSHOP; - else if (GET_CODE (operands[0]) == MEM) - optype0 = MEMOP; - else - optype0 = RNDOP; - - if (REG_P (operands[1])) - optype1 = REGOP; - else if (CONSTANT_P (operands[1]) - || GET_CODE (operands[1]) == CONST_DOUBLE) - optype1 = CNSTOP; - else if (offsettable_memref_p (operands[1])) - optype1 = OFFSOP; - else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) - optype1 = POPOP; - else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) - optype1 = PUSHOP; - else if (GET_CODE (operands[1]) == MEM) - optype1 = MEMOP; - else - optype1 = RNDOP; - - /* Check for the cases that the operand constraints are not - supposed to allow to happen. Abort if we get one, - because generating code for these cases is painful. */ - - if (optype0 == RNDOP || optype1 == RNDOP) - abort (); - - /* check if we move a CPU reg to an FPU reg, or vice versa! */ - if (optype0 == REGOP && optype1 == REGOP) - /* bogus - 64 bit cannot reside in CPU! */ - if (CPU_REG_P(REGNO(operands[0])) - || CPU_REG_P (REGNO(operands[1]))) - abort(); - - if (optype0 == REGOP || optype1 == REGOP) - { - /* check for use of clrd???? - if you ever allow ac4 and ac5 (now we require secondary load) - you must check whether - you want to load into them or store from them - - then dump ac0 into $help$ movce ac4/5 to ac0, do the - store from ac0, and restore ac0 - if you can find - an unused ac[0-3], use that and you save a store and a load!*/ - - if (FPU_REG_P(REGNO(operands[0]))) - { - if (GET_CODE(operands[1]) == CONST_DOUBLE) - { - union { double d; int i[2]; } u; - u.i[0] = CONST_DOUBLE_LOW (operands[1]); - u.i[1] = CONST_DOUBLE_HIGH (operands[1]); - - if (u.d == 0.0) - return "clrd %0"; - } - - return "ldd %1, %0"; - } - - if (FPU_REG_P(REGNO(operands[1]))) - return "std %1, %0"; - } - - /* If one operand is decrementing and one is incrementing - decrement the former register explicitly - and change that operand into ordinary indexing. */ - - if (optype0 == PUSHOP && optype1 == POPOP) - { - operands[0] = XEXP (XEXP (operands[0], 0), 0); - output_asm_insn ("sub $8,%0", operands); - operands[0] = gen_rtx (MEM, DImode, operands[0]); - optype0 = OFFSOP; - } - if (optype0 == POPOP && optype1 == PUSHOP) - { - operands[1] = XEXP (XEXP (operands[1], 0), 0); - output_asm_insn ("sub $8,%1", operands); - operands[1] = gen_rtx (MEM, SImode, operands[1]); - optype1 = OFFSOP; - } - - /* If an operand is an unoffsettable memory ref, find a register - we can increment temporarily to make it refer to the second word. */ - - if (optype0 == MEMOP) - addreg0 = find_addr_reg (XEXP (operands[0], 0)); - - if (optype1 == MEMOP) - addreg1 = find_addr_reg (XEXP (operands[1], 0)); - - /* Ok, we can do one word at a time. - Normally we do the low-numbered word first, - but if either operand is autodecrementing then we - do the high-numbered word first. - - In either case, set up in LATEHALF the operands to use - for the high-numbered word and in some cases alter the - operands in OPERANDS to be suitable for the low-numbered word. */ - - if (optype0 == REGOP) - latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); - else if (optype0 == OFFSOP) - latehalf[0] = adj_offsettable_operand (operands[0], 4); - else - latehalf[0] = operands[0]; - - if (optype1 == REGOP) - latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); - else if (optype1 == OFFSOP) - latehalf[1] = adj_offsettable_operand (operands[1], 4); - else if (optype1 == CNSTOP) - { - if (GET_CODE (operands[1]) == CONST_DOUBLE) - { - /* floats only. not yet supported! - - -- compute it into PDP float format, - internally, - just use IEEE and ignore possible problems ;-) - - we might get away with it !!!! */ - - abort(); - -#ifndef HOST_WORDS_BIG_ENDIAN - latehalf[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); - operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); -#else /* HOST_WORDS_BIG_ENDIAN */ - latehalf[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); - operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); -#endif /* HOST_WORDS_BIG_ENDIAN */ - } - else if (GET_CODE(operands[1]) == CONST_INT) - { - latehalf[1] = GEN_INT (0); - } - else - abort(); - - } - else - latehalf[1] = operands[1]; - - /* If insn is effectively movd N(sp),-(sp) then we will do the - high word first. We should use the adjusted operand 1 (which is N+4(sp)) - for the low word as well, to compensate for the first decrement of sp. */ - if (optype0 == PUSHOP - && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM - && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) - operands[1] = latehalf[1]; - - /* If one or both operands autodecrementing, - do the two words, high-numbered first. */ - - /* Likewise, the first move would clobber the source of the second one, - do them in the other order. This happens only for registers; - such overlap can't happen in memory unless the user explicitly - sets it up, and that is an undefined circumstance. */ - - if (optype0 == PUSHOP || optype1 == PUSHOP - || (optype0 == REGOP && optype1 == REGOP - && REGNO (operands[0]) == REGNO (latehalf[1]))) - { - /* Make any unoffsettable addresses point at high-numbered word. */ - if (addreg0) - output_asm_insn ("add $4,%0", &addreg0); - if (addreg1) - output_asm_insn ("add $4,%0", &addreg1); - - /* Do that word. */ - output_asm_insn(output_move_double(latehalf), latehalf); - - /* Undo the adds we just did. */ - if (addreg0) - output_asm_insn ("sub $4,%0", &addreg0); - if (addreg1) - output_asm_insn ("sub $4,%0", &addreg1); - - /* Do low-numbered word. */ - return output_move_double (operands); - } - - /* Normal case: do the two words, low-numbered first. */ - - output_asm_insn (output_move_double (operands), operands); - - /* Make any unoffsettable addresses point at high-numbered word. */ - if (addreg0) - output_asm_insn ("add $4,%0", &addreg0); - if (addreg1) - output_asm_insn ("add $4,%0", &addreg1); - - /* Do that word. */ - output_asm_insn (output_move_double (latehalf), latehalf); - - /* Undo the adds we just did. */ - if (addreg0) - output_asm_insn ("sub $4,%0", &addreg0); - if (addreg1) - output_asm_insn ("sub $4,%0", &addreg1); - - return ""; -} - - -/* Return a REG that occurs in ADDR with coefficient 1. - ADDR can be effectively incremented by incrementing REG. */ - -static rtx -find_addr_reg (addr) - rtx addr; -{ - while (GET_CODE (addr) == PLUS) - { - if (GET_CODE (XEXP (addr, 0)) == REG) - addr = XEXP (addr, 0); - if (GET_CODE (XEXP (addr, 1)) == REG) - addr = XEXP (addr, 1); - if (CONSTANT_P (XEXP (addr, 0))) - addr = XEXP (addr, 1); - if (CONSTANT_P (XEXP (addr, 1))) - addr = XEXP (addr, 0); - } - if (GET_CODE (addr) == REG) - return addr; - return 0; -} - -/* Output an ascii string. */ -output_ascii (file, p, size) - FILE *file; - char *p; - int size; -{ - int i; - - fprintf (file, "\t.byte \""); - - for (i = 0; i < size; i++) - { - register int c = p[i]; - if (c == '\"' || c == '\\') - putc ('\\', file); - if (c >= ' ' && c < 0177) - putc (c, file); - else - { - fprintf (file, "\\%03o", c); - /* After an octal-escape, if a digit follows, - terminate one string constant and start another. - The Vax assembler fails to stop reading the escape - after three digits, so this is the only way we - can get it to parse the data properly. */ - if (i < size - 1 && p[i + 1] >= '0' && p[i + 1] <= '9') - fprintf (file, "\"\n\tstring \""); - } - } - fprintf (file, "\"\n"); -} - - -/* --- stole from out-vax, needs changes */ - -print_operand_address (file, addr) - FILE *file; - register rtx addr; -{ - register rtx reg1, reg2, breg, ireg; - rtx offset; - - retry: - - switch (GET_CODE (addr)) - { - case MEM: - fprintf (file, "@"); - addr = XEXP (addr, 0); - goto retry; - - case REG: - fprintf (file, "(%s)", reg_names[REGNO (addr)]); - break; - - case PRE_DEC: - fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); - break; - - case POST_INC: - fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); - break; - - case PLUS: - reg1 = 0; reg2 = 0; - ireg = 0; breg = 0; - offset = 0; - if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) - || GET_CODE (XEXP (addr, 0)) == MEM) - { - offset = XEXP (addr, 0); - addr = XEXP (addr, 1); - } - else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) - || GET_CODE (XEXP (addr, 1)) == MEM) - { - offset = XEXP (addr, 1); - addr = XEXP (addr, 0); - } - if (GET_CODE (addr) != PLUS) - ; - else if (GET_CODE (XEXP (addr, 0)) == MULT) - { - reg1 = XEXP (addr, 0); - addr = XEXP (addr, 1); - } - else if (GET_CODE (XEXP (addr, 1)) == MULT) - { - reg1 = XEXP (addr, 1); - addr = XEXP (addr, 0); - } - else if (GET_CODE (XEXP (addr, 0)) == REG) - { - reg1 = XEXP (addr, 0); - addr = XEXP (addr, 1); - } - else if (GET_CODE (XEXP (addr, 1)) == REG) - { - reg1 = XEXP (addr, 1); - addr = XEXP (addr, 0); - } - if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) - { - if (reg1 == 0) - reg1 = addr; - else - reg2 = addr; - addr = 0; - } - if (offset != 0) - { - if (addr != 0) abort (); - addr = offset; - } - if (reg1 != 0 && GET_CODE (reg1) == MULT) - { - breg = reg2; - ireg = reg1; - } - else if (reg2 != 0 && GET_CODE (reg2) == MULT) - { - breg = reg1; - ireg = reg2; - } - else if (reg2 != 0 || GET_CODE (addr) == MEM) - { - breg = reg2; - ireg = reg1; - } - else - { - breg = reg1; - ireg = reg2; - } - if (addr != 0) - output_address (addr); - if (breg != 0) - { - if (GET_CODE (breg) != REG) - abort (); - fprintf (file, "(%s)", reg_names[REGNO (breg)]); - } - if (ireg != 0) - { - if (GET_CODE (ireg) == MULT) - ireg = XEXP (ireg, 0); - if (GET_CODE (ireg) != REG) - abort (); - abort(); - fprintf (file, "[%s]", reg_names[REGNO (ireg)]); - } - break; - - default: - output_addr_const (file, addr); - } -} - -/* register move costs, indexed by regs */ - -static int move_costs[N_REG_CLASSES][N_REG_CLASSES] = -{ - /* NO MUL GEN LFPU NLFPU FPU ALL */ - -/* NO */ { 0, 0, 0, 0, 0, 0, 0}, -/* MUL */ { 0, 2, 2, 10, 22, 22, 22}, -/* GEN */ { 0, 2, 2, 10, 22, 22, 22}, -/* LFPU */ { 0, 10, 10, 2, 2, 2, 10}, -/* NLFPU */ { 0, 22, 22, 2, 2, 2, 22}, -/* FPU */ { 0, 22, 22, 2, 2, 2, 22}, -/* ALL */ { 0, 22, 22, 10, 22, 22, 22} -} ; - - -/* -- note that some moves are tremendously expensive, - because they require lots of tricks! do we have to - charge the costs incurred by secondary reload class - -- as we do here with 22 -- or not ? */ - -int -register_move_cost(c1, c2) - enum reg_class c1, c2; -{ - return move_costs[(int)c1][(int)c2]; -} - -char * -output_jump(pos, neg, length) - int length; - char *pos, *neg; -{ - static int x = 0; - - static char buf[1000]; - -#if 0 -/* currently we don't need this, because the tstdf and cmpdf - copy the condition code immediately, and other float operations are not - yet recognized as changing the FCC - if so, then the length-cost of all - jump insns increases by one, because we have to potentially copy the - FCC! */ - if (cc_status.flags & CC_IN_FPU) - output_asm_insn("cfcc", NULL); -#endif - - switch (length) - { - case 1: - - strcpy(buf, pos); - strcat(buf, " %l0"); - - return buf; - - case 3: - - sprintf(buf, "%s JMP_%d\n\tjmp %%l0\nJMP_%d:", neg, x, x); - - x++; - - return buf; - - default: - - abort(); - } - -} - -void -notice_update_cc_on_set(exp, insn) - rtx exp; - rtx insn; -{ - if (GET_CODE (SET_DEST (exp)) == CC0) - { - cc_status.flags = 0; - cc_status.value1 = SET_DEST (exp); - cc_status.value2 = SET_SRC (exp); - -/* - if (GET_MODE(SET_SRC(exp)) == DFmode) - cc_status.flags |= CC_IN_FPU; -*/ - } - else if ((GET_CODE (SET_DEST (exp)) == REG - || GET_CODE (SET_DEST (exp)) == MEM) - && GET_CODE (SET_SRC (exp)) != PC - && (GET_MODE (SET_DEST(exp)) == HImode - || GET_MODE (SET_DEST(exp)) == QImode) - && (GET_CODE (SET_SRC(exp)) == PLUS - || GET_CODE (SET_SRC(exp)) == MINUS - || GET_CODE (SET_SRC(exp)) == AND - || GET_CODE (SET_SRC(exp)) == IOR - || GET_CODE (SET_SRC(exp)) == XOR - || GET_CODE (SET_SRC(exp)) == NOT - || GET_CODE (SET_SRC(exp)) == NEG - || GET_CODE (SET_SRC(exp)) == REG - || GET_CODE (SET_SRC(exp)) == MEM)) - { - cc_status.flags = 0; - cc_status.value1 = SET_SRC (exp); - cc_status.value2 = SET_DEST (exp); - - if (cc_status.value1 && GET_CODE (cc_status.value1) == REG - && cc_status.value2 - && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) - cc_status.value2 = 0; - if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM - && cc_status.value2 - && GET_CODE (cc_status.value2) == MEM) - cc_status.value2 = 0; - } - else if (GET_CODE (SET_SRC (exp)) == CALL) - { - CC_STATUS_INIT; - } - else if (GET_CODE (SET_DEST (exp)) == REG) - /* what's this ? */ - { - if ((cc_status.value1 - && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1))) - cc_status.value1 = 0; - if ((cc_status.value2 - && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2))) - cc_status.value2 = 0; - } - else if (SET_DEST(exp) == pc_rtx) - { - /* jump */ - } - else /* if (GET_CODE (SET_DEST (exp)) == MEM) */ - { - /* the last else is a bit paranoiac, but since nearly all instructions - play with condition codes, it's reasonable! */ - - CC_STATUS_INIT; /* paranoia*/ - } -} - - -int simple_memory_operand(op, mode) - rtx op; - enum machine_mode mode; -{ - rtx addr, plus0, plus1; - int offset = 0; - - /* Eliminate non-memory operations */ - if (GET_CODE (op) != MEM) - return FALSE; - -#if 0 - /* dword operations really put out 2 instructions, so eliminate them. */ - if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4)) - return FALSE; -#endif - - /* Decode the address now. */ - - indirection: - - addr = XEXP (op, 0); - - switch (GET_CODE (addr)) - { - case REG: - /* (R0) - no extra cost */ - return 1; - - case PRE_DEC: - case POST_INC: - /* -(R0), (R0)+ - cheap! */ - return 0; - - case MEM: - /* cheap - is encoded in addressing mode info! - - -- except for @(R0), which has to be @0(R0) !!! */ - - if (GET_CODE (XEXP (addr, 0)) == REG) - return 0; - - op=addr; - goto indirection; - - case CONST_INT: - case LABEL_REF: - case CONST: - case SYMBOL_REF: - /* @#address - extra cost */ - return 0; - - case PLUS: - /* X(R0) - extra cost */ - return 0; - } - - return FALSE; -} - - -/* - * output a block move: - * - * operands[0] ... to - * operands[1] ... from - * operands[2] ... length - * operands[3] ... alignment - * operands[4] ... scratch register - */ - - -char * -output_block_move(operands) - rtx *operands; -{ - static int count = 0; - char buf[200]; - - if (GET_CODE(operands[2]) == CONST_INT - && ! optimize_size) - { - if (INTVAL(operands[2]) < 16 - && INTVAL(operands[3]) == 1) - { - register int i; - - for (i = 1; i <= INTVAL(operands[2]); i++) - output_asm_insn("movb (%1)+, (%0)+", operands); - - return ""; - } - else if (INTVAL(operands[2]) < 32) - { - register int i; - - for (i = 1; i <= INTVAL(operands[2])/2; i++) - output_asm_insn("mov (%1)+, (%0)+", operands); - - /* may I assume that moved quantity is - multiple of alignment ??? - - I HOPE SO ! - */ - - return ""; - } - - - /* can do other clever things, maybe... */ - } - - if (CONSTANT_P(operands[2]) ) - { - /* just move count to scratch */ - output_asm_insn("mov %2, %4", operands); - } - else - { - /* just clobber the register */ - operands[4] = operands[2]; - } - - - /* switch over alignment */ - switch (INTVAL(operands[3])) - { - case 1: - - /* - x: - movb (%1)+, (%0)+ - - if (TARGET_45) - sob %4,x - else - dec %4 - bgt x - - */ - - sprintf(buf, "\nmovestrhi%d:", count); - output_asm_insn(buf, NULL); - - output_asm_insn("movb (%1)+, (%0)+", operands); - - if (TARGET_45) - { - sprintf(buf, "sob %%4, movestrhi%d", count); - output_asm_insn(buf, operands); - } - else - { - output_asm_insn("dec %4", operands); - - sprintf(buf, "bgt movestrhi%d", count); - output_asm_insn(buf, NULL); - } - - count ++; - break; - - case 2: - - /* - asr %4 - - x: - - mov (%1)+, (%0)+ - - if (TARGET_45) - sob %4, x - else - dec %4 - bgt x - */ - - generate_compact_code: - - output_asm_insn("asr %4", operands); - - sprintf(buf, "\nmovestrhi%d:", count); - output_asm_insn(buf, NULL); - - output_asm_insn("mov (%1)+, (%0)+", operands); - - if (TARGET_45) - { - sprintf(buf, "sob %%4, movestrhi%d", count); - output_asm_insn(buf, operands); - } - else - { - output_asm_insn("dec %4", operands); - - sprintf(buf, "bgt movestrhi%d", count); - output_asm_insn(buf, NULL); - } - - count ++; - break; - - case 4: - - /* - - asr %4 - asr %4 - - x: - - mov (%1)+, (%0)+ - mov (%1)+, (%0)+ - - if (TARGET_45) - sob %4, x - else - dec %4 - bgt x - */ - - if (optimize_size) - goto generate_compact_code; - - output_asm_insn("asr %4", operands); - output_asm_insn("asr %4", operands); - - sprintf(buf, "\nmovestrhi%d:", count); - output_asm_insn(buf, NULL); - - output_asm_insn("mov (%1)+, (%0)+", operands); - output_asm_insn("mov (%1)+, (%0)+", operands); - - if (TARGET_45) - { - sprintf(buf, "sob %%4, movestrhi%d", count); - output_asm_insn(buf, operands); - } - else - { - output_asm_insn("dec %4", operands); - - sprintf(buf, "bgt movestrhi%d", count); - output_asm_insn(buf, NULL); - } - - count ++; - break; - - default: - - /* - - asr %4 - asr %4 - asr %4 - - x: - - mov (%1)+, (%0)+ - mov (%1)+, (%0)+ - mov (%1)+, (%0)+ - mov (%1)+, (%0)+ - - if (TARGET_45) - sob %4, x - else - dec %4 - bgt x - */ - - - if (optimize_size) - goto generate_compact_code; - - output_asm_insn("asr %4", operands); - output_asm_insn("asr %4", operands); - output_asm_insn("asr %4", operands); - - sprintf(buf, "\nmovestrhi%d:", count); - output_asm_insn(buf, NULL); - - output_asm_insn("mov (%1)+, (%0)+", operands); - output_asm_insn("mov (%1)+, (%0)+", operands); - output_asm_insn("mov (%1)+, (%0)+", operands); - output_asm_insn("mov (%1)+, (%0)+", operands); - - if (TARGET_45) - { - sprintf(buf, "sob %%4, movestrhi%d", count); - output_asm_insn(buf, operands); - } - else - { - output_asm_insn("dec %4", operands); - - sprintf(buf, "bgt movestrhi%d", count); - output_asm_insn(buf, NULL); - } - - count ++; - break; - - ; - - } - - return ""; -} - -/* for future use */ -int -comparison_operator_index(op) - rtx op; -{ - switch (GET_CODE(op)) - { - case NE: - return 0; - - case EQ: - return 1; - - case GE: - return 2; - - case GT: - return 3; - - case LE: - return 4; - - case LT: - return 5; - - case GEU: - return 6; - - case GTU: - return 7; - - case LEU: - return 8; - - case LTU: - return 9; - - default: - return -1; - } -} - -/* tests whether the rtx is a comparison operator */ -int -comp_operator (op, mode) - rtx op; - enum machine_mode mode; -{ - return comparison_operator_index(op) >= 0; -} - - -int -legitimate_address_p (mode, address) - enum machine_mode mode; - rtx address; -{ -/* #define REG_OK_STRICT */ - GO_IF_LEGITIMATE_ADDRESS(mode, address, win); - - return 0; - - win: - return 1; - -/* #undef REG_OK_STRICT */ -} diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h deleted file mode 100755 index 7912bea..0000000 --- a/gcc/config/pdp11/pdp11.h +++ /dev/null @@ -1,1393 +0,0 @@ -/* Definitions of target machine for GNU compiler, for the pdp-11 - Copyright (C) 1994, 1995, 1996, 1998 Free Software Foundation, Inc. - Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - - -/* declarations */ -char *output_jump(); -char *output_move_double(); -char *output_move_quad(); -char *output_block_move(); - -/* check whether load_fpu_reg or not */ -#define LOAD_FPU_REG_P(x) ((x)>=8 && (x)<=11) -#define NO_LOAD_FPU_REG_P(x) ((x)==12 || (x)==13) -#define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x)) -#define CPU_REG_P(x) ((x)<8) - -/* Names to predefine in the preprocessor for this target machine. */ - -#define CPP_PREDEFINES "-Dpdp11" - -/* Print subsidiary information on the compiler version in use. */ -#define TARGET_VERSION fprintf (stderr, " (pdp11)"); - - -/* Generate DBX debugging information. */ - -/* #define DBX_DEBUGGING_INFO */ - -/* Run-time compilation parameters selecting different hardware subsets. -*/ - -extern int target_flags; - -/* Macro to define tables used to set the flags. - This is a list in braces of pairs in braces, - each pair being { "NAME", VALUE } - where VALUE is the bits to set or minus the bits to clear. - An empty string NAME is used to identify the default VALUE. */ - -#define TARGET_SWITCHES \ -{ { "fpu", 1}, \ - { "soft-float", -1}, \ -/* return float result in ac0 */\ - { "ac0", 2}, \ - { "no-ac0", -2}, \ -/* is 11/40 */ \ - { "40", 4}, \ - { "no-40", -4}, \ -/* is 11/45 */ \ - { "45", 8}, \ - { "no-45", -8}, \ -/* is 11/10 */ \ - { "10", -12}, \ -/* use movstrhi for bcopy */ \ - { "bcopy", 16}, \ - { "bcopy-builtin", -16}, \ -/* use 32 bit for int */ \ - { "int32", 32}, \ - { "no-int16", 32}, \ - { "int16", -32}, \ - { "no-int32", -32}, \ -/* use 32 bit for float */ \ - { "float32", 64}, \ - { "no-float64", 64}, \ - { "float64", -64}, \ - { "no-float32", -64}, \ -/* allow abshi pattern? - can trigger "optimizations" which make code SLOW! */\ - { "abshi", 128}, \ - { "no-abshi", -128}, \ -/* is branching expensive - on a PDP, it's actually really cheap */ \ -/* this is just to play around and check what code gcc generates */ \ - { "branch-expensive", 256}, \ - { "branch-cheap", -256}, \ -/* split instruction and data memory? */ \ - { "split", 1024 }, \ - { "no-split", -1024 }, \ -/* default */ \ - { "", TARGET_DEFAULT} \ -} - -#define TARGET_DEFAULT (1 | 8 | 128) - -#define TARGET_FPU (target_flags & 1) -#define TARGET_SOFT_FLOAT (!TARGET_FPU) - -#define TARGET_AC0 ((target_flags & 2) && TARGET_FPU) -#define TARGET_NO_AC0 (! TARGET_AC0) - -#define TARGET_45 (target_flags & 8) -#define TARGET_40_PLUS ((target_flags & 4) || (target_flags & 8)) -#define TARGET_10 (! TARGET_40_PLUS) - -#define TARGET_BCOPY_BUILTIN (! (target_flags & 16)) - -#define TARGET_INT16 (! TARGET_INT32) -#define TARGET_INT32 (target_flags & 32) - -#define TARGET_FLOAT32 (target_flags & 64) -#define TARGET_FLOAT64 (! TARGET_FLOAT32) - -#define TARGET_ABSHI_BUILTIN (target_flags & 128) - -#define TARGET_BRANCH_EXPENSIVE (target_flags & 256) -#define TARGET_BRANCH_CHEAP (!TARGET_BRANCH_EXPENSIVE) - -#define TARGET_SPLIT (target_flags & 1024) -#define TARGET_NOSPLIT (! TARGET_SPLIT) - - -/* TYPE SIZES */ -#define CHAR_TYPE_SIZE 8 -#define SHORT_TYPE_SIZE 16 -#define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32) -#define LONG_TYPE_SIZE 32 -#define LONG_LONG_TYPE_SIZE 64 - -/* if we set FLOAT_TYPE_SIZE to 32, we could have the benefit - of saving core for huge arrays - the definitions are - already in md - but floats can never reside in - an FPU register - we keep the FPU in double float mode - all the time !! */ -#define FLOAT_TYPE_SIZE (TARGET_FLOAT32 ? 32 : 64) -#define DOUBLE_TYPE_SIZE 64 -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* machine types from ansi */ -#define SIZE_TYPE "unsigned int" /* definition of size_t */ - -/* is used in cexp.y - we don't have target_flags there, - so just give default definition - - hope it does not come back to haunt us! */ -#define WCHAR_TYPE "int" /* or long int???? */ -#define WCHAR_TYPE_SIZE 16 - -#define PTRDIFF_TYPE "int" - -/* target machine storage layout */ - -/* Define this if most significant bit is lowest numbered - in instructions that operate on numbered bit-fields. */ -#define BITS_BIG_ENDIAN 0 - -/* Define this if most significant byte of a word is the lowest numbered. */ -#define BYTES_BIG_ENDIAN 0 - -/* Define this if most significant word of a multiword number is numbered. */ -#define WORDS_BIG_ENDIAN 1 - -/* number of bits in an addressable storage unit */ -#define BITS_PER_UNIT 8 - -/* Width in bits of a "word", which is the contents of a machine register. - Note that this is not necessarily the width of data type `int'; - if using 16-bit ints on a 68000, this would still be 32. - But on a machine with 16-bit registers, this would be 16. */ -/* This is a machine with 16-bit registers */ -#define BITS_PER_WORD 16 - -/* Width of a word, in units (bytes). - - UNITS OR BYTES - seems like units */ -#define UNITS_PER_WORD 2 - -/* Maximum sized of reasonable data type - DImode or Dfmode ...*/ -#define MAX_FIXED_MODE_SIZE 64 - -/* Width in bits of a pointer. - See also the macro `Pmode' defined below. */ -#define POINTER_SIZE 16 - -/* Allocation boundary (in *bits*) for storing pointers in memory. */ -#define POINTER_BOUNDARY 16 - -/* Allocation boundary (in *bits*) for storing arguments in argument list. */ -#define PARM_BOUNDARY 16 - -/* Allocation boundary (in *bits*) for the code of a function. */ -#define FUNCTION_BOUNDARY 16 - -/* Alignment of field after `int : 0' in a structure. */ -#define EMPTY_FIELD_BOUNDARY 16 - -/* No data type wants to be aligned rounder than this. */ -#define BIGGEST_ALIGNMENT 16 - -/* Define this if move instructions will actually fail to work - when given unaligned data. */ -#define STRICT_ALIGNMENT 1 - -/* Standard register usage. */ - -/* Number of actual hardware registers. - The hardware registers are assigned numbers for the compiler - from 0 to just below FIRST_PSEUDO_REGISTER. - All registers that the compiler knows about must be given numbers, - even those that are not normally considered general registers. - - we have 8 integer registers, plus 6 float - (don't use scratch float !) */ - -#define FIRST_PSEUDO_REGISTER 14 - -/* 1 for registers that have pervasive standard uses - and are not available for the register allocator. - - On the pdp, these are: - Reg 7 = pc; - reg 6 = sp; - reg 5 = fp; not necessarily! -*/ - -/* don't let them touch fp regs for the time being !*/ - -#define FIXED_REGISTERS \ -{0, 0, 0, 0, 0, 0, 1, 1, \ - 0, 0, 0, 0, 0, 0 } - - - -/* 1 for registers not available across function calls. - These must include the FIXED_REGISTERS and also any - registers that can be used without being saved. - The latter must include the registers where values are returned - and the register where structure-value addresses are passed. - Aside from that, you can include as many other registers as you like. */ - -/* don't know about fp */ -#define CALL_USED_REGISTERS \ -{1, 1, 0, 0, 0, 0, 1, 1, \ - 0, 0, 0, 0, 0, 0 } - - -/* Make sure everything's fine if we *don't* have an FPU. - This assumes that putting a register in fixed_regs will keep the - compiler's mitts completely off it. We don't bother to zero it out - of register classes. -*/ -#define CONDITIONAL_REGISTER_USAGE \ -{ \ - int i; \ - HARD_REG_SET x; \ - if (!TARGET_FPU) \ - { \ - COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); \ - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ - if (TEST_HARD_REG_BIT (x, i)) \ - fixed_regs[i] = call_used_regs[i] = 1; \ - } \ - \ - if (TARGET_AC0) \ - call_used_regs[8] = 1; \ -} - -/* Return number of consecutive hard regs needed starting at reg REGNO - to hold something of mode MODE. - This is ordinarily the length in words of a value of mode MODE - but can be less for certain modes in special long registers. -*/ - -#define HARD_REGNO_NREGS(REGNO, MODE) \ -((REGNO < 8)? \ - ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \ - :1) - - -/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. - On the pdp, the cpu registers can hold any mode - check alignment - - FPU can only hold DF - simplifies life! -*/ -#define HARD_REGNO_MODE_OK(REGNO, MODE) \ -((REGNO < 8)? \ - ((GET_MODE_BITSIZE(MODE) <= 16) \ - || (GET_MODE_BITSIZE(MODE) == 32 && !(REGNO & 1))) \ - :(MODE) == DFmode) - - -/* Value is 1 if it is a good idea to tie two pseudo registers - when one has mode MODE1 and one has mode MODE2. - If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, - for any hard reg, then this must be 0 for correct output. */ -#define MODES_TIEABLE_P(MODE1, MODE2) 0 - -/* Specify the registers used for certain standard purposes. - The values of these macros are register numbers. */ - -/* the pdp11 pc overloaded on a register that the compiler knows about. */ -#define PC_REGNUM 7 - -/* Register to use for pushing function arguments. */ -#define STACK_POINTER_REGNUM 6 - -/* Base register for access to local variables of the function. */ -#define FRAME_POINTER_REGNUM 5 - -/* Value should be nonzero if functions must have frame pointers. - Zero means the frame pointer need not be set up (and parms - may be accessed via the stack pointer) in functions that seem suitable. - This is computed in `reload', in reload1.c. - */ - -#define FRAME_POINTER_REQUIRED 0 - -/* Base register for access to arguments of the function. */ -#define ARG_POINTER_REGNUM 5 - -/* Register in which static-chain is passed to a function. */ -/* ??? - i don't want to give up a reg for this! */ -#define STATIC_CHAIN_REGNUM 4 - -/* Register in which address to store a structure value - is passed to a function. - let's make it an invisible first argument!!! */ - -#define STRUCT_VALUE 0 - - -/* Define the classes of registers for register constraints in the - machine description. Also define ranges of constants. - - One of the classes must always be named ALL_REGS and include all hard regs. - If there is more than one class, another class must be named NO_REGS - and contain no registers. - - The name GENERAL_REGS must be the name of a class (or an alias for - another name such as ALL_REGS). This is the class of registers - that is allowed by "g" or "r" in a register constraint. - Also, registers outside this class are allocated only when - instructions express preferences for them. - - The classes must be numbered in nondecreasing order; that is, - a larger-numbered class must never be contained completely - in a smaller-numbered class. - - For any two classes, it is very desirable that there be another - class that represents their union. */ - -/* The pdp has a couple of classes: - -MUL_REGS are used for odd numbered regs, to use in 16 bit multiplication - (even numbered do 32 bit multiply) -LMUL_REGS long multiply registers (even numbered regs ) - (don't need them, all 32 bit regs are even numbered!) -GENERAL_REGS is all cpu -LOAD_FPU_REGS is the first four cpu regs, they are easier to load -NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them -FPU_REGS is all fpu regs -*/ - -enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES }; - -#define N_REG_CLASSES (int) LIM_REG_CLASSES - -/* have to allow this till cmpsi/tstsi are fixed in a better way !! */ -#define SMALL_REGISTER_CLASSES 1 - -/* Since GENERAL_REGS is the same class as ALL_REGS, - don't give it a different class number; just make it an alias. */ - -/* #define GENERAL_REGS ALL_REGS */ - -/* Give names of register classes as strings for dump file. */ - -#define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" } - -/* Define which registers fit in which classes. - This is an initializer for a vector of HARD_REG_SET - of length N_REG_CLASSES. */ - -#define REG_CLASS_CONTENTS {0, 0x00aa, 0x00ff, 0x0f00, 0x3000, 0x3f00, 0x3fff} - -/* The same information, inverted: - Return the class number of the smallest class containing - reg number REGNO. This could be a conditional expression - or could index an array. */ - -#define REGNO_REG_CLASS(REGNO) \ -((REGNO)>=8?((REGNO)<=11?LOAD_FPU_REGS:NO_LOAD_FPU_REGS):((REGNO&1)?MUL_REGS:GENERAL_REGS)) - - -/* The class value for index registers, and the one for base regs. */ -#define INDEX_REG_CLASS GENERAL_REGS -#define BASE_REG_CLASS GENERAL_REGS - -/* Get reg_class from a letter such as appears in the machine description. */ - -#define REG_CLASS_FROM_LETTER(C) \ -((C) == 'f' ? FPU_REGS : \ - ((C) == 'd' ? MUL_REGS : \ - ((C) == 'a' ? LOAD_FPU_REGS : NO_REGS))) - - -/* The letters I, J, K, L and M in a register constraint string - can be used to stand for particular ranges of immediate operands. - This macro defines what the ranges are. - C is the letter, and VALUE is a constant value. - Return 1 if VALUE is in the range specified by C. - - I bits 31-16 0000 - J bits 15-00 0000 - K completely random 32 bit - L,M,N -1,1,0 respectively - O where doing shifts in sequence is faster than - one big shift -*/ - -#define CONST_OK_FOR_LETTER_P(VALUE, C) \ - ((C) == 'I' ? ((VALUE) & 0xffff0000) == 0 \ - : (C) == 'J' ? ((VALUE) & 0x0000ffff) == 0 \ - : (C) == 'K' ? (((VALUE) & 0xffff0000) != 0 \ - && ((VALUE) & 0x0000ffff) != 0) \ - : (C) == 'L' ? ((VALUE) == 1) \ - : (C) == 'M' ? ((VALUE) == -1) \ - : (C) == 'N' ? ((VALUE) == 0) \ - : (C) == 'O' ? (abs(VALUE) >1 && abs(VALUE) <= 4) \ - : 0) - -/* Similar, but for floating constants, and defining letters G and H. - Here VALUE is the CONST_DOUBLE rtx itself. */ - -#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ - ((C) == 'G' && XINT (VALUE, 0) == 0 && XINT (VALUE, 1) == 0) - - -/* Letters in the range `Q' through `U' may be defined in a - machine-dependent fashion to stand for arbitrary operand types. - The machine description macro `EXTRA_CONSTRAINT' is passed the - operand as its first argument and the constraint letter as its - second operand. - - `Q' is for memory references using take more than 1 instruction. - `R' is for memory references which take 1 word for the instruction. */ - -#define EXTRA_CONSTRAINT(OP,CODE) \ - ((GET_CODE (OP) != MEM) ? 0 \ - : !legitimate_address_p (GET_MODE (OP), XEXP (OP, 0)) ? 0 \ - : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \ - : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \ - : 0) - -/* Given an rtx X being reloaded into a reg required to be - in class CLASS, return the class of reg to actually use. - In general this is just CLASS; but on some machines - in some cases it is preferable to use a more restrictive class. - -loading is easier into LOAD_FPU_REGS than FPU_REGS! */ - -#define PREFERRED_RELOAD_CLASS(X,CLASS) \ -(((CLASS) != FPU_REGS)?(CLASS):LOAD_FPU_REGS) - -#define SECONDARY_RELOAD_CLASS(CLASS,MODE,x) \ -(((CLASS) == NO_LOAD_FPU_REGS && !(REG_P(x) && LOAD_FPU_REG_P(REGNO(x))))?LOAD_FPU_REGS:NO_REGS) - -/* Return the maximum number of consecutive registers - needed to represent mode MODE in a register of class CLASS. */ -#define CLASS_MAX_NREGS(CLASS, MODE) \ -((CLASS == GENERAL_REGS || CLASS == MUL_REGS)? \ - ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \ - 1 \ -) - - -/* Stack layout; function entry, exit and calling. */ - -/* Define this if pushing a word on the stack - makes the stack pointer a smaller address. */ -#define STACK_GROWS_DOWNWARD - -/* Define this if the nominal address of the stack frame - is at the high-address end of the local variables; - that is, each additional local variable allocated - goes at a more negative offset in the frame. -*/ -#define FRAME_GROWS_DOWNWARD - -/* Offset within stack frame to start allocating local variables at. - If FRAME_GROWS_DOWNWARD, this is the offset to the END of the - first local allocated. Otherwise, it is the offset to the BEGINNING - of the first local allocated. */ -#define STARTING_FRAME_OFFSET 0 - -/* If we generate an insn to push BYTES bytes, - this says how many the stack pointer really advances by. - On the pdp11, the stack is on an even boundary */ -#define PUSH_ROUNDING(BYTES) ((BYTES + 1) & ~1) - -/* current_first_parm_offset stores the # of registers pushed on the - stack */ -extern int current_first_parm_offset; - -/* Offset of first parameter from the argument pointer register value. - For the pdp11, this is non-zero to account for the return address. - 1 - return address - 2 - frame pointer (always saved, even when not used!!!!) - -- chnage some day !!!:q! - -*/ -#define FIRST_PARM_OFFSET(FNDECL) 4 - -/* Value is 1 if returning from a function call automatically - pops the arguments described by the number-of-args field in the call. - FUNDECL is the declaration node of the function (as a tree), - FUNTYPE is the data type of the function (as a tree), - or for a library call it is an identifier node for the subroutine name. */ - -#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 - -/* Define how to find the value returned by a function. - VALTYPE is the data type of the value (as a tree). - If the precise function being called is known, FUNC is its FUNCTION_DECL; - otherwise, FUNC is 0. */ -#define BASE_RETURN_VALUE_REG(MODE) \ - ((MODE) == DFmode ? 8 : 0) - -/* On the pdp11 the value is found in R0 (or ac0??? -not without FPU!!!! ) */ - -#define FUNCTION_VALUE(VALTYPE, FUNC) \ - gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE))) - -/* and the called function leaves it in the first register. - Difference only on machines with register windows. */ - -#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ - gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE))) - -/* Define how to find the value returned by a library function - assuming the value has mode MODE. */ - -#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG(MODE)) - -/* 1 if N is a possible register number for a function value - as seen by the caller. - On the pdp, the first "output" reg is the only register thus used. - -maybe ac0 ? - as option someday! */ - -#define FUNCTION_VALUE_REGNO_P(N) (((N) == 0) || (TARGET_AC0 && (N) == 8)) - -/* should probably return DImode and DFmode in memory,lest - we fill up all regs! - - have to, else we crash - exception: maybe return result in - ac0 if DFmode and FPU present - compatibility problem with - libraries for non-floating point ... -*/ - -#define RETURN_IN_MEMORY(TYPE) \ - (TYPE_MODE(TYPE) == DImode || (TYPE_MODE(TYPE) == DFmode && ! TARGET_AC0)) - - -/* 1 if N is a possible register number for function argument passing. - - not used on pdp */ - -#define FUNCTION_ARG_REGNO_P(N) 0 - -/* Define a data type for recording info about an argument list - during the scan of that argument list. This data type should - hold all necessary information about the function itself - and about the args processed so far, enough to enable macros - such as FUNCTION_ARG to determine where the next arg should go. - -*/ - -#define CUMULATIVE_ARGS int - -/* Initialize a variable CUM of type CUMULATIVE_ARGS - for a call to a function whose data type is FNTYPE. - For a library call, FNTYPE is 0. - - ...., the offset normally starts at 0, but starts at 1 word - when the function gets a structure-value-address as an - invisible first argument. */ - -#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ - ((CUM) = 0) - -/* Update the data in CUM to advance over an argument - of mode MODE and data type TYPE. - (TYPE is null for libcalls where that information may not be available.) - -*/ - - -#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ - ((CUM) += ((MODE) != BLKmode \ - ? (GET_MODE_SIZE (MODE)) \ - : (int_size_in_bytes (TYPE)))) - -/* Determine where to put an argument to a function. - Value is zero to push the argument on the stack, - or a hard register in which to store the argument. - - MODE is the argument's machine mode. - TYPE is the data type of the argument (as a tree). - This is null for libcalls where that information may - not be available. - CUM is a variable of type CUMULATIVE_ARGS which gives info about - the preceding args and about the function being called. - NAMED is nonzero if this argument is a named parameter - (otherwise it is an extra parameter matching an ellipsis). */ - -#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 - -/* Define where a function finds its arguments. - This would be different from FUNCTION_ARG if we had register windows. */ -/* -#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ - FUNCTION_ARG (CUM, MODE, TYPE, NAMED) -*/ - -/* For an arg passed partly in registers and partly in memory, - this is the number of registers used. - For args passed entirely in registers or entirely in memory, zero. */ - -#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 - -/* This macro generates the assembly code for function entry. */ -#define FUNCTION_PROLOGUE(FILE, SIZE) \ - output_function_prologue(FILE, SIZE); - -/* Output assembler code to FILE to increment profiler label # LABELNO - for profiling a function entry. */ - -#define FUNCTION_PROFILER(FILE, LABELNO) \ - abort (); - -/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, - the stack pointer does not matter. The value is tested only in - functions that have frame pointers. - No definition is equivalent to always zero. */ - -extern int may_call_alloca; -extern int current_function_pretend_args_size; - -#define EXIT_IGNORE_STACK 1 - -/* This macro generates the assembly code for function exit, - on machines that need it. If FUNCTION_EPILOGUE is not defined - then individual return instructions are generated for each - return statement. Args are same as for FUNCTION_PROLOGUE. -*/ - -#define FUNCTION_EPILOGUE(FILE, SIZE) \ - output_function_epilogue(FILE, SIZE); - -#define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) \ -{ \ - int offset, regno; \ - offset = get_frame_size(); \ - for (regno = 0; regno < 8; regno++) \ - if (regs_ever_live[regno] && ! call_used_regs[regno]) \ - offset += 2; \ - for (regno = 8; regno < 14; regno++) \ - if (regs_ever_live[regno] && ! call_used_regs[regno]) \ - offset += 8; \ - /* offset -= 2; no fp on stack frame */ \ - (DEPTH_VAR) = offset; \ -} - - -/* Addressing modes, and classification of registers for them. */ - -#define HAVE_POST_INCREMENT 1 -/* #define HAVE_POST_DECREMENT 0 */ - -#define HAVE_PRE_DECREMENT 1 -/* #define HAVE_PRE_INCREMENT 0 */ - -/* Macros to check register numbers against specific register classes. */ - -/* These assume that REGNO is a hard or pseudo reg number. - They give nonzero only if REGNO is a hard reg of the suitable class - or a pseudo reg currently allocated to a suitable hard reg. - Since they use reg_renumber, they are safe only once reg_renumber - has been allocated, which happens in local-alloc.c. */ - -#define REGNO_OK_FOR_INDEX_P(REGNO) \ - ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) -#define REGNO_OK_FOR_BASE_P(REGNO) \ - ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) - -/* Now macros that check whether X is a register and also, - strictly, whether it is in a specified class. -*/ - - - -/* Maximum number of registers that can appear in a valid memory address. */ - -#define MAX_REGS_PER_ADDRESS 2 - -/* Recognize any constant value that is a valid address. */ - -#define CONSTANT_ADDRESS_P(X) CONSTANT_P (X) - -/* Nonzero if the constant value X is a legitimate general operand. - It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ - -#define LEGITIMATE_CONSTANT_P(X) (1) - -/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx - and check its validity for a certain class. - We have two alternate definitions for each of them. - The usual definition accepts all pseudo regs; the other rejects - them unless they have been allocated suitable hard regs. - The symbol REG_OK_STRICT causes the latter definition to be used. - - Most source files want to accept pseudo regs in the hope that - they will get allocated to the class that the insn wants them to be in. - Source files for reload pass need to be strict. - After reload, it makes no difference, since pseudo regs have - been eliminated by then. */ - -#ifndef REG_OK_STRICT - -/* Nonzero if X is a hard reg that can be used as an index - or if it is a pseudo reg. */ -#define REG_OK_FOR_INDEX_P(X) (1) -/* Nonzero if X is a hard reg that can be used as a base reg - or if it is a pseudo reg. */ -#define REG_OK_FOR_BASE_P(X) (1) - -#else - -/* Nonzero if X is a hard reg that can be used as an index. */ -#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) -/* Nonzero if X is a hard reg that can be used as a base reg. */ -#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) - -#endif - -/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression - that is a valid memory address for an instruction. - The MODE argument is the machine mode for the MEM expression - that wants to use this address. - -*/ - -#define GO_IF_LEGITIMATE_ADDRESS(mode, operand, ADDR) \ -{ \ - rtx xfoob; \ - \ - /* accept (R0) */ \ - if (GET_CODE (operand) == REG \ - && REG_OK_FOR_BASE_P(operand)) \ - goto ADDR; \ - \ - /* accept @#address */ \ - if (CONSTANT_ADDRESS_P (operand)) \ - goto ADDR; \ - \ - /* accept X(R0) */ \ - if (GET_CODE (operand) == PLUS \ - && GET_CODE (XEXP (operand, 0)) == REG \ - && REG_OK_FOR_BASE_P (XEXP (operand, 0)) \ - && CONSTANT_ADDRESS_P (XEXP (operand, 1))) \ - goto ADDR; \ - \ - /* accept -(R0) */ \ - if (GET_CODE (operand) == PRE_DEC \ - && GET_CODE (XEXP (operand, 0)) == REG \ - && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \ - goto ADDR; \ - \ - /* accept (R0)+ */ \ - if (GET_CODE (operand) == POST_INC \ - && GET_CODE (XEXP (operand, 0)) == REG \ - && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \ - goto ADDR; \ - \ - /* handle another level of indirection ! */ \ - if (GET_CODE(operand) != MEM) \ - goto fail; \ - \ - xfoob = XEXP (operand, 0); \ - \ - /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently */ \ - /* also forbidden for float, because we have to handle this */ \ - /* in output_move_double and/or output_move_quad() - we could */ \ - /* do it, but currently it's not worth it!!! */ \ - /* now that DFmode cannot go into CPU register file, */ \ - /* maybe I should allow float ... */ \ - /* but then I have to handle memory-to-memory moves in movdf ?? */ \ - \ - if (GET_MODE_BITSIZE(mode) > 16) \ - goto fail; \ - \ - /* accept @(R0) - which is @0(R0) */ \ - if (GET_CODE (xfoob) == REG \ - && REG_OK_FOR_BASE_P(xfoob)) \ - goto ADDR; \ - \ - /* accept @address */ \ - if (CONSTANT_ADDRESS_P (xfoob)) \ - goto ADDR; \ - \ - /* accept @X(R0) */ \ - if (GET_CODE (xfoob) == PLUS \ - && GET_CODE (XEXP (xfoob, 0)) == REG \ - && REG_OK_FOR_BASE_P (XEXP (xfoob, 0)) \ - && CONSTANT_ADDRESS_P (XEXP (xfoob, 1))) \ - goto ADDR; \ - \ - /* accept @-(R0) */ \ - if (GET_CODE (xfoob) == PRE_DEC \ - && GET_CODE (XEXP (xfoob, 0)) == REG \ - && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \ - goto ADDR; \ - \ - /* accept @(R0)+ */ \ - if (GET_CODE (xfoob) == POST_INC \ - && GET_CODE (XEXP (xfoob, 0)) == REG \ - && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \ - goto ADDR; \ - \ - /* anything else is invalid */ \ - fail: ; \ -} - - -/* Try machine-dependent ways of modifying an illegitimate address - to be legitimate. If we find one, return the new, valid address. - This macro is used in only one place: `memory_address' in explow.c. - - OLDX is the address as it was before break_out_memory_refs was called. - In some cases it is useful to look at this to decide what needs to be done. - - MODE and WIN are passed so that this macro can use - GO_IF_LEGITIMATE_ADDRESS. - - It is always safe for this macro to do nothing. It exists to recognize - opportunities to optimize the output. */ - -#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} - - -/* Go to LABEL if ADDR (a legitimate address expression) - has an effect that depends on the machine mode it is used for. - On the pdp this is for predec/postinc */ - -#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ - { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \ - goto LABEL; \ - } - - -/* Specify the machine mode that this machine uses - for the index in the tablejump instruction. */ -#define CASE_VECTOR_MODE HImode - -/* Define this if a raw index is all that is needed for a - `tablejump' insn. */ -#define CASE_TAKES_INDEX_RAW - -/* Define as C expression which evaluates to nonzero if the tablejump - instruction expects the table to contain offsets from the address of the - table. - Do not define this if the table should contain absolute addresses. */ -/* #define CASE_VECTOR_PC_RELATIVE 1 */ - -/* Specify the tree operation to be used to convert reals to integers. */ -#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR - -/* This is the kind of divide that is easiest to do in the general case. */ -#define EASY_DIV_EXPR TRUNC_DIV_EXPR - -/* Define this as 1 if `char' should by default be signed; else as 0. */ -#define DEFAULT_SIGNED_CHAR 1 - -/* Max number of bytes we can move from memory to memory - in one reasonably fast instruction. -*/ - -#define MOVE_MAX 2 - -/* Zero extension is faster if the target is known to be zero */ -/* #define SLOW_ZERO_EXTEND */ - -/* Nonzero if access to memory by byte is slow and undesirable. - -*/ -#define SLOW_BYTE_ACCESS 0 - -/* Do not break .stabs pseudos into continuations. */ -#define DBX_CONTIN_LENGTH 0 - -/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits - is done just by pretending it is already truncated. */ -#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 - - -/* Add any extra modes needed to represent the condition code. - - CCFPmode is used for FPU, but should we use a separate reg? */ -#define EXTRA_CC_MODES CCFPmode - -/* the name for the mode above */ -#define EXTRA_CC_NAMES "CCFPmode" - -/* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE, - return the mode to be used for the comparison. For floating-point, CCFPmode - should be used. */ - -#define SELECT_CC_MODE(OP,X,Y) \ -(GET_MODE_CLASS(GET_MODE(X)) == MODE_FLOAT? CCFPmode : CCmode) - -/* We assume that the store-condition-codes instructions store 0 for false - and some other value for true. This is the value stored for true. */ - -/* #define STORE_FLAG_VALUE 1 */ - -/* Specify the machine mode that pointers have. - After generation of rtl, the compiler makes no further distinction - between pointers and any other objects of this machine mode. */ -#define Pmode HImode - -/* A function address in a call instruction - is a word address (for indexing purposes) - so give the MEM rtx a word's mode. */ -#define FUNCTION_MODE HImode - -/* Define this if addresses of constant functions - shouldn't be put through pseudo regs where they can be cse'd. - Desirable on machines where ordinary constants are expensive - but a CALL with constant address is cheap. */ -/* #define NO_FUNCTION_CSE */ - -/* Compute the cost of computing a constant rtl expression RTX - whose rtx-code is CODE. The body of this macro is a portion - of a switch statement. If the code is computed here, - return it with a return statement. Otherwise, break from the switch. - - -1, 0, 1 are cheaper for add, sub ... -*/ - -#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ - case CONST_INT: \ - if (INTVAL(RTX) == 0 \ - || INTVAL(RTX) == -1 \ - || INTVAL(RTX) == 1) \ - return 0; \ - case CONST: \ - case LABEL_REF: \ - case SYMBOL_REF: \ - /* twice as expensive as REG */ \ - return 2; \ - case CONST_DOUBLE: \ - /* twice (or 4 times) as expensive as 16 bit */ \ - return 4; - -/* cost of moving one register class to another */ -#define REGISTER_MOVE_COST(CLASS1, CLASS2) register_move_cost(CLASS1, CLASS2) - -/* Tell emit-rtl.c how to initialize special values on a per-function base. */ -extern int optimize; -extern struct rtx_def *cc0_reg_rtx; - -#define CC_STATUS_MDEP rtx - -#define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) - -/* Tell final.c how to eliminate redundant test instructions. */ - -/* Here we define machine-dependent flags and fields in cc_status - (see `conditions.h'). */ - -#define CC_IN_FPU 04000 - -/* Do UPDATE_CC if EXP is a set, used in - NOTICE_UPDATE_CC - - floats only do compare correctly, else nullify ... - - get cc0 out soon ... -*/ - -/* Store in cc_status the expressions - that the condition codes will describe - after execution of an instruction whose pattern is EXP. - Do not alter them if the instruction would not alter the cc's. */ - -#define NOTICE_UPDATE_CC(EXP, INSN) \ -{ if (GET_CODE (EXP) == SET) \ - { \ - notice_update_cc_on_set(EXP, INSN); \ - } \ - else if (GET_CODE (EXP) == PARALLEL \ - && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ - { \ - notice_update_cc_on_set(XVECEXP (EXP, 0, 0), INSN); \ - } \ - else if (GET_CODE (EXP) == CALL) \ - { /* all bets are off */ CC_STATUS_INIT; } \ - if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ - && cc_status.value2 \ - && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ - printf ("here!\n", cc_status.value2 = 0); \ -} - -/* Control the assembler format that we output. */ - -/* Output at beginning of assembler file. */ - -#if 0 -#define ASM_FILE_START(FILE) \ -( \ -fprintf (FILE, "\t.data\n"), \ -fprintf (FILE, "$help$: . = .+8 ; space for tmp moves!\n") \ -/* do we need reg def's R0 = %0 etc ??? */ \ -) -#else -#define ASM_FILE_START(FILE) (0) -#endif - - -/* Output to assembler file text saying following lines - may contain character constants, extra white space, comments, etc. */ - -#define ASM_APP_ON "" - -/* Output to assembler file text saying following lines - no longer contain unusual constructs. */ - -#define ASM_APP_OFF "" - -/* Output before read-only data. */ - -#define TEXT_SECTION_ASM_OP "\t.text\n" - -/* Output before writable data. */ - -#define DATA_SECTION_ASM_OP "\t.data\n" - -/* How to refer to registers in assembler output. - This sequence is indexed by compiler's hard-register-number (see above). */ - -#define REGISTER_NAMES \ -{"r0", "r1", "r2", "r3", "r4", "fp", "sp", "pc", \ - "ac0", "ac1", "ac2", "ac3", "ac4", "ac5" } - -/* How to renumber registers for dbx and gdb. */ - -#define DBX_REGISTER_NUMBER(REGNO) (REGNO) - -/* This is how to output the definition of a user-level label named NAME, - such as the label on a static function or variable NAME. */ - -#define ASM_OUTPUT_LABEL(FILE,NAME) \ - do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) - -/* This is how to output a command to make the user-level label named NAME - defined for reference from other files. */ - -#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ - do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs("\n", FILE); } while (0) - -/* The prefix to add to user-visible assembler symbols. */ - -#define USER_LABEL_PREFIX "_" - -/* This is how to output an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. */ - -#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ - fprintf (FILE, "%s_%d:\n", PREFIX, NUM) - -/* This is how to store into the string LABEL - the symbol_ref name of an internal numbered label where - PREFIX is the class of label and NUM is the number within the class. - This is suitable for output with `assemble_name'. */ - -#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ - sprintf (LABEL, "*%s_%d", PREFIX, NUM) - -/* This is how to output an assembler line defining a `double' constant. */ - -#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ - fprintf (FILE, "\tdouble %.20e\n", (VALUE)) - -/* This is how to output an assembler line defining a `float' constant. */ - -#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ - fprintf (FILE, "\tfloat %.12e\n", (VALUE)) - -/* This is how to output an assembler line defining an `int' constant. */ - -#define ASM_OUTPUT_INT(FILE,VALUE) \ -( fprintf (FILE, "\t.word "), \ - output_addr_const (FILE, (VALUE)), \ - fprintf (FILE, "\n")) - -/* Likewise for `short' and `char' constants. */ - -#define ASM_OUTPUT_SHORT(FILE,VALUE) \ -( fprintf (FILE, "\t.word "), \ - output_addr_const (FILE, (VALUE)), \ - fprintf (FILE, " /*short*/\n")) - -#define ASM_OUTPUT_CHAR(FILE,VALUE) \ -( fprintf (FILE, "\t.byte "), \ - output_addr_const (FILE, (VALUE)), \ - fprintf (FILE, " /* char */\n")) - -/* This is how to output an assembler line for a numeric constant byte.- - - do we really NEED it ? let's output it with a comment and grep the - assembly source ;-) -*/ - -#define ASM_OUTPUT_BYTE(FILE,VALUE) \ - fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) - -#define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ - output_ascii (FILE, P, SIZE) - -#define ASM_OUTPUT_ADDR_VEC_PROLOGUE(FILE, MODE, LEN) \ - fprintf (FILE, "\t/* HELP! */\n"); - -/* This is how to output an element of a case-vector that is absolute. */ - -#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ - fprintf (FILE, "\t.word L_%d\n", VALUE) - -/* This is how to output an element of a case-vector that is relative. - Don't define this if it is not supported. */ - -/* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */ - -/* This is how to output an assembler line - that says to advance the location counter - to a multiple of 2**LOG bytes. - - who needs this???? -*/ - -#define ASM_OUTPUT_ALIGN(FILE,LOG) \ - if ((LOG) != 0) \ - fprintf (FILE, "\t.align %d\n", 1<<(LOG)) - -#define ASM_OUTPUT_SKIP(FILE,SIZE) \ - fprintf (FILE, "\t.=.+ %d\n", (SIZE)) - -/* This says how to output an assembler line - to define a global common symbol. */ - -#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -( fprintf ((FILE), ".globl "), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), "\n"), \ - assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ": .=.+ %d\n", (ROUNDED)) \ -) - -/* This says how to output an assembler line - to define a local common symbol. */ - -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -( assemble_name ((FILE), (NAME)), \ - fprintf ((FILE), ":\t.=.+ %d\n", (ROUNDED))) - -/* Store in OUTPUT a string (made with alloca) containing - an assembler-name for a local static variable named NAME. - LABELNO is an integer which is different for each call. */ - -#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ -( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ - sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) - -/* Define the parentheses used to group arithmetic operations - in assembler code. */ - -#define ASM_OPEN_PAREN "(" -#define ASM_CLOSE_PAREN ")" - -/* Define results of standard character escape sequences. */ -#define TARGET_BELL 007 -#define TARGET_BS 010 -#define TARGET_TAB 011 -#define TARGET_NEWLINE 012 -#define TARGET_VT 013 -#define TARGET_FF 014 -#define TARGET_CR 015 - -/* Print operand X (an rtx) in assembler syntax to file FILE. - CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. - For `%' followed by punctuation, CODE is the punctuation and X is null. - -*/ - - -#define PRINT_OPERAND(FILE, X, CODE) \ -{ if (CODE == '#') fprintf (FILE, "#"); \ - else if (GET_CODE (X) == REG) \ - fprintf (FILE, "%s", reg_names[REGNO (X)]); \ - else if (GET_CODE (X) == MEM) \ - output_address (XEXP (X, 0)); \ - else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != SImode) \ - { union { double d; int i[2]; } u; \ - u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \ - fprintf (FILE, "#%.20e", u.d); } \ - else { putc ('$', FILE); output_addr_const (FILE, X); }} - -/* Print a memory address as an operand to reference that memory location. */ - -#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ - print_operand_address (FILE, ADDR) - -#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ -( \ - fprintf (FILE, "\tmov %s, -(sp)\n", reg_names[REGNO]) \ -) - -#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ -( \ - fprintf (FILE, "\tmov (sp)+, %s\n", reg_names[REGNO]) \ -) - - -#define ASM_IDENTIFY_GCC(FILE) \ - fprintf(FILE, "gcc_compiled:\n") - -#define ASM_OUTPUT_DOUBLE_INT(a,b) fprintf(a,"%d", b) - -/* trampoline - how should i do it in separate i+d ? - have some allocate_trampoline magic??? - - the following should work for shared I/D: */ - -/* lets see whether this works as trampoline: -MV #STATIC, $4 0x940Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM -JMP FUNCTION 0x0058 0x0000 <- FUNCTION -*/ - -#define TRAMPOLINE_TEMPLATE(FILE) \ -{ \ - if (TARGET_SPLIT) \ - abort(); \ - \ - ASM_OUTPUT_INT (FILE, GEN_INT (0x9400+STATIC_CHAIN_REGNUM)); \ - ASM_OUTPUT_INT (FILE, const0_rtx); \ - ASM_OUTPUT_INT (FILE, GEN_INT(0x0058)); \ - ASM_OUTPUT_INT (FILE, const0_rtx); \ -} - -#define TRAMPOLINE_SIZE 8 -#define TRAMPOLINE_ALIGN 16 - -/* Emit RTL insns to initialize the variable parts of a trampoline. - FNADDR is an RTX for the address of the function's pure code. - CXT is an RTX for the static chain value for the function. */ - -#define INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT) \ -{ \ - if (TARGET_SPLIT) \ - abort(); \ - \ - emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 2)), CXT); \ - emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 6)), FNADDR); \ -} - - -/* Some machines may desire to change what optimizations are - performed for various optimization levels. This macro, if - defined, is executed once just after the optimization level is - determined and before the remainder of the command options have - been parsed. Values set in this macro are used as the default - values for the other command line options. - - LEVEL is the optimization level specified; 2 if -O2 is - specified, 1 if -O is specified, and 0 if neither is specified. */ - -#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ -{ \ - if (LEVEL >= 3) \ - { \ - if (! SIZE) \ - flag_inline_functions = 1; \ - flag_omit_frame_pointer = 1; \ - /* flag_unroll_loops = 1; */ \ - } \ -} - - -/* Provide the costs of a rtl expression. This is in the body of a - switch on CODE. - - we don't say how expensive SImode is - pretty expensive!!! - - there is something wrong in MULT because MULT is not - as cheap as total = 2 even if we can shift! - - if optimizing for size make mult etc cheap, but not 1, so when - in doubt the faster insn is chosen. -*/ - -#define RTX_COSTS(X,CODE,OUTER_CODE) \ - case MULT: \ - if (optimize_size) \ - total = COSTS_N_INSNS(2); \ - else \ - total = COSTS_N_INSNS (11); \ - break; \ - case DIV: \ - if (optimize_size) \ - total = COSTS_N_INSNS(2); \ - else \ - total = COSTS_N_INSNS (25); \ - break; \ - case MOD: \ - if (optimize_size) \ - total = COSTS_N_INSNS(2); \ - else \ - total = COSTS_N_INSNS (26); \ - break; \ - case ABS: \ - /* equivalent to length, so same for optimize_size */ \ - total = COSTS_N_INSNS (3); \ - break; \ - case ZERO_EXTEND: \ - /* only used for: qi->hi */ \ - total = COSTS_N_INSNS(1); \ - break; \ - case SIGN_EXTEND: \ - if (GET_MODE(X) == HImode) \ - total = COSTS_N_INSNS(1); \ - else if (GET_MODE(X) == SImode) \ - total = COSTS_N_INSNS(6); \ - else \ - total = COSTS_N_INSNS(2); \ - break; \ - /* case LSHIFT: */ \ - case ASHIFT: \ - case LSHIFTRT: \ - case ASHIFTRT: \ - if (optimize_size) \ - total = COSTS_N_INSNS(1); \ - else if (GET_MODE(X) == QImode) \ - { \ - if (GET_CODE(XEXP (X,1)) != CONST_INT) \ - total = COSTS_N_INSNS(8); /* worst case */ \ - else \ - total = COSTS_N_INSNS(INTVAL(XEXP (X,1))); \ - } \ - else if (GET_MODE(X) == HImode) \ - { \ - if (GET_CODE(XEXP (X,1)) == CONST_INT) \ - { \ - if (abs (INTVAL (XEXP (X, 1))) == 1) \ - total = COSTS_N_INSNS(1); \ - else \ - total = COSTS_N_INSNS(2.5 + 0.5 *INTVAL(XEXP(X,1))); \ - } \ - else /* worst case */ \ - total = COSTS_N_INSNS (10); \ - } \ - else if (GET_MODE(X) == SImode) \ - { \ - if (GET_CODE(XEXP (X,1)) == CONST_INT) \ - total = COSTS_N_INSNS(2.5 + 0.5 *INTVAL(XEXP(X,1))); \ - else /* worst case */ \ - total = COSTS_N_INSNS(18); \ - } \ - break; - - -/* there is no point in avoiding branches on a pdp, - since branches are really cheap - I just want to find out - how much difference the BRANCH_COST macro makes in code */ -#define BRANCH_COST (TARGET_BRANCH_CHEAP ? 0 : 1) - - -#define COMPARE_FLAG_MODE HImode - diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md deleted file mode 100755 index 621b874..0000000 --- a/gcc/config/pdp11/pdp11.md +++ /dev/null @@ -1,1824 +0,0 @@ -;;- Machine description for the pdp11 for GNU C compiler -;; Copyright (C) 1994, 1995, 1997 Free Software Foundation, Inc. -;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). - -;; This file is part of GNU CC. - -;; GNU CC is free software; you can redistribute it and/or modify -;; it under the terms of the GNU General Public License as published by -;; the Free Software Foundation; either version 1, or (at your option) -;; any later version. - -;; GNU CC is distributed in the hope that it will be useful, -;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;; GNU General Public License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GNU CC; see the file COPYING. If not, write to -;; the Free Software Foundation, 59 Temple Place - Suite 330, -;; Boston, MA 02111-1307, USA. - - -;; HI is 16 bit -;; QI is 8 bit - -;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. - -;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code -;;- updates for most instructions. - -;;- Operand classes for the register allocator: - -;; Compare instructions. - -;; currently we only support df floats, which saves us quite some -;; hassle switching the FP mode! -;; we assume that CPU is always in long float mode, and -;; 16 bit integer mode - currently, the prologue for main does this, -;; but maybe we should just set up a NEW crt0 properly, -;; -- and what about signal handling code? -;; (we don't even let sf floats in the register file, so -;; we only should have to worry about truncating and widening -;; when going to memory) - -;; abort() call by g++ - must define libfunc for cmp_optab -;; and ucmp_optab for mode SImode, because we don't have that!!! -;; - yet since no libfunc is there, we abort () - -;; The only thing that remains to be done then is output -;; the floats in a way the assembler can handle it (and -;; if you're really into it, use a PDP11 float emulation -;; library to do floating point constant folding - but -;; I guess you'll get reasonable results even when not -;; doing this) -;; the last thing to do is fix the UPDATE_CC macro to check -;; for floating point condition codes, and set cc_status -;; properly, also setting the CC_IN_FCCR flag. - -;; define attributes -;; currently type is only fpu or arith or unknown, maybe branch later ? -;; default is arith -(define_attr "type" "unknown,arith,fp" (const_string "arith")) - -;; length default is 1 word each -(define_attr "length" "" (const_int 1)) - -;; a user's asm statement -(define_asm_attributes - [(set_attr "type" "unknown") -; all bets are off how long it is - make it 256, forces long jumps -; whenever jumping around it !!! - (set_attr "length" "256")]) - -;; define function units - -;; arithmetic - values here immediately when next insn issued -;; or does it mean the number of cycles after this insn was issued? -;; how do I say that fpu insns use cpu also? (pre-interaction phase) - -;(define_function_unit "cpu" 1 1 (eq_attr "type" "arith") 0 0) -;(define_function_unit "fpu" 1 1 (eq_attr "type" "fp") 0 0) - -;; compare -(define_insn "cmpdf" - [(set (cc0) - (compare (match_operand:DF 0 "general_operand" "fR,Q,F") - (match_operand:DF 1 "register_operand" "a,a,a")))] - "TARGET_FPU" - "* -{ - cc_status.flags = CC_IN_FPU; - return \"cmpd %0, %1\;cfcc\"; -}" - [(set_attr "length" "2,3,6")]) - -;; a bit of brain damage, maybe inline later - -;; problem is - gcc seems to NEED SImode because -;; of the cmp weirdness - maybe change gcc to handle this? - -(define_expand "cmpsi" - [(set (reg:SI 0) - (match_operand:SI 0 "general_operand" "g")) - (set (reg:SI 2) - (match_operand:SI 1 "general_operand" "g")) - (parallel [(set (cc0) - (compare (reg:SI 0) - (reg:SI 2))) - (clobber (reg:SI 0))])] - "0" ;; disable for test - "") - -;; check for next insn for branch code - does this still -;; work in gcc 2.* ? - -(define_insn "" - [(set (cc0) - (compare (reg:SI 0) - (reg:SI 2))) - (clobber (reg:SI 0))] - "" - "* -{ - rtx br_insn = NEXT_INSN (insn); - RTX_CODE br_code; - - if (GET_CODE (br_insn) != JUMP_INSN) - abort(); - br_code = GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0)); - - switch(br_code) - { - case GEU: - case LTU: - case GTU: - case LEU: - - return \"jsr pc, ___ucmpsi\;cmp $1,r0\"; - - case GE: - case LT: - case GT: - case LE: - case EQ: - case NE: - - return \"jsr pc, ___cmpsi\;tst r0\"; - - default: - - abort(); - } -}" - [(set_attr "length" "4")]) - - -(define_insn "cmphi" - [(set (cc0) - (compare (match_operand:HI 0 "general_operand" "rR,rR,Qi,Qi") - (match_operand:HI 1 "general_operand" "rR,Qi,rR,Qi")))] - "" - "cmp %0,%1" - [(set_attr "length" "1,2,2,3")]) - -(define_insn "cmpqi" - [(set (cc0) - (compare (match_operand:QI 0 "general_operand" "rR,rR,Qi,Qi") - (match_operand:QI 1 "general_operand" "rR,Qi,rR,Qi")))] - "" - "cmpb %0,%1" - [(set_attr "length" "1,2,2,3")]) - - -;; We have to have this because cse can optimize the previous pattern -;; into this one. - -(define_insn "tstdf" - [(set (cc0) - (match_operand:DF 0 "general_operand" "fR,Q"))] - "TARGET_FPU" - "* -{ - cc_status.flags = CC_IN_FPU; - return \"tstd %0\;cfcc\"; -}" - [(set_attr "length" "2,3")]) - - -(define_expand "tstsi" - [(set (reg:SI 0) - (match_operand:SI 0 "general_operand" "g")) - (parallel [(set (cc0) - (reg:SI 0)) - (clobber (reg:SI 0))])] - "0" ;; disable for test - "") - -(define_insn "" - [(set (cc0) - (reg:SI 0)) - (clobber (reg:SI 0))] - "" - "jsr pc, ___tstsi\;tst r0" - [(set_attr "length" "3")]) - - -(define_insn "tsthi" - [(set (cc0) - (match_operand:HI 0 "general_operand" "rR,Q"))] - "" - "tst %0" - [(set_attr "length" "1,2")]) - -(define_insn "tstqi" - [(set (cc0) - (match_operand:QI 0 "general_operand" "rR,Q"))] - "" - "tstb %0" - [(set_attr "length" "1,2")]) - -;; sob instruction - we need an assembler which can make this instruction -;; valid under _all_ circumstances! - -(define_insn "" - [(set (pc) - (if_then_else - (ne (plus:HI (match_operand:HI 0 "register_operand" "r") - (const_int -1)) - (const_int 0)) - (label_ref (match_operand 1 "" "")) - (pc))) - (set (match_dup 0) - (plus:HI (match_dup 0) - (const_int -1)))] - "TARGET_40_PLUS" - "* -{ - static int labelcount = 0; - static char buf[1000]; - - if (get_attr_length (insn) == 1) - return \"sob %0, %l1\"; - - /* emulate sob */ - output_asm_insn (\"dec %0\", operands); - - sprintf (buf, \"bge LONG_SOB%d\", labelcount); - output_asm_insn (buf, NULL); - - output_asm_insn (\"jmp %l1\", operands); - - sprintf (buf, \"LONG_SOB%d:\", labelcount++); - output_asm_insn (buf, NULL); - - return \"\"; -}" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -256)) - (ge (minus (match_dup 0) - (pc)) - (const_int 0))) - (const_int 4) - (const_int 1)))]) - -;; These control RTL generation for conditional jump insns -;; and match them for register allocation. - -;; problem with too short jump distance! we need an assembler which can -;; make this valid for all jump distances! -;; e.g. gas! - -;; these must be changed to check for CC_IN_FCCR if float is to be -;; enabled - -(define_insn "beq" - [(set (pc) - (if_then_else (eq (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* return output_jump(\"beq\", \"bne\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - - -(define_insn "bne" - [(set (pc) - (if_then_else (ne (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* return output_jump(\"bne\", \"beq\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "bgt" - [(set (pc) - (if_then_else (gt (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* return output_jump(\"bgt\", \"ble\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "bgtu" - [(set (pc) - (if_then_else (gtu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* return output_jump(\"bhi\", \"blos\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "blt" - [(set (pc) - (if_then_else (lt (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* return output_jump(\"blt\", \"bge\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - - -(define_insn "bltu" - [(set (pc) - (if_then_else (ltu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* return output_jump(\"blo\", \"bhis\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "bge" - [(set (pc) - (if_then_else (ge (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* return output_jump(\"bge\", \"blt\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "bgeu" - [(set (pc) - (if_then_else (geu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* return output_jump(\"bhis\", \"blo\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "ble" - [(set (pc) - (if_then_else (le (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* return output_jump(\"ble\", \"bgt\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "bleu" - [(set (pc) - (if_then_else (leu (cc0) - (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* return output_jump(\"blos\", \"bhi\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - - -;; These match inverted jump insns for register allocation. - -(define_insn "" - [(set (pc) - (if_then_else (eq (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* return output_jump(\"bne\", \"beq\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "" - [(set (pc) - (if_then_else (ne (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* return output_jump(\"beq\", \"bne\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "" - [(set (pc) - (if_then_else (gt (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* return output_jump(\"ble\", \"bgt\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "" - [(set (pc) - (if_then_else (gtu (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* return output_jump(\"blos\", \"bhi\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "" - [(set (pc) - (if_then_else (lt (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* return output_jump(\"bge\", \"blt\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "" - [(set (pc) - (if_then_else (ltu (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* return output_jump(\"bhis\", \"blo\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "" - [(set (pc) - (if_then_else (ge (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* return output_jump(\"blt\", \"bge\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "" - [(set (pc) - (if_then_else (geu (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* return output_jump(\"blo\", \"bhis\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "" - [(set (pc) - (if_then_else (le (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* return output_jump(\"bgt\", \"ble\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -(define_insn "" - [(set (pc) - (if_then_else (leu (cc0) - (const_int 0)) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* return output_jump(\"bhi\", \"blos\", get_attr_length(insn));" - [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0) - (pc)) - (const_int -128)) - (ge (minus (match_dup 0) - (pc)) - (const_int 128))) - (const_int 3) - (const_int 1)))]) - -;; Move instructions - -(define_insn "movdi" - [(set (match_operand:DI 0 "general_operand" "=g") - (match_operand:DI 1 "general_operand" "g"))] - "" - "* return output_move_quad (operands);" -;; what's the mose expensive code - say twice movsi = 16 - [(set_attr "length" "16")]) - -(define_insn "movsi" - [(set (match_operand:SI 0 "general_operand" "=r,r,r,rm,m") - (match_operand:SI 1 "general_operand" "rN,IJ,K,m,r"))] - "" - "* return output_move_double (operands);" -;; what's the most expensive code ? - I think 8! -;; we could split it up and make several sub-cases... - [(set_attr "length" "2,3,4,8,8")]) - -(define_insn "movhi" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") - (match_operand:HI 1 "general_operand" "rRN,Qi,rRN,Qi"))] - "" - "* -{ - if (operands[1] == const0_rtx) - return \"clr %0\"; - - return \"mov %1, %0\"; -}" - [(set_attr "length" "1,2,2,3")]) - -(define_insn "movqi" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") - (match_operand:QI 1 "general_operand" "rRN,Qi,rRN,Qi"))] - "" - "* -{ - if (operands[1] == const0_rtx) - return \"clrb %0\"; - - return \"movb %1, %0\"; -}" - [(set_attr "length" "1,2,2,3")]) - -;; do we have to supply all these moves? e.g. to -;; NO_LOAD_FPU_REGs ? -(define_insn "movdf" - [(set (match_operand:DF 0 "general_operand" "=f,R,f,Q,f,m") - (match_operand:DF 1 "general_operand" "fR,f,Q,f,F,m"))] - "" - "* return output_move_quad (operands);" -;; just a guess.. - [(set_attr "length" "1,1,2,2,5,16")]) - -(define_insn "movsf" - [(set (match_operand:SF 0 "general_operand" "=g,r,g") - (match_operand:SF 1 "general_operand" "r,rmF,g"))] - "TARGET_FPU" - "* return output_move_double (operands);" - [(set_attr "length" "8,8,8")]) - -;; maybe fiddle a bit with move_ratio, then -;; let constraints only accept a register ... - -(define_expand "movstrhi" - [(parallel [(set (match_operand:BLK 0 "general_operand" "=g,g") - (match_operand:BLK 1 "general_operand" "g,g")) - (use (match_operand:HI 2 "arith_operand" "n,&mr")) - (use (match_operand:HI 3 "immediate_operand" "i,i")) - (clobber (match_scratch:HI 4 "=&r,X")) - (clobber (match_dup 5)) - (clobber (match_dup 6)) - (clobber (match_dup 2))])] - "(TARGET_BCOPY_BUILTIN)" - " -{ - operands[0] - = change_address (operands[0], VOIDmode, - copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); - operands[1] - = change_address (operands[1], VOIDmode, - copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); - - operands[5] = XEXP (operands[0], 0); - operands[6] = XEXP (operands[1], 0); -}") - - -(define_insn "" ; "movstrhi" - [(set (mem:BLK (match_operand:HI 0 "general_operand" "=r,r")) - (mem:BLK (match_operand:HI 1 "general_operand" "r,r"))) - (use (match_operand:HI 2 "arith_operand" "n,&r")) - (use (match_operand:HI 3 "immediate_operand" "i,i")) - (clobber (match_scratch:HI 4 "=&r,X")) - (clobber (match_dup 0)) - (clobber (match_dup 1)) - (clobber (match_dup 2))] - "(TARGET_BCOPY_BUILTIN)" - "* return output_block_move (operands);" -;;; just a guess - [(set_attr "length" "40")]) - - - -;;- truncation instructions - -(define_insn "truncdfsf2" - [(set (match_operand:SF 0 "general_operand" "=r,R,Q") - (float_truncate:SF (match_operand:DF 1 "register_operand" "a,a,a")))] - "TARGET_FPU" - "* if (which_alternative ==0) - { - output_asm_insn(\"stcdf %1, -(sp)\", operands); - output_asm_insn(\"mov (sp)+, %0\", operands); - operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1); - output_asm_insn(\"mov (sp)+, %0\", operands); - return \"\"; - } - else if (which_alternative == 1) - return \"stcdf %1, %0\"; - else - return \"stcdf %1, %0\"; - " - [(set_attr "length" "3,1,2")]) - - -(define_expand "truncsihi2" - [(set (match_operand:HI 0 "general_operand" "=g") - (subreg:HI - (match_operand:SI 1 "general_operand" "or") - 0))] - "" - "") - - -;;- zero extension instructions - -(define_insn "zero_extendqihi2" - [(set (match_operand:HI 0 "general_operand" "=r") - (zero_extend:HI (match_operand:QI 1 "general_operand" "0")))] - "" - "bic $(256*255), %0" - [(set_attr "length" "2")]) - -(define_expand "zero_extendhisi2" - [(set (subreg:HI - (match_dup 0) - 1) - (match_operand:HI 1 "register_operand" "r")) - (set (subreg:HI - (match_operand:SI 0 "register_operand" "=r") - 0) - (const_int 0))] - "" - "/* operands[1] = make_safe_from (operands[1], operands[0]); */") - - -;;- sign extension instructions - -(define_insn "extendsfdf2" - [(set (match_operand:DF 0 "register_operand" "=a,a,a") - (float_extend:DF (match_operand:SF 1 "general_operand" "r,R,Q")))] - "TARGET_FPU" - "@ - mov %1, -(sp)\;ldcfd (sp)+,%0 - ldcfd %1, %0 - ldcfd %1, %0" - [(set_attr "length" "2,1,2")]) - -;; does movb sign extend in register-to-register move? -(define_insn "extendqihi2" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (sign_extend:HI (match_operand:QI 1 "general_operand" "rR,Q")))] - "" - "movb %1, %0" - [(set_attr "length" "1,2")]) - -(define_insn "extendqisi2" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (sign_extend:SI (match_operand:QI 1 "general_operand" "rR,Q")))] - "TARGET_40_PLUS" - "* -{ - rtx latehalf[2]; - - /* make register pair available */ - latehalf[0] = operands[0]; - operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1); - - output_asm_insn(\"movb %1, %0\", operands); - output_asm_insn(\"sxt %0\", latehalf); - - return \"\"; -}" - [(set_attr "length" "2,3")]) - -;; maybe we have to use define_expand to say that we have the instruction, -;; unconditionally, and then match dependent on CPU type: - -(define_expand "extendhisi2" - [(set (match_operand:SI 0 "general_operand" "=g") - (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))] - "" - "") - -(define_insn "" ; "extendhisi2" - [(set (match_operand:SI 0 "general_operand" "=o,<,r") - (sign_extend:SI (match_operand:HI 1 "general_operand" "g,g,g")))] - "TARGET_40_PLUS" - "* -{ - rtx latehalf[2]; - - /* we don't want to mess with auto increment */ - - switch(which_alternative) - { - case 0: - - latehalf[0] = operands[0]; - operands[0] = adj_offsettable_operand(operands[0], 2); - - output_asm_insn(\"mov %1, %0\", operands); - output_asm_insn(\"sxt %0\", latehalf); - - return \"\"; - - case 1: - - /* - auto-decrement - right direction ;-) */ - output_asm_insn(\"mov %1, %0\", operands); - output_asm_insn(\"sxt %0\", operands); - - return \"\"; - - case 2: - - /* make register pair available */ - latehalf[0] = operands[0]; - operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1); - - output_asm_insn(\"mov %1, %0\", operands); - output_asm_insn(\"sxt %0\", latehalf); - - return \"\"; - - default: - - abort(); - } -}" - [(set_attr "length" "5,3,3")]) - - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extend:SI (match_operand:HI 1 "general_operand" "0")))] - "(! TARGET_40_PLUS)" - "* -{ - static count = 0; - char buf[100]; - rtx lateoperands[2]; - - lateoperands[0] = operands[0]; - operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1); - - output_asm_insn(\"tst %0\", operands); - sprintf(buf, \"bge extendhisi%d\", count); - output_asm_insn(buf, NULL); - output_asm_insn(\"mov -1, %0\", lateoperands); - sprintf(buf, \"bne extendhisi%d\", count+1); - output_asm_insn(buf, NULL); - sprintf(buf, \"\\nextendhisi%d:\", count); - output_asm_insn(buf, NULL); - output_asm_insn(\"clr %0\", lateoperands); - sprintf(buf, \"\\nextendhisi%d:\", count+1); - output_asm_insn(buf, NULL); - - count += 2; - - return \"\"; -}" - [(set_attr "length" "6")]) - -;; make float to int and vice versa -;; using the cc_status.flag field we could probably cut down -;; on seti and setl -;; assume that we are normally in double and integer mode - -;; what do pdp library routines do to fpu mode ? - -(define_insn "floatsidf2" - [(set (match_operand:DF 0 "register_operand" "=a,a,a") - (float:DF (match_operand:SI 1 "general_operand" "r,R,Q")))] - "TARGET_FPU" - "* if (which_alternative ==0) - { - rtx latehalf[2]; - - latehalf[0] = NULL; - latehalf[1] = gen_rtx(REG, HImode, REGNO (operands[0])+1); - output_asm_insn(\"mov %1, -(sp)\", latehalf); - output_asm_insn(\"mov %1, -(sp)\", operands); - - output_asm_insn(\"setl\", operands); - output_asm_insn(\"ldcld (sp)+, %0\", operands); - output_asm_insn(\"seti\", operands); - return \"\"; - } - else if (which_alternative == 1) - return \"setl\;ldcld %1, %0\;seti\"; - else - return \"setl\;ldcld %1, %0\;seti\"; - " - [(set_attr "length" "5,3,4")]) - -(define_insn "floathidf2" - [(set (match_operand:DF 0 "register_operand" "=a,a") - (float:DF (match_operand:HI 1 "general_operand" "rR,Qi")))] - "TARGET_FPU" - "ldcid %1, %0" - [(set_attr "length" "1,2")]) - -;; cut float to int -(define_insn "fix_truncdfsi2" - [(set (match_operand:SI 0 "general_operand" "=r,R,Q") - (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a,a,a"))))] - "TARGET_FPU" - "* if (which_alternative ==0) - { - output_asm_insn(\"setl\", operands); - output_asm_insn(\"stcdl %1, -(sp)\", operands); - output_asm_insn(\"seti\", operands); - output_asm_insn(\"mov (sp)+, %0\", operands); - operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1); - output_asm_insn(\"mov (sp)+, %0\", operands); - return \"\"; - } - else if (which_alternative == 1) - return \"setl\;stcdl %1, %0\;seti\"; - else - return \"setl\;stcdl %1, %0\;seti\"; - " - [(set_attr "length" "5,3,4")]) - -(define_insn "fix_truncdfhi2" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") - (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "a,a"))))] - "TARGET_FPU" - "stcdi %1, %0" - [(set_attr "length" "1,2")]) - - -;;- arithmetic instructions -;;- add instructions - -(define_insn "adddf3" - [(set (match_operand:DF 0 "register_operand" "=a,a,a") - (plus:DF (match_operand:DF 1 "register_operand" "%0,0,0") - (match_operand:DF 2 "general_operand" "fR,Q,F")))] - "TARGET_FPU" - "addd %2, %0" - [(set_attr "length" "1,2,5")]) - -(define_insn "addsi3" - [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o") - (plus:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0") - (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))] - "" - "* -{ /* Here we trust that operands don't overlap - - or is lateoperands the low word?? - looks like it! */ - - unsigned int i; - rtx lateoperands[3]; - - lateoperands[0] = operands[0]; - - if (REG_P (operands[0])) - operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1); - else - operands[0] = adj_offsettable_operand (operands[0], 2); - - if (! CONSTANT_P(operands[2])) - { - lateoperands[2] = operands[2]; - - if (REG_P (operands[2])) - operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1); - else - operands[2] = adj_offsettable_operand(operands[2], 2); - - output_asm_insn (\"add %2, %0\", operands); - output_asm_insn (\"adc %0\", lateoperands); - output_asm_insn (\"add %2, %0\", lateoperands); - return \"\"; - } - - lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff); - operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff); - - if (INTVAL(operands[2])) - { - output_asm_insn (\"add %2, %0\", operands); - output_asm_insn (\"adc %0\", lateoperands); - } - - if (INTVAL(lateoperands[2])) - output_asm_insn (\"add %2, %0\", lateoperands); - - return \"\"; -}" - [(set_attr "length" "3,5,6,8,3,1,5,5,3,8")]) - -(define_insn "addhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") - (plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0") - (match_operand:HI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))] - "" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT) - if (INTVAL(operands[2]) == 1) - return \"inc %0\"; - else if (INTVAL(operands[2]) == -1) - return \"dec %0\"; - - return \"add %2, %0\"; -}" - [(set_attr "length" "1,2,2,3")]) - -(define_insn "addqi3" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") - (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0") - (match_operand:QI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))] - "" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT) - if (INTVAL(operands[2]) == 1) - return \"incb %0\"; - else if (INTVAL(operands[2]) == -1) - return \"decb %0\"; - - return \"addb %2, %0\"; -}" - [(set_attr "length" "1,2,2,3")]) - - -;;- subtract instructions -;; we don't have to care for constant second -;; args, since they are canonical plus:xx now! -;; also for minus:DF ?? - -(define_insn "subdf3" - [(set (match_operand:DF 0 "register_operand" "=a,a") - (minus:DF (match_operand:DF 1 "register_operand" "0,0") - (match_operand:DF 2 "general_operand" "fR,Q")))] - "TARGET_FPU" - "subd %2, %0" - [(set_attr "length" "1,2")]) - -(define_insn "subsi3" - [(set (match_operand:SI 0 "general_operand" "=r,r,o,o") - (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0") - (match_operand:SI 2 "general_operand" "r,o,r,o")))] - "" - "* -{ /* Here we trust that operands don't overlap - - or is lateoperands the low word?? - looks like it! */ - - unsigned int i; - rtx lateoperands[3]; - - lateoperands[0] = operands[0]; - - if (REG_P (operands[0])) - operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1); - else - operands[0] = adj_offsettable_operand (operands[0], 2); - - lateoperands[2] = operands[2]; - - if (REG_P (operands[2])) - operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1); - else - operands[2] = adj_offsettable_operand(operands[2], 2); - - output_asm_insn (\"sub %2, %0\", operands); - output_asm_insn (\"sbc %0\", lateoperands); - output_asm_insn (\"sub %2, %0\", lateoperands); - return \"\"; -}" -;; offsettable memory addresses always are expensive!!! - [(set_attr "length" "3,5,6,8")]) - -(define_insn "subhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") - (minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0") - (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))] - "" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT) - abort(); - - return \"sub %2, %0\"; -}" - [(set_attr "length" "1,2,2,3")]) - -(define_insn "subqi3" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") - (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0") - (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))] - "" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT) - abort(); - - return \"subb %2, %0\"; -}" - [(set_attr "length" "1,2,2,3")]) - -;;;;- and instructions -;; Bit-and on the pdp (like on the vax) is done with a clear-bits insn. -(define_expand "andsi3" - [(set (match_operand:SI 0 "general_operand" "=g") - (and:SI (match_operand:SI 1 "general_operand" "0") - (not:SI (match_operand:SI 2 "general_operand" "g"))))] - "" - " -{ - extern rtx expand_unop (); - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (~INTVAL (operands[2])); - else - operands[2] = expand_unop (SImode, one_cmpl_optab, operands[2], 0, 1); -}") - -(define_expand "andhi3" - [(set (match_operand:HI 0 "general_operand" "=g") - (and:HI (match_operand:HI 1 "general_operand" "0") - (not:HI (match_operand:HI 2 "general_operand" "g"))))] - "" - " -{ - extern rtx expand_unop (); - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (~INTVAL (operands[2])); - else - operands[2] = expand_unop (HImode, one_cmpl_optab, operands[2], 0, 1); -}") - -(define_expand "andqi3" - [(set (match_operand:QI 0 "general_operand" "=g") - (and:QI (match_operand:QI 1 "general_operand" "0") - (not:QI (match_operand:QI 2 "general_operand" "g"))))] - "" - " -{ - extern rtx expand_unop (); - rtx op = operands[2]; - if (GET_CODE (op) == CONST_INT) - operands[2] = GEN_INT (((1 << 8) - 1) & ~INTVAL (op)); - else - operands[2] = expand_unop (QImode, one_cmpl_optab, op, 0, 1); -}") - -(define_insn "andcbsi3" - [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o") - (and:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0") - (not:SI (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K"))))] - "" - "* -{ /* Here we trust that operands don't overlap - - or is lateoperands the low word?? - looks like it! */ - - unsigned int i; - rtx lateoperands[3]; - - lateoperands[0] = operands[0]; - - if (REG_P (operands[0])) - operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1); - else - operands[0] = adj_offsettable_operand (operands[0], 2); - - if (! CONSTANT_P(operands[2])) - { - lateoperands[2] = operands[2]; - - if (REG_P (operands[2])) - operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1); - else - operands[2] = adj_offsettable_operand(operands[2], 2); - - output_asm_insn (\"bic %2, %0\", operands); - output_asm_insn (\"bic %2, %0\", lateoperands); - return \"\"; - } - - lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff); - operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff); - - /* these have different lengths, so we should have - different constraints! */ - if (INTVAL(operands[2])) - output_asm_insn (\"bic %2, %0\", operands); - - if (INTVAL(lateoperands[2])) - output_asm_insn (\"bic %2, %0\", lateoperands); - - return \"\"; -}" - [(set_attr "length" "2,4,4,6,2,2,4,3,3,6")]) - -(define_insn "andcbhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") - (and:HI (match_operand:HI 1 "general_operand" "0,0,0,0") - (not:HI (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi"))))] - "" - "bic %2, %0" - [(set_attr "length" "1,2,2,3")]) - -(define_insn "andcbqi3" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") - (and:QI (match_operand:QI 1 "general_operand" "0,0,0,0") - (not:QI (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi"))))] - "" - "bicb %2, %0" - [(set_attr "length" "1,2,2,3")]) - -;;- Bit set (inclusive or) instructions -(define_insn "iorsi3" - [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o") - (ior:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0") - (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))] - "" - "* -{ /* Here we trust that operands don't overlap - - or is lateoperands the low word?? - looks like it! */ - - unsigned int i; - rtx lateoperands[3]; - - lateoperands[0] = operands[0]; - - if (REG_P (operands[0])) - operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1); - else - operands[0] = adj_offsettable_operand (operands[0], 2); - - if (! CONSTANT_P(operands[2])) - { - lateoperands[2] = operands[2]; - - if (REG_P (operands[2])) - operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1); - else - operands[2] = adj_offsettable_operand(operands[2], 2); - - output_asm_insn (\"bis %2, %0\", operands); - output_asm_insn (\"bis %2, %0\", lateoperands); - return \"\"; - } - - lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff); - operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff); - - /* these have different lengths, so we should have - different constraints! */ - if (INTVAL(operands[2])) - output_asm_insn (\"bis %2, %0\", operands); - - if (INTVAL(lateoperands[2])) - output_asm_insn (\"bis %2, %0\", lateoperands); - - return \"\"; -}" - [(set_attr "length" "2,4,4,6,2,2,4,3,3,6")]) - -(define_insn "iorhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q") - (ior:HI (match_operand:HI 1 "general_operand" "%0,0,0,0") - (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))] - "" - "bis %2, %0" - [(set_attr "length" "1,2,2,3")]) - -(define_insn "iorqi3" - [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q") - (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0") - (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))] - "" - "bisb %2, %0") - -;;- xor instructions -(define_insn "xorsi3" - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") - (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0") - (match_operand:SI 2 "arith_operand" "r,I,J,K")))] - "TARGET_40_PLUS" - "* -{ /* Here we trust that operands don't overlap */ - - unsigned int i; - rtx lateoperands[3]; - - lateoperands[0] = operands[0]; - operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1); - - if (REG_P(operands[2])) - { - lateoperands[2] = operands[2]; - operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1); - - output_asm_insn (\"xor %2, %0\", operands); - output_asm_insn (\"xor %2, %0\", lateoperands); - - return \"\"; - } - - lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff); - operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff); - - if (INTVAL(operands[2])) - output_asm_insn (\"xor %2, %0\", operands); - - if (INTVAL(lateoperands[2])) - output_asm_insn (\"xor %2, %0\", lateoperands); - - return \"\"; -}" - [(set_attr "length" "2,1,1,2")]) - -(define_insn "xorhi3" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") - (xor:HI (match_operand:HI 1 "general_operand" "%0,0") - (match_operand:HI 2 "register_operand" "r,r")))] - "TARGET_40_PLUS" - "xor %2, %0" - [(set_attr "length" "1,2")]) - -;;- one complement instructions - -(define_insn "one_cmplhi2" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") - (not:HI (match_operand:HI 1 "general_operand" "0,0")))] - "" - "com %0" - [(set_attr "length" "1,2")]) - -(define_insn "one_cmplqi2" - [(set (match_operand:QI 0 "general_operand" "=rR,Q") - (not:QI (match_operand:QI 1 "general_operand" "0,0")))] - "" - "comb %0" - [(set_attr "length" "1,2")]) - -;;- arithmetic shift instructions -(define_insn "ashlsi3" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (ashift:SI (match_operand:SI 1 "register_operand" "0,0") - (match_operand:HI 2 "general_operand" "rR,Qi")))] - "TARGET_45" - "ashc %2,%0" - [(set_attr "length" "1,2")]) - -;; Arithmetic right shift on the pdp works by negating the shift count. -(define_expand "ashrsi3" - [(set (match_operand:SI 0 "register_operand" "=r") - (ashift:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:HI 2 "general_operand" "g")))] - "" - " -{ - operands[2] = negate_rtx (HImode, operands[2]); -}") - -;; define asl aslb asr asrb - ashc missing! - -;; asl -(define_insn "" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") - (ashift:HI (match_operand:HI 1 "general_operand" "0,0") - (const_int 1)))] - "" - "asl %0" - [(set_attr "length" "1,2")]) - -;; and another possibility for asr is << -1 -;; might cause problems since -1 can also be encoded as 65535! -;; not in gcc2 ??? - -;; asr -(define_insn "" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") - (ashift:HI (match_operand:HI 1 "general_operand" "0,0") - (const_int -1)))] - "" - "asr %0" - [(set_attr "length" "1,2")]) - -;; shift is by arbitrary count is expensive, -;; shift by one cheap - so let's do that, if -;; space doesn't matter -(define_insn "" - [(set (match_operand:HI 0 "general_operand" "=r") - (ashift:HI (match_operand:HI 1 "general_operand" "0") - (match_operand:HI 2 "expand_shift_operand" "O")))] - "! optimize_size" - "* -{ - register int i; - - for (i = 1; i <= abs(INTVAL(operands[2])); i++) - if (INTVAL(operands[2]) < 0) - output_asm_insn(\"asr %0\", operands); - else - output_asm_insn(\"asl %0\", operands); - - return \"\"; -}" -;; longest is 4 - [(set (attr "length") (const_int 4))]) - -;; aslb -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=r,o") - (ashift:QI (match_operand:QI 1 "general_operand" "0,0") - (match_operand:HI 2 "const_immediate_operand" "n,n")))] - "" - "* -{ /* allowing predec or post_inc is possible, but hairy! */ - int i, cnt; - - cnt = INTVAL(operands[2]) & 0x0007; - - for (i=0 ; i < cnt ; i++) - output_asm_insn(\"aslb %0\", operands); - - return \"\"; -}" -;; set attribute length ( match_dup 2 & 7 ) *(1 or 2) !!! - [(set_attr_alternative "length" - [(const_int 7) - (const_int 14)])]) - -;;; asr -;(define_insn "" -; [(set (match_operand:HI 0 "general_operand" "=rR,Q") -; (ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0") -; (const_int 1)))] -; "" -; "asr %0" -; [(set_attr "length" "1,2")]) - -;; asrb -(define_insn "" - [(set (match_operand:QI 0 "general_operand" "=r,o") - (ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0") - (match_operand:HI 2 "const_immediate_operand" "n,n")))] - "" - "* -{ /* allowing predec or post_inc is possible, but hairy! */ - int i, cnt; - - cnt = INTVAL(operands[2]) & 0x0007; - - for (i=0 ; i < cnt ; i++) - output_asm_insn(\"asrb %0\", operands); - - return \"\"; -}" - [(set_attr_alternative "length" - [(const_int 7) - (const_int 14)])]) - -;; the following is invalid - too complex!!! - just say 14 !!! -; [(set (attr "length") (plus (and (match_dup 2) -; (const_int 7)) -; (and (match_dup 2) -; (const_int 7))))]) - - - -;; can we get +-1 in the next pattern? should -;; have been caught by previous patterns! - -(define_insn "ashlhi3" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (ashift:HI (match_operand:HI 1 "register_operand" "0,0") - (match_operand:HI 2 "general_operand" "rR,Qi")))] - "" - "* -{ - if (GET_CODE(operands[2]) == CONST_INT) - if (INTVAL(operands[2]) == 1) - return \"asl %0\"; - else if (INTVAL(operands[2]) == -1) - return \"asr %0\"; - - return \"ash %2,%0\"; -}" - [(set_attr "length" "1,2")]) - -;; Arithmetic right shift on the pdp works by negating the shift count. -(define_expand "ashrhi3" - [(set (match_operand:HI 0 "register_operand" "=r") - (ashift:HI (match_operand:HI 1 "register_operand" "0") - (match_operand:HI 2 "general_operand" "g")))] - "" - " -{ - operands[2] = negate_rtx (HImode, operands[2]); -}") - -;;;;- logical shift instructions -;;(define_insn "lshrsi3" -;; [(set (match_operand:HI 0 "register_operand" "=r") -;; (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") -;; (match_operand:HI 2 "arith_operand" "rI")))] -;; "" -;; "srl %0,%2") - -;; absolute - -(define_insn "absdf2" - [(set (match_operand:DF 0 "general_operand" "=fR,Q") - (abs:DF (match_operand:DF 1 "general_operand" "0,0")))] - "TARGET_FPU" - "absd %0" - [(set_attr "length" "1,2")]) - -(define_insn "abshi2" - [(set (match_operand:HI 0 "general_operand" "=r,o") - (abs:HI (match_operand:HI 1 "general_operand" "0,0")))] - "TARGET_ABSHI_BUILTIN" - "* -{ - static count = 0; - char buf[200]; - - output_asm_insn(\"tst %0\", operands); - sprintf(buf, \"bge abshi%d\", count); - output_asm_insn(buf, NULL); - output_asm_insn(\"neg %0\", operands); - sprintf(buf, \"\\nabshi%d:\", count++); - output_asm_insn(buf, NULL); - - return \"\"; -}" - [(set_attr "length" "3,5")]) - - -;; define expand abshi - is much better !!! - but -;; will it be optimized into an abshi2 ? -;; it will leave better code, because the tsthi might be -;; optimized away!! -; -- just a thought - don't have time to check -; -;(define_expand "abshi2" -; [(match_operand:HI 0 "general_operand" "") -; (match_operand:HI 1 "general_operand" "")] -; "" -; " -;{ -; rtx label = gen_label_rtx (); -; -; /* do I need this? */ -; do_pending_stack_adjust (); -; -; emit_move_insn (operands[0], operands[1]); -; -; emit_insn (gen_tsthi (operands[0])); -; emit_insn (gen_bge (label1)); -; -; emit_insn (gen_neghi(operands[0], operands[0]) -; -; emit_barrier (); -; -; emit_label (label); -; -; /* allow REG_NOTES to be set on last insn (labels don't have enough -; fields, and can't be used for REG_NOTES anyway). */ -; emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx)); -; DONE; -;}") - -;; negate insns - -(define_insn "negdf2" - [(set (match_operand:DF 0 "general_operand" "=fR,Q") - (neg:DF (match_operand:DF 1 "register_operand" "0,0")))] - "TARGET_FPU" - "negd %0" - [(set_attr "length" "1,2")]) - -(define_insn "neghi2" - [(set (match_operand:HI 0 "general_operand" "=rR,Q") - (neg:HI (match_operand:HI 1 "general_operand" "0,0")))] - "" - "neg %0" - [(set_attr "length" "1,2")]) - -(define_insn "negqi2" - [(set (match_operand:QI 0 "general_operand" "=rR,Q") - (neg:QI (match_operand:QI 1 "general_operand" "0,0")))] - "" - "negb %0" - [(set_attr "length" "1,2")]) - - -;; Unconditional and other jump instructions -(define_insn "jump" - [(set (pc) - (label_ref (match_operand 0 "" "")))] - "" - "jmp %l0" - [(set_attr "length" "2")]) - -(define_insn "" - [(set (pc) - (label_ref (match_operand 0 "" ""))) - (clobber (const_int 1))] - "" - "jmp %l0" - [(set_attr "length" "2")]) - -(define_insn "tablejump" - [(set (pc) (match_operand:HI 0 "general_operand" "rR,Q")) - (use (label_ref (match_operand 1 "" "")))] - "" - "jmp %0" - [(set_attr "length" "1,2")]) - -;; indirect jump - let's be conservative! -;; allow only register_operand, even though we could also -;; allow labels etc. - -(define_insn "indirect_jump" - [(set (pc) (match_operand:HI 0 "register_operand" "r"))] - "" - "jmp (%0)") - -;;- jump to subroutine - -(define_insn "call" - [(call (match_operand:HI 0 "general_operand" "R,Q") - (match_operand:HI 1 "general_operand" "g,g")) -;; (use (reg:HI 0)) what was that ??? - ] - ;;- Don't use operand 1 for most machines. - "" - "jsr pc, %0" - [(set_attr "length" "1,2")]) - -;;- jump to subroutine -(define_insn "call_value" - [(set (match_operand 0 "" "") - (call (match_operand:HI 1 "general_operand" "R,Q") - (match_operand:HI 2 "general_operand" "g,g"))) -;; (use (reg:HI 0)) - what was that ???? - ] - ;;- Don't use operand 2 for most machines. - "" - "jsr pc, %1" - [(set_attr "length" "1,2")]) - -;;- nop instruction -(define_insn "nop" - [(const_int 0)] - "" - "nop") - - -;;- multiply - -(define_insn "muldf3" - [(set (match_operand:DF 0 "register_operand" "=a,a,a") - (mult:DF (match_operand:DF 1 "register_operand" "%0,0,0") - (match_operand:DF 2 "general_operand" "fR,Q,F")))] - "TARGET_FPU" - "muld %2, %0" - [(set_attr "length" "1,2,5")]) - -;; 16 bit result multiply: -;; currently we multiply only into odd registers, so we don't use two -;; registers - but this is a bit inefficient at times. If we define -;; a register class for each register, then we can specify properly -;; which register need which scratch register .... - -(define_insn "mulhi3" - [(set (match_operand:HI 0 "register_operand" "=d,d") ; multiply regs - (mult:HI (match_operand:HI 1 "register_operand" "%0,0") - (match_operand:HI 2 "general_operand" "rR,Qi")))] - "TARGET_45" - "mul %2, %0" - [(set_attr "length" "1,2")]) - -;; 32 bit result -(define_expand "mulhisi3" - [(set (match_dup 3) - (match_operand:HI 1 "general_operand" "g,g")) - (set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered! - (mult:SI (truncate:HI - (match_dup 0)) - (match_operand:HI 2 "general_operand" "rR,Qi")))] - "TARGET_45" - "operands[3] = gen_lowpart(HImode, operands[1]);") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered! - (mult:SI (truncate:HI - (match_operand:SI 1 "register_operand" "%0,0")) - (match_operand:HI 2 "general_operand" "rR,Qi")))] - "TARGET_45" - "mul %2, %0" - [(set_attr "length" "1,2")]) - -;(define_insn "mulhisi3" -; [(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered! -; (mult:SI (truncate:HI -; (match_operand:SI 1 "register_operand" "%0,0")) -; (match_operand:HI 2 "general_operand" "rR,Qi")))] -; "TARGET_45" -; "mul %2, %0" -; [(set_attr "length" "1,2")]) - -;;- divide -(define_insn "divdf3" - [(set (match_operand:DF 0 "register_operand" "=a,a,a") - (div:DF (match_operand:DF 1 "register_operand" "0,0,0") - (match_operand:DF 2 "general_operand" "fR,Q,F")))] - "TARGET_FPU" - "divd %2, %0" - [(set_attr "length" "1,2,5")]) - - -(define_expand "divhi3" - [(set (subreg:HI (match_dup 1) 0) - (div:HI (match_operand:SI 1 "general_operand" "0") - (match_operand:HI 2 "general_operand" "g"))) - (set (match_operand:HI 0 "general_operand" "=r") - (subreg:HI (match_dup 1) 0))] - "TARGET_45" - "") - -(define_insn "" - [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0) - (div:HI (match_operand:SI 1 "general_operand" "0") - (match_operand:HI 2 "general_operand" "g")))] - "TARGET_45" - "div %2,%0" - [(set_attr "length" "2")]) - -(define_expand "modhi3" - [(set (subreg:HI (match_dup 1) 1) - (mod:HI (match_operand:SI 1 "general_operand" "0") - (match_operand:HI 2 "general_operand" "g"))) - (set (match_operand:HI 0 "general_operand" "=r") - (subreg:HI (match_dup 1) 1))] - "TARGET_45" - "") - -(define_insn "" - [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 1) - (mod:HI (match_operand:SI 1 "general_operand" "0") - (match_operand:HI 2 "general_operand" "g")))] - "TARGET_45" - "div %2,%0" - [(set_attr "length" "2")]) - -;(define_expand "divmodhi4" -; [(parallel [(set (subreg:HI (match_dup 1) 0) -; (div:HI (match_operand:SI 1 "general_operand" "0") -; (match_operand:HI 2 "general_operand" "g"))) -; (set (subreg:HI (match_dup 1) 1) -; (mod:HI (match_dup 1) -; (match_dup 2)))]) -; (set (match_operand:HI 3 "general_operand" "=r") -; (subreg:HI (match_dup 1) 1)) -; (set (match_operand:HI 0 "general_operand" "=r") -; (subreg:HI (match_dup 1) 0))] -; "TARGET_45" -; "") -; -;(define_insn "" -; [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0) -; (div:HI (match_operand:SI 1 "general_operand" "0") -; (match_operand:HI 2 "general_operand" "g"))) -; (set (subreg:HI (match_dup 0) 1) -; (mod:HI (match_dup 1) -; (match_dup 2)))] -; "TARGET_45" -; "div %2, %0") -; - -;; is rotate doing the right thing to be included here ???? diff --git a/gcc/config/pdp11/t-pdp11 b/gcc/config/pdp11/t-pdp11 deleted file mode 100755 index ebcdbb3..0000000 --- a/gcc/config/pdp11/t-pdp11 +++ /dev/null @@ -1,8 +0,0 @@ -LIBGCC1 = libgcc1.null -CROSS_LIBGCC1 = libgcc1.null - -# forget the libgcc1... -LIBGCC1_TEST = - -TARGET_LIBGCC2_CFLAGS = -O2 -mfloat32 -#LIB2FUNCS_EXTRA = diff --git a/gcc/config/pdp11/xm-pdp11.h b/gcc/config/pdp11/xm-pdp11.h deleted file mode 100755 index f6a5467..0000000 --- a/gcc/config/pdp11/xm-pdp11.h +++ /dev/null @@ -1,27 +0,0 @@ -/* Configuration for GNU C-compiler for pdp-11 family. - Copyright (C) 1994, 1995 Free Software Foundation, Inc. - Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -/* gcc can never run on a PDP, since it needs too much memory */ -/* but we need the xm-pdp.h file to compile libgcc2 */ - -/* target machine dependencies. - tm.h is a symbolic link to the actual target specific file. */ -#include "tm.h" |