From 469212f7ee42d04e3160d357ed1f088f12edd391 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Mon, 4 Jan 2021 13:40:33 -0600 Subject: CPU and GPU Reg Funcs Decomp (#16) * decomp/doc cpu funcs and gpu reg funcs * use Cpu32 macro funcs * address review comments * decomp SetBGOBJEnableFlags --- asm/code_800D090.s | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'asm/code_800D090.s') diff --git a/asm/code_800D090.s b/asm/code_800D090.s index a77aeab..3fd539a 100644 --- a/asm/code_800D090.s +++ b/asm/code_800D090.s @@ -7522,7 +7522,7 @@ sub_8010960: adds r1, r5 movs r2, 0 ldrsh r1, [r1, r2] - bl sub_800CCA0 + bl SetBG2RegOffsets ldr r1, [r6] adds r4, r1, r4 movs r2, 0 @@ -7530,7 +7530,7 @@ sub_8010960: adds r1, r5 movs r2, 0 ldrsh r1, [r1, r2] - bl sub_800CCAC + bl SetBG3RegOffsets movs r0, 0x1 bl sub_8010A88 bl sub_8010A00 @@ -9139,7 +9139,7 @@ sub_801169C: adds r1, r6 movs r3, 0 ldrsh r1, [r1, r3] - bl sub_800CCA0 + bl SetBG2RegOffsets ldr r1, [r5] adds r4, r1, r4 movs r2, 0 @@ -9147,7 +9147,7 @@ sub_801169C: adds r1, r6 movs r3, 0 ldrsh r1, [r1, r3] - bl sub_800CCAC + bl SetBG3RegOffsets bl sub_8010F28 bl sub_80111C4 lsls r0, 24 -- cgit v1.2.3