diff options
Diffstat (limited to 'arm9/asm/RUNTIME_s32_div_f.s')
| -rw-r--r-- | arm9/asm/RUNTIME_s32_div_f.s | 139 |
1 files changed, 139 insertions, 0 deletions
diff --git a/arm9/asm/RUNTIME_s32_div_f.s b/arm9/asm/RUNTIME_s32_div_f.s new file mode 100644 index 00000000..2dc6cc7e --- /dev/null +++ b/arm9/asm/RUNTIME_s32_div_f.s @@ -0,0 +1,139 @@ + .include "asm/macros.inc"
+ .include "global.inc"
+
+ .text
+
+ arm_func_start _s32_div_f
+_s32_div_f: ; 0x020EBC80
+ eor r12, r0, r1
+ and r12, r12, #0x80000000
+ cmp r0, #0x0
+ rsblt r0, r0, #0x0
+ addlt r12, r12, #0x1
+ cmp r1, #0x0
+ rsblt r1, r1, #0x0
+ beq _020EBE78
+ cmp r0, r1
+ movcc r1, r0
+ movcc r0, #0x0
+ blo _020EBE78
+ mov r2, #0x1c
+ mov r3, r0, lsr #0x4
+ cmp r1, r3, lsr #0xc
+ suble r2, r2, #0x10
+ movle r3, r3, lsr #0x10
+ cmp r1, r3, lsr #0x4
+ suble r2, r2, #0x8
+ movle r3, r3, lsr #0x8
+ cmp r1, r3
+ suble r2, r2, #0x4
+ movle r3, r3, lsr #0x4
+ mov r0, r0, lsl r2
+ rsb r1, r1, #0x0
+ adds r0, r0, r0
+ add r2, r2, r2, lsl #0x1
+ add pc, pc, r2, lsl #0x2
+ mov r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ adcs r3, r1, r3, lsl #0x1
+ subcc r3, r3, r1
+ adcs r0, r0, r0
+ mov r1, r3
+_020EBE78:
+ ands r3, r12, #0x80000000
+ rsbne r0, r0, #0x0
+ ands r3, r12, #0x1
+ rsbne r1, r1, #0x0
+ bx lr
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