diff options
Diffstat (limited to 'arm9/lib/include')
| -rw-r--r-- | arm9/lib/include/CARD_backup.h | 6 | ||||
| -rw-r--r-- | arm9/lib/include/CTRDG_common.h | 6 | ||||
| -rw-r--r-- | arm9/lib/include/FS_overlay.h | 28 | ||||
| -rw-r--r-- | arm9/lib/include/OS_interrupt.h | 3 | ||||
| -rw-r--r-- | arm9/lib/include/OS_printf.h | 7 | ||||
| -rw-r--r-- | arm9/lib/include/PAD_pad.h | 38 | ||||
| -rw-r--r-- | arm9/lib/include/SPI_pm.h | 38 | ||||
| -rw-r--r-- | arm9/lib/include/gx.h | 1 | ||||
| -rw-r--r-- | arm9/lib/include/registers.h | 511 |
9 files changed, 586 insertions, 52 deletions
diff --git a/arm9/lib/include/CARD_backup.h b/arm9/lib/include/CARD_backup.h new file mode 100644 index 00000000..de594beb --- /dev/null +++ b/arm9/lib/include/CARD_backup.h @@ -0,0 +1,6 @@ +#ifndef NITRO_CARD_BACKUP_H_ +#define NITRO_CARD_BACKUP_H_ + +BOOL CARD_TryWaitBackupAsync(void); + +#endif //NITRO_CARD_BACKUP_H_ diff --git a/arm9/lib/include/CTRDG_common.h b/arm9/lib/include/CTRDG_common.h new file mode 100644 index 00000000..c83602b8 --- /dev/null +++ b/arm9/lib/include/CTRDG_common.h @@ -0,0 +1,6 @@ +#ifndef NITRO_CTRDG_COMMON_H_ +#define NITRO_CTRDG_COMMON_H_ + +BOOL CTRDG_IsPulledOut(void); + +#endif //NITRO_CTRDG_COMMON_H_ diff --git a/arm9/lib/include/FS_overlay.h b/arm9/lib/include/FS_overlay.h index 6025d04a..14c7ce66 100644 --- a/arm9/lib/include/FS_overlay.h +++ b/arm9/lib/include/FS_overlay.h @@ -1,6 +1,10 @@ #ifndef NITRO_FS_OVERLAY_H_ #define NITRO_FS_OVERLAY_H_ +#if defined(__cplusplus) +extern "C" { +#endif + #include "nitro.h" #include "MI_exMemory.h" #include "FS_file.h" @@ -8,7 +12,10 @@ typedef u32 FSOverlayID; -typedef void (*FSOverlayInitFunc) (void); +#define FS_EXTERN_OVERLAY(name) extern u32 SDK_OVERLAY_ ## name ## _ID[1] +#define FS_OVERLAY_ID(name) ((u32)&(SDK_OVERLAY_ ## name ## _ID)) + +typedef void (*FSOverlayInitFunc)(void); typedef struct FSOverlayInfoHeader { @@ -19,8 +26,8 @@ typedef struct FSOverlayInfoHeader FSOverlayInitFunc *sinit_init; FSOverlayInitFunc *sinit_init_end; u32 file_id; - u32 compressed:24; - u32 flag:8; + u32 compressed: 24; + u32 flag: 8; } FSOverlayInfoHeader; typedef struct FSOverlayInfo @@ -30,26 +37,35 @@ typedef struct FSOverlayInfo CARDRomRegion file_pos; } FSOverlayInfo; -static inline u8 *const FS_GetOverlayAddress(FSOverlayInfo * p_ovi) +static inline u8 *const FS_GetOverlayAddress(FSOverlayInfo *p_ovi) { return p_ovi->header.ram_address; } -static inline u32 const FS_GetOverlayImageSize(FSOverlayInfo * p_ovi) +static inline u32 const FS_GetOverlayImageSize(FSOverlayInfo *p_ovi) { return p_ovi->header.ram_size; } -static inline u32 const FS_GetOverlayTotalSize(FSOverlayInfo * p_ovi) +static inline u32 const FS_GetOverlayTotalSize(FSOverlayInfo *p_ovi) { return p_ovi->header.ram_size + p_ovi->header.bss_size; } BOOL FS_LoadOverlayInfo(FSOverlayInfo *p_ovi, MIProcessor target, FSOverlayID id); + BOOL FS_LoadOverlay(MIProcessor target, FSOverlayID id); + BOOL FS_UnloadOverlay(MIProcessor target, FSOverlayID id); + BOOL FS_LoadOverlayImage(FSOverlayInfo *p_ovi); + void FS_StartOverlay(FSOverlayInfo *p_ovi); + BOOL FS_LoadOverlayImageAsync(FSOverlayInfo *p_ovi, FSFile *p_file); +#if defined(__cplusplus) +}; +#endif + #endif //NITRO_FS_OVERLAY_H_ diff --git a/arm9/lib/include/OS_interrupt.h b/arm9/lib/include/OS_interrupt.h index b8425b4e..21ce2ea0 100644 --- a/arm9/lib/include/OS_interrupt.h +++ b/arm9/lib/include/OS_interrupt.h @@ -19,11 +19,12 @@ typedef struct typedef u32 OSIrqMask; extern OSIrqFunction OS_IRQTable[]; -extern OSIrqCallbackInfo OSi_IrqCallbackInfo[7+1]; +extern OSIrqCallbackInfo OSi_IrqCallbackInfo[8]; void OS_InitIrqTable(); void OS_SetIrqFunction(OSIrqMask intrBit, OSIrqFunction function); OSIrqFunction OS_GetIrqFunction(OSIrqMask intrBit); void OSi_EnterDmaCallback(u32 dmaNo, void (*callback) (void *), void *arg); +void OSi_EnterTimerCallback(u32 timerNo, void (*callback) (void *), void *arg); #endif //POKEDIAMOND_OS_INTERRUPT_H diff --git a/arm9/lib/include/OS_printf.h b/arm9/lib/include/OS_printf.h index 7c02252b..7c2e09b4 100644 --- a/arm9/lib/include/OS_printf.h +++ b/arm9/lib/include/OS_printf.h @@ -5,4 +5,11 @@ #define OS_TPanic(...) OS_Terminate() #define OS_TWarning(...) ((void)0) +#include "types.h" + +s32 OS_SPrintf(s8 *buffer, const s8 *format, ...); +s32 OS_VSPrintf(s8 *buffer, const s8 *format, void *args); +s32 OS_SNPrintf(s8 *buffer, s32 bufsz, const s8 *format, ...); +s32 OS_VSNPrintf(s8 *buffer, s32 bufsz, const s8 *format, void *args); + #endif //NITRO_OS_PRINTF_H_ diff --git a/arm9/lib/include/PAD_pad.h b/arm9/lib/include/PAD_pad.h new file mode 100644 index 00000000..0cb8a6f0 --- /dev/null +++ b/arm9/lib/include/PAD_pad.h @@ -0,0 +1,38 @@ +#ifndef NITRO_PAD_PAD_H_ +#define NITRO_PAD_PAD_H_ + + +//================================================================================ +// BUTTONS + +//---- masked value +#define PAD_PLUS_KEY_MASK 0x00f0 // mask : cross keys +#define PAD_BUTTON_MASK 0x2f0f // mask : buttons +#define PAD_DEBUG_BUTTON_MASK 0x2000 // mask : debug button +#define PAD_ALL_MASK 0x2fff // mask : all buttons +#define PAD_RCNTPORT_MASK 0x2c00 // mask : factors ARM7 can read from RCNT register +#define PAD_KEYPORT_MASK 0x03ff // mask : factors ARM7/9 can read from KEY register + +#define PAD_DETECT_FOLD_MASK 0x8000 // mask : folding + +//---- button and key +#define PAD_BUTTON_A 0x0001 // A +#define PAD_BUTTON_B 0x0002 // B +#define PAD_BUTTON_SELECT 0x0004 // SELECT +#define PAD_BUTTON_START 0x0008 // START +#define PAD_KEY_RIGHT 0x0010 // RIGHT of cross key +#define PAD_KEY_LEFT 0x0020 // LEFT of cross key +#define PAD_KEY_UP 0x0040 // UP of cross key +#define PAD_KEY_DOWN 0x0080 // DOWN of cross key +#define PAD_BUTTON_R 0x0100 // R +#define PAD_BUTTON_L 0x0200 // L +#define PAD_BUTTON_X 0x0400 // X +#define PAD_BUTTON_Y 0x0800 // Y +#define PAD_BUTTON_DEBUG 0x2000 // Debug button + +static inline BOOL PAD_DetectFold(void) +{ + return (BOOL)((*(vu16 *)HW_BUTTON_XY_BUF & PAD_DETECT_FOLD_MASK) >> 15); +} + +#endif //NITRO_PAD_PAD_H_ diff --git a/arm9/lib/include/SPI_pm.h b/arm9/lib/include/SPI_pm.h new file mode 100644 index 00000000..b5063ed8 --- /dev/null +++ b/arm9/lib/include/SPI_pm.h @@ -0,0 +1,38 @@ +#ifndef NITRO_SPI_PM_H_ +#define NITRO_SPI_PM_H_ + +ENUMS_ALWAYS_INT_ON + +#define PM_TRIGGER_KEY (1 << 0) +#define PM_TRIGGER_RTC_ALARM (1 << 1) +#define PM_TRIGGER_COVER_OPEN (1 << 2) +#define PM_TRIGGER_CARD (1 << 3) +#define PM_TRIGGER_CARTRIDGE (1 << 4) +typedef u32 PMWakeUpTrigger; + +#define PM_PAD_LOGIC_OR (0 << REG_PAD_KEYCNT_LOGIC_SHIFT) +#define PM_PAD_LOGIC_AND (1 << REG_PAD_KEYCNT_LOGIC_SHIFT) +typedef u32 PMLogic; + +typedef enum +{ + PM_BACKLIGHT_OFF = 0, + PM_BACKLIGHT_ON = 1 +} PMBackLightSwitch; + +typedef enum +{ + PM_LCD_TOP = 0, + PM_LCD_BOTTOM = 1, + PM_LCD_ALL = 2 +} +PMLCDTarget; + +void PM_GetBackLight(PMBackLightSwitch * top, PMBackLightSwitch * bottom); +void PM_GoSleepMode(PMWakeUpTrigger trigger, PMLogic logic, u16 keyPattern); +u32 PM_SetBackLight(PMLCDTarget target, PMBackLightSwitch status); +void PM_ForceToPowerOff(void); + +ENUMS_ALWAYS_INT_RESET + +#endif //NITRO_SPI_PM_H_ diff --git a/arm9/lib/include/gx.h b/arm9/lib/include/gx.h index c4be4deb..5abc2693 100644 --- a/arm9/lib/include/gx.h +++ b/arm9/lib/include/gx.h @@ -22,7 +22,6 @@ void MIi_CpuClear32(u32, void *, u32); //Todos before PR //TODO: Add defines for GX commands, add structs/unions for HW registers -//TODO: Add ARM_FUNC attributes #define HW_REG_DIV_NUMER 0x04000290 #define HW_REG_DIV_DENOM 0x04000298 diff --git a/arm9/lib/include/registers.h b/arm9/lib/include/registers.h index 45b36334..598ba3f9 100644 --- a/arm9/lib/include/registers.h +++ b/arm9/lib/include/registers.h @@ -7,49 +7,472 @@ #include "types.h" -#define HW_REG_BASE 0x04000000 -#define REG_VCOUNT_OFFSET 0x006 -#define REG_VCOUNT_ADDR (HW_REG_BASE + REG_VCOUNT_OFFSET) -#define reg_GX_VCOUNT (*(REGType16v *)REG_VCOUNT_ADDR) - -#define REG_KEYINPUT_OFFSET 0x130 -#define REG_KEYINPUT_ADDR (HW_REG_BASE + REG_KEYINPUT_OFFSET) -#define reg_PAD_KEYINPUT (*(REGType16v *)REG_KEYINPUT_ADDR) - -#define REG_DIVCNT_OFFSET 0x280 -#define REG_DIVCNT_ADDR (HW_REG_BASE + REG_DIVCNT_OFFSET) -#define reg_CP_DIVCNT (*(REGType16v *)REG_DIVCNT_ADDR) - -#define REG_DIV_NUMER_OFFSET 0x290 -#define REG_DIV_NUMER_ADDR (HW_REG_BASE + REG_DIV_NUMER_OFFSET) -#define reg_CP_DIV_NUMER (*(REGType64v *)REG_DIV_NUMER_ADDR) - -#define REG_DIV_DENOM_OFFSET 0x298 -#define REG_DIV_DENOM_ADDR (HW_REG_BASE + REG_DIV_DENOM_OFFSET) -#define reg_CP_DIV_DENOM (*(REGType64v *)REG_DIV_DENOM_ADDR) - -#define REG_DIV_RESULT_OFFSET 0x2A0 -#define REG_DIV_RESULT_ADDR (HW_REG_BASE + REG_DIV_RESULT_OFFSET) -#define reg_CP_DIV_RESULT (*(REGType64v *)REG_DIV_RESULT_ADDR) - -#define REG_DIVREM_RESULT_OFFSET 0x2A8 -#define REG_DIVREM_RESULT_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_OFFSET) -#define reg_CP_DIVREM_RESULT (*(REGType64v *)REG_DIVREM_RESULT_ADDR) - -#define REG_SQRTCNT_OFFSET 0x2B0 -#define REG_SQRTCNT_ADDR (HW_REG_BASE + REG_SQRTCNT_OFFSET) -#define reg_CP_SQRTCNT (*(REGType16v *)REG_SQRTCNT_ADDR) - -#define REG_SQRT_RESULT_OFFSET 0x2B4 -#define REG_SQRT_RESULT_ADDR (HW_REG_BASE + REG_SQRT_RESULT_OFFSET) -#define reg_CP_SQRT_RESULT (*(REGType32v *)REG_SQRT_RESULT_ADDR) - -#define REG_SQRT_PARAM_OFFSET 0x2B8 -#define REG_SQRT_PARAM_ADDR (HW_REG_BASE + REG_SQRT_PARAM_OFFSET) -#define reg_CP_SQRT_PARAM (*(REGType64v *)REG_SQRT_PARAM_ADDR) - -#define REG_GXSTAT_OFFSET 0x600 -#define REG_GXSTAT_ADDR (HW_REG_BASE + REG_GXSTAT_OFFSET) -#define reg_G3X_GXSTAT (*(REGType32v *)REG_GXSTAT_ADDR) +#define reg_GX_DISPCNT (*(REGType32v *)0x4000000) +#define reg_GX_DISPSTAT (*(REGType16v *)0x4000004) +#define reg_GX_VCOUNT (*(REGType16v *)0x4000006) + +#define reg_G2_BG0CNT (*(REGType16v *)0x4000008) +#define reg_G2_BG1CNT (*(REGType16v *)0x400000a) +#define reg_G2_BG2CNT (*(REGType16v *)0x400000c) +#define reg_G2_BG3CNT (*(REGType16v *)0x400000e) +#define reg_G2_BG0OFS (*(REGType32v *)0x4000010) +#define reg_G2_BG0HOFS (*(REGType16v *)0x4000010) +#define reg_G2_BG0VOFS (*(REGType16v *)0x4000012) +#define reg_G2_BG1OFS (*(REGType32v *)0x4000014) +#define reg_G2_BG1HOFS (*(REGType16v *)0x4000014) +#define reg_G2_BG1VOFS (*(REGType16v *)0x4000016) +#define reg_G2_BG2OFS (*(REGType32v *)0x4000018) +#define reg_G2_BG2HOFS (*(REGType16v *)0x4000018) +#define reg_G2_BG2VOFS (*(REGType16v *)0x400001a) +#define reg_G2_BG3OFS (*(REGType32v *)0x400001c) +#define reg_G2_BG3HOFS (*(REGType16v *)0x400001c) +#define reg_G2_BG3VOFS (*(REGType16v *)0x400001e) +#define reg_G2_BG2PA (*(REGType16v *)0x4000020) +#define reg_G2_BG2PB (*(REGType16v *)0x4000022) +#define reg_G2_BG2PC (*(REGType16v *)0x4000024) +#define reg_G2_BG2PD (*(REGType16v *)0x4000026) +#define reg_G2_BG2X (*(REGType32v *)0x4000028) +#define reg_G2_BG2Y (*(REGType32v *)0x400002c) +#define reg_G2_BG3PA (*(REGType16v *)0x4000030) +#define reg_G2_BG3PB (*(REGType16v *)0x4000032) +#define reg_G2_BG3PC (*(REGType16v *)0x4000034) +#define reg_G2_BG3PD (*(REGType16v *)0x4000036) +#define reg_G2_BG3X (*(REGType32v *)0x4000038) +#define reg_G2_BG3Y (*(REGType32v *)0x400003c) +#define reg_G2_WIN0H (*(REGType16v *)0x4000040) +#define reg_G2_WIN1H (*(REGType16v *)0x4000042) +#define reg_G2_WIN0V (*(REGType16v *)0x4000044) +#define reg_G2_WIN1V (*(REGType16v *)0x4000046) +#define reg_G2_WININ (*(REGType16v *)0x4000048) +#define reg_G2_WINOUT (*(REGType16v *)0x400004a) +#define reg_G2_MOSAIC (*(REGType16v *)0x400004c) +#define reg_G2_BLDCNT (*(REGType16v *)0x4000050) +#define reg_G2_BLDALPHA (*(REGType16v *)0x4000052) +#define reg_G2_BLDY (*(REGType16v *)0x4000054) + +#define reg_G3X_DISP3DCNT (*(REGType16v *)0x4000060) + +#define reg_GX_DISPCAPCNT (*(REGType32v *)0x4000064) +#define reg_GX_DISP_MMEM_FIFO (*(REGType32v *)0x4000068) +#define reg_GX_DISP_MMEM_FIFO_L (*(REGType16v *)0x4000068) +#define reg_GX_DISP_MMEM_FIFO_H (*(REGType16v *)0x400006a) +#define reg_GX_MASTER_BRIGHT (*(REGType16v *)0x400006c) +#define reg_GX_TVOUTCNT (*(REGType16v *)0x4000070) + +#define reg_MI_DMA0SAD (*(REGType32v *)0x40000b0) +#define reg_MI_DMA0DAD (*(REGType32v *)0x40000b4) +#define reg_MI_DMA0CNT (*(REGType32v *)0x40000b8) +#define reg_MI_DMA1SAD (*(REGType32v *)0x40000bc) +#define reg_MI_DMA1DAD (*(REGType32v *)0x40000c0) +#define reg_MI_DMA1CNT (*(REGType32v *)0x40000c4) +#define reg_MI_DMA2SAD (*(REGType32v *)0x40000c8) +#define reg_MI_DMA2DAD (*(REGType32v *)0x40000cc) +#define reg_MI_DMA2CNT (*(REGType32v *)0x40000d0) +#define reg_MI_DMA3SAD (*(REGType32v *)0x40000d4) +#define reg_MI_DMA3DAD (*(REGType32v *)0x40000d8) +#define reg_MI_DMA3CNT (*(REGType32v *)0x40000dc) +#define reg_MI_DMA0_CLR_DATA (*(REGType32v *)0x40000e0) +#define reg_MI_DMA1_CLR_DATA (*(REGType32v *)0x40000e4) +#define reg_MI_DMA2_CLR_DATA (*(REGType32v *)0x40000e8) +#define reg_MI_DMA3_CLR_DATA (*(REGType32v *)0x40000ec) + +#define reg_OS_TM0CNT_L (*(REGType16v *)0x4000100) +#define reg_OS_TM0CNT_H (*(REGType16v *)0x4000102) +#define reg_OS_TM1CNT_L (*(REGType16v *)0x4000104) +#define reg_OS_TM1CNT_H (*(REGType16v *)0x4000106) +#define reg_OS_TM2CNT_L (*(REGType16v *)0x4000108) +#define reg_OS_TM2CNT_H (*(REGType16v *)0x400010a) +#define reg_OS_TM3CNT_L (*(REGType16v *)0x400010c) +#define reg_OS_TM3CNT_H (*(REGType16v *)0x400010e) + +#define reg_EXI_SIODATA32 (*(REGType32v *)0x4000120) +#define reg_EXI_SIOCNT (*(REGType16v *)0x4000128) +#define reg_EXI_SIOSEL (*(REGType32v *)0x400012c) + +#define reg_PAD_KEYINPUT (*(REGType16v *)0x4000130) +#define reg_PAD_KEYCNT (*(REGType16v *)0x4000132) + +#define reg_PXI_SUBPINTF (*(REGType16v *)0x4000180) +#define reg_PXI_SUBP_FIFO_CNT (*(REGType16v *)0x4000184) +#define reg_PXI_SEND_FIFO (*(REGType32v *)0x4000188) + +#define reg_MI_MCCNT0 (*(REGType16v *)0x40001a0) +#define reg_MI_MCD0 (*(REGType16v *)0x40001a2) +#define reg_MI_MCCNT1 (*(REGType32v *)0x40001a4) +#define reg_MI_MCCMD0 (*(REGType32v *)0x40001a8) +#define reg_MI_MCCMD1 (*(REGType32v *)0x40001ac) +#define reg_MI_EXMEMCNT (*(REGType16v *)0x4000204) + +#define reg_OS_IME (*(REGType16v *)0x4000208) +#define reg_OS_IE (*(REGType32v *)0x4000210) +#define reg_OS_IF (*(REGType32v *)0x4000214) +#define reg_OS_PAUSE (*(REGType16v *)0x4000300) + +#define reg_GX_VRAMCNT (*(REGType32v *)0x4000240) +#define reg_GX_VRAMCNT_A (*(REGType8v *)0x4000240) +#define reg_GX_VRAMCNT_B (*(REGType8v *)0x4000241) +#define reg_GX_VRAMCNT_C (*(REGType8v *)0x4000242) +#define reg_GX_VRAMCNT_D (*(REGType8v *)0x4000243) +#define reg_GX_WVRAMCNT (*(REGType32v *)0x4000244) +#define reg_GX_VRAMCNT_E (*(REGType8v *)0x4000244) +#define reg_GX_VRAMCNT_F (*(REGType8v *)0x4000245) +#define reg_GX_VRAMCNT_G (*(REGType8v *)0x4000246) +#define reg_GX_VRAMCNT_WRAM (*(REGType8v *)0x4000247) +#define reg_GX_VRAM_HI_CNT (*(REGType16v *)0x4000248) +#define reg_GX_VRAMCNT_H (*(REGType8v *)0x4000248) +#define reg_GX_VRAMCNT_I (*(REGType8v *)0x4000249) + +#define reg_CP_DIVCNT (*(REGType16v *)0x4000280) +#define reg_CP_DIV_NUMER (*(REGType64v *)0x4000290) +#define reg_CP_DIV_NUMER_L (*(REGType32v *)0x4000290) +#define reg_CP_DIV_NUMER_H (*(REGType32v *)0x4000294) +#define reg_CP_DIV_DENOM (*(REGType64v *)0x4000298) +#define reg_CP_DIV_DENOM_L (*(REGType32v *)0x4000298) +#define reg_CP_DIV_DENOM_H (*(REGType32v *)0x400029c) +#define reg_CP_DIV_RESULT (*(REGType64v *)0x40002A0) +#define reg_CP_DIV_RESULT_L (*(REGType32v *)0x40002A0) +#define reg_CP_DIV_RESULT_H (*(REGType32v *)0x40002A4) +#define reg_CP_DIVREM_RESULT (*(REGType64v *)0x40002A8) +#define reg_CP_DIVREM_RESULT_L (*(REGType32v *)0x40002A8) +#define reg_CP_DIVREM_RESULT_H (*(REGType32v *)0x40002Ac) +#define reg_CP_SQRTCNT (*(REGType16v *)0x40002B0) +#define reg_CP_SQRT_RESULT (*(REGType32v *)0x40002B4) +#define reg_CP_SQRT_PARAM (*(REGType64v *)0x40002B8) +#define reg_CP_SQRT_PARAM_L (*(REGType32v *)0x40002B8) +#define reg_CP_SQRT_PARAM_H (*(REGType32v *)0x40002Bc) + +#define reg_GX_POWCNT (*(REGType16v *)0x4000304) + +#define reg_G3X_RDLINES_COUNT (*(const REGType16v *)0x4000320) +#define reg_G3X_EDGE_COLOR_0 (*(REGType32v *)0x4000330) +#define reg_G3X_EDGE_COLOR_0_L (*(REGType16v *)0x4000330) +#define reg_G3X_EDGE_COLOR_0_H (*(REGType16v *)0x4000332) +#define reg_G3X_EDGE_COLOR_1 (*(REGType32v *)0x4000334) +#define reg_G3X_EDGE_COLOR_1_L (*(REGType16v *)0x4000334) +#define reg_G3X_EDGE_COLOR_1_H (*(REGType16v *)0x4000336) +#define reg_G3X_EDGE_COLOR_2 (*(REGType32v *)0x4000338) +#define reg_G3X_EDGE_COLOR_2_L (*(REGType16v *)0x4000338) +#define reg_G3X_EDGE_COLOR_2_H (*(REGType16v *)0x400033a) +#define reg_G3X_EDGE_COLOR_3 (*(REGType32v *)0x400033c) +#define reg_G3X_EDGE_COLOR_3_L (*(REGType16v *)0x400033c) +#define reg_G3X_EDGE_COLOR_3_H (*(REGType16v *)0x400033e) +#define reg_G3X_ALPHA_TEST_REF (*(REGType16v *)0x4000340) +#define reg_G3X_CLEAR_COLOR (*(REGType32v *)0x4000350) +#define reg_G3X_CLEAR_DEPTH (*(REGType16v *)0x4000354) +#define reg_G3X_CLRIMAGE_OFFSET (*(REGType16v *)0x4000356) +#define reg_G3X_FOG_COLOR (*(REGType32v *)0x4000358) +#define reg_G3X_FOG_OFFSET (*(REGType16v *)0x400035c) +#define reg_G3X_FOG_TABLE_0 (*(REGType32v *)0x4000360) +#define reg_G3X_FOG_TABLE_0_L (*(REGType16v *)0x4000360) +#define reg_G3X_FOG_TABLE_0_H (*(REGType16v *)0x4000362) +#define reg_G3X_FOG_TABLE_1 (*(REGType32v *)0x4000364) +#define reg_G3X_FOG_TABLE_1_L (*(REGType16v *)0x4000364) +#define reg_G3X_FOG_TABLE_1_H (*(REGType16v *)0x4000366) +#define reg_G3X_FOG_TABLE_2 (*(REGType32v *)0x4000368) +#define reg_G3X_FOG_TABLE_2_L (*(REGType16v *)0x4000368) +#define reg_G3X_FOG_TABLE_2_H (*(REGType16v *)0x400036a) +#define reg_G3X_FOG_TABLE_3 (*(REGType32v *)0x400036c) +#define reg_G3X_FOG_TABLE_3_L (*(REGType16v *)0x400036c) +#define reg_G3X_FOG_TABLE_3_H (*(REGType16v *)0x400036e) +#define reg_G3X_FOG_TABLE_4 (*(REGType32v *)0x4000370) +#define reg_G3X_FOG_TABLE_4_L (*(REGType16v *)0x4000370) +#define reg_G3X_FOG_TABLE_4_H (*(REGType16v *)0x4000372) +#define reg_G3X_FOG_TABLE_5 (*(REGType32v *)0x4000374) +#define reg_G3X_FOG_TABLE_5_L (*(REGType16v *)0x4000374) +#define reg_G3X_FOG_TABLE_5_H (*(REGType16v *)0x4000376) +#define reg_G3X_FOG_TABLE_6 (*(REGType32v *)0x4000378) +#define reg_G3X_FOG_TABLE_6_L (*(REGType16v *)0x4000378) +#define reg_G3X_FOG_TABLE_6_H (*(REGType16v *)0x400037a) +#define reg_G3X_FOG_TABLE_7 (*(REGType32v *)0x400037c) +#define reg_G3X_FOG_TABLE_7_L (*(REGType16v *)0x400037c) +#define reg_G3X_FOG_TABLE_7_H (*(REGType16v *)0x400037e) +#define reg_G3X_TOON_TABLE_0 (*(REGType32v *)0x4000380) +#define reg_G3X_TOON_TABLE_0_L (*(REGType16v *)0x4000380) +#define reg_G3X_TOON_TABLE_0_H (*(REGType16v *)0x4000382) +#define reg_G3X_TOON_TABLE_1 (*(REGType32v *)0x4000384) +#define reg_G3X_TOON_TABLE_1_L (*(REGType16v *)0x4000384) +#define reg_G3X_TOON_TABLE_1_H (*(REGType16v *)0x4000386) +#define reg_G3X_TOON_TABLE_2 (*(REGType32v *)0x4000388) +#define reg_G3X_TOON_TABLE_2_L (*(REGType16v *)0x4000388) +#define reg_G3X_TOON_TABLE_2_H (*(REGType16v *)0x400038a) +#define reg_G3X_TOON_TABLE_3 (*(REGType32v *)0x400038c) +#define reg_G3X_TOON_TABLE_3_L (*(REGType16v *)0x400038c) +#define reg_G3X_TOON_TABLE_3_H (*(REGType16v *)0x400038e) +#define reg_G3X_TOON_TABLE_4 (*(REGType32v *)0x4000390) +#define reg_G3X_TOON_TABLE_4_L (*(REGType16v *)0x4000390) +#define reg_G3X_TOON_TABLE_4_H (*(REGType16v *)0x4000392) +#define reg_G3X_TOON_TABLE_5 (*(REGType32v *)0x4000394) +#define reg_G3X_TOON_TABLE_5_L (*(REGType16v *)0x4000394) +#define reg_G3X_TOON_TABLE_5_H (*(REGType16v *)0x4000396) +#define reg_G3X_TOON_TABLE_7 (*(REGType32v *)0x400039c) +#define reg_G3X_TOON_TABLE_7_L (*(REGType16v *)0x400039c) +#define reg_G3X_TOON_TABLE_7_H (*(REGType16v *)0x400039e) +#define reg_G3X_TOON_TABLE_8 (*(REGType32v *)0x40003a0) +#define reg_G3X_TOON_TABLE_8_L (*(REGType16v *)0x40003a0) +#define reg_G3X_TOON_TABLE_8_H (*(REGType16v *)0x40003a2) +#define reg_G3X_TOON_TABLE_9 (*(REGType32v *)0x40003a4) +#define reg_G3X_TOON_TABLE_9_L (*(REGType16v *)0x40003a4) +#define reg_G3X_TOON_TABLE_9_H (*(REGType16v *)0x40003a6) +#define reg_G3X_TOON_TABLE_10 (*(REGType32v *)0x40003a8) +#define reg_G3X_TOON_TABLE_10_L (*(REGType16v *)0x40003a8) +#define reg_G3X_TOON_TABLE_10_H (*(REGType16v *)0x40003aa) +#define reg_G3X_TOON_TABLE_11 (*(REGType32v *)0x40003ac) +#define reg_G3X_TOON_TABLE_11_L (*(REGType16v *)0x40003ac) +#define reg_G3X_TOON_TABLE_11_H (*(REGType16v *)0x40003ae) +#define reg_G3X_TOON_TABLE_12 (*(REGType32v *)0x40003b0) +#define reg_G3X_TOON_TABLE_12_L (*(REGType16v *)0x40003b0) +#define reg_G3X_TOON_TABLE_12_H (*(REGType16v *)0x40003b2) +#define reg_G3X_TOON_TABLE_13 (*(REGType32v *)0x40003b4) +#define reg_G3X_TOON_TABLE_13_L (*(REGType16v *)0x40003b4) +#define reg_G3X_TOON_TABLE_13_H (*(REGType16v *)0x40003b6) +#define reg_G3X_TOON_TABLE_14 (*(REGType32v *)0x40003b8) +#define reg_G3X_TOON_TABLE_14_L (*(REGType16v *)0x40003b8) +#define reg_G3X_TOON_TABLE_14_H (*(REGType16v *)0x40003ba) +#define reg_G3X_TOON_TABLE_15 (*(REGType32v *)0x40003bc) +#define reg_G3X_TOON_TABLE_15_L (*(REGType16v *)0x40003bc) +#define reg_G3X_TOON_TABLE_15_H (*(REGType16v *)0x40003be) +#define reg_G3X_GXFIFO (*(REGType32v *)0x4000400) + +#define reg_G3_MTX_MODE (*(REGType32v *)0x4000440) +#define reg_G3_MTX_PUSH (*(REGType32v *)0x4000444) +#define reg_G3_MTX_POP (*(REGType32v *)0x4000448) +#define reg_G3_MTX_STORE (*(REGType32v *)0x400044c) +#define reg_G3_MTX_RESTORE (*(REGType32v *)0x4000450) +#define reg_G3_MTX_IDENTITY (*(REGType32v *)0x4000454) +#define reg_G3_MTX_LOAD_4x4 (*(REGType32v *)0x4000458) +#define reg_G3_MTX_LOAD_4x3 (*(REGType32v *)0x400045c) +#define reg_G3_MTX_MULT_4x4 (*(REGType32v *)0x4000460) +#define reg_G3_MTX_MULT_4x3 (*(REGType32v *)0x4000464) +#define reg_G3_MTX_MULT_3x3 (*(REGType32v *)0x4000468) +#define reg_G3_MTX_SCALE (*(REGType32v *)0x400046c) +#define reg_G3_MTX_TRANS (*(REGType32v *)0x4000470) +#define reg_G3_COLOR (*(REGType32v *)0x4000480) +#define reg_G3_NORMAL (*(REGType32v *)0x4000484) +#define reg_G3_TEXCOORD (*(REGType32v *)0x4000488) +#define reg_G3_VTX_16 (*(REGType32v *)0x400048c) +#define reg_G3_VTX_10 (*(REGType32v *)0x4000490) +#define reg_G3_VTX_XY (*(REGType32v *)0x4000494) +#define reg_G3_VTX_XZ (*(REGType32v *)0x4000498) +#define reg_G3_VTX_YZ (*(REGType32v *)0x400049c) +#define reg_G3_VTX_DIFF (*(REGType32v *)0x40004a0) +#define reg_G3_POLYGON_ATTR (*(REGType32v *)0x40004a4) +#define reg_G3_TEXIMAGE_PARAM (*(REGType32v *)0x40004a8) +#define reg_G3_TEXPLTT_BASE (*(REGType32v *)0x40004ac) +#define reg_G3_DIF_AMB (*(REGType32v *)0x40004c0) +#define reg_G3_SPE_EMI (*(REGType32v *)0x40004c4) +#define reg_G3_LIGHT_VECTOR (*(REGType32v *)0x40004c8) +#define reg_G3_LIGHT_COLOR (*(REGType32v *)0x40004cc) +#define reg_G3_SHININESS (*(REGType32v *)0x40004d0) +#define reg_G3_BEGIN_VTXS (*(REGType32v *)0x4000500) +#define reg_G3_END_VTXS (*(REGType32v *)0x4000504) +#define reg_G3_SWAP_BUFFERS (*(REGType32v *)0x4000540) +#define reg_G3_VIEWPORT (*(REGType32v *)0x4000580) +#define reg_G3_BOX_TEST (*(REGType32v *)0x40005c0) +#define reg_G3_POS_TEST (*(REGType32v *)0x40005c4) +#define reg_G3_VEC_TEST (*(REGType32v *)0x40005c8) + +#define reg_G3X_GXSTAT (*(REGType32v *)0x4000600) +#define reg_G3X_LISTRAM_COUNT (*(REGType16v *)0x4000604) +#define reg_G3X_VTXRAM_COUNT (*(REGType16v *)0x4000606) +#define reg_G3X_DISP_1DOT_DEPTH (*(REGType16v *)0x4000610) +#define reg_G3X_POS_RESULT_X (*(const REGType32v *)0x4000620) +#define reg_G3X_POS_RESULT_Y (*(const REGType32v *)0x4000624) +#define reg_G3X_POS_RESULT_Z (*(const REGType32v *)0x4000628) +#define reg_G3X_POS_RESULT_W (*(const REGType32v *)0x400062c) +#define reg_G3X_VEC_RESULT_X (*(const REGType16v *)0x4000630) +#define reg_G3X_VEC_RESULT_Y (*(const REGType16v *)0x4000632) +#define reg_G3X_VEC_RESULT_Z (*(const REGType16v *)0x4000634) +#define reg_G3X_CLIPMTX_RESULT_0 (*(const REGType32v *)0x4000640) +#define reg_G3X_CLIPMTX_RESULT_1 (*(const REGType32v *)0x4000644) +#define reg_G3X_CLIPMTX_RESULT_2 (*(const REGType32v *)0x4000648) +#define reg_G3X_CLIPMTX_RESULT_3 (*(const REGType32v *)0x400064c) +#define reg_G3X_CLIPMTX_RESULT_4 (*(const REGType32v *)0x4000650) +#define reg_G3X_CLIPMTX_RESULT_5 (*(const REGType32v *)0x4000654) +#define reg_G3X_CLIPMTX_RESULT_6 (*(const REGType32v *)0x4000658) +#define reg_G3X_CLIPMTX_RESULT_7 (*(const REGType32v *)0x400065c) +#define reg_G3X_CLIPMTX_RESULT_8 (*(const REGType32v *)0x4000660) +#define reg_G3X_CLIPMTX_RESULT_9 (*(const REGType32v *)0x4000664) +#define reg_G3X_CLIPMTX_RESULT_10 (*(const REGType32v *)0x4000668) +#define reg_G3X_CLIPMTX_RESULT_11 (*(const REGType32v *)0x400066c) +#define reg_G3X_CLIPMTX_RESULT_12 (*(const REGType32v *)0x4000670) +#define reg_G3X_CLIPMTX_RESULT_13 (*(const REGType32v *)0x4000674) +#define reg_G3X_CLIPMTX_RESULT_14 (*(const REGType32v *)0x4000678) +#define reg_G3X_CLIPMTX_RESULT_15 (*(const REGType32v *)0x400067c) +#define reg_G3X_VECMTX_RESULT_0 (*(const REGType32v *)0x4000680) +#define reg_G3X_VECMTX_RESULT_1 (*(const REGType32v *)0x4000684) +#define reg_G3X_VECMTX_RESULT_2 (*(const REGType32v *)0x4000688) +#define reg_G3X_VECMTX_RESULT_3 (*(const REGType32v *)0x400068c) +#define reg_G3X_VECMTX_RESULT_4 (*(const REGType32v *)0x4000690) +#define reg_G3X_VECMTX_RESULT_5 (*(const REGType32v *)0x4000694) +#define reg_G3X_VECMTX_RESULT_6 (*(const REGType32v *)0x4000698) +#define reg_G3X_VECMTX_RESULT_7 (*(const REGType32v *)0x400069c) +#define reg_G3X_VECMTX_RESULT_8 (*(const REGType32v *)0x40006a0) + +#define reg_GXS_DB_DISPCNT (*(REGType32v *)0x4001000) + +#define reg_G2S_DB_BG0CNT (*(REGType16v *)0x4001008) +#define reg_G2S_DB_BG1CNT (*(REGType16v *)0x400100a) +#define reg_G2S_DB_BG2CNT (*(REGType16v *)0x400100c) +#define reg_G2S_DB_BG3CNT (*(REGType16v *)0x400100e) +#define reg_G2S_DB_BG0OFS (*(REGType32v *)0x4001010) +#define reg_G2S_DB_BG0HOFS (*(REGType16v *)0x4001010) +#define reg_G2S_DB_BG0VOFS (*(REGType16v *)0x4001012) +#define reg_G2S_DB_BG1OFS (*(REGType32v *)0x4001014) +#define reg_G2S_DB_BG1HOFS (*(REGType16v *)0x4001014) +#define reg_G2S_DB_BG1VOFS (*(REGType16v *)0x4001016) +#define reg_G2S_DB_BG2OFS (*(REGType32v *)0x4001018) +#define reg_G2S_DB_BG2HOFS (*(REGType16v *)0x4001018) +#define reg_G2S_DB_BG2VOFS (*(REGType16v *)0x400101a) +#define reg_G2S_DB_BG3OFS (*(REGType32v *)0x400101c) +#define reg_G2S_DB_BG3HOFS (*(REGType16v *)0x400101c) +#define reg_G2S_DB_BG3VOFS (*(REGType16v *)0x400101e) +#define reg_G2S_DB_BG2PA (*(REGType16v *)0x4001020) +#define reg_G2S_DB_BG2PB (*(REGType16v *)0x4001022) +#define reg_G2S_DB_BG2PC (*(REGType16v *)0x4001024) +#define reg_G2S_DB_BG2PD (*(REGType16v *)0x4001026) +#define reg_G2S_DB_BG2X (*(REGType32v *)0x4001028) +#define reg_G2S_DB_BG2Y (*(REGType32v *)0x400102c) +#define reg_G2S_DB_BG3PA (*(REGType16v *)0x4001030) +#define reg_G2S_DB_BG3PB (*(REGType16v *)0x4001032) +#define reg_G2S_DB_BG3PC (*(REGType16v *)0x4001034) +#define reg_G2S_DB_BG3PD (*(REGType16v *)0x4001036) +#define reg_G2S_DB_BG3X (*(REGType32v *)0x4001038) +#define reg_G2S_DB_BG3Y (*(REGType32v *)0x400103c) +#define reg_G2S_DB_WIN0H (*(REGType16v *)0x4001040) +#define reg_G2S_DB_WIN1H (*(REGType16v *)0x4001042) +#define reg_G2S_DB_WIN0V (*(REGType16v *)0x4001044) +#define reg_G2S_DB_WIN1V (*(REGType16v *)0x4001046) +#define reg_G2S_DB_WININ (*(REGType16v *)0x4001048) +#define reg_G2S_DB_WINOUT (*(REGType16v *)0x400104a) +#define reg_G2S_DB_MOSAIC (*(REGType16v *)0x400104c) +#define reg_G2S_DB_BLDCNT (*(REGType16v *)0x4001050) +#define reg_G2S_DB_BLDALPHA (*(REGType16v *)0x4001052) +#define reg_G2S_DB_BLDY (*(REGType16v *)0x4001054) + +#define reg_GXS_DB_MASTER_BRIGHT (*(REGType16v *)0x400106c) + +#define reg_PXI_RECV_FIFO (*(REGType32v *)0x4100000) + +#define reg_MI_MCD1 (*(REGType32v *)0x4100010) + +#define REG_PAD_KEYINPUT_L_SHIFT 9 +#define REG_PAD_KEYINPUT_L_SIZE 1 +#define REG_PAD_KEYINPUT_L_MASK 0x0200 + +#define REG_PAD_KEYINPUT_R_SHIFT 8 +#define REG_PAD_KEYINPUT_R_SIZE 1 +#define REG_PAD_KEYINPUT_R_MASK 0x0100 + +#define REG_PAD_KEYINPUT_DOWN_SHIFT 7 +#define REG_PAD_KEYINPUT_DOWN_SIZE 1 +#define REG_PAD_KEYINPUT_DOWN_MASK 0x0080 + +#define REG_PAD_KEYINPUT_UP_SHIFT 6 +#define REG_PAD_KEYINPUT_UP_SIZE 1 +#define REG_PAD_KEYINPUT_UP_MASK 0x0040 + +#define REG_PAD_KEYINPUT_LEFT_SHIFT 5 +#define REG_PAD_KEYINPUT_LEFT_SIZE 1 +#define REG_PAD_KEYINPUT_LEFT_MASK 0x0020 + +#define REG_PAD_KEYINPUT_RIGHT_SHIFT 4 +#define REG_PAD_KEYINPUT_RIGHT_SIZE 1 +#define REG_PAD_KEYINPUT_RIGHT_MASK 0x0010 + +#define REG_PAD_KEYINPUT_START_SHIFT 3 +#define REG_PAD_KEYINPUT_START_SIZE 1 +#define REG_PAD_KEYINPUT_START_MASK 0x0008 + +#define REG_PAD_KEYINPUT_SEL_SHIFT 2 +#define REG_PAD_KEYINPUT_SEL_SIZE 1 +#define REG_PAD_KEYINPUT_SEL_MASK 0x0004 + +#define REG_PAD_KEYINPUT_B_SHIFT 1 +#define REG_PAD_KEYINPUT_B_SIZE 1 +#define REG_PAD_KEYINPUT_B_MASK 0x0002 + +#define REG_PAD_KEYINPUT_A_SHIFT 0 +#define REG_PAD_KEYINPUT_A_SIZE 1 +#define REG_PAD_KEYINPUT_A_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_PAD_KEYINPUT_FIELD( l, r, down, up, left, right, start, sel, b, a ) \ + (u16)( \ + ((u32)(l) << REG_PAD_KEYINPUT_L_SHIFT) | \ + ((u32)(r) << REG_PAD_KEYINPUT_R_SHIFT) | \ + ((u32)(down) << REG_PAD_KEYINPUT_DOWN_SHIFT) | \ + ((u32)(up) << REG_PAD_KEYINPUT_UP_SHIFT) | \ + ((u32)(left) << REG_PAD_KEYINPUT_LEFT_SHIFT) | \ + ((u32)(right) << REG_PAD_KEYINPUT_RIGHT_SHIFT) | \ + ((u32)(start) << REG_PAD_KEYINPUT_START_SHIFT) | \ + ((u32)(sel) << REG_PAD_KEYINPUT_SEL_SHIFT) | \ + ((u32)(b) << REG_PAD_KEYINPUT_B_SHIFT) | \ + ((u32)(a) << REG_PAD_KEYINPUT_A_SHIFT)) +#endif + +#define REG_PAD_KEYCNT_LOGIC_SHIFT 15 +#define REG_PAD_KEYCNT_LOGIC_SIZE 1 +#define REG_PAD_KEYCNT_LOGIC_MASK 0x8000 + +#define REG_PAD_KEYCNT_INTR_SHIFT 14 +#define REG_PAD_KEYCNT_INTR_SIZE 1 +#define REG_PAD_KEYCNT_INTR_MASK 0x4000 + +#define REG_PAD_KEYCNT_L_SHIFT 9 +#define REG_PAD_KEYCNT_L_SIZE 1 +#define REG_PAD_KEYCNT_L_MASK 0x0200 + +#define REG_PAD_KEYCNT_R_SHIFT 8 +#define REG_PAD_KEYCNT_R_SIZE 1 +#define REG_PAD_KEYCNT_R_MASK 0x0100 + +#define REG_PAD_KEYCNT_DOWN_SHIFT 7 +#define REG_PAD_KEYCNT_DOWN_SIZE 1 +#define REG_PAD_KEYCNT_DOWN_MASK 0x0080 + +#define REG_PAD_KEYCNT_UP_SHIFT 6 +#define REG_PAD_KEYCNT_UP_SIZE 1 +#define REG_PAD_KEYCNT_UP_MASK 0x0040 + +#define REG_PAD_KEYCNT_LEFT_SHIFT 5 +#define REG_PAD_KEYCNT_LEFT_SIZE 1 +#define REG_PAD_KEYCNT_LEFT_MASK 0x0020 + +#define REG_PAD_KEYCNT_RIGHT_SHIFT 4 +#define REG_PAD_KEYCNT_RIGHT_SIZE 1 +#define REG_PAD_KEYCNT_RIGHT_MASK 0x0010 + +#define REG_PAD_KEYCNT_START_SHIFT 3 +#define REG_PAD_KEYCNT_START_SIZE 1 +#define REG_PAD_KEYCNT_START_MASK 0x0008 + +#define REG_PAD_KEYCNT_SEL_SHIFT 2 +#define REG_PAD_KEYCNT_SEL_SIZE 1 +#define REG_PAD_KEYCNT_SEL_MASK 0x0004 + +#define REG_PAD_KEYCNT_B_SHIFT 1 +#define REG_PAD_KEYCNT_B_SIZE 1 +#define REG_PAD_KEYCNT_B_MASK 0x0002 + +#define REG_PAD_KEYCNT_A_SHIFT 0 +#define REG_PAD_KEYCNT_A_SIZE 1 +#define REG_PAD_KEYCNT_A_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_PAD_KEYCNT_FIELD( logic, intr, l, r, down, up, left, right, start, sel, b, a ) \ + (u16)( \ + ((u32)(logic) << REG_PAD_KEYCNT_LOGIC_SHIFT) | \ + ((u32)(intr) << REG_PAD_KEYCNT_INTR_SHIFT) | \ + ((u32)(l) << REG_PAD_KEYCNT_L_SHIFT) | \ + ((u32)(r) << REG_PAD_KEYCNT_R_SHIFT) | \ + ((u32)(down) << REG_PAD_KEYCNT_DOWN_SHIFT) | \ + ((u32)(up) << REG_PAD_KEYCNT_UP_SHIFT) | \ + ((u32)(left) << REG_PAD_KEYCNT_LEFT_SHIFT) | \ + ((u32)(right) << REG_PAD_KEYCNT_RIGHT_SHIFT) | \ + ((u32)(start) << REG_PAD_KEYCNT_START_SHIFT) | \ + ((u32)(sel) << REG_PAD_KEYCNT_SEL_SHIFT) | \ + ((u32)(b) << REG_PAD_KEYCNT_B_SHIFT) | \ + ((u32)(a) << REG_PAD_KEYCNT_A_SHIFT)) +#endif #endif //POKEDIAMOND_REGISTERS_H |