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-rw-r--r--arm9/lib/include/CARD_common.h2
-rw-r--r--arm9/lib/include/CTRDG_backup.h45
-rw-r--r--arm9/lib/include/CTRDG_common.h137
-rw-r--r--arm9/lib/include/CTRDG_flash.h27
-rw-r--r--arm9/lib/include/CTRDG_flash_AT29LV512.h10
-rw-r--r--arm9/lib/include/CTRDG_task.h25
-rw-r--r--arm9/lib/include/MI_dma.h3
-rw-r--r--arm9/lib/include/MI_exMemory.h58
-rw-r--r--arm9/lib/include/MI_memory.h5
-rw-r--r--arm9/lib/include/OS_interrupt.h8
-rw-r--r--arm9/lib/include/OS_protectionRegion.h4
-rw-r--r--arm9/lib/include/OS_spinLock.h6
-rw-r--r--arm9/lib/include/PXI_fifo.h20
-rw-r--r--arm9/lib/include/consts.h16
-rw-r--r--arm9/lib/include/mmap.h3
-rw-r--r--arm9/lib/include/registers.h1
-rw-r--r--arm9/lib/include/syscall.h13
17 files changed, 371 insertions, 12 deletions
diff --git a/arm9/lib/include/CARD_common.h b/arm9/lib/include/CARD_common.h
index c8a247ee..1ae31b7a 100644
--- a/arm9/lib/include/CARD_common.h
+++ b/arm9/lib/include/CARD_common.h
@@ -224,8 +224,6 @@ void CARD_UnlockBackup(u16 lock_id);
#define CARD_RETRY_COUNT_MAX 10
-extern BOOL PXI_SendWordByFifo(u32 param1, u32 data, u32 param2);
-
static inline void CARDi_SendPxi(u32 data)
{
while (PXI_SendWordByFifo(PXI_FIFO_TAG_FS, data, TRUE) < 0)
diff --git a/arm9/lib/include/CTRDG_backup.h b/arm9/lib/include/CTRDG_backup.h
new file mode 100644
index 00000000..272744ad
--- /dev/null
+++ b/arm9/lib/include/CTRDG_backup.h
@@ -0,0 +1,45 @@
+#ifndef POKEDIAMOND_CTRDG_BACKUP_H
+#define POKEDIAMOND_CTRDG_BACKUP_H
+
+#include "nitro/types.h"
+#include "CTRDG_flash.h"
+#include "CTRDG_task.h"
+
+#define CTRDG_BACKUP_PHASE_PROGRAM 0x0001
+#define CTRDG_BACKUP_PHASE_SECTOR_ERASE 0x0002
+#define CTRDG_BACKUP_PHASE_CHIP_ERASE 0x0003
+
+typedef struct CTRDGiFlashTypePlusTag
+{
+ u16 (*CTRDGi_WriteAgbFlashSector)(u16 secNo, u8 *src);
+ u16 (*CTRDGi_EraseAgbFlashChip)(void);
+ u16 (*CTRDGi_EraseAgbFlashSector)(u16 secNo);
+ void (*CTRDGi_WriteAgbFlashSectorAsync)(u16 secNo, u8 *src, CTRDG_TASK_FUNC callback);
+ void (*CTRDGi_EraseAgbFlashChipAsync)(CTRDG_TASK_FUNC callback);
+ void (*CTRDGi_EraseAgbFlashSectorAsync)(u16 secNo, CTRDG_TASK_FUNC callback);
+ u16 (*CTRDGi_PollingSR)(u16 phase, u8 *adr, u16 lastData);
+ const u16 (*maxtime);
+ CTRDGFlashType type;
+} CTRDGiFlashTypePlus;
+
+typedef enum
+{
+ CTRDG_BACKUP_TYPE_FLASH_512K,
+ CTRDG_BACKUP_TYPE_FLASH_1M,
+ CTRDG_BACKUP_TYPE_SRAM
+} CTRDGBackupType;
+
+extern const u16 (*ctrdgi_fl_maxtime);
+
+extern u16 (*CTRDGi_PollingSR)(u16 phase, u8 *adr, u16 lastData);
+extern const CTRDGFlashType *AgbFlash;
+extern u16 (*CTRDGi_WriteAgbFlashSector)(u16 secNo, u8 *src);
+extern u16 (*CTRDGi_EraseAgbFlashChip)(void);
+extern u16 (*CTRDGi_EraseAgbFlashSector)(u16 secNo);
+extern void (*CTRDGi_WriteAgbFlashSectorAsync)(u16 secNo, u8 *src, CTRDG_TASK_FUNC callback);
+extern void (*CTRDGi_EraseAgbFlashChipAsync)(CTRDG_TASK_FUNC callback);
+extern void (*CTRDGi_EraseAgbFlashSectorAsync)(u16 secNo, CTRDG_TASK_FUNC callback);
+
+u16 CTRDG_IdentifyAgbBackup(CTRDGBackupType type);
+
+#endif //POKEDIAMOND_CTRDG_BACKUP_H
diff --git a/arm9/lib/include/CTRDG_common.h b/arm9/lib/include/CTRDG_common.h
index 32049f3c..2d37c6f8 100644
--- a/arm9/lib/include/CTRDG_common.h
+++ b/arm9/lib/include/CTRDG_common.h
@@ -1,8 +1,137 @@
-#ifndef NITRO_CTRDG_COMMON_H_
-#define NITRO_CTRDG_COMMON_H_
+#ifndef POKEDIAMOND_CTRDG_COMMON_H
+#define POKEDIAMOND_CTRDG_COMMON_H
-#include "nitro/types.h"
+#include "consts.h"
+#include "OS_spinLock.h"
+#include "OS_system.h"
+#include "MI_exMemory.h"
+typedef struct CTRDGWork
+{
+ vu16 subpInitialized;
+ u16 lockID;
+
+} CTRDGWork;
+
+typedef struct CTRDGModuleID
+{
+ union
+ {
+ struct
+ {
+ u8 bitID;
+ u8 numberID:5;
+ u8 :2;
+ u8 disableExLsiID:1;
+ };
+ u16 raw;
+ };
+} CTRDGModuleID;
+
+typedef struct CTRDGModuleInfo
+{
+ CTRDGModuleID moduleID;
+ u8 exLsiID[3];
+ u8 isAgbCartridge:1;
+ u8 detectPullOut:1;
+ u8 :0; //??
+ u16 makerCode;
+ u32 gameCode;
+} CTRDGModuleInfo;
+
+typedef struct CTRDGLockByProc
+{
+ BOOL locked;
+ OSIntrMode irq;
+} CTRDGLockByProc;
+
+typedef struct CTRDGHeader
+{
+ u32 startAddress;
+ u8 nintendoLogo[0x9c];
+
+ u8 titleName[12];
+ u32 gameCode;
+ u16 makerCode;
+
+ u8 isRomCode;
+
+ u8 machineCode;
+ u8 deviceType;
+
+ u8 exLsiID[3];
+
+ u8 reserved[4];
+ u8 softVersion;
+ u8 complement;
+
+ u16 moduleID;
+} CTRDGHeader;
+
+typedef struct CTRDGRomCycle
+{
+ MICartridgeRomCycle1st c1;
+ MICartridgeRomCycle2nd c2;
+} CTRDGRomCycle;
+
+#define CTRDGi_GetModuleInfoAddr() ((CTRDGModuleInfo *)HW_CTRDG_MODULE_INFO_BUF)
+#define CTRDGi_GetHeaderAddr() ((CTRDGHeader *)HW_CTRDG_ROM)
+#define CTRDGi_GetModuleIDImageAddr() ((u16 *)(HW_CTRDG_ROM + 0x0001fffe))
+
+#define CTRDG_IS_ROM_CODE 0x96
+#define CTRDG_LOCKED_BY_MYPROC_FLAG OS_MAINP_LOCKED_FLAG
+
+#define CTRDGi_FORWARD_TYPE_DMA 0x00000000
+#define CTRDGi_FORWARD_TYPE_CPU 0x00000001
+#define CTRDGi_FORWARD_TYPE_MASK 0x00000001
+
+#define CTRDGi_FORWARD_WIDTH_8 0x00000000
+#define CTRDGi_FORWARD_WIDTH_16 0x00000010
+#define CTRDGi_FORWARD_WIDTH_32 0x00000020
+
+#define CTRDGi_FORWARD_DMA16 (CTRDGi_FORWARD_TYPE_DMA | CTRDGi_FORWARD_WIDTH_16)
+#define CTRDGi_FORWARD_DMA32 (CTRDGi_FORWARD_TYPE_DMA | CTRDGi_FORWARD_WIDTH_32)
+#define CTRDGi_FORWARD_CPU8 (CTRDGi_FORWARD_TYPE_CPU | CTRDGi_FORWARD_WIDTH_8)
+#define CTRDGi_FORWARD_CPU16 (CTRDGi_FORWARD_TYPE_CPU | CTRDGi_FORWARD_WIDTH_16)
+#define CTRDGi_FORWARD_CPU32 (CTRDGi_FORWARD_TYPE_CPU | CTRDGi_FORWARD_WIDTH_32)
+
+#define CTRDGi_ACCESS_DIR_WRITE 0x00000000
+#define CTRDGi_ACCESS_DIR_READ 0x00000001
+
+#define CTRDGi_ACCESS_WIDTH_8 0x00000010
+#define CTRDGi_ACCESS_WIDTH_16 0x00000020
+#define CTRDGi_ACCESS_WIDTH_32 0x00000040
+
+#define CTRDGi_ACCESS_WRITE8 (CTRDGi_ACCESS_DIR_WRITE | CTRDGi_ACCESS_WIDTH_8)
+#define CTRDGi_ACCESS_WRITE16 (CTRDGi_ACCESS_DIR_WRITE | CTRDGi_ACCESS_WIDTH_16)
+#define CTRDGi_ACCESS_WRITE32 (CTRDGi_ACCESS_DIR_WRITE | CTRDGi_ACCESS_WIDTH_32)
+#define CTRDGi_ACCESS_READ8 (CTRDGi_ACCESS_DIR_READ | CTRDGi_ACCESS_WIDTH_8)
+#define CTRDGi_ACCESS_READ16 (CTRDGi_ACCESS_DIR_READ | CTRDGi_ACCESS_WIDTH_16)
+#define CTRDGi_ACCESS_READ32 (CTRDGi_ACCESS_DIR_READ | CTRDGi_ACCESS_WIDTH_32)
+
+void CTRDGi_InitCommon(void);
+BOOL CTRDG_IsAgbCartridge(void);
+BOOL CTRDG_IsOptionCartridge(void);
+BOOL CTRDGi_IsAgbCartridgeAtInit(void);
+u32 CTRDG_GetAgbGameCode(void);
+u32 CTRDGi_GetAgbGameCodeAtInit(void);
+u16 CTRDG_GetAgbMakerCode(void);
+u16 CTRDGi_GetAgbMakerCodeAtInit(void);
BOOL CTRDG_IsPulledOut(void);
+BOOL CTRDG_IsExisting(void);
+void CTRDGi_ChangeLatestAccessCycle(CTRDGRomCycle *r);
+void CTRDGi_RestoreAccessCycle(CTRDGRomCycle *r);
+void CTRDGi_LockByProcessor(u16 lockID, CTRDGLockByProc *info);
+void CTRDGi_UnlockByProcessor(u16 lockID, CTRDGLockByProc *info);
+void CTRDGi_SendtoPxi(u32 data);
+BOOL CTRDG_CpuCopy8(const void *src, void *dest, u32 size);
+BOOL CTRDG_CpuCopy16(const void *src, void *dest, u32 size);
+BOOL CTRDG_CpuCopy32(const void *src, void *dest, u32 size);
+BOOL CTRDGi_CopyCommon(u32 dmaNo, const void *src, void *dest, u32 size, u32 forwardType);
+BOOL CTRDG_Read32(const u32 *address, u32 *rdata);
+BOOL CTRDGi_AccessCommon(void *address, u32 data, void *rdata, u32 accessType);
+BOOL CTRDG_IsEnabled(void);
+void CTRDG_Enable(BOOL enable);
+void CTRDG_CheckEnabled(void);
-#endif //NITRO_CTRDG_COMMON_H_
+#endif //POKEDIAMOND_CTRDG_COMMON_H
diff --git a/arm9/lib/include/CTRDG_flash.h b/arm9/lib/include/CTRDG_flash.h
new file mode 100644
index 00000000..aa02d951
--- /dev/null
+++ b/arm9/lib/include/CTRDG_flash.h
@@ -0,0 +1,27 @@
+#ifndef POKEDIAMOND_CTRDG_FLASH_H
+#define POKEDIAMOND_CTRDG_FLASH_H
+
+#include "nitro/types.h"
+#include "MI_exMemory.h"
+
+#define CTRDG_AGB_FLASH_ADR 0x0A000000
+
+typedef struct CTRDGiFlashSectorTag
+{
+ u32 size;
+ u16 shift;
+ u16 count;
+ u16 top;
+ u8 reserved[2];
+} CTRDGiFlashSector;
+
+typedef struct CTRDGFlashTypeTag
+{
+ u32 romSize;
+ CTRDGiFlashSector sector;
+ MICartridgeRamCycle agbWait[2];
+ u16 makerID;
+ u16 deviceID;
+} CTRDGFlashType;
+
+#endif //POKEDIAMOND_CTRDG_FLASH_H
diff --git a/arm9/lib/include/CTRDG_flash_AT29LV512.h b/arm9/lib/include/CTRDG_flash_AT29LV512.h
new file mode 100644
index 00000000..908dd6cf
--- /dev/null
+++ b/arm9/lib/include/CTRDG_flash_AT29LV512.h
@@ -0,0 +1,10 @@
+#ifndef POKEDIAMOND_CTRDG_FLASH_AT29LV512_H
+#define POKEDIAMOND_CTRDG_FLASH_AT29LV512_H
+
+#include "nitro/types.h"
+#include "CTRDG_task.h"
+
+u32 CTRDGi_EraseFlashChipCoreAT(CTRDGTaskInfo *arg);
+u32 CTRDGi_EraseFlashSectorCoreAT(CTRDGTaskInfo *arg);
+
+#endif //POKEDIAMOND_CTRDG_FLASH_AT29LV512_H
diff --git a/arm9/lib/include/CTRDG_task.h b/arm9/lib/include/CTRDG_task.h
new file mode 100644
index 00000000..2cf7a233
--- /dev/null
+++ b/arm9/lib/include/CTRDG_task.h
@@ -0,0 +1,25 @@
+#ifndef POKEDIAMOND_CTRDG_TASK_H
+#define POKEDIAMOND_CTRDG_TASK_H
+
+#include "nitro/types.h"
+
+struct CTRDGTaskInfo_tag;
+
+typedef u32 (*CTRDG_TASK_FUNC) (struct CTRDGTaskInfo_tag *);
+
+typedef struct CTRDGTaskInfo_tag
+{
+ CTRDG_TASK_FUNC task;
+ CTRDG_TASK_FUNC callback;
+ u32 result;
+ u8 *data;
+ u8 *adr;
+ u32 offset;
+ u32 size;
+ u8 *dst;
+ u16 sec_num;
+ u8 busy;
+ u8 param[1];
+} CTRDGTaskInfo;
+
+#endif //POKEDIAMOND_CTRDG_TASK_H
diff --git a/arm9/lib/include/MI_dma.h b/arm9/lib/include/MI_dma.h
index 8ce3f417..99d1cb84 100644
--- a/arm9/lib/include/MI_dma.h
+++ b/arm9/lib/include/MI_dma.h
@@ -21,6 +21,9 @@ typedef void (*MIDmaCallback)(void *);
#define MI_DMA_SRC_FIX (2UL << 23)
#define MI_DMA_SRC_INC (0UL << 23)
+#define MI_DMA_16BIT_BUS (0UL << 26)
+#define MI_DMA_32BIT_BUS (1UL << 26)
+
#define MIi_DMA_TIMING_ANY (u32)(~0)
#define MI_DMA_TIMING_H_BLANK (2UL << 27)
diff --git a/arm9/lib/include/MI_exMemory.h b/arm9/lib/include/MI_exMemory.h
index 8bd355ac..aa90a73c 100644
--- a/arm9/lib/include/MI_exMemory.h
+++ b/arm9/lib/include/MI_exMemory.h
@@ -1,5 +1,5 @@
-#ifndef NITRO_MI_EXMEMORY_H_
-#define NITRO_MI_EXMEMORY_H_
+#ifndef POKEDIAMOND_MI_EXMEMORY_H
+#define POKEDIAMOND_MI_EXMEMORY_H
#include "consts.h"
@@ -8,6 +8,28 @@ typedef enum {
MI_PROCESSOR_ARM7 = 1
} MIProcessor;
+typedef enum
+{
+ MI_CTRDG_ROMCYCLE1_10 = 0,
+ MI_CTRDG_ROMCYCLE1_8 = 1,
+ MI_CTRDG_ROMCYCLE1_6 = 2,
+ MI_CTRDG_ROMCYCLE1_18 = 3
+} MICartridgeRomCycle1st;
+
+typedef enum
+{
+ MI_CTRDG_ROMCYCLE2_6 = 0,
+ MI_CTRDG_ROMCYCLE2_4 = 1
+} MICartridgeRomCycle2nd;
+
+typedef enum
+{
+ MI_CTRDG_RAMCYCLE_10 = 0,
+ MI_CTRDG_RAMCYCLE_8 = 1,
+ MI_CTRDG_RAMCYCLE_6 = 2,
+ MI_CTRDG_RAMCYCLE_18 = 3
+} MICartridgeRamCycle;
+
static inline void MIi_SetCardProcessor(MIProcessor proc)
{
reg_MI_EXMEMCNT =
@@ -20,4 +42,34 @@ static inline void MIi_SetCartridgeProcessor(MIProcessor proc)
(u16)((reg_MI_EXMEMCNT & ~0x0080) | (proc << 7));
}
-#endif //NITRO_MI_EXMEMORY_H_
+static inline MICartridgeRomCycle1st MI_GetCartridgeRomCycle1st(void)
+{
+ return (MICartridgeRomCycle1st)((reg_MI_EXMEMCNT & 0xc) >> 2);
+}
+
+static inline MICartridgeRomCycle2nd MI_GetCartridgeRomCycle2nd(void)
+{
+ return (MICartridgeRomCycle2nd)((reg_MI_EXMEMCNT & 0x10) >> 4);
+}
+
+static inline void MI_SetCartridgeRomCycle1st(MICartridgeRomCycle1st c1)
+{
+ reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~0xc) | (c1 << 2));
+}
+
+static inline void MI_SetCartridgeRomCycle2nd(MICartridgeRomCycle2nd c2)
+{
+ reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~0x10) | (c2 << 4));
+}
+
+static inline void MI_SetCartridgeRamCycle(MICartridgeRamCycle c)
+{
+ reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~3) | (c << 0));
+}
+
+static inline MICartridgeRamCycle MI_GetCartridgeRamCycle(void)
+{
+ return (MICartridgeRamCycle)((reg_MI_EXMEMCNT & 3) >> 0);
+}
+
+#endif //POKEDIAMOND_MI_EXMEMORY_H
diff --git a/arm9/lib/include/MI_memory.h b/arm9/lib/include/MI_memory.h
index 450e5e58..339ff9b8 100644
--- a/arm9/lib/include/MI_memory.h
+++ b/arm9/lib/include/MI_memory.h
@@ -45,6 +45,11 @@ static inline void MI_CpuCopy16(const void *src, void *dest, u32 size)
MIi_CpuCopy16(src, dest, size);
}
+static inline void MI_CpuCopy32(const void *src, void *dest, u32 size)
+{
+ MIi_CpuCopy32(src, dest, size);
+}
+
static inline void MI_CpuFillFast(void *dest, u32 data, u32 size)
{
MIi_CpuClearFast(data, dest, size);
diff --git a/arm9/lib/include/OS_interrupt.h b/arm9/lib/include/OS_interrupt.h
index 3d139079..d063b817 100644
--- a/arm9/lib/include/OS_interrupt.h
+++ b/arm9/lib/include/OS_interrupt.h
@@ -12,6 +12,7 @@
#define OS_IE_V_COUNT (1UL << REG_OS_IE_VE_SHIFT)
#define OS_IE_TIMER0 (1UL << REG_OS_IE_T0_SHIFT)
#define OS_IE_TIMER1 (1UL << REG_OS_IE_T1_SHIFT)
+#define OS_IE_SPFIFO_RECV (1UL << REG_OS_IE_IFN_SHIFT)
#define OS_IE_CARD_DATA (1UL << REG_OS_IE_MC_SHIFT)
extern OSIrqFunction OS_IRQTable[];
@@ -42,6 +43,13 @@ static inline BOOL OS_EnableIrq(void)
return (BOOL)prep;
}
+static inline BOOL OS_RestoreIrq(BOOL enable)
+{
+ u16 prep = reg_OS_IME;
+ reg_OS_IME = (u16)enable;
+ return (BOOL)prep;
+}
+
static inline OSIrqMask OS_GetIrqMask(void)
{
return reg_OS_IE;
diff --git a/arm9/lib/include/OS_protectionRegion.h b/arm9/lib/include/OS_protectionRegion.h
index 9b65258d..00b7ae63 100644
--- a/arm9/lib/include/OS_protectionRegion.h
+++ b/arm9/lib/include/OS_protectionRegion.h
@@ -41,4 +41,8 @@ static inline u32 OSi_CalcPRParam(u32 address, u32 size, OSiProtectionRegionBase
OS_SetProtectionRegion##regionNo(OSi_CalcPRParam(address, HW_C6_PR_##sizeStr, OSi_PR_BASE_MASK_##sizeStr) \
| 1)
+#define OS_PR3_ACCESS_MASK (HW_C5_PERMIT_MASK << HW_C5_PR3_SFT)
+#define OS_PR3_ACCESS_RW (HW_C5_PERMIT_RW << HW_C5_PR3_SFT)
+#define OS_PR3_ACCESS_RO (HW_C5_PERMIT_RO << HW_C5_PR3_SFT)
+
#endif //POKEDIAMOND_OS_PROTECTIONREGION_H
diff --git a/arm9/lib/include/OS_spinLock.h b/arm9/lib/include/OS_spinLock.h
index c26e3b9f..09c2cf2c 100644
--- a/arm9/lib/include/OS_spinLock.h
+++ b/arm9/lib/include/OS_spinLock.h
@@ -5,7 +5,11 @@
#include "nitro/OS_spinLock_shared.h"
#include "syscall.h"
-#define OS_LOCK_ID_ERROR (-3)
+#define OS_ReadOwnerOfLockCartridge() OS_ReadOwnerOfLockWord( (OSLockWord *)HW_CTRDG_LOCK_BUF )
+#define OS_MAINP_LOCKED_FLAG 0x40
+#define OS_LOCK_SUCCESS 0
+
+#define OS_LOCK_ID_ERROR (-3)
static inline void OSi_WaitByLoop(void)
{
diff --git a/arm9/lib/include/PXI_fifo.h b/arm9/lib/include/PXI_fifo.h
index becba32e..b1ca33f3 100644
--- a/arm9/lib/include/PXI_fifo.h
+++ b/arm9/lib/include/PXI_fifo.h
@@ -2,6 +2,7 @@
#define POKEDIAMOND_ARM9_PXI_FIFO_H
#include "nitro/PXI_fifo_shared.h"
+#include "nitro/types.h"
typedef enum
{
@@ -13,4 +14,23 @@ typedef enum
PXI_FIFO_NO_CALLBACK_ENTRY = -5
} PXIFifoStatus;
+typedef void (*PXIFifoCallback) (PXIFifoTag tag, u32 data, BOOL err);
+
+typedef union
+{
+ struct
+ {
+ u32 tag:5;
+ u32 err:1;
+ u32 data:26;
+ } e;
+ u32 raw;
+} PXIFifoMessage;
+
+void PXI_InitFifo(void);
+void PXI_SetFifoRecvCallback(s32 fifotag, PXIFifoCallback callback);
+BOOL PXI_IsCallbackReady(s32 fifotag, PXIProc proc);
+s32 PXI_SendWordByFifo(s32 fifotag, u32 data, BOOL err);
+void PXIi_HandlerRecvFifoNotEmpty(void);
+
#endif //POKEDIAMOND_ARM9_PXI_FIFO_H
diff --git a/arm9/lib/include/consts.h b/arm9/lib/include/consts.h
index 7c56a9a3..a41f22ae 100644
--- a/arm9/lib/include/consts.h
+++ b/arm9/lib/include/consts.h
@@ -6,6 +6,13 @@
#include "registers.h"
#include "systemWork.h"
+#define HW_C5_PERMIT_MASK 0xf
+
+#define HW_C5_PERMIT_RO 5
+#define HW_C5_PERMIT_RW 1
+
+#define HW_C5_PR3_SFT 12
+
#define HW_C6_PR_4KB 0x16
#define HW_C6_PR_8KB 0x18
#define HW_C6_PR_16KB 0x1a
@@ -35,8 +42,6 @@
#define HW_CACHE_LINE_SIZE 32
-#define PXI_PROC_ARM7 0x01
-
#define OSi_CONSOLE_NOT_DETECT 0xffffffff
#define OS_CONSOLE_NITRO 0x80000000
@@ -50,4 +55,11 @@
#define HW_CPU_CLOCK_ARM9 67027964
+#define REG_PXI_SUBP_FIFO_CNT_E_MASK 0x8000
+#define REG_PXI_SUBP_FIFO_CNT_ERR_MASK 0x4000
+#define REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK 0x0400
+#define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK 0x0100
+#define REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK 0x0008
+#define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK 0x0002
+
#endif //POKEDIAMOND_ARM9_CONSTS_H
diff --git a/arm9/lib/include/mmap.h b/arm9/lib/include/mmap.h
index de5a8057..69e9c696 100644
--- a/arm9/lib/include/mmap.h
+++ b/arm9/lib/include/mmap.h
@@ -34,6 +34,7 @@ extern u32 SDK_AUTOLOAD_DTCM_START[];
#define HW_BOOT_CHECK_INFO_BUF (HW_MAIN_MEM + 0x007ffc00)
#define HW_RESET_PARAMETER_BUF (HW_MAIN_MEM + 0x007ffc20)
#define HW_ROM_BASE_OFFSET_BUF (HW_MAIN_MEM + 0x007ffc2c)
+#define HW_CTRDG_MODULE_INFO_BUF (HW_MAIN_MEM + 0x007ffc30)
#define HW_ROM_HEADER_BUF (HW_MAIN_MEM + 0x007ffe00) // ROM registration area data buffer
#define HW_RED_RESERVED (HW_MAIN_MEM + 0x007ff800) // Some kind of reserved data for shared memory
#define HW_MAIN_MEM_EX_END (HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE)
@@ -93,6 +94,8 @@ extern u32 SDK_AUTOLOAD_DTCM_START[];
#define HW_DB_OAM_END 0x07000800
#define HW_DB_OAM_SIZE (HW_DB_OAM_END-HW_DB_OAM)
+#define HW_CTRDG_RAM_END 0x0a010000
+
#define HW_DTCM_SYSRV_OFS_INTR_VECTOR 0x3c
#define HW_RESET_VECTOR 0xffff0000
diff --git a/arm9/lib/include/registers.h b/arm9/lib/include/registers.h
index 44a21bf0..d55347d5 100644
--- a/arm9/lib/include/registers.h
+++ b/arm9/lib/include/registers.h
@@ -350,6 +350,7 @@
#define REG_OS_IE_VE_SHIFT 2
#define REG_OS_IE_T0_SHIFT 3
#define REG_OS_IE_T1_SHIFT 4
+#define REG_OS_IE_IFN_SHIFT 18
#define REG_OS_IE_MC_SHIFT 19
#define REG_OS_TM0CNT_H_I_MASK 0x0040
diff --git a/arm9/lib/include/syscall.h b/arm9/lib/include/syscall.h
index 427134a7..8e7962df 100644
--- a/arm9/lib/include/syscall.h
+++ b/arm9/lib/include/syscall.h
@@ -1,6 +1,19 @@
#ifndef POKEDIAMOND_ARM9_SYSCALL_H
#define POKEDIAMOND_ARM9_SYSCALL_H
+#include "consts.h"
+#include "MI_dma.h"
+
+void SVC_CpuSet(const void *srcp, void *destp, u32 dmaCntData);
+
+#define SVC_CpuClear( data, destp, size, bit ) \
+do{ \
+ vu##bit tmp = (vu##bit )(data); \
+ SVC_CpuSet((u8 *)&(tmp), (u8 *)(destp), ( \
+ MI_DMA_SRC_FIX | \
+ MI_DMA_##bit##BIT_BUS | ((size)/((bit)/8) & 0x1fffff))); \
+} while(0)
+
void SVC_WaitByLoop(u32 ct);
#endif //POKEDIAMOND_ARM9_SYSCALL_H
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-18 16:34:08 +0000