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-rw-r--r--arm9/lib/src/GX_asm.c16
-rw-r--r--arm9/lib/src/GX_g3.c36
-rw-r--r--arm9/lib/src/GX_g3b.c122
-rw-r--r--arm9/lib/src/GX_g3x.c242
-rw-r--r--arm9/lib/src/GX_vramcnt_c.c24
5 files changed, 440 insertions, 0 deletions
diff --git a/arm9/lib/src/GX_asm.c b/arm9/lib/src/GX_asm.c
new file mode 100644
index 00000000..1eb0a011
--- /dev/null
+++ b/arm9/lib/src/GX_asm.c
@@ -0,0 +1,16 @@
+#include "global.h"
+#include "main.h"
+#include "gx.h"
+
+//looks like asm and says asm on the tin...
+ARM_FUNC asm void GX_SendFifo48B(void *src, void *dst){
+ ldmia r0!, {r2-r3,r12}
+ stmia r1, {r2-r3,r12}
+ ldmia r0!, {r2-r3,r12}
+ stmia r1, {r2-r3,r12}
+ ldmia r0!, {r2-r3,r12}
+ stmia r1, {r2-r3,r12}
+ ldmia r0!, {r2-r3,r12}
+ stmia r1, {r2-r3,r12}
+ bx lr
+}
diff --git a/arm9/lib/src/GX_g3.c b/arm9/lib/src/GX_g3.c
new file mode 100644
index 00000000..66e34dc7
--- /dev/null
+++ b/arm9/lib/src/GX_g3.c
@@ -0,0 +1,36 @@
+#include "global.h"
+#include "main.h"
+#include "gx.h"
+
+
+void G3_BeginMakeDL(struct DL *displaylist, void *r1, u32 r2){
+ displaylist->var0C = r2;
+ displaylist->var08 = r1;
+ displaylist->var00 = r1;
+ displaylist->var04 = (u32 *)r1 + 1;
+ displaylist->var10 = 0x0;
+}
+
+s32 G3_EndMakeDL(struct DL *displaylist){
+ if (displaylist->var08 == displaylist->var00)
+ return 0;
+ //pads the buffer with 0 to 4byte alignment if needed
+ switch((u32)displaylist->var00 & 0x3)
+ {
+ case 0:
+ return displaylist->var00 - displaylist->var08;
+ case 1:
+ *displaylist->var00++ = 0x0;
+ case 2:
+ *displaylist->var00++ = 0x0;
+ case 3:
+ *displaylist->var00++ = 0x0;
+ }
+ if (displaylist->var10)
+ {
+ *displaylist->var04++ = 0x0;
+ displaylist->var10 = 0x0;
+ }
+ displaylist->var00 = (u8 *)displaylist->var04;
+ return displaylist->var00 - displaylist->var08;
+}
diff --git a/arm9/lib/src/GX_g3b.c b/arm9/lib/src/GX_g3b.c
new file mode 100644
index 00000000..1e25adb5
--- /dev/null
+++ b/arm9/lib/src/GX_g3b.c
@@ -0,0 +1,122 @@
+#include "global.h"
+#include "main.h"
+#include "gx.h"
+
+
+void MI_Copy64B(void *src, void *dst);
+
+void G3BS_LoadMtx44(struct DL *displaylist, struct Mtx44 *mtx){
+ *(u32 *)displaylist->var00 = 0x16;
+ MI_Copy64B(mtx, displaylist->var04);
+}
+
+void G3B_PushMtx(struct DL *displaylist){
+ *(u32 *)displaylist->var00 = 0x11;
+ displaylist->var00 = (u8 *)displaylist->var04;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+void G3B_PopMtx(struct DL *displaylist, void *mtx){
+ *(u32 *)displaylist->var00 = 0x12;
+ *displaylist->var04 = (u32)mtx;
+ displaylist->var00 = (u8 *)displaylist->var04 + 0x4;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+void G3B_LoadMtx44(struct DL *displaylist, struct Mtx44 *mtx){
+ G3BS_LoadMtx44(displaylist, mtx);
+ displaylist->var00 = (u8 *)displaylist->var04 + sizeof(struct Mtx44);
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+//color format is RGB555, stored in the lower bits
+void G3B_Color(struct DL * displaylist, u32 vtx_col){
+ *(u32 *)displaylist->var00 = 0x20;
+ *displaylist->var04 = vtx_col;
+ displaylist->var00 = (u8 *)displaylist->var04 + 0x4;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+/*
+Only feed normalized Vectors
+only the fractional part and the sign, which is in the first nonfraction bit
+since the vector is assumed to be normalized, are used
+*/
+void G3B_Normal(struct DL * displaylist, fx16 x, fx16 y, fx16 z){
+ *(u32 *)displaylist->var00 = 0x21;
+ *displaylist->var04 = ((x >> 3) & 0x3FF) | (((y >> 3) & 0x3FF) << 0xA) | (((z >> 3) & 0x3FF) << 0x14) ;
+ displaylist->var00 = (u8 *)displaylist->var04 + 0x4;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+void G3B_Vtx(struct DL * displaylist, fx32 x, fx32 y, fx32 z){
+ *(u32 *)displaylist->var00 = 0x23;
+ displaylist->var04[0] = (u32)(u16)x | (u32)(u16)y << 0x10;
+ displaylist->var04[1] = (u32)(u16)z;
+ displaylist->var00 = (u8 *)displaylist->var04 + 0x8;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+//TODO: name arguments
+void G3B_PolygonAttr(struct DL *displaylist, u32 r1, u32 r2, u32 r3, u32 r4, u32 r5, u32 r6){
+ *(u32 *)displaylist->var00 = 0x29;
+ *displaylist->var04 = r1 | r2 << 0x4 | r3 << 0x6 | r6 | r4 << 0x18 | r5 << 0x10;
+ displaylist->var00 = (u8 *)displaylist->var04 + 0x4;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+void G3B_MaterialColorDiffAmb(struct DL *displaylist, u32 diffuse_col, u32 ambient_col, u32 replace){
+ *(u32 *)displaylist->var00 = 0x30;
+ u32 replace_vtx_color_with_diffuse;
+ if (replace)
+ replace_vtx_color_with_diffuse = TRUE;
+ else
+ replace_vtx_color_with_diffuse = FALSE;
+ *displaylist->var04 = diffuse_col | ambient_col << 0x10 | replace_vtx_color_with_diffuse << 0xF;
+ displaylist->var00 = (u8 *)displaylist->var04 + 0x4;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+void G3B_MaterialColorSpecEmi(struct DL *displaylist, u32 specular_col, u32 emission_col, u32 shiny_table){
+ *(u32 *)displaylist->var00 = 0x31;
+ u32 enable_shininess_table;
+ if (shiny_table)
+ enable_shininess_table = TRUE;
+ else
+ enable_shininess_table = FALSE;
+ *displaylist->var04 = specular_col | emission_col << 0x10 | enable_shininess_table << 0xF;
+ displaylist->var00 = (u8 *)displaylist->var04 + 0x4;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+/*
+Only feed normalized Vectors
+only the fractional part and the sign, which is in the first nonfraction bit
+since the vector is assumed to be normalized, are used
+*/
+void G3B_LightVector(struct DL * displaylist, u32 light_num, fx16 x, fx16 y, fx16 z){
+ *(u32 *)displaylist->var00 = 0x32;
+ *displaylist->var04 = ((x >> 3) & 0x3FF) | (((y >> 3) & 0x3FF) << 0xA) | (((z >> 3) & 0x3FF) << 0x14) | light_num << 0x1E;
+ displaylist->var00 = (u8 *)displaylist->var04 + 0x4;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+void G3B_LightColor(struct DL * displaylist, u32 light_num, u32 col){
+ *(u32 *)displaylist->var00 = 0x33;
+ *displaylist->var04 = col | light_num << 0x1E;
+ displaylist->var00 = (u8 *)displaylist->var04 + 0x4;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+void G3B_Begin(struct DL * displaylist, u32 type){
+ *(u32 *)displaylist->var00 = 0x40;
+ *displaylist->var04 = type;
+ displaylist->var00 = (u8 *)displaylist->var04 + 0x4;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
+
+void G3B_End(struct DL * displaylist){
+ *(u32 *)displaylist->var00 = 0x41;
+ displaylist->var00 = (u8 *)displaylist->var04;
+ displaylist->var04 = (u32 *)displaylist->var00 + 1;
+}
diff --git a/arm9/lib/src/GX_g3x.c b/arm9/lib/src/GX_g3x.c
new file mode 100644
index 00000000..f9c2adb7
--- /dev/null
+++ b/arm9/lib/src/GX_g3x.c
@@ -0,0 +1,242 @@
+#include "global.h"
+#include "main.h"
+#include "gx.h"
+
+extern u32 gUnk02106814;
+void MI_Copy64B(void *, void *);
+void MIi_CpuCopy16(void *, void *, u32);
+void GXi_NopClearFifo128_(void *);
+void MI_Copy16B(void *, void *);
+void MI_DmaFill32Async(u32, void *, u32, u32, u32, u32);
+void MI_DmaFill32(u32, void *, u32, u32);
+void MIi_CpuClear32(u32, void *, u32);
+
+asm void GXi_NopClearFifo128_(void *reg){
+ mov r1, #0x0
+ mov r2, #0x0
+ mov r3, #0x0
+ mov r12, #0x0
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ stmia r0, {r1-r3,r12}
+ bx lr
+}
+
+void G3X_Init(){
+ G3X_ClearFifo();
+ SETREG32(HW_REG_END_VTXS, 0x0);
+ while (READREG32(HW_REG_GXSTAT) & 0x8000000); //wait for geometry engine to not be busy
+ SETREG16(HW_REG_DISP3DCNT, 0x0);
+ SETREG32(HW_REG_GXSTAT, 0x0);
+ SETREG32(HW_REG_BG0HOFS, 0x0);
+ SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x2000);
+ SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x1000);
+ SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & ~0x3002);
+ SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & ~0x3000 | 0x10);
+ SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & (u16)~0x3004);
+ SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
+ SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) & ~0xC0000000 | 0x80000000);
+ G3X_InitMtxStack();
+ SETREG32(HW_REG_CLEAR_COLOR, 0x0);
+ SETREG16(HW_REG_CLEAR_DEPTH, 0x7FFF);
+ SETREG16(HW_REG_CLRIMAGE_OFFSET, 0x0);
+ SETREG32(HW_REG_FOG_COLOR, 0x0);
+ SETREG16(HW_REG_FOG_OFFSET, 0x0);
+ SETREG16(HW_REG_BG0CNT, READREG16(HW_REG_BG0CNT) & ~0x3);
+ G3X_InitTable();
+ SETREG32(HW_REG_POLYGON_ATTR, 0x1F0080);
+ SETREG32(HW_REG_TEXIMAGE_PARAM, 0x0);
+ SETREG32(HW_REG_PLTT_BASE, 0x0);
+}
+
+void G3X_ResetMtxStack(){
+ while (READREG32(HW_REG_GXSTAT) & 0x8000000);
+ SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
+ SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x2000);
+ SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x1000);
+ G3X_ResetMtxStack_2();
+ SETREG32(HW_REG_POLYGON_ATTR, 0x1F0080);
+ SETREG32(HW_REG_TEXIMAGE_PARAM, 0x0);
+ SETREG32(HW_REG_PLTT_BASE, 0x0);
+}
+
+void G3X_ClearFifo(){
+ GXi_NopClearFifo128_((void *)HW_REG_GXFIFO);
+ while (READREG32(HW_REG_GXSTAT) & 0x8000000);
+}
+
+void G3X_InitMtxStack(){
+ u32 PV_level, PJ_level;
+ SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
+ while (G3X_GetMtxStackLevelPV(&PV_level));
+ while (G3X_GetMtxStackLevelPJ(&PJ_level));
+ SETREG32(HW_REG_MTX_MODE, 0x3);
+ SETREG32(HW_REG_MTX_IDENTITY, 0x0);
+ SETREG32(HW_REG_MTX_MODE, 0x0);
+ if (PJ_level)
+ {
+ SETREG32(HW_REG_MTX_POP, PJ_level);
+ }
+ SETREG32(HW_REG_MTX_IDENTITY, 0x0);
+ SETREG32(HW_REG_MTX_MODE, 0x2);
+ SETREG32(HW_REG_MTX_POP, PV_level);
+ SETREG32(HW_REG_MTX_IDENTITY, 0x0);
+}
+
+void G3X_ResetMtxStack_2(){
+ u32 PV_level, PJ_level;
+ SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
+ while (G3X_GetMtxStackLevelPV(&PV_level));
+ while (G3X_GetMtxStackLevelPJ(&PJ_level));
+ SETREG32(HW_REG_MTX_MODE, 0x3);
+ SETREG32(HW_REG_MTX_IDENTITY, 0x0);
+ SETREG32(HW_REG_MTX_MODE, 0x0);
+ if (PJ_level)
+ {
+ SETREG32(HW_REG_MTX_POP, PJ_level);
+ }
+
+ SETREG32(HW_REG_MTX_MODE, 0x2);
+ SETREG32(HW_REG_MTX_POP, PV_level);
+ SETREG32(HW_REG_MTX_IDENTITY, 0x0);
+
+}
+
+void G3X_SetFog(u32 enable, u32 alphamode, u32 depth, s32 offset){
+ if (enable)
+ {
+ SETREG16(HW_REG_FOG_OFFSET, offset);
+ SETREG16(HW_REG_DISP3DCNT, (READREG16(HW_REG_DISP3DCNT) &~0x3f40) | (((depth << 0x8)| (alphamode << 0x6)|0x80 )));
+
+ }
+ else
+ {
+ SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & (u16)~0x3080);
+ }
+}
+
+u32 G3X_GetClipMtx(struct Mtx44 *dst){
+ if (READREG32(HW_REG_GXSTAT) & 0x8000000)
+ {
+ return -1;
+ }
+ else
+ {
+ MI_Copy64B((void *)HW_REG_CLIPMTX_RESULT, dst);
+ return 0;
+ }
+}
+
+u32 G3X_GetVectorMtx(struct Mtx33 *dst){
+ if (READREG32(HW_REG_GXSTAT) & 0x8000000)
+ {
+ return -1;
+ }
+ else
+ {
+ MI_Copy36B((void *)HW_REG_VECMTX_RESULT, dst);
+ return 0;
+ }
+}
+
+void G3X_SetEdgeColorTable(void *tbl_ptr){
+ MIi_CpuCopy16(tbl_ptr, (void *)HW_REG_EDGE_COLOR, 0x10);
+}
+
+void G3X_SetFogTable(void *tbl_ptr){
+ MI_Copy16B(tbl_ptr, (void *)HW_REG_FOG_TABLE);
+}
+
+void G3X_SetClearColor(u32 col, u32 alpha, u32 depth, u32 polygon_id, u32 enable_fog){
+ u32 temp = col | (alpha << 0x10) | (polygon_id << 0x18);
+ if (enable_fog)
+ temp |= 0x8000;
+ SETREG32(HW_REG_CLEAR_COLOR, temp);
+ SETREG16(HW_REG_CLEAR_DEPTH, depth);
+}
+
+void G3X_InitTable(){
+ if (gUnk02106814 != -1)
+ {
+ MI_DmaFill32Async(gUnk02106814, (void *)HW_REG_EDGE_COLOR, 0x0, 0x10, 0x0, 0x0);
+ MI_DmaFill32(gUnk02106814, (void *)HW_REG_FOG_TABLE, 0x0, 0x60);
+ }
+ else
+ {
+ MIi_CpuClear32(0x0, (void *)HW_REG_EDGE_COLOR, 0x10);
+ MIi_CpuClear32(0x0, (void *)HW_REG_FOG_TABLE, 0x60);
+ }
+ for (int i = 0; i < 0x20; i++)
+ {
+ SETREG32(HW_REG_SHININESS, 0x0);
+ }
+}
+
+u32 G3X_GetMtxStackLevelPV(u32 *level){
+ if (READREG32(HW_REG_GXSTAT) & 0x4000)
+ {
+ return -1;
+ }
+ else
+ {
+ *level = (READREG32(HW_REG_GXSTAT) & 0x1F00) >> 0x8;
+ return 0;
+ }
+}
+
+u32 G3X_GetMtxStackLevelPJ(u32 *level){
+ if (READREG32(HW_REG_GXSTAT) & 0x4000)
+ {
+ return -1;
+ }
+ else
+ {
+ *level = (READREG32(HW_REG_GXSTAT) & 0x2000) >> 0xD;
+ return 0;
+ }
+}
+
+u32 G3X_GetBoxTestResult(u32 *result){
+ if (READREG32(HW_REG_GXSTAT) & 0x1)
+ {
+ return -1;
+ }
+ else
+ {
+ *result = (READREG32(HW_REG_GXSTAT) & 0x2);
+ return 0;
+ }
+}
+
+void G3X_SetHOffset(u32 offset){
+ SETREG32(HW_REG_BG0HOFS, offset);
+}
diff --git a/arm9/lib/src/GX_vramcnt_c.c b/arm9/lib/src/GX_vramcnt_c.c
new file mode 100644
index 00000000..50107888
--- /dev/null
+++ b/arm9/lib/src/GX_vramcnt_c.c
@@ -0,0 +1,24 @@
+#include "global.h"
+#include "main.h"
+#include "gx.h"
+
+void GX_VRAMCNT_SetLCDC_(u32 r0){
+ if (r0 & (0x1 << 0))
+ SETREG8(HW_REG_VRAMCNT_A, 0x80);
+ if (r0 & (0x1 << 1))
+ SETREG8(HW_REG_VRAMCNT_B, 0x80);
+ if (r0 & (0x1 << 2))
+ SETREG8(HW_REG_VRAMCNT_C, 0x80);
+ if (r0 & (0x1 << 3))
+ SETREG8(HW_REG_VRAMCNT_D, 0x80);
+ if (r0 & (0x1 << 4))
+ SETREG8(HW_REG_VRAMCNT_E, 0x80);
+ if (r0 & (0x1 << 5))
+ SETREG8(HW_REG_VRAMCNT_F, 0x80);
+ if (r0 & (0x1 << 6))
+ SETREG8(HW_REG_VRAMCNT_G, 0x80);
+ if (r0 & (0x1 << 7))
+ SETREG8(HW_REG_VRAMCNT_H, 0x80);
+ if (r0 & (0x1 << 8))
+ SETREG8(HW_REG_VRAMCNT_I, 0x80);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-11 17:03:54 +0000