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-rw-r--r--arm9/lib/include/MI_dma.h61
-rw-r--r--arm9/lib/include/gx.h8
-rw-r--r--arm9/lib/src/MI_dma.c307
3 files changed, 368 insertions, 8 deletions
diff --git a/arm9/lib/include/MI_dma.h b/arm9/lib/include/MI_dma.h
index 15dc2c06..e8938ef9 100644
--- a/arm9/lib/include/MI_dma.h
+++ b/arm9/lib/include/MI_dma.h
@@ -2,7 +2,68 @@
#define POKEDIAMOND_ARM9_MI_DMA_H
#include "nitro/MI_dma_shared.h"
+#include "consts.h"
+#include "OS_system.h"
typedef void (*MIDmaCallback)(void *);
+#define REG_ADDR_DMA0CNT 0x40000b8
+#define REG_ADDR_DMA0_CLR_DATA 0x40000e0
+
+#define MI_CNT_CLEAR32(size) (0x85000000 | ((size)/4))
+#define MI_CNT_CLEAR32_IF(size) (0xc5000000 | ((size)/4))
+#define MI_CNT_COPY32(size) (0x84000000 | ((size)/4))
+#define MI_CNT_COPY32_IF(size) (0xc4000000 | ((size)/4))
+#define MI_CNT_COPY16(size) (0x80000000 | ((size)/2))
+
+typedef union
+{
+ u32 b32;
+ u16 b16;
+} MIiDmaClearSrc;
+
+void MI_DmaFill32(u32 dmaNo, void *dest, u32 data, u32 size);
+void MI_DmaCopy32(u32 dmaNo, const void *src, void *dest, u32 size);
+void MI_DmaCopy16(u32 dmaNo, const void *src, void *dest, u32 size);
+void MI_DmaFill32Async(u32 dmaNo, void *dest, u32 data, u32 size, MIDmaCallback callback, void *arg);
+void MI_DmaCopy32Async(u32 dmaNo, const void *src, void *dest, u32 size, MIDmaCallback callback, void *arg);
+void MI_WaitDma(u32 dmaNo);
+void MI_StopDma(u32 dmaNo);
+void MIi_CheckAnotherAutoDMA(u32 dmaNo, u32 dmaType);
+void MIi_CheckDma0SourceAddress(u32 dmaNo, u32 src, u32 size, u32 dir);
+void MIi_DmaSetParams(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
+void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
+void MIi_DmaSetParams_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
+void MIi_DmaSetParams_wait_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
+
+static inline void MIi_DmaSetParams_wait_src32(u32 dmaNo, u32 data, u32 dest, u32 ctrl)
+{
+ OSIntrMode lastIntrMode = OS_DisableInterrupts();
+
+ MIiDmaClearSrc *scrp = (MIiDmaClearSrc *) ((u32)REG_ADDR_DMA0_CLR_DATA + dmaNo * 4);
+ scrp->b32 = data;
+ MIi_DmaSetParams_wait_noInt(dmaNo, (u32)scrp, dest, ctrl);
+
+ (void)OS_RestoreInterrupts(lastIntrMode);
+}
+
+static inline void MIi_DmaSetParams_src32(u32 dmaNo, u32 data, u32 dest, u32 ctrl)
+{
+ OSIntrMode lastIntrMode = OS_DisableInterrupts();
+
+ MIiDmaClearSrc *srcp = (MIiDmaClearSrc *) ((u32)REG_ADDR_DMA0_CLR_DATA + dmaNo * 4);
+ srcp->b32 = data;
+ MIi_DmaSetParams_noInt(dmaNo, (u32)srcp, dest, ctrl);
+
+ (void)OS_RestoreInterrupts(lastIntrMode);
+}
+
+static inline void MIi_CallCallback(MIDmaCallback callback, void *arg)
+{
+ if (callback)
+ {
+ (callback) (arg);
+ }
+}
+
#endif //POKEDIAMOND_ARM9_MI_DMA_H
diff --git a/arm9/lib/include/gx.h b/arm9/lib/include/gx.h
index f1c9fa50..bc89aa04 100644
--- a/arm9/lib/include/gx.h
+++ b/arm9/lib/include/gx.h
@@ -9,17 +9,9 @@
void GXi_NopClearFifo128_(void *);
void MI_Copy16B(const void *, void *);
-void MI_DmaFill32Async(u32, void *, u32, u32, u32, u32);
-void MI_DmaFill32(u32, void *, u32, u32);
-void MIi_CpuClear32(u32, void *, u32);
void MI_Copy64B(void *src, void *dst);
-void MI_WaitDma(u32);
-void MI_DmaCopy32Async(u32, const void *, void *, u32, void *, void *);
-void MI_DmaCopy16(u32 unk, const void *src, void *dst, u32 size);
-void MI_DmaCopy32(u32 unk, const void *src, void *dst, u32 size);
void MIi_CpuCopy32(const void *src, void *dst, u32 size);
void OSi_UnlockVram(u16, u16);
-void MIi_CpuClear32(u32, void *, u32);
#include "GXcommon.h"
#include "GX_struct_2d.h"
diff --git a/arm9/lib/src/MI_dma.c b/arm9/lib/src/MI_dma.c
new file mode 100644
index 00000000..565b1ef6
--- /dev/null
+++ b/arm9/lib/src/MI_dma.c
@@ -0,0 +1,307 @@
+#include "MI_dma.h"
+#include "function_target.h"
+#include "OS_interrupt.h"
+#include "OS_terminate_proc.h"
+#include "sections.h"
+
+#pragma section ITCM begin
+ARM_FUNC void MIi_DmaSetParams(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
+{
+ OSIntrMode lastIntrMode = OS_DisableInterrupts();
+ vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
+ *p = (vu32)src;
+ *(p + 1) = (vu32)dest;
+ *(p + 2) = (vu32)ctrl;
+ (void)OS_RestoreInterrupts(lastIntrMode);
+}
+
+ARM_FUNC void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
+{
+ OSIntrMode enabled = OS_DisableInterrupts();
+ vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
+ *p = (vu32)src;
+ *(p + 1) = (vu32)dest;
+ *(p + 2) = (vu32)ctrl;
+
+ //delay cycles
+ {
+ u32 delay = reg_MI_DMA0SAD;
+ }
+ {
+ u32 delay = reg_MI_DMA0SAD;
+ }
+
+ if (!dmaNo)
+ {
+ *p = (vu32)0;
+ *(p + 1) = (vu32)0;
+ *(p + 2) = (vu32)0x81400001;
+ }
+
+ (void)OS_RestoreInterrupts(enabled);
+}
+
+ARM_FUNC void MIi_DmaSetParams_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
+{
+ vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
+ *p = (vu32)src;
+ *(p + 1) = (vu32)dest;
+ *(p + 2) = (vu32)ctrl;
+}
+
+ARM_FUNC void MIi_DmaSetParams_wait_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
+{
+ vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
+ *p = (vu32)src;
+ *(p + 1) = (vu32)dest;
+ *(p + 2) = (vu32)ctrl;
+
+ //delay cycles
+ {
+ u32 delay = reg_MI_DMA0SAD;
+ }
+ {
+ u32 delay = reg_MI_DMA0SAD;
+ }
+
+ if (!dmaNo)
+ {
+ *p = (vu32)0;
+ *(p + 1) = (vu32)0;
+ *(p + 2) = (vu32)0x81400001;
+ }
+
+ //delay cycles
+ {
+ u32 delay = reg_MI_DMA0SAD;
+ }
+ {
+ u32 delay = reg_MI_DMA0SAD;
+ }
+}
+#pragma section ITCM end
+
+ARM_FUNC void MI_DmaFill32(u32 dmaNo, void *dest, u32 data, u32 size)
+{
+ vu32 *dmaCntp;
+ if (!size)
+ {
+ return;
+ }
+
+ do
+ {
+ dmaCntp = &((vu32 *)REG_ADDR_DMA0SAD)[dmaNo * 3 + 2];
+ while (*dmaCntp & 0x80000000) {}
+ } while(0);
+
+ MIi_DmaSetParams_wait_src32(dmaNo, data, (u32)dest, MI_CNT_CLEAR32(size));
+
+ do
+ {
+ while (*dmaCntp & 0x80000000) {}
+ } while(0);
+}
+
+ARM_FUNC void MI_DmaCopy32(u32 dmaNo, const void *src, void *dest, u32 size)
+{
+ vu32 *dmaCntp;
+ MIi_CheckDma0SourceAddress(dmaNo, (u32)src, size, DMA_SRC_INC);
+
+ if (!size)
+ {
+ return;
+ }
+
+ do
+ {
+ dmaCntp = &((vu32 *)REG_ADDR_DMA0SAD)[dmaNo * 3 + 2];
+ while (*dmaCntp & 0x80000000) {}
+ } while(0);
+
+ MIi_DmaSetParams_wait(dmaNo, (u32)src, (u32)dest, MI_CNT_COPY32(size));
+
+ do
+ {
+ while (*dmaCntp & 0x80000000) {}
+ } while(0);
+}
+
+ARM_FUNC void MI_DmaCopy16(u32 dmaNo, const void *src, void *dest, u32 size)
+{
+ vu32 *dmaCntp;
+
+ if (!size)
+ {
+ return;
+ }
+
+ MIi_CheckDma0SourceAddress(dmaNo, (u32)src, size, DMA_SRC_INC);
+
+ do
+ {
+ dmaCntp = &((vu32 *)REG_ADDR_DMA0SAD)[dmaNo * 3 + 2];
+ while (*dmaCntp & 0x80000000) {}
+ } while(0);
+
+ MIi_DmaSetParams_wait(dmaNo, (u32)src, (u32)dest, MI_CNT_COPY16(size));
+
+ do
+ {
+ while (*dmaCntp & 0x80000000) {}
+ } while(0);
+}
+
+ARM_FUNC void MI_DmaFill32Async(u32 dmaNo, void *dest, u32 data, u32 size, MIDmaCallback callback, void *arg)
+{
+ if (!size)
+ {
+ MIi_CallCallback(callback, arg);
+ }
+ else
+ {
+ MI_WaitDma(dmaNo);
+
+ if (callback)
+ {
+ OSi_EnterDmaCallback(dmaNo, callback, arg);
+ MIi_DmaSetParams_src32(dmaNo, data, (u32)dest, MI_CNT_CLEAR32_IF(size));
+ }
+ else
+ {
+ MIi_DmaSetParams_src32(dmaNo, data, (u32)dest, MI_CNT_CLEAR32(size));
+ }
+ }
+}
+
+ARM_FUNC void MI_DmaCopy32Async(u32 dmaNo, const void *src, void *dest, u32 size, MIDmaCallback callback, void *arg)
+{
+ MIi_CheckDma0SourceAddress(dmaNo, (u32)src, size, DMA_SRC_INC);
+
+ if (!size)
+ {
+ MIi_CallCallback(callback, arg);
+ }
+ else
+ {
+ MI_WaitDma(dmaNo);
+
+ if (callback)
+ {
+ OSi_EnterDmaCallback(dmaNo, callback, arg);
+ MIi_DmaSetParams(dmaNo, (u32)src, (u32)dest, MI_CNT_COPY32_IF(size));
+ }
+ else
+ {
+ MIi_DmaSetParams(dmaNo, (u32)src, (u32)dest, MI_CNT_COPY32(size));
+ }
+ }
+}
+
+ARM_FUNC void MI_WaitDma(u32 dmaNo)
+{
+ OSIntrMode lastIntrMode = OS_DisableInterrupts();
+ vu32 *dmaCntp = &((vu32 *)REG_ADDR_DMA0SAD)[dmaNo * 3 + 2];
+
+ while (*dmaCntp & 0x80000000) {}
+
+ if (!dmaNo)
+ {
+ vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
+ *p = (vu32)0;
+ *(p + 1) = (vu32)0;
+ *(p + 2) = (vu32)0x81400001;
+ }
+
+ (void)OS_RestoreInterrupts(lastIntrMode);
+}
+
+ARM_FUNC void MI_StopDma(u32 dmaNo)
+{
+ OSIntrMode lastIntrMode = OS_DisableInterrupts();
+ vu16 *dmaCntp = &((vu16 *)REG_ADDR_DMA0SAD)[dmaNo * 6 + 5];
+
+ *dmaCntp &= ~0x3a00;
+ *dmaCntp &= ~0x8000;
+
+ //delay cycles
+ {
+ s32 delay = dmaCntp[0];
+ }
+ {
+ s32 delay = dmaCntp[0];
+ }
+
+ if (!dmaNo)
+ {
+ vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
+ *p = (vu32)0;
+ *(p + 1) = (vu32)0;
+ *(p + 2) = (vu32)0x81400001;
+ }
+
+ (void)OS_RestoreInterrupts(lastIntrMode);
+}
+
+ARM_FUNC void MIi_CheckAnotherAutoDMA(u32 dmaNo, u32 dmaType)
+{
+ u32 dmaCnt;
+ u32 timing;
+ for (int i = 0; i < 3; i++)
+ {
+ if (i == dmaNo) continue;
+
+ dmaCnt = *(REGType32v *)(REG_ADDR_DMA0CNT + i * 12);
+
+ if (!(dmaCnt & 0x80000000)) continue;
+
+ timing = dmaCnt & 0x38000000;
+
+ if (timing == dmaType
+ || (timing == 0x8000000 && dmaType == 0x10000000)
+ || (timing == 0x10000000 && dmaType == 0x8000000))
+ {
+ continue;
+ }
+
+ if (timing == 0x18000000
+ || timing == 0x20000000
+ || timing == 0x28000000
+ || timing == 0x30000000
+ || timing == 0x38000000
+ || timing == 0x8000000
+ || timing == 0x10000000)
+ {
+ OS_Terminate();
+ }
+ }
+}
+
+ARM_FUNC void MIi_CheckDma0SourceAddress(u32 dmaNo, u32 src, u32 size, u32 dir)
+{
+ if (!dmaNo)
+ {
+ u32 addStart = src & 0xff000000;
+ u32 addEnd;
+
+ switch (dir)
+ {
+ case 0: //dma_src_inc
+ addEnd = src + size;
+ break;
+ case 0x800000: //dma_src_dec
+ addEnd = src - size;
+ break;
+ default:
+ addEnd = src;
+ break;
+ }
+ addEnd &= 0xff000000;
+
+ if (addStart == 0x04000000 || addStart >= 0x08000000 ||
+ addEnd == 0x04000000 || addEnd >= 0x08000000)
+ {
+ OS_Terminate();
+ }
+ }
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-04 16:42:06 +0000