From e508916babf251f7ed4c26f45964cdecf20f00ce Mon Sep 17 00:00:00 2001 From: Egor Ananyin Date: Fri, 12 Jun 2020 19:24:29 +0300 Subject: Decompile (?) some of MI --- arm7/lib/src/MI_memory.c | 219 +++++++++++++++++++++++++++++++++++++++++++++++ arm7/lib/src/MI_swap.c | 6 ++ 2 files changed, 225 insertions(+) create mode 100644 arm7/lib/src/MI_memory.c create mode 100644 arm7/lib/src/MI_swap.c (limited to 'arm7/lib/src') diff --git a/arm7/lib/src/MI_memory.c b/arm7/lib/src/MI_memory.c new file mode 100644 index 00000000..51a0f33e --- /dev/null +++ b/arm7/lib/src/MI_memory.c @@ -0,0 +1,219 @@ +#include "function_target.h" +#include "MI_memory.h" + +asm void MIi_CpuClear16(register u16 value, register u16 * dst, register u32 size) { + mov r3, #0 +loop: + cmp r3, r2 + strlth r0, [r1, r3] + addlt r3, r3, #2 + blt loop + bx lr +} + +asm void MIi_CpuCopy16(register u16 * src, register u16 * dst, register u32 size) { + mov ip, #0 +_037FB31C: + cmp ip, r2 + ldrlth r3, [r0, ip] + strlth r3, [r1, ip] + addlt ip, ip, #2 + blt _037FB31C + bx lr +} + +asm void MIi_CpuClear32(register u32 value, register u32 * dst, register u32 size) { + add ip, r1, r2 +_037FB338: + cmp r1, ip + stmltia r1!, {r0} + blt _037FB338 + bx lr +} + +asm void MIi_CpuCopy32(register u32 * src, register u32 * dst, register u32 size) { + add ip, r1, r2 +_037FB34C: + cmp r1, ip + ldmltia r0!, {r2} + stmltia r1!, {r2} + blt _037FB34C + bx lr +} + +asm void MIi_CpuClearFast(register u32 value, register u32 * dst, register u32 size) { + stmdb sp!, {r4, r5, r6, r7, r8, r9} + add r9, r1, r2 + mov ip, r2, lsr #5 + add ip, r1, ip, lsl #5 + mov r2, r0 + mov r3, r2 + mov r4, r2 + mov r5, r2 + mov r6, r2 + mov r7, r2 + mov r8, r2 +_037FB38C: + cmp r1, ip + stmltia r1!, {r0, r2, r3, r4, r5, r6, r7, r8} + blt _037FB38C +_037FB398: + cmp r1, r9 + stmltia r1!, {r0} + blt _037FB398 + ldmia sp!, {r4, r5, r6, r7, r8, r9} + bx lr +} + +asm void MIi_CpuCopyFast(register u32 * src, register u32 * dst, register u32 size) { + stmdb sp!, {r4-r9, r10} + add r10, r1, r2 + mov ip, r2, lsr #5 + add ip, r1, ip, lsl #5 +_037FB3BC: + cmp r1, ip + ldmltia r0!, {r2-r9} + stmltia r1!, {r2-r9} + blt _037FB3BC +_037FB3CC: + cmp r1, r10 + ldmltia r0!, {r2} + stmltia r1!, {r2} + blt _037FB3CC + ldmia sp!, {r4-r9, r10} + bx lr +} + +asm void MI_CpuFill8(register u8 value, register u8 * dst, register u32 size) { + cmp r2, #0 + bxeq lr + tst r0, #1 + beq _037FB410 + ldrh ip, [r0, #-1] + and ip, ip, #0xff + orr r3, ip, r1, lsl #8 + strh r3, [r0, #-1] + add r0, r0, #1 + subs r2, r2, #1 + bxeq lr +_037FB410: + cmp r2, #2 + bcc _037FB458 + orr r1, r1, r1, lsl #8 + tst r0, #2 + beq _037FB430 + strh r1, [r0], #2 + subs r2, r2, #2 + bxeq lr +_037FB430: + orr r1, r1, r1, lsl #16 + bics r3, r2, #3 + beq _037FB450 + sub r2, r2, r3 + add ip, r3, r0 +_037FB444: + str r1, [r0], #4 + cmp r0, ip + bcc _037FB444 +_037FB450: + tst r2, #2 + strneh r1, [r0], #2 +_037FB458: + tst r2, #1 + bxeq lr + ldrh r3, [r0] + and r3, r3, #0xff00 + and r1, r1, #0xff + orr r1, r1, r3 + strh r1, [r0] + bx lr +} + +asm void MI_CpuCopy8(register u8 * src, register u8 * dst, register u32 size) { + cmp r2, #0 + bxeq lr + tst r1, #1 + beq _037FB4B8 + ldrh ip, [r1, #-1] + and ip, ip, #0xff + tst r0, #1 + ldrneh r3, [r0, #-1] + movne r3, r3, lsr #8 + ldreqh r3, [r0] + orr r3, ip, r3, lsl #8 + strh r3, [r1, #-1] + add r0, r0, #1 + add r1, r1, #1 + subs r2, r2, #1 + bxeq lr +_037FB4B8: + eor ip, r1, r0 + tst ip, #1 + beq _037FB50C + bic r0, r0, #1 + ldrh ip, [r0], #2 + mov r3, ip, lsr #8 + subs r2, r2, #2 + bcc _037FB4F0 +_037FB4D8: + ldrh ip, [r0], #2 + orr ip, r3, ip, lsl #8 + strh ip, [r1], #2 + mov r3, ip, lsr #16 + subs r2, r2, #2 + bcs _037FB4D8 +_037FB4F0: + tst r2, #1 + bxeq lr + ldrh ip, [r1] + and ip, ip, #0xff00 + orr ip, ip, r3 + strh ip, [r1] + bx lr +_037FB50C: + tst ip, #2 + beq _037FB538 + bics r3, r2, #1 + beq _037FB584 + sub r2, r2, r3 + add ip, r3, r1 +_037FB524: + ldrh r3, [r0], #2 + strh r3, [r1], #2 + cmp r1, ip + bcc _037FB524 + b _037FB584 +_037FB538: + cmp r2, #2 + bcc _037FB584 + tst r1, #2 + beq _037FB558 + ldrh r3, [r0], #2 + strh r3, [r1], #2 + subs r2, r2, #2 + bxeq lr +_037FB558: + bics r3, r2, #3 + beq _037FB578 + sub r2, r2, r3 + add ip, r3, r1 +_037FB568: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r1, ip + bcc _037FB568 +_037FB578: + tst r2, #2 + ldrneh r3, [r0], #2 + strneh r3, [r1], #2 +_037FB584: + tst r2, #1 + bxeq lr + ldrh r2, [r1] + ldrh r0, [r0] + and r2, r2, #0xff00 + and r0, r0, #0xff + orr r0, r2, r0 + strh r0, [r1] + bx lr +} diff --git a/arm7/lib/src/MI_swap.c b/arm7/lib/src/MI_swap.c new file mode 100644 index 00000000..87a64060 --- /dev/null +++ b/arm7/lib/src/MI_swap.c @@ -0,0 +1,6 @@ +#include "MI_swap.h" + +asm u32 MI_SwapWord(register u32 data, register u32 * dst) { + swp r0, r0, [r1] + bx lr +} -- cgit v1.2.3 From 5c34c97254b35f93d9254e63265446f9f7d50817 Mon Sep 17 00:00:00 2001 From: red031000 Date: Fri, 12 Jun 2020 18:08:19 +0100 Subject: arm7 OS_reset --- arm7/lib/src/OS_init.c | 1 - arm7/lib/src/OS_reset.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 arm7/lib/src/OS_reset.c (limited to 'arm7/lib/src') diff --git a/arm7/lib/src/OS_init.c b/arm7/lib/src/OS_init.c index f4972638..583bb75e 100644 --- a/arm7/lib/src/OS_init.c +++ b/arm7/lib/src/OS_init.c @@ -7,7 +7,6 @@ extern void OS_InitIrqTable(void); extern void OS_InitTick(void); extern void OS_InitAlarm(void); extern void OS_InitThread(void); -extern void OS_InitReset(void); extern void CTRDG_Init(void); ARM_FUNC void OS_Init(void) diff --git a/arm7/lib/src/OS_reset.c b/arm7/lib/src/OS_reset.c new file mode 100644 index 00000000..c40fcff3 --- /dev/null +++ b/arm7/lib/src/OS_reset.c @@ -0,0 +1,59 @@ +#include "function_target.h" +#include "OS_reset.h" +#include "OS_interrupt.h" + +static u16 OSi_IsInitReset = 0; +vu16 OSi_IsResetOccurred = 0; + +extern void MI_StopDma(u32 dma); +extern OSIrqMask OS_SetIrqMask(OSIrqMask mask); +extern OSIrqMask OS_ResetRequestIrqMask(OSIrqMask mask); +extern void SND_Shutdown(void); +extern void PXI_SetFifoRecvCallback(u32 param1, void* callback); +extern void OS_Terminate(void); +extern u32 PXI_SendWordByFifo(u32 param1, u32 data, u32 param2); +extern void FUN_038073EC(void); //OSi_DoResetSystem, in wram + +ARM_FUNC void OS_InitReset(void) +{ + if (OSi_IsInitReset) + return; + OSi_IsInitReset = TRUE; + + PXI_SetFifoRecvCallback(PXI_FIFO_TAG_OS, OSi_CommonCallback); +} + +ARM_FUNC BOOL OS_IsResetOccurred(void) +{ + return OSi_IsResetOccurred; +} + +ARM_FUNC static void OSi_CommonCallback(PXIFifoTag tag, u32 data, BOOL err) +{ +#pragma unused(tag, err) + u16 command = (u16)((data & OS_PXI_COMMAND_MASK) >> OS_PXI_COMMAND_SHIFT); + if (command == OS_PXI_COMMAND_RESET) + { + OSi_IsResetOccurred = TRUE; + return; + } + OS_Terminate(); +} + +ARM_FUNC static void OSi_SendToPxi(u16 data) +{ + while (PXI_SendWordByFifo(PXI_FIFO_TAG_OS, (u32) data << 0x8, FALSE)) {} +} + +ARM_FUNC void OS_ResetSystem(void) { + MI_StopDma(0); + MI_StopDma(1); + MI_StopDma(2); + MI_StopDma(3); + + (void)OS_SetIrqMask(0x40000); + (void)OS_ResetRequestIrqMask((u32)~0); + SND_Shutdown(); + OSi_SendToPxi(OS_PXI_COMMAND_RESET); + FUN_038073EC(); //OSi_DoResetSystem, in wram +} -- cgit v1.2.3 From 870046733d4b15ee55566114aad3367dbe09e37d Mon Sep 17 00:00:00 2001 From: Egor Ananyin Date: Fri, 12 Jun 2020 20:23:15 +0300 Subject: Decompile MI_dma.c --- arm7/lib/src/MI_dma.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 arm7/lib/src/MI_dma.c (limited to 'arm7/lib/src') diff --git a/arm7/lib/src/MI_dma.c b/arm7/lib/src/MI_dma.c new file mode 100644 index 00000000..fc2ff0c9 --- /dev/null +++ b/arm7/lib/src/MI_dma.c @@ -0,0 +1,36 @@ +#include "function_target.h" +#include "MI_dma.h" +#include "OS_system.h" + +ARM_FUNC void MI_WaitDma(u32 channel) { + OSIntrMode mode = OS_DisableInterrupts(); + vu32 * addr = (vu32 *)(REG_ADDR_DMA0SAD + (channel * 3 + 2) * 4); + while(addr[0] & 0x80000000) ; + if (channel == 0) { + addr = (vu32 *)(REG_ADDR_DMA0SAD + channel * 12); + addr[0] = 0; + addr[1] = 0; + addr[2] = 0x81400001; + } + mode = OS_RestoreInterrupts(mode); +} + +ARM_FUNC void MI_StopDma(u32 channel) { + OSIntrMode mode = OS_DisableInterrupts(); + vu16 * addr = (vu16 *)(REG_ADDR_DMA0SAD + (channel * 6 + 5) * 2); + addr[0] &= ~(DMA_START_MASK | DMA_REPEAT); + addr[0] &= ~DMA_ENABLE; + { + s32 dummy = addr[0]; + } + { + s32 dummy = addr[0]; + } + if (channel == 0) { + vu32 * addr32 = (vu32 *)(REG_ADDR_DMA0SAD + channel * 12); + addr32[0] = 0; + addr32[1] = 0; + addr32[2] = 0x81400001; + } + mode = OS_RestoreInterrupts(mode); +} -- cgit v1.2.3 From 3e4255a382f593fc75d786b4a0e33a46bf7af7c5 Mon Sep 17 00:00:00 2001 From: Egor Ananyin Date: Fri, 12 Jun 2020 20:38:13 +0300 Subject: Tabs to spaces --- arm7/lib/src/MI_memory.c | 340 +++++++++++++++++++++++------------------------ arm7/lib/src/MI_swap.c | 2 +- 2 files changed, 171 insertions(+), 171 deletions(-) (limited to 'arm7/lib/src') diff --git a/arm7/lib/src/MI_memory.c b/arm7/lib/src/MI_memory.c index 51a0f33e..acb982a4 100644 --- a/arm7/lib/src/MI_memory.c +++ b/arm7/lib/src/MI_memory.c @@ -4,216 +4,216 @@ asm void MIi_CpuClear16(register u16 value, register u16 * dst, register u32 size) { mov r3, #0 loop: - cmp r3, r2 - strlth r0, [r1, r3] - addlt r3, r3, #2 - blt loop - bx lr + cmp r3, r2 + strlth r0, [r1, r3] + addlt r3, r3, #2 + blt loop + bx lr } asm void MIi_CpuCopy16(register u16 * src, register u16 * dst, register u32 size) { - mov ip, #0 + mov ip, #0 _037FB31C: - cmp ip, r2 - ldrlth r3, [r0, ip] - strlth r3, [r1, ip] - addlt ip, ip, #2 - blt _037FB31C - bx lr + cmp ip, r2 + ldrlth r3, [r0, ip] + strlth r3, [r1, ip] + addlt ip, ip, #2 + blt _037FB31C + bx lr } asm void MIi_CpuClear32(register u32 value, register u32 * dst, register u32 size) { - add ip, r1, r2 + add ip, r1, r2 _037FB338: - cmp r1, ip - stmltia r1!, {r0} - blt _037FB338 - bx lr + cmp r1, ip + stmltia r1!, {r0} + blt _037FB338 + bx lr } asm void MIi_CpuCopy32(register u32 * src, register u32 * dst, register u32 size) { - add ip, r1, r2 + add ip, r1, r2 _037FB34C: - cmp r1, ip - ldmltia r0!, {r2} - stmltia r1!, {r2} - blt _037FB34C - bx lr + cmp r1, ip + ldmltia r0!, {r2} + stmltia r1!, {r2} + blt _037FB34C + bx lr } asm void MIi_CpuClearFast(register u32 value, register u32 * dst, register u32 size) { - stmdb sp!, {r4, r5, r6, r7, r8, r9} - add r9, r1, r2 - mov ip, r2, lsr #5 - add ip, r1, ip, lsl #5 - mov r2, r0 - mov r3, r2 - mov r4, r2 - mov r5, r2 - mov r6, r2 - mov r7, r2 - mov r8, r2 + stmdb sp!, {r4, r5, r6, r7, r8, r9} + add r9, r1, r2 + mov ip, r2, lsr #5 + add ip, r1, ip, lsl #5 + mov r2, r0 + mov r3, r2 + mov r4, r2 + mov r5, r2 + mov r6, r2 + mov r7, r2 + mov r8, r2 _037FB38C: - cmp r1, ip - stmltia r1!, {r0, r2, r3, r4, r5, r6, r7, r8} - blt _037FB38C + cmp r1, ip + stmltia r1!, {r0, r2, r3, r4, r5, r6, r7, r8} + blt _037FB38C _037FB398: - cmp r1, r9 - stmltia r1!, {r0} - blt _037FB398 - ldmia sp!, {r4, r5, r6, r7, r8, r9} - bx lr + cmp r1, r9 + stmltia r1!, {r0} + blt _037FB398 + ldmia sp!, {r4, r5, r6, r7, r8, r9} + bx lr } asm void MIi_CpuCopyFast(register u32 * src, register u32 * dst, register u32 size) { - stmdb sp!, {r4-r9, r10} - add r10, r1, r2 - mov ip, r2, lsr #5 - add ip, r1, ip, lsl #5 + stmdb sp!, {r4-r9, r10} + add r10, r1, r2 + mov ip, r2, lsr #5 + add ip, r1, ip, lsl #5 _037FB3BC: - cmp r1, ip - ldmltia r0!, {r2-r9} - stmltia r1!, {r2-r9} - blt _037FB3BC + cmp r1, ip + ldmltia r0!, {r2-r9} + stmltia r1!, {r2-r9} + blt _037FB3BC _037FB3CC: - cmp r1, r10 - ldmltia r0!, {r2} - stmltia r1!, {r2} - blt _037FB3CC - ldmia sp!, {r4-r9, r10} - bx lr + cmp r1, r10 + ldmltia r0!, {r2} + stmltia r1!, {r2} + blt _037FB3CC + ldmia sp!, {r4-r9, r10} + bx lr } asm void MI_CpuFill8(register u8 value, register u8 * dst, register u32 size) { - cmp r2, #0 - bxeq lr - tst r0, #1 - beq _037FB410 - ldrh ip, [r0, #-1] - and ip, ip, #0xff - orr r3, ip, r1, lsl #8 - strh r3, [r0, #-1] - add r0, r0, #1 - subs r2, r2, #1 - bxeq lr + cmp r2, #0 + bxeq lr + tst r0, #1 + beq _037FB410 + ldrh ip, [r0, #-1] + and ip, ip, #0xff + orr r3, ip, r1, lsl #8 + strh r3, [r0, #-1] + add r0, r0, #1 + subs r2, r2, #1 + bxeq lr _037FB410: - cmp r2, #2 - bcc _037FB458 - orr r1, r1, r1, lsl #8 - tst r0, #2 - beq _037FB430 - strh r1, [r0], #2 - subs r2, r2, #2 - bxeq lr + cmp r2, #2 + bcc _037FB458 + orr r1, r1, r1, lsl #8 + tst r0, #2 + beq _037FB430 + strh r1, [r0], #2 + subs r2, r2, #2 + bxeq lr _037FB430: - orr r1, r1, r1, lsl #16 - bics r3, r2, #3 - beq _037FB450 - sub r2, r2, r3 - add ip, r3, r0 + orr r1, r1, r1, lsl #16 + bics r3, r2, #3 + beq _037FB450 + sub r2, r2, r3 + add ip, r3, r0 _037FB444: - str r1, [r0], #4 - cmp r0, ip - bcc _037FB444 + str r1, [r0], #4 + cmp r0, ip + bcc _037FB444 _037FB450: - tst r2, #2 - strneh r1, [r0], #2 + tst r2, #2 + strneh r1, [r0], #2 _037FB458: - tst r2, #1 - bxeq lr - ldrh r3, [r0] - and r3, r3, #0xff00 - and r1, r1, #0xff - orr r1, r1, r3 - strh r1, [r0] - bx lr + tst r2, #1 + bxeq lr + ldrh r3, [r0] + and r3, r3, #0xff00 + and r1, r1, #0xff + orr r1, r1, r3 + strh r1, [r0] + bx lr } -asm void MI_CpuCopy8(register u8 * src, register u8 * dst, register u32 size) { - cmp r2, #0 - bxeq lr - tst r1, #1 - beq _037FB4B8 - ldrh ip, [r1, #-1] - and ip, ip, #0xff - tst r0, #1 - ldrneh r3, [r0, #-1] - movne r3, r3, lsr #8 - ldreqh r3, [r0] - orr r3, ip, r3, lsl #8 - strh r3, [r1, #-1] - add r0, r0, #1 - add r1, r1, #1 - subs r2, r2, #1 - bxeq lr +asm void MI_CpuCopy8(register u8 * src, register u8 * dst, u32 size) { + cmp r2, #0 + bxeq lr + tst r1, #1 + beq _037FB4B8 + ldrh ip, [r1, #-1] + and ip, ip, #0xff + tst r0, #1 + ldrneh r3, [r0, #-1] + movne r3, r3, lsr #8 + ldreqh r3, [r0] + orr r3, ip, r3, lsl #8 + strh r3, [r1, #-1] + add r0, r0, #1 + add r1, r1, #1 + subs r2, r2, #1 + bxeq lr _037FB4B8: - eor ip, r1, r0 - tst ip, #1 - beq _037FB50C - bic r0, r0, #1 - ldrh ip, [r0], #2 - mov r3, ip, lsr #8 - subs r2, r2, #2 - bcc _037FB4F0 + eor ip, r1, r0 + tst ip, #1 + beq _037FB50C + bic r0, r0, #1 + ldrh ip, [r0], #2 + mov r3, ip, lsr #8 + subs r2, r2, #2 + bcc _037FB4F0 _037FB4D8: - ldrh ip, [r0], #2 - orr ip, r3, ip, lsl #8 - strh ip, [r1], #2 - mov r3, ip, lsr #16 - subs r2, r2, #2 - bcs _037FB4D8 + ldrh ip, [r0], #2 + orr ip, r3, ip, lsl #8 + strh ip, [r1], #2 + mov r3, ip, lsr #16 + subs r2, r2, #2 + bcs _037FB4D8 _037FB4F0: - tst r2, #1 - bxeq lr - ldrh ip, [r1] - and ip, ip, #0xff00 - orr ip, ip, r3 - strh ip, [r1] - bx lr + tst r2, #1 + bxeq lr + ldrh ip, [r1] + and ip, ip, #0xff00 + orr ip, ip, r3 + strh ip, [r1] + bx lr _037FB50C: - tst ip, #2 - beq _037FB538 - bics r3, r2, #1 - beq _037FB584 - sub r2, r2, r3 - add ip, r3, r1 + tst ip, #2 + beq _037FB538 + bics r3, r2, #1 + beq _037FB584 + sub r2, r2, r3 + add ip, r3, r1 _037FB524: - ldrh r3, [r0], #2 - strh r3, [r1], #2 - cmp r1, ip - bcc _037FB524 - b _037FB584 + ldrh r3, [r0], #2 + strh r3, [r1], #2 + cmp r1, ip + bcc _037FB524 + b _037FB584 _037FB538: - cmp r2, #2 - bcc _037FB584 - tst r1, #2 - beq _037FB558 - ldrh r3, [r0], #2 - strh r3, [r1], #2 - subs r2, r2, #2 - bxeq lr + cmp r2, #2 + bcc _037FB584 + tst r1, #2 + beq _037FB558 + ldrh r3, [r0], #2 + strh r3, [r1], #2 + subs r2, r2, #2 + bxeq lr _037FB558: - bics r3, r2, #3 - beq _037FB578 - sub r2, r2, r3 - add ip, r3, r1 + bics r3, r2, #3 + beq _037FB578 + sub r2, r2, r3 + add ip, r3, r1 _037FB568: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r1, ip - bcc _037FB568 + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r1, ip + bcc _037FB568 _037FB578: - tst r2, #2 - ldrneh r3, [r0], #2 - strneh r3, [r1], #2 + tst r2, #2 + ldrneh r3, [r0], #2 + strneh r3, [r1], #2 _037FB584: - tst r2, #1 - bxeq lr - ldrh r2, [r1] - ldrh r0, [r0] - and r2, r2, #0xff00 - and r0, r0, #0xff - orr r0, r2, r0 - strh r0, [r1] - bx lr + tst r2, #1 + bxeq lr + ldrh r2, [r1] + ldrh r0, [r0] + and r2, r2, #0xff00 + and r0, r0, #0xff + orr r0, r2, r0 + strh r0, [r1] + bx lr } diff --git a/arm7/lib/src/MI_swap.c b/arm7/lib/src/MI_swap.c index 87a64060..71e523f8 100644 --- a/arm7/lib/src/MI_swap.c +++ b/arm7/lib/src/MI_swap.c @@ -2,5 +2,5 @@ asm u32 MI_SwapWord(register u32 data, register u32 * dst) { swp r0, r0, [r1] - bx lr + bx lr } -- cgit v1.2.3