diff options
| -rw-r--r-- | asm/MetroTRK/dispatch.s | 92 | ||||
| -rw-r--r-- | asm/MetroTRK/flush_cache.s | 21 | ||||
| -rw-r--r-- | asm/MetroTRK/mainloop.s | 8 | ||||
| -rw-r--r-- | asm/MetroTRK/msg.s | 17 | ||||
| -rw-r--r-- | asm/MetroTRK/msgbuf.s | 624 | ||||
| -rw-r--r-- | asm/MetroTRK/msghndlr.s | 1202 | ||||
| -rw-r--r-- | asm/MetroTRK/mutex_TRK.s | 18 | ||||
| -rw-r--r-- | asm/MetroTRK/notify.s | 48 | ||||
| -rw-r--r-- | asm/MetroTRK/nubevent.s | 161 | ||||
| -rw-r--r-- | asm/MetroTRK/nubinit.s | 119 | ||||
| -rw-r--r-- | asm/MetroTRK/serpoll.s | 131 | ||||
| -rw-r--r-- | asm/MetroTRK/string_TRK.s | 14 | ||||
| -rw-r--r-- | asm/MetroTRK/support.s | 486 | ||||
| -rw-r--r-- | asm/MetroTRK/targimpl.s | 1869 | ||||
| -rw-r--r-- | asm/MetroTRK/usr_put.s | 47 | ||||
| -rw-r--r-- | asm/text_6.s | 2933 | ||||
| -rw-r--r-- | asm/text_6_2.s | 1885 | ||||
| -rw-r--r-- | asm/text_8.s | 6 | ||||
| -rw-r--r-- | obj_files.mk | 15 |
19 files changed, 4876 insertions, 4820 deletions
diff --git a/asm/MetroTRK/dispatch.s b/asm/MetroTRK/dispatch.s new file mode 100644 index 0000000..66f9b52 --- /dev/null +++ b/asm/MetroTRK/dispatch.s @@ -0,0 +1,92 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKDispatchMessage
+TRKDispatchMessage:
+/* 801D577C 001D13DC 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 801D5780 001D13E0 7C 08 02 A6 */ mflr r0
+/* 801D5784 001D13E4 38 80 00 00 */ li r4, 0
+/* 801D5788 001D13E8 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D578C 001D13EC 93 E1 00 0C */ stw r31, 0xc(r1)
+/* 801D5790 001D13F0 3B E0 05 00 */ li r31, 0x500
+/* 801D5794 001D13F4 93 C1 00 08 */ stw r30, 8(r1)
+/* 801D5798 001D13F8 7C 7E 1B 78 */ mr r30, r3
+/* 801D579C 001D13FC 4B FF FB 6D */ bl TRKSetBufferPosition
+/* 801D57A0 001D1400 88 1E 00 14 */ lbz r0, 0x14(r30)
+/* 801D57A4 001D1404 28 00 00 1A */ cmplwi r0, 0x1a
+/* 801D57A8 001D1408 41 81 00 F8 */ bgt lbl_801D58A0
+/* 801D57AC 001D140C 3C 60 80 42 */ lis r3, lbl_80423188@ha
+/* 801D57B0 001D1410 54 00 10 3A */ slwi r0, r0, 2
+/* 801D57B4 001D1414 38 63 31 88 */ addi r3, r3, lbl_80423188@l
+/* 801D57B8 001D1418 7C 03 00 2E */ lwzx r0, r3, r0
+/* 801D57BC 001D141C 7C 09 03 A6 */ mtctr r0
+/* 801D57C0 001D1420 4E 80 04 20 */ bctr
+/* 801D57C4 001D1424 7F C3 F3 78 */ mr r3, r30
+/* 801D57C8 001D1428 48 00 11 35 */ bl TRKDoConnect
+/* 801D57CC 001D142C 7C 7F 1B 78 */ mr r31, r3
+/* 801D57D0 001D1430 48 00 00 D0 */ b lbl_801D58A0
+/* 801D57D4 001D1434 7F C3 F3 78 */ mr r3, r30
+/* 801D57D8 001D1438 48 00 10 89 */ bl TRKDoDisconnect
+/* 801D57DC 001D143C 7C 7F 1B 78 */ mr r31, r3
+/* 801D57E0 001D1440 48 00 00 C0 */ b lbl_801D58A0
+/* 801D57E4 001D1444 7F C3 F3 78 */ mr r3, r30
+/* 801D57E8 001D1448 48 00 0F FD */ bl TRKDoReset
+/* 801D57EC 001D144C 7C 7F 1B 78 */ mr r31, r3
+/* 801D57F0 001D1450 48 00 00 B0 */ b lbl_801D58A0
+/* 801D57F4 001D1454 7F C3 F3 78 */ mr r3, r30
+/* 801D57F8 001D1458 48 00 0F 71 */ bl TRKDoOverride
+/* 801D57FC 001D145C 7C 7F 1B 78 */ mr r31, r3
+/* 801D5800 001D1460 48 00 00 A0 */ b lbl_801D58A0
+/* 801D5804 001D1464 7F C3 F3 78 */ mr r3, r30
+/* 801D5808 001D1468 48 00 0F 59 */ bl TRKDoVersions
+/* 801D580C 001D146C 7C 7F 1B 78 */ mr r31, r3
+/* 801D5810 001D1470 48 00 00 90 */ b lbl_801D58A0
+/* 801D5814 001D1474 7F C3 F3 78 */ mr r3, r30
+/* 801D5818 001D1478 48 00 0F 41 */ bl TRKDoSupportMask
+/* 801D581C 001D147C 7C 7F 1B 78 */ mr r31, r3
+/* 801D5820 001D1480 48 00 00 80 */ b lbl_801D58A0
+/* 801D5824 001D1484 7F C3 F3 78 */ mr r3, r30
+/* 801D5828 001D1488 48 00 0C E9 */ bl TRKDoReadMemory
+/* 801D582C 001D148C 7C 7F 1B 78 */ mr r31, r3
+/* 801D5830 001D1490 48 00 00 70 */ b lbl_801D58A0
+/* 801D5834 001D1494 7F C3 F3 78 */ mr r3, r30
+/* 801D5838 001D1498 48 00 0A BD */ bl TRKDoWriteMemory
+/* 801D583C 001D149C 7C 7F 1B 78 */ mr r31, r3
+/* 801D5840 001D14A0 48 00 00 60 */ b lbl_801D58A0
+/* 801D5844 001D14A4 7F C3 F3 78 */ mr r3, r30
+/* 801D5848 001D14A8 48 00 08 89 */ bl TRKDoReadRegisters
+/* 801D584C 001D14AC 7C 7F 1B 78 */ mr r31, r3
+/* 801D5850 001D14B0 48 00 00 50 */ b lbl_801D58A0
+/* 801D5854 001D14B4 7F C3 F3 78 */ mr r3, r30
+/* 801D5858 001D14B8 48 00 05 BD */ bl TRKDoWriteRegisters
+/* 801D585C 001D14BC 7C 7F 1B 78 */ mr r31, r3
+/* 801D5860 001D14C0 48 00 00 40 */ b lbl_801D58A0
+/* 801D5864 001D14C4 7F C3 F3 78 */ mr r3, r30
+/* 801D5868 001D14C8 48 00 04 C9 */ bl TRKDoContinue
+/* 801D586C 001D14CC 7C 7F 1B 78 */ mr r31, r3
+/* 801D5870 001D14D0 48 00 00 30 */ b lbl_801D58A0
+/* 801D5874 001D14D4 7F C3 F3 78 */ mr r3, r30
+/* 801D5878 001D14D8 48 00 01 E5 */ bl TRKDoStep
+/* 801D587C 001D14DC 7C 7F 1B 78 */ mr r31, r3
+/* 801D5880 001D14E0 48 00 00 20 */ b lbl_801D58A0
+/* 801D5884 001D14E4 7F C3 F3 78 */ mr r3, r30
+/* 801D5888 001D14E8 48 00 01 09 */ bl TRKDoStop
+/* 801D588C 001D14EC 7C 7F 1B 78 */ mr r31, r3
+/* 801D5890 001D14F0 48 00 00 10 */ b lbl_801D58A0
+/* 801D5894 001D14F4 7F C3 F3 78 */ mr r3, r30
+/* 801D5898 001D14F8 48 00 00 2D */ bl TRKDoSetOption
+/* 801D589C 001D14FC 7C 7F 1B 78 */ mr r31, r3
+lbl_801D58A0:
+/* 801D58A0 001D1500 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D58A4 001D1504 7F E3 FB 78 */ mr r3, r31
+/* 801D58A8 001D1508 83 E1 00 0C */ lwz r31, 0xc(r1)
+/* 801D58AC 001D150C 83 C1 00 08 */ lwz r30, 8(r1)
+/* 801D58B0 001D1510 7C 08 03 A6 */ mtlr r0
+/* 801D58B4 001D1514 38 21 00 10 */ addi r1, r1, 0x10
+/* 801D58B8 001D1518 4E 80 00 20 */ blr
+
+.global TRKInitializeDispatcher
+TRKInitializeDispatcher:
+/* 801D58BC 001D151C 38 60 00 00 */ li r3, 0
+/* 801D58C0 001D1520 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/flush_cache.s b/asm/MetroTRK/flush_cache.s new file mode 100644 index 0000000..28802b1 --- /dev/null +++ b/asm/MetroTRK/flush_cache.s @@ -0,0 +1,21 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global TRK_flush_cache +TRK_flush_cache: +/* 801D7104 001D2D64 3C A0 FF FF */ lis r5, 0xFFFFFFF1@h +/* 801D7108 001D2D68 60 A5 FF F1 */ ori r5, r5, 0xFFFFFFF1@l +/* 801D710C 001D2D6C 7C A5 18 38 */ and r5, r5, r3 +/* 801D7110 001D2D70 7C 65 18 50 */ subf r3, r5, r3 +/* 801D7114 001D2D74 7C 84 1A 14 */ add r4, r4, r3 +lbl_801D7118: +/* 801D7118 001D2D78 7C 00 28 6C */ dcbst 0, r5 +/* 801D711C 001D2D7C 7C 00 28 AC */ dcbf 0, r5 +/* 801D7120 001D2D80 7C 00 04 AC */ sync 0 +/* 801D7124 001D2D84 7C 00 2F AC */ icbi 0, r5 +/* 801D7128 001D2D88 30 A5 00 08 */ addic r5, r5, 8 +/* 801D712C 001D2D8C 34 84 FF F8 */ addic. r4, r4, -8 +/* 801D7130 001D2D90 40 80 FF E8 */ bge lbl_801D7118 +/* 801D7134 001D2D94 4C 00 01 2C */ isync +/* 801D7138 001D2D98 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/mainloop.s b/asm/MetroTRK/mainloop.s index 96306a6..c828d7d 100644 --- a/asm/MetroTRK/mainloop.s +++ b/asm/MetroTRK/mainloop.s @@ -34,20 +34,20 @@ lbl_801D488C: lbl_801D489C:
/* 801D489C 001D04FC 80 61 00 10 */ lwz r3, 0x10(r1)
/* 801D48A0 001D0500 48 00 0B 3D */ bl TRKGetBuffer
-/* 801D48A4 001D0504 48 00 0E D9 */ bl func_801D577C
+/* 801D48A4 001D0504 48 00 0E D9 */ bl TRKDispatchMessage
/* 801D48A8 001D0508 48 00 00 1C */ b lbl_801D48C4
lbl_801D48AC:
/* 801D48AC 001D050C 3B E0 00 01 */ li r31, 1
/* 801D48B0 001D0510 48 00 00 14 */ b lbl_801D48C4
lbl_801D48B4:
/* 801D48B4 001D0514 38 61 00 08 */ addi r3, r1, 8
-/* 801D48B8 001D0518 48 00 31 85 */ bl func_801D7A3C
+/* 801D48B8 001D0518 48 00 31 85 */ bl TRKTargetInterrupt
/* 801D48BC 001D051C 48 00 00 08 */ b lbl_801D48C4
lbl_801D48C0:
/* 801D48C0 001D0520 48 00 2D 75 */ bl TRKTargetSupportRequest
lbl_801D48C4:
/* 801D48C4 001D0524 38 61 00 08 */ addi r3, r1, 8
-/* 801D48C8 001D0528 48 00 00 69 */ bl func_801D4930
+/* 801D48C8 001D0528 48 00 00 69 */ bl TRKDestructEvent
/* 801D48CC 001D052C 48 00 00 44 */ b lbl_801D4910
lbl_801D48D0:
/* 801D48D0 001D0530 2C 1E 00 00 */ cmpwi r30, 0
@@ -63,7 +63,7 @@ lbl_801D48F0: /* 801D48F4 001D0554 48 00 0C CD */ bl TRKGetInput
/* 801D48F8 001D0558 48 00 00 18 */ b lbl_801D4910
lbl_801D48FC:
-/* 801D48FC 001D055C 48 00 2D 29 */ bl func_801D7624
+/* 801D48FC 001D055C 48 00 2D 29 */ bl TRKTargetStopped
/* 801D4900 001D0560 2C 03 00 00 */ cmpwi r3, 0
/* 801D4904 001D0564 40 82 00 08 */ bne lbl_801D490C
/* 801D4908 001D0568 48 00 50 51 */ bl TRKTargetContinue
diff --git a/asm/MetroTRK/msg.s b/asm/MetroTRK/msg.s new file mode 100644 index 0000000..2f5a89c --- /dev/null +++ b/asm/MetroTRK/msg.s @@ -0,0 +1,17 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKMessageSend
+TRKMessageSend:
+/* 801D4CDC 001D093C 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 801D4CE0 001D0940 7C 08 02 A6 */ mflr r0
+/* 801D4CE4 001D0944 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D4CE8 001D0948 80 83 00 08 */ lwz r4, 8(r3)
+/* 801D4CEC 001D094C 38 63 00 10 */ addi r3, r3, 0x10
+/* 801D4CF0 001D0950 48 00 49 1D */ bl func_801D960C
+/* 801D4CF4 001D0954 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D4CF8 001D0958 38 60 00 00 */ li r3, 0
+/* 801D4CFC 001D095C 7C 08 03 A6 */ mtlr r0
+/* 801D4D00 001D0960 38 21 00 10 */ addi r1, r1, 0x10
+/* 801D4D04 001D0964 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/msgbuf.s b/asm/MetroTRK/msgbuf.s new file mode 100644 index 0000000..c1e7092 --- /dev/null +++ b/asm/MetroTRK/msgbuf.s @@ -0,0 +1,624 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKReadBuffer_ui32
+TRKReadBuffer_ui32:
+/* 801D4D08 001D0968 94 21 FF D0 */ stwu r1, -0x30(r1)
+/* 801D4D0C 001D096C 7C 08 02 A6 */ mflr r0
+/* 801D4D10 001D0970 3C C0 80 49 */ lis r6, lbl_8048EE18@ha
+/* 801D4D14 001D0974 90 01 00 34 */ stw r0, 0x34(r1)
+/* 801D4D18 001D0978 BF 01 00 10 */ stmw r24, 0x10(r1)
+/* 801D4D1C 001D097C 7C 7C 1B 78 */ mr r28, r3
+/* 801D4D20 001D0980 7C BD 2B 78 */ mr r29, r5
+/* 801D4D24 001D0984 7C 9F 23 78 */ mr r31, r4
+/* 801D4D28 001D0988 3B 66 EE 18 */ addi r27, r6, lbl_8048EE18@l
+/* 801D4D2C 001D098C 3B C0 00 00 */ li r30, 0
+/* 801D4D30 001D0990 38 60 00 00 */ li r3, 0
+/* 801D4D34 001D0994 48 00 00 A0 */ b lbl_801D4DD4
+lbl_801D4D38:
+/* 801D4D38 001D0998 80 1B 00 00 */ lwz r0, 0(r27)
+/* 801D4D3C 001D099C 2C 00 00 00 */ cmpwi r0, 0
+/* 801D4D40 001D09A0 41 82 00 0C */ beq lbl_801D4D4C
+/* 801D4D44 001D09A4 7F F9 FB 78 */ mr r25, r31
+/* 801D4D48 001D09A8 48 00 00 08 */ b lbl_801D4D50
+lbl_801D4D4C:
+/* 801D4D4C 001D09AC 3B 21 00 08 */ addi r25, r1, 8
+lbl_801D4D50:
+/* 801D4D50 001D09B0 80 7C 00 0C */ lwz r3, 0xc(r28)
+/* 801D4D54 001D09B4 3B 00 00 04 */ li r24, 4
+/* 801D4D58 001D09B8 80 1C 00 08 */ lwz r0, 8(r28)
+/* 801D4D5C 001D09BC 3B 40 00 00 */ li r26, 0
+/* 801D4D60 001D09C0 7C 03 00 50 */ subf r0, r3, r0
+/* 801D4D64 001D09C4 7C 18 00 40 */ cmplw r24, r0
+/* 801D4D68 001D09C8 40 81 00 0C */ ble lbl_801D4D74
+/* 801D4D6C 001D09CC 3B 40 03 02 */ li r26, 0x302
+/* 801D4D70 001D09D0 7C 18 03 78 */ mr r24, r0
+lbl_801D4D74:
+/* 801D4D74 001D09D4 38 83 00 10 */ addi r4, r3, 0x10
+/* 801D4D78 001D09D8 7F 23 CB 78 */ mr r3, r25
+/* 801D4D7C 001D09DC 7F 05 C3 78 */ mr r5, r24
+/* 801D4D80 001D09E0 7C 9C 22 14 */ add r4, r28, r4
+/* 801D4D84 001D09E4 4B E2 F3 E1 */ bl TRK_memcpy
+/* 801D4D88 001D09E8 80 1C 00 0C */ lwz r0, 0xc(r28)
+/* 801D4D8C 001D09EC 7C 00 C2 14 */ add r0, r0, r24
+/* 801D4D90 001D09F0 90 1C 00 0C */ stw r0, 0xc(r28)
+/* 801D4D94 001D09F4 80 1B 00 00 */ lwz r0, 0(r27)
+/* 801D4D98 001D09F8 2C 00 00 00 */ cmpwi r0, 0
+/* 801D4D9C 001D09FC 40 82 00 2C */ bne lbl_801D4DC8
+/* 801D4DA0 001D0A00 2C 1A 00 00 */ cmpwi r26, 0
+/* 801D4DA4 001D0A04 40 82 00 24 */ bne lbl_801D4DC8
+/* 801D4DA8 001D0A08 88 19 00 03 */ lbz r0, 3(r25)
+/* 801D4DAC 001D0A0C 98 1F 00 00 */ stb r0, 0(r31)
+/* 801D4DB0 001D0A10 88 19 00 02 */ lbz r0, 2(r25)
+/* 801D4DB4 001D0A14 98 1F 00 01 */ stb r0, 1(r31)
+/* 801D4DB8 001D0A18 88 19 00 01 */ lbz r0, 1(r25)
+/* 801D4DBC 001D0A1C 98 1F 00 02 */ stb r0, 2(r31)
+/* 801D4DC0 001D0A20 88 19 00 00 */ lbz r0, 0(r25)
+/* 801D4DC4 001D0A24 98 1F 00 03 */ stb r0, 3(r31)
+lbl_801D4DC8:
+/* 801D4DC8 001D0A28 7F 43 D3 78 */ mr r3, r26
+/* 801D4DCC 001D0A2C 3B FF 00 04 */ addi r31, r31, 4
+/* 801D4DD0 001D0A30 3B DE 00 01 */ addi r30, r30, 1
+lbl_801D4DD4:
+/* 801D4DD4 001D0A34 2C 03 00 00 */ cmpwi r3, 0
+/* 801D4DD8 001D0A38 40 82 00 0C */ bne lbl_801D4DE4
+/* 801D4DDC 001D0A3C 7C 1E E8 00 */ cmpw r30, r29
+/* 801D4DE0 001D0A40 41 80 FF 58 */ blt lbl_801D4D38
+lbl_801D4DE4:
+/* 801D4DE4 001D0A44 BB 01 00 10 */ lmw r24, 0x10(r1)
+/* 801D4DE8 001D0A48 80 01 00 34 */ lwz r0, 0x34(r1)
+/* 801D4DEC 001D0A4C 7C 08 03 A6 */ mtlr r0
+/* 801D4DF0 001D0A50 38 21 00 30 */ addi r1, r1, 0x30
+/* 801D4DF4 001D0A54 4E 80 00 20 */ blr
+
+.global TRKReadBuffer_ui8
+TRKReadBuffer_ui8:
+/* 801D4DF8 001D0A58 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D4DFC 001D0A5C 7C 08 02 A6 */ mflr r0
+/* 801D4E00 001D0A60 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D4E04 001D0A64 BF 41 00 08 */ stmw r26, 8(r1)
+/* 801D4E08 001D0A68 7C 7A 1B 78 */ mr r26, r3
+/* 801D4E0C 001D0A6C 7C 9B 23 78 */ mr r27, r4
+/* 801D4E10 001D0A70 7C BC 2B 78 */ mr r28, r5
+/* 801D4E14 001D0A74 3B A0 00 00 */ li r29, 0
+/* 801D4E18 001D0A78 38 60 00 00 */ li r3, 0
+/* 801D4E1C 001D0A7C 48 00 00 50 */ b lbl_801D4E6C
+lbl_801D4E20:
+/* 801D4E20 001D0A80 80 7A 00 0C */ lwz r3, 0xc(r26)
+/* 801D4E24 001D0A84 3B C0 00 01 */ li r30, 1
+/* 801D4E28 001D0A88 80 1A 00 08 */ lwz r0, 8(r26)
+/* 801D4E2C 001D0A8C 3B E0 00 00 */ li r31, 0
+/* 801D4E30 001D0A90 7C 03 00 50 */ subf r0, r3, r0
+/* 801D4E34 001D0A94 7C 1E 00 40 */ cmplw r30, r0
+/* 801D4E38 001D0A98 40 81 00 0C */ ble lbl_801D4E44
+/* 801D4E3C 001D0A9C 3B E0 03 02 */ li r31, 0x302
+/* 801D4E40 001D0AA0 7C 1E 03 78 */ mr r30, r0
+lbl_801D4E44:
+/* 801D4E44 001D0AA4 38 83 00 10 */ addi r4, r3, 0x10
+/* 801D4E48 001D0AA8 7F C5 F3 78 */ mr r5, r30
+/* 801D4E4C 001D0AAC 7C 7B EA 14 */ add r3, r27, r29
+/* 801D4E50 001D0AB0 7C 9A 22 14 */ add r4, r26, r4
+/* 801D4E54 001D0AB4 4B E2 F3 11 */ bl TRK_memcpy
+/* 801D4E58 001D0AB8 80 1A 00 0C */ lwz r0, 0xc(r26)
+/* 801D4E5C 001D0ABC 7F E3 FB 78 */ mr r3, r31
+/* 801D4E60 001D0AC0 3B BD 00 01 */ addi r29, r29, 1
+/* 801D4E64 001D0AC4 7C 00 F2 14 */ add r0, r0, r30
+/* 801D4E68 001D0AC8 90 1A 00 0C */ stw r0, 0xc(r26)
+lbl_801D4E6C:
+/* 801D4E6C 001D0ACC 2C 03 00 00 */ cmpwi r3, 0
+/* 801D4E70 001D0AD0 40 82 00 0C */ bne lbl_801D4E7C
+/* 801D4E74 001D0AD4 7C 1D E0 00 */ cmpw r29, r28
+/* 801D4E78 001D0AD8 41 80 FF A8 */ blt lbl_801D4E20
+lbl_801D4E7C:
+/* 801D4E7C 001D0ADC BB 41 00 08 */ lmw r26, 8(r1)
+/* 801D4E80 001D0AE0 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D4E84 001D0AE4 7C 08 03 A6 */ mtlr r0
+/* 801D4E88 001D0AE8 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D4E8C 001D0AEC 4E 80 00 20 */ blr
+
+.global TRKReadBuffer1_ui64
+TRKReadBuffer1_ui64:
+/* 801D4E90 001D0AF0 94 21 FF D0 */ stwu r1, -0x30(r1)
+/* 801D4E94 001D0AF4 7C 08 02 A6 */ mflr r0
+/* 801D4E98 001D0AF8 3C A0 80 49 */ lis r5, lbl_8048EE18@ha
+/* 801D4E9C 001D0AFC 90 01 00 34 */ stw r0, 0x34(r1)
+/* 801D4EA0 001D0B00 BF 61 00 1C */ stmw r27, 0x1c(r1)
+/* 801D4EA4 001D0B04 7C 7B 1B 78 */ mr r27, r3
+/* 801D4EA8 001D0B08 7C 9E 23 78 */ mr r30, r4
+/* 801D4EAC 001D0B0C 80 05 EE 18 */ lwz r0, lbl_8048EE18@l(r5)
+/* 801D4EB0 001D0B10 2C 00 00 00 */ cmpwi r0, 0
+/* 801D4EB4 001D0B14 41 82 00 0C */ beq lbl_801D4EC0
+/* 801D4EB8 001D0B18 7F DF F3 78 */ mr r31, r30
+/* 801D4EBC 001D0B1C 48 00 00 08 */ b lbl_801D4EC4
+lbl_801D4EC0:
+/* 801D4EC0 001D0B20 3B E1 00 08 */ addi r31, r1, 8
+lbl_801D4EC4:
+/* 801D4EC4 001D0B24 80 7B 00 0C */ lwz r3, 0xc(r27)
+/* 801D4EC8 001D0B28 3B 80 00 08 */ li r28, 8
+/* 801D4ECC 001D0B2C 80 1B 00 08 */ lwz r0, 8(r27)
+/* 801D4ED0 001D0B30 3B A0 00 00 */ li r29, 0
+/* 801D4ED4 001D0B34 7C 03 00 50 */ subf r0, r3, r0
+/* 801D4ED8 001D0B38 7C 1C 00 40 */ cmplw r28, r0
+/* 801D4EDC 001D0B3C 40 81 00 0C */ ble lbl_801D4EE8
+/* 801D4EE0 001D0B40 3B A0 03 02 */ li r29, 0x302
+/* 801D4EE4 001D0B44 7C 1C 03 78 */ mr r28, r0
+lbl_801D4EE8:
+/* 801D4EE8 001D0B48 38 83 00 10 */ addi r4, r3, 0x10
+/* 801D4EEC 001D0B4C 7F E3 FB 78 */ mr r3, r31
+/* 801D4EF0 001D0B50 7F 85 E3 78 */ mr r5, r28
+/* 801D4EF4 001D0B54 7C 9B 22 14 */ add r4, r27, r4
+/* 801D4EF8 001D0B58 4B E2 F2 6D */ bl TRK_memcpy
+/* 801D4EFC 001D0B5C 80 1B 00 0C */ lwz r0, 0xc(r27)
+/* 801D4F00 001D0B60 3C 60 80 49 */ lis r3, lbl_8048EE18@ha
+/* 801D4F04 001D0B64 7C 00 E2 14 */ add r0, r0, r28
+/* 801D4F08 001D0B68 90 1B 00 0C */ stw r0, 0xc(r27)
+/* 801D4F0C 001D0B6C 80 03 EE 18 */ lwz r0, lbl_8048EE18@l(r3)
+/* 801D4F10 001D0B70 2C 00 00 00 */ cmpwi r0, 0
+/* 801D4F14 001D0B74 40 82 00 4C */ bne lbl_801D4F60
+/* 801D4F18 001D0B78 2C 1D 00 00 */ cmpwi r29, 0
+/* 801D4F1C 001D0B7C 40 82 00 44 */ bne lbl_801D4F60
+/* 801D4F20 001D0B80 88 1F 00 07 */ lbz r0, 7(r31)
+/* 801D4F24 001D0B84 98 1E 00 00 */ stb r0, 0(r30)
+/* 801D4F28 001D0B88 88 1F 00 06 */ lbz r0, 6(r31)
+/* 801D4F2C 001D0B8C 98 1E 00 01 */ stb r0, 1(r30)
+/* 801D4F30 001D0B90 88 1F 00 05 */ lbz r0, 5(r31)
+/* 801D4F34 001D0B94 98 1E 00 02 */ stb r0, 2(r30)
+/* 801D4F38 001D0B98 88 1F 00 04 */ lbz r0, 4(r31)
+/* 801D4F3C 001D0B9C 98 1E 00 03 */ stb r0, 3(r30)
+/* 801D4F40 001D0BA0 88 1F 00 03 */ lbz r0, 3(r31)
+/* 801D4F44 001D0BA4 98 1E 00 04 */ stb r0, 4(r30)
+/* 801D4F48 001D0BA8 88 1F 00 02 */ lbz r0, 2(r31)
+/* 801D4F4C 001D0BAC 98 1E 00 05 */ stb r0, 5(r30)
+/* 801D4F50 001D0BB0 88 1F 00 01 */ lbz r0, 1(r31)
+/* 801D4F54 001D0BB4 98 1E 00 06 */ stb r0, 6(r30)
+/* 801D4F58 001D0BB8 88 1F 00 00 */ lbz r0, 0(r31)
+/* 801D4F5C 001D0BBC 98 1E 00 07 */ stb r0, 7(r30)
+lbl_801D4F60:
+/* 801D4F60 001D0BC0 7F A3 EB 78 */ mr r3, r29
+/* 801D4F64 001D0BC4 BB 61 00 1C */ lmw r27, 0x1c(r1)
+/* 801D4F68 001D0BC8 80 01 00 34 */ lwz r0, 0x34(r1)
+/* 801D4F6C 001D0BCC 7C 08 03 A6 */ mtlr r0
+/* 801D4F70 001D0BD0 38 21 00 30 */ addi r1, r1, 0x30
+/* 801D4F74 001D0BD4 4E 80 00 20 */ blr
+
+.global TRKAppendBuffer_ui32
+TRKAppendBuffer_ui32:
+/* 801D4F78 001D0BD8 94 21 FF D0 */ stwu r1, -0x30(r1)
+/* 801D4F7C 001D0BDC 7C 08 02 A6 */ mflr r0
+/* 801D4F80 001D0BE0 3C C0 80 49 */ lis r6, lbl_8048EE18@ha
+/* 801D4F84 001D0BE4 90 01 00 34 */ stw r0, 0x34(r1)
+/* 801D4F88 001D0BE8 BF 21 00 14 */ stmw r25, 0x14(r1)
+/* 801D4F8C 001D0BEC 7C 7B 1B 78 */ mr r27, r3
+/* 801D4F90 001D0BF0 7C BC 2B 78 */ mr r28, r5
+/* 801D4F94 001D0BF4 7C 9E 23 78 */ mr r30, r4
+/* 801D4F98 001D0BF8 3B E6 EE 18 */ addi r31, r6, lbl_8048EE18@l
+/* 801D4F9C 001D0BFC 3B A0 00 00 */ li r29, 0
+/* 801D4FA0 001D0C00 38 60 00 00 */ li r3, 0
+/* 801D4FA4 001D0C04 48 00 00 AC */ b lbl_801D5050
+lbl_801D4FA8:
+/* 801D4FA8 001D0C08 80 1F 00 00 */ lwz r0, 0(r31)
+/* 801D4FAC 001D0C0C 80 7E 00 00 */ lwz r3, 0(r30)
+/* 801D4FB0 001D0C10 2C 00 00 00 */ cmpwi r0, 0
+/* 801D4FB4 001D0C14 90 61 00 08 */ stw r3, 8(r1)
+/* 801D4FB8 001D0C18 41 82 00 0C */ beq lbl_801D4FC4
+/* 801D4FBC 001D0C1C 38 81 00 08 */ addi r4, r1, 8
+/* 801D4FC0 001D0C20 48 00 00 28 */ b lbl_801D4FE8
+lbl_801D4FC4:
+/* 801D4FC4 001D0C24 88 C1 00 0B */ lbz r6, 0xb(r1)
+/* 801D4FC8 001D0C28 38 81 00 0C */ addi r4, r1, 0xc
+/* 801D4FCC 001D0C2C 88 A1 00 0A */ lbz r5, 0xa(r1)
+/* 801D4FD0 001D0C30 88 61 00 09 */ lbz r3, 9(r1)
+/* 801D4FD4 001D0C34 88 01 00 08 */ lbz r0, 8(r1)
+/* 801D4FD8 001D0C38 98 C1 00 0C */ stb r6, 0xc(r1)
+/* 801D4FDC 001D0C3C 98 A1 00 0D */ stb r5, 0xd(r1)
+/* 801D4FE0 001D0C40 98 61 00 0E */ stb r3, 0xe(r1)
+/* 801D4FE4 001D0C44 98 01 00 0F */ stb r0, 0xf(r1)
+lbl_801D4FE8:
+/* 801D4FE8 001D0C48 80 BB 00 0C */ lwz r5, 0xc(r27)
+/* 801D4FEC 001D0C4C 3B 20 00 04 */ li r25, 4
+/* 801D4FF0 001D0C50 3B 40 00 00 */ li r26, 0
+/* 801D4FF4 001D0C54 20 05 08 80 */ subfic r0, r5, 0x880
+/* 801D4FF8 001D0C58 28 00 00 04 */ cmplwi r0, 4
+/* 801D4FFC 001D0C5C 40 80 00 0C */ bge lbl_801D5008
+/* 801D5000 001D0C60 3B 40 03 01 */ li r26, 0x301
+/* 801D5004 001D0C64 7C 19 03 78 */ mr r25, r0
+lbl_801D5008:
+/* 801D5008 001D0C68 28 19 00 01 */ cmplwi r25, 1
+/* 801D500C 001D0C6C 40 82 00 14 */ bne lbl_801D5020
+/* 801D5010 001D0C70 88 64 00 00 */ lbz r3, 0(r4)
+/* 801D5014 001D0C74 38 05 00 10 */ addi r0, r5, 0x10
+/* 801D5018 001D0C78 7C 7B 01 AE */ stbx r3, r27, r0
+/* 801D501C 001D0C7C 48 00 00 14 */ b lbl_801D5030
+lbl_801D5020:
+/* 801D5020 001D0C80 38 65 00 10 */ addi r3, r5, 0x10
+/* 801D5024 001D0C84 7F 25 CB 78 */ mr r5, r25
+/* 801D5028 001D0C88 7C 7B 1A 14 */ add r3, r27, r3
+/* 801D502C 001D0C8C 4B E2 F1 39 */ bl TRK_memcpy
+lbl_801D5030:
+/* 801D5030 001D0C90 80 1B 00 0C */ lwz r0, 0xc(r27)
+/* 801D5034 001D0C94 7F 43 D3 78 */ mr r3, r26
+/* 801D5038 001D0C98 3B DE 00 04 */ addi r30, r30, 4
+/* 801D503C 001D0C9C 3B BD 00 01 */ addi r29, r29, 1
+/* 801D5040 001D0CA0 7C 00 CA 14 */ add r0, r0, r25
+/* 801D5044 001D0CA4 90 1B 00 0C */ stw r0, 0xc(r27)
+/* 801D5048 001D0CA8 80 1B 00 0C */ lwz r0, 0xc(r27)
+/* 801D504C 001D0CAC 90 1B 00 08 */ stw r0, 8(r27)
+lbl_801D5050:
+/* 801D5050 001D0CB0 2C 03 00 00 */ cmpwi r3, 0
+/* 801D5054 001D0CB4 40 82 00 0C */ bne lbl_801D5060
+/* 801D5058 001D0CB8 7C 1D E0 00 */ cmpw r29, r28
+/* 801D505C 001D0CBC 41 80 FF 4C */ blt lbl_801D4FA8
+lbl_801D5060:
+/* 801D5060 001D0CC0 BB 21 00 14 */ lmw r25, 0x14(r1)
+/* 801D5064 001D0CC4 80 01 00 34 */ lwz r0, 0x34(r1)
+/* 801D5068 001D0CC8 7C 08 03 A6 */ mtlr r0
+/* 801D506C 001D0CCC 38 21 00 30 */ addi r1, r1, 0x30
+/* 801D5070 001D0CD0 4E 80 00 20 */ blr
+
+.global TRKAppendBuffer_ui8
+TRKAppendBuffer_ui8:
+/* 801D5074 001D0CD4 39 20 00 00 */ li r9, 0
+/* 801D5078 001D0CD8 38 00 00 00 */ li r0, 0
+/* 801D507C 001D0CDC 48 00 00 48 */ b lbl_801D50C4
+lbl_801D5080:
+/* 801D5080 001D0CE0 80 E3 00 0C */ lwz r7, 0xc(r3)
+/* 801D5084 001D0CE4 89 04 00 00 */ lbz r8, 0(r4)
+/* 801D5088 001D0CE8 28 07 08 80 */ cmplwi r7, 0x880
+/* 801D508C 001D0CEC 41 80 00 0C */ blt lbl_801D5098
+/* 801D5090 001D0CF0 38 E0 03 01 */ li r7, 0x301
+/* 801D5094 001D0CF4 48 00 00 24 */ b lbl_801D50B8
+lbl_801D5098:
+/* 801D5098 001D0CF8 38 C7 00 01 */ addi r6, r7, 1
+/* 801D509C 001D0CFC 38 07 00 10 */ addi r0, r7, 0x10
+/* 801D50A0 001D0D00 90 C3 00 0C */ stw r6, 0xc(r3)
+/* 801D50A4 001D0D04 38 E0 00 00 */ li r7, 0
+/* 801D50A8 001D0D08 7D 03 01 AE */ stbx r8, r3, r0
+/* 801D50AC 001D0D0C 80 C3 00 08 */ lwz r6, 8(r3)
+/* 801D50B0 001D0D10 38 06 00 01 */ addi r0, r6, 1
+/* 801D50B4 001D0D14 90 03 00 08 */ stw r0, 8(r3)
+lbl_801D50B8:
+/* 801D50B8 001D0D18 7C E0 3B 78 */ mr r0, r7
+/* 801D50BC 001D0D1C 39 29 00 01 */ addi r9, r9, 1
+/* 801D50C0 001D0D20 38 84 00 01 */ addi r4, r4, 1
+lbl_801D50C4:
+/* 801D50C4 001D0D24 2C 00 00 00 */ cmpwi r0, 0
+/* 801D50C8 001D0D28 40 82 00 0C */ bne lbl_801D50D4
+/* 801D50CC 001D0D2C 7C 09 28 00 */ cmpw r9, r5
+/* 801D50D0 001D0D30 41 80 FF B0 */ blt lbl_801D5080
+lbl_801D50D4:
+/* 801D50D4 001D0D34 7C 03 03 78 */ mr r3, r0
+/* 801D50D8 001D0D38 4E 80 00 20 */ blr
+
+.global TRKAppendBuffer1_ui64
+TRKAppendBuffer1_ui64:
+/* 801D50DC 001D0D3C 94 21 FF D0 */ stwu r1, -0x30(r1)
+/* 801D50E0 001D0D40 7C 08 02 A6 */ mflr r0
+/* 801D50E4 001D0D44 3C 80 80 49 */ lis r4, lbl_8048EE18@ha
+/* 801D50E8 001D0D48 90 01 00 34 */ stw r0, 0x34(r1)
+/* 801D50EC 001D0D4C 93 E1 00 2C */ stw r31, 0x2c(r1)
+/* 801D50F0 001D0D50 7C 7F 1B 78 */ mr r31, r3
+/* 801D50F4 001D0D54 93 C1 00 28 */ stw r30, 0x28(r1)
+/* 801D50F8 001D0D58 93 A1 00 24 */ stw r29, 0x24(r1)
+/* 801D50FC 001D0D5C 80 04 EE 18 */ lwz r0, lbl_8048EE18@l(r4)
+/* 801D5100 001D0D60 90 A1 00 08 */ stw r5, 8(r1)
+/* 801D5104 001D0D64 2C 00 00 00 */ cmpwi r0, 0
+/* 801D5108 001D0D68 90 C1 00 0C */ stw r6, 0xc(r1)
+/* 801D510C 001D0D6C 41 82 00 0C */ beq lbl_801D5118
+/* 801D5110 001D0D70 38 81 00 08 */ addi r4, r1, 8
+/* 801D5114 001D0D74 48 00 00 48 */ b lbl_801D515C
+lbl_801D5118:
+/* 801D5118 001D0D78 89 41 00 0F */ lbz r10, 0xf(r1)
+/* 801D511C 001D0D7C 38 81 00 10 */ addi r4, r1, 0x10
+/* 801D5120 001D0D80 89 21 00 0E */ lbz r9, 0xe(r1)
+/* 801D5124 001D0D84 89 01 00 0D */ lbz r8, 0xd(r1)
+/* 801D5128 001D0D88 88 E1 00 0C */ lbz r7, 0xc(r1)
+/* 801D512C 001D0D8C 88 C1 00 0B */ lbz r6, 0xb(r1)
+/* 801D5130 001D0D90 88 A1 00 0A */ lbz r5, 0xa(r1)
+/* 801D5134 001D0D94 88 61 00 09 */ lbz r3, 9(r1)
+/* 801D5138 001D0D98 88 01 00 08 */ lbz r0, 8(r1)
+/* 801D513C 001D0D9C 99 41 00 10 */ stb r10, 0x10(r1)
+/* 801D5140 001D0DA0 99 21 00 11 */ stb r9, 0x11(r1)
+/* 801D5144 001D0DA4 99 01 00 12 */ stb r8, 0x12(r1)
+/* 801D5148 001D0DA8 98 E1 00 13 */ stb r7, 0x13(r1)
+/* 801D514C 001D0DAC 98 C1 00 14 */ stb r6, 0x14(r1)
+/* 801D5150 001D0DB0 98 A1 00 15 */ stb r5, 0x15(r1)
+/* 801D5154 001D0DB4 98 61 00 16 */ stb r3, 0x16(r1)
+/* 801D5158 001D0DB8 98 01 00 17 */ stb r0, 0x17(r1)
+lbl_801D515C:
+/* 801D515C 001D0DBC 80 7F 00 0C */ lwz r3, 0xc(r31)
+/* 801D5160 001D0DC0 3B A0 00 08 */ li r29, 8
+/* 801D5164 001D0DC4 3B C0 00 00 */ li r30, 0
+/* 801D5168 001D0DC8 20 03 08 80 */ subfic r0, r3, 0x880
+/* 801D516C 001D0DCC 28 00 00 08 */ cmplwi r0, 8
+/* 801D5170 001D0DD0 40 80 00 0C */ bge lbl_801D517C
+/* 801D5174 001D0DD4 3B C0 03 01 */ li r30, 0x301
+/* 801D5178 001D0DD8 7C 1D 03 78 */ mr r29, r0
+lbl_801D517C:
+/* 801D517C 001D0DDC 28 1D 00 01 */ cmplwi r29, 1
+/* 801D5180 001D0DE0 40 82 00 14 */ bne lbl_801D5194
+/* 801D5184 001D0DE4 88 04 00 00 */ lbz r0, 0(r4)
+/* 801D5188 001D0DE8 7C 7F 1A 14 */ add r3, r31, r3
+/* 801D518C 001D0DEC 98 03 00 10 */ stb r0, 0x10(r3)
+/* 801D5190 001D0DF0 48 00 00 14 */ b lbl_801D51A4
+lbl_801D5194:
+/* 801D5194 001D0DF4 38 63 00 10 */ addi r3, r3, 0x10
+/* 801D5198 001D0DF8 7F A5 EB 78 */ mr r5, r29
+/* 801D519C 001D0DFC 7C 7F 1A 14 */ add r3, r31, r3
+/* 801D51A0 001D0E00 4B E2 EF C5 */ bl TRK_memcpy
+lbl_801D51A4:
+/* 801D51A4 001D0E04 80 1F 00 0C */ lwz r0, 0xc(r31)
+/* 801D51A8 001D0E08 7F C3 F3 78 */ mr r3, r30
+/* 801D51AC 001D0E0C 7C 00 EA 14 */ add r0, r0, r29
+/* 801D51B0 001D0E10 90 1F 00 0C */ stw r0, 0xc(r31)
+/* 801D51B4 001D0E14 80 1F 00 0C */ lwz r0, 0xc(r31)
+/* 801D51B8 001D0E18 90 1F 00 08 */ stw r0, 8(r31)
+/* 801D51BC 001D0E1C 83 E1 00 2C */ lwz r31, 0x2c(r1)
+/* 801D51C0 001D0E20 83 C1 00 28 */ lwz r30, 0x28(r1)
+/* 801D51C4 001D0E24 83 A1 00 24 */ lwz r29, 0x24(r1)
+/* 801D51C8 001D0E28 80 01 00 34 */ lwz r0, 0x34(r1)
+/* 801D51CC 001D0E2C 7C 08 03 A6 */ mtlr r0
+/* 801D51D0 001D0E30 38 21 00 30 */ addi r1, r1, 0x30
+/* 801D51D4 001D0E34 4E 80 00 20 */ blr
+
+.global TRKReadBuffer
+TRKReadBuffer:
+/* 801D51D8 001D0E38 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D51DC 001D0E3C 7C 08 02 A6 */ mflr r0
+/* 801D51E0 001D0E40 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D51E4 001D0E44 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D51E8 001D0E48 3B E0 00 00 */ li r31, 0
+/* 801D51EC 001D0E4C 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D51F0 001D0E50 7C BE 2B 79 */ or. r30, r5, r5
+/* 801D51F4 001D0E54 93 A1 00 14 */ stw r29, 0x14(r1)
+/* 801D51F8 001D0E58 7C 7D 1B 78 */ mr r29, r3
+/* 801D51FC 001D0E5C 7C 83 23 78 */ mr r3, r4
+/* 801D5200 001D0E60 40 82 00 0C */ bne lbl_801D520C
+/* 801D5204 001D0E64 38 60 00 00 */ li r3, 0
+/* 801D5208 001D0E68 48 00 00 40 */ b lbl_801D5248
+lbl_801D520C:
+/* 801D520C 001D0E6C 80 9D 00 0C */ lwz r4, 0xc(r29)
+/* 801D5210 001D0E70 80 1D 00 08 */ lwz r0, 8(r29)
+/* 801D5214 001D0E74 7C 04 00 50 */ subf r0, r4, r0
+/* 801D5218 001D0E78 7C 1E 00 40 */ cmplw r30, r0
+/* 801D521C 001D0E7C 40 81 00 0C */ ble lbl_801D5228
+/* 801D5220 001D0E80 3B E0 03 02 */ li r31, 0x302
+/* 801D5224 001D0E84 7C 1E 03 78 */ mr r30, r0
+lbl_801D5228:
+/* 801D5228 001D0E88 38 84 00 10 */ addi r4, r4, 0x10
+/* 801D522C 001D0E8C 7F C5 F3 78 */ mr r5, r30
+/* 801D5230 001D0E90 7C 9D 22 14 */ add r4, r29, r4
+/* 801D5234 001D0E94 4B E2 EF 31 */ bl TRK_memcpy
+/* 801D5238 001D0E98 80 1D 00 0C */ lwz r0, 0xc(r29)
+/* 801D523C 001D0E9C 7F E3 FB 78 */ mr r3, r31
+/* 801D5240 001D0EA0 7C 00 F2 14 */ add r0, r0, r30
+/* 801D5244 001D0EA4 90 1D 00 0C */ stw r0, 0xc(r29)
+lbl_801D5248:
+/* 801D5248 001D0EA8 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D524C 001D0EAC 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D5250 001D0EB0 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D5254 001D0EB4 83 A1 00 14 */ lwz r29, 0x14(r1)
+/* 801D5258 001D0EB8 7C 08 03 A6 */ mtlr r0
+/* 801D525C 001D0EBC 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D5260 001D0EC0 4E 80 00 20 */ blr
+
+.global TRKAppendBuffer
+TRKAppendBuffer:
+/* 801D5264 001D0EC4 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D5268 001D0EC8 7C 08 02 A6 */ mflr r0
+/* 801D526C 001D0ECC 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D5270 001D0ED0 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D5274 001D0ED4 3B E0 00 00 */ li r31, 0
+/* 801D5278 001D0ED8 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D527C 001D0EDC 7C BE 2B 79 */ or. r30, r5, r5
+/* 801D5280 001D0EE0 93 A1 00 14 */ stw r29, 0x14(r1)
+/* 801D5284 001D0EE4 7C 7D 1B 78 */ mr r29, r3
+/* 801D5288 001D0EE8 40 82 00 0C */ bne lbl_801D5294
+/* 801D528C 001D0EEC 38 60 00 00 */ li r3, 0
+/* 801D5290 001D0EF0 48 00 00 5C */ b lbl_801D52EC
+lbl_801D5294:
+/* 801D5294 001D0EF4 80 7D 00 0C */ lwz r3, 0xc(r29)
+/* 801D5298 001D0EF8 20 03 08 80 */ subfic r0, r3, 0x880
+/* 801D529C 001D0EFC 7C 00 F0 40 */ cmplw r0, r30
+/* 801D52A0 001D0F00 40 80 00 0C */ bge lbl_801D52AC
+/* 801D52A4 001D0F04 3B E0 03 01 */ li r31, 0x301
+/* 801D52A8 001D0F08 7C 1E 03 78 */ mr r30, r0
+lbl_801D52AC:
+/* 801D52AC 001D0F0C 28 1E 00 01 */ cmplwi r30, 1
+/* 801D52B0 001D0F10 40 82 00 14 */ bne lbl_801D52C4
+/* 801D52B4 001D0F14 88 04 00 00 */ lbz r0, 0(r4)
+/* 801D52B8 001D0F18 7C 7D 1A 14 */ add r3, r29, r3
+/* 801D52BC 001D0F1C 98 03 00 10 */ stb r0, 0x10(r3)
+/* 801D52C0 001D0F20 48 00 00 14 */ b lbl_801D52D4
+lbl_801D52C4:
+/* 801D52C4 001D0F24 38 63 00 10 */ addi r3, r3, 0x10
+/* 801D52C8 001D0F28 7F C5 F3 78 */ mr r5, r30
+/* 801D52CC 001D0F2C 7C 7D 1A 14 */ add r3, r29, r3
+/* 801D52D0 001D0F30 4B E2 EE 95 */ bl TRK_memcpy
+lbl_801D52D4:
+/* 801D52D4 001D0F34 80 1D 00 0C */ lwz r0, 0xc(r29)
+/* 801D52D8 001D0F38 7F E3 FB 78 */ mr r3, r31
+/* 801D52DC 001D0F3C 7C 00 F2 14 */ add r0, r0, r30
+/* 801D52E0 001D0F40 90 1D 00 0C */ stw r0, 0xc(r29)
+/* 801D52E4 001D0F44 80 1D 00 0C */ lwz r0, 0xc(r29)
+/* 801D52E8 001D0F48 90 1D 00 08 */ stw r0, 8(r29)
+lbl_801D52EC:
+/* 801D52EC 001D0F4C 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D52F0 001D0F50 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D52F4 001D0F54 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D52F8 001D0F58 83 A1 00 14 */ lwz r29, 0x14(r1)
+/* 801D52FC 001D0F5C 7C 08 03 A6 */ mtlr r0
+/* 801D5300 001D0F60 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D5304 001D0F64 4E 80 00 20 */ blr
+
+.global TRKSetBufferPosition
+TRKSetBufferPosition:
+/* 801D5308 001D0F68 28 04 08 80 */ cmplwi r4, 0x880
+/* 801D530C 001D0F6C 38 A0 00 00 */ li r5, 0
+/* 801D5310 001D0F70 40 81 00 0C */ ble lbl_801D531C
+/* 801D5314 001D0F74 38 A0 03 01 */ li r5, 0x301
+/* 801D5318 001D0F78 48 00 00 18 */ b lbl_801D5330
+lbl_801D531C:
+/* 801D531C 001D0F7C 90 83 00 0C */ stw r4, 0xc(r3)
+/* 801D5320 001D0F80 80 03 00 08 */ lwz r0, 8(r3)
+/* 801D5324 001D0F84 7C 04 00 40 */ cmplw r4, r0
+/* 801D5328 001D0F88 40 81 00 08 */ ble lbl_801D5330
+/* 801D532C 001D0F8C 90 83 00 08 */ stw r4, 8(r3)
+lbl_801D5330:
+/* 801D5330 001D0F90 7C A3 2B 78 */ mr r3, r5
+/* 801D5334 001D0F94 4E 80 00 20 */ blr
+
+.global TRKResetBuffer
+TRKResetBuffer:
+/* 801D5338 001D0F98 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 801D533C 001D0F9C 7C 08 02 A6 */ mflr r0
+/* 801D5340 001D0FA0 2C 04 00 00 */ cmpwi r4, 0
+/* 801D5344 001D0FA4 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D5348 001D0FA8 38 00 00 00 */ li r0, 0
+/* 801D534C 001D0FAC 90 03 00 08 */ stw r0, 8(r3)
+/* 801D5350 001D0FB0 90 03 00 0C */ stw r0, 0xc(r3)
+/* 801D5354 001D0FB4 40 82 00 14 */ bne lbl_801D5368
+/* 801D5358 001D0FB8 38 63 00 10 */ addi r3, r3, 0x10
+/* 801D535C 001D0FBC 38 80 00 00 */ li r4, 0
+/* 801D5360 001D0FC0 38 A0 08 80 */ li r5, 0x880
+/* 801D5364 001D0FC4 4B E2 ED D1 */ bl TRK_memset
+lbl_801D5368:
+/* 801D5368 001D0FC8 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D536C 001D0FCC 7C 08 03 A6 */ mtlr r0
+/* 801D5370 001D0FD0 38 21 00 10 */ addi r1, r1, 0x10
+/* 801D5374 001D0FD4 4E 80 00 20 */ blr
+
+.global TRKReleaseBuffer
+TRKReleaseBuffer:
+/* 801D5378 001D0FD8 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 801D537C 001D0FDC 7C 08 02 A6 */ mflr r0
+/* 801D5380 001D0FE0 2C 03 FF FF */ cmpwi r3, -1
+/* 801D5384 001D0FE4 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D5388 001D0FE8 93 E1 00 0C */ stw r31, 0xc(r1)
+/* 801D538C 001D0FEC 41 82 00 3C */ beq lbl_801D53C8
+/* 801D5390 001D0FF0 2C 03 00 00 */ cmpwi r3, 0
+/* 801D5394 001D0FF4 41 80 00 34 */ blt lbl_801D53C8
+/* 801D5398 001D0FF8 2C 03 00 03 */ cmpwi r3, 3
+/* 801D539C 001D0FFC 40 80 00 2C */ bge lbl_801D53C8
+/* 801D53A0 001D1000 1C 83 08 90 */ mulli r4, r3, 0x890
+/* 801D53A4 001D1004 3C 60 80 49 */ lis r3, lbl_8048EE20@ha
+/* 801D53A8 001D1008 38 03 EE 20 */ addi r0, r3, lbl_8048EE20@l
+/* 801D53AC 001D100C 7F E0 22 14 */ add r31, r0, r4
+/* 801D53B0 001D1010 7F E3 FB 78 */ mr r3, r31
+/* 801D53B4 001D1014 48 00 1C A9 */ bl TRKAcquireMutex
+/* 801D53B8 001D1018 38 00 00 00 */ li r0, 0
+/* 801D53BC 001D101C 7F E3 FB 78 */ mr r3, r31
+/* 801D53C0 001D1020 90 1F 00 04 */ stw r0, 4(r31)
+/* 801D53C4 001D1024 48 00 1C 91 */ bl TRKReleaseMutex
+lbl_801D53C8:
+/* 801D53C8 001D1028 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D53CC 001D102C 83 E1 00 0C */ lwz r31, 0xc(r1)
+/* 801D53D0 001D1030 7C 08 03 A6 */ mtlr r0
+/* 801D53D4 001D1034 38 21 00 10 */ addi r1, r1, 0x10
+/* 801D53D8 001D1038 4E 80 00 20 */ blr
+
+.global TRKGetBuffer
+TRKGetBuffer:
+/* 801D53DC 001D103C 2C 03 00 00 */ cmpwi r3, 0
+/* 801D53E0 001D1040 38 00 00 00 */ li r0, 0
+/* 801D53E4 001D1044 41 80 00 1C */ blt lbl_801D5400
+/* 801D53E8 001D1048 2C 03 00 03 */ cmpwi r3, 3
+/* 801D53EC 001D104C 40 80 00 14 */ bge lbl_801D5400
+/* 801D53F0 001D1050 1C 83 08 90 */ mulli r4, r3, 0x890
+/* 801D53F4 001D1054 3C 60 80 49 */ lis r3, lbl_8048EE20@ha
+/* 801D53F8 001D1058 38 03 EE 20 */ addi r0, r3, lbl_8048EE20@l
+/* 801D53FC 001D105C 7C 00 22 14 */ add r0, r0, r4
+lbl_801D5400:
+/* 801D5400 001D1060 7C 03 03 78 */ mr r3, r0
+/* 801D5404 001D1064 4E 80 00 20 */ blr
+
+.global TRKGetFreeBuffer
+TRKGetFreeBuffer:
+/* 801D5408 001D1068 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D540C 001D106C 7C 08 02 A6 */ mflr r0
+/* 801D5410 001D1070 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D5414 001D1074 38 00 00 00 */ li r0, 0
+/* 801D5418 001D1078 BF 61 00 0C */ stmw r27, 0xc(r1)
+/* 801D541C 001D107C 7C 9C 23 78 */ mr r28, r4
+/* 801D5420 001D1080 7C 7B 1B 78 */ mr r27, r3
+/* 801D5424 001D1084 3B C0 03 00 */ li r30, 0x300
+/* 801D5428 001D1088 3B A0 00 00 */ li r29, 0
+/* 801D542C 001D108C 90 04 00 00 */ stw r0, 0(r4)
+/* 801D5430 001D1090 48 00 00 6C */ b lbl_801D549C
+lbl_801D5434:
+/* 801D5434 001D1094 2C 1D 00 00 */ cmpwi r29, 0
+/* 801D5438 001D1098 3B E0 00 00 */ li r31, 0
+/* 801D543C 001D109C 41 80 00 1C */ blt lbl_801D5458
+/* 801D5440 001D10A0 2C 1D 00 03 */ cmpwi r29, 3
+/* 801D5444 001D10A4 40 80 00 14 */ bge lbl_801D5458
+/* 801D5448 001D10A8 1C 9D 08 90 */ mulli r4, r29, 0x890
+/* 801D544C 001D10AC 3C 60 80 49 */ lis r3, lbl_8048EE20@ha
+/* 801D5450 001D10B0 38 03 EE 20 */ addi r0, r3, lbl_8048EE20@l
+/* 801D5454 001D10B4 7F E0 22 14 */ add r31, r0, r4
+lbl_801D5458:
+/* 801D5458 001D10B8 7F E3 FB 78 */ mr r3, r31
+/* 801D545C 001D10BC 48 00 1C 01 */ bl TRKAcquireMutex
+/* 801D5460 001D10C0 80 1F 00 04 */ lwz r0, 4(r31)
+/* 801D5464 001D10C4 2C 00 00 00 */ cmpwi r0, 0
+/* 801D5468 001D10C8 40 82 00 28 */ bne lbl_801D5490
+/* 801D546C 001D10CC 38 60 00 00 */ li r3, 0
+/* 801D5470 001D10D0 38 00 00 01 */ li r0, 1
+/* 801D5474 001D10D4 90 7F 00 08 */ stw r3, 8(r31)
+/* 801D5478 001D10D8 3B C0 00 00 */ li r30, 0
+/* 801D547C 001D10DC 90 7F 00 0C */ stw r3, 0xc(r31)
+/* 801D5480 001D10E0 90 1F 00 04 */ stw r0, 4(r31)
+/* 801D5484 001D10E4 93 FC 00 00 */ stw r31, 0(r28)
+/* 801D5488 001D10E8 93 BB 00 00 */ stw r29, 0(r27)
+/* 801D548C 001D10EC 3B A0 00 03 */ li r29, 3
+lbl_801D5490:
+/* 801D5490 001D10F0 7F E3 FB 78 */ mr r3, r31
+/* 801D5494 001D10F4 48 00 1B C1 */ bl TRKReleaseMutex
+/* 801D5498 001D10F8 3B BD 00 01 */ addi r29, r29, 1
+lbl_801D549C:
+/* 801D549C 001D10FC 2C 1D 00 03 */ cmpwi r29, 3
+/* 801D54A0 001D1100 41 80 FF 94 */ blt lbl_801D5434
+/* 801D54A4 001D1104 2C 1E 03 00 */ cmpwi r30, 0x300
+/* 801D54A8 001D1108 40 82 00 10 */ bne lbl_801D54B8
+/* 801D54AC 001D110C 3C 60 80 40 */ lis r3, lbl_803FD660@ha
+/* 801D54B0 001D1110 38 63 D6 60 */ addi r3, r3, lbl_803FD660@l
+/* 801D54B4 001D1114 48 00 02 41 */ bl usr_puts_serial
+lbl_801D54B8:
+/* 801D54B8 001D1118 7F C3 F3 78 */ mr r3, r30
+/* 801D54BC 001D111C BB 61 00 0C */ lmw r27, 0xc(r1)
+/* 801D54C0 001D1120 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D54C4 001D1124 7C 08 03 A6 */ mtlr r0
+/* 801D54C8 001D1128 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D54CC 001D112C 4E 80 00 20 */ blr
+
+.global TRKInitializeMessageBuffers
+TRKInitializeMessageBuffers:
+/* 801D54D0 001D1130 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D54D4 001D1134 7C 08 02 A6 */ mflr r0
+/* 801D54D8 001D1138 3C 60 80 49 */ lis r3, lbl_8048EE20@ha
+/* 801D54DC 001D113C 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D54E0 001D1140 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D54E4 001D1144 3B E0 00 00 */ li r31, 0
+/* 801D54E8 001D1148 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D54EC 001D114C 3B C3 EE 20 */ addi r30, r3, lbl_8048EE20@l
+/* 801D54F0 001D1150 93 A1 00 14 */ stw r29, 0x14(r1)
+/* 801D54F4 001D1154 3B A0 00 00 */ li r29, 0
+lbl_801D54F8:
+/* 801D54F8 001D1158 7F C3 F3 78 */ mr r3, r30
+/* 801D54FC 001D115C 48 00 1B 69 */ bl TRKInitializeMutex
+/* 801D5500 001D1160 7F C3 F3 78 */ mr r3, r30
+/* 801D5504 001D1164 48 00 1B 59 */ bl TRKAcquireMutex
+/* 801D5508 001D1168 93 FE 00 04 */ stw r31, 4(r30)
+/* 801D550C 001D116C 7F C3 F3 78 */ mr r3, r30
+/* 801D5510 001D1170 48 00 1B 45 */ bl TRKReleaseMutex
+/* 801D5514 001D1174 3B BD 00 01 */ addi r29, r29, 1
+/* 801D5518 001D1178 3B DE 08 90 */ addi r30, r30, 0x890
+/* 801D551C 001D117C 2C 1D 00 03 */ cmpwi r29, 3
+/* 801D5520 001D1180 41 80 FF D8 */ blt lbl_801D54F8
+/* 801D5524 001D1184 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D5528 001D1188 38 60 00 00 */ li r3, 0
+/* 801D552C 001D118C 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D5530 001D1190 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D5534 001D1194 83 A1 00 14 */ lwz r29, 0x14(r1)
+/* 801D5538 001D1198 7C 08 03 A6 */ mtlr r0
+/* 801D553C 001D119C 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D5540 001D11A0 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/msghndlr.s b/asm/MetroTRK/msghndlr.s new file mode 100644 index 0000000..49e388c --- /dev/null +++ b/asm/MetroTRK/msghndlr.s @@ -0,0 +1,1202 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKDoSetOption
+TRKDoSetOption:
+/* 801D58C4 001D1524 94 21 FF B0 */ stwu r1, -0x50(r1)
+/* 801D58C8 001D1528 7C 08 02 A6 */ mflr r0
+/* 801D58CC 001D152C 3C 80 80 40 */ lis r4, lbl_803FD680@ha
+/* 801D58D0 001D1530 90 01 00 54 */ stw r0, 0x54(r1)
+/* 801D58D4 001D1534 93 E1 00 4C */ stw r31, 0x4c(r1)
+/* 801D58D8 001D1538 3B E4 D6 80 */ addi r31, r4, lbl_803FD680@l
+/* 801D58DC 001D153C 93 C1 00 48 */ stw r30, 0x48(r1)
+/* 801D58E0 001D1540 88 03 00 18 */ lbz r0, 0x18(r3)
+/* 801D58E4 001D1544 8B C3 00 1C */ lbz r30, 0x1c(r3)
+/* 801D58E8 001D1548 28 00 00 01 */ cmplwi r0, 1
+/* 801D58EC 001D154C 40 82 00 30 */ bne lbl_801D591C
+/* 801D58F0 001D1550 38 7F 00 00 */ addi r3, r31, 0
+/* 801D58F4 001D1554 4B FF FE 01 */ bl usr_puts_serial
+/* 801D58F8 001D1558 28 1E 00 00 */ cmplwi r30, 0
+/* 801D58FC 001D155C 41 82 00 10 */ beq lbl_801D590C
+/* 801D5900 001D1560 38 7F 00 20 */ addi r3, r31, 0x20
+/* 801D5904 001D1564 4B FF FD F1 */ bl usr_puts_serial
+/* 801D5908 001D1568 48 00 00 0C */ b lbl_801D5914
+lbl_801D590C:
+/* 801D590C 001D156C 38 7F 00 28 */ addi r3, r31, 0x28
+/* 801D5910 001D1570 4B FF FD E5 */ bl usr_puts_serial
+lbl_801D5914:
+/* 801D5914 001D1574 7F C3 F3 78 */ mr r3, r30
+/* 801D5918 001D1578 48 00 40 85 */ bl SetUseSerialIO
+lbl_801D591C:
+/* 801D591C 001D157C 38 61 00 08 */ addi r3, r1, 8
+/* 801D5920 001D1580 38 80 00 00 */ li r4, 0
+/* 801D5924 001D1584 38 A0 00 40 */ li r5, 0x40
+/* 801D5928 001D1588 4B E2 E8 0D */ bl TRK_memset
+/* 801D592C 001D158C 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5930 001D1590 38 00 00 80 */ li r0, 0x80
+/* 801D5934 001D1594 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D5938 001D1598 38 C0 00 40 */ li r6, 0x40
+/* 801D593C 001D159C 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D5940 001D15A0 38 A0 00 00 */ li r5, 0
+/* 801D5944 001D15A4 98 01 00 0C */ stb r0, 0xc(r1)
+/* 801D5948 001D15A8 38 61 00 08 */ addi r3, r1, 8
+/* 801D594C 001D15AC 38 E8 00 01 */ addi r7, r8, 1
+/* 801D5950 001D15B0 38 80 00 40 */ li r4, 0x40
+/* 801D5954 001D15B4 91 01 00 14 */ stw r8, 0x14(r1)
+/* 801D5958 001D15B8 38 07 00 01 */ addi r0, r7, 1
+/* 801D595C 001D15BC 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D5960 001D15C0 90 C1 00 08 */ stw r6, 8(r1)
+/* 801D5964 001D15C4 98 A1 00 10 */ stb r5, 0x10(r1)
+/* 801D5968 001D15C8 90 09 00 00 */ stw r0, 0(r9)
+/* 801D596C 001D15CC 90 E1 00 14 */ stw r7, 0x14(r1)
+/* 801D5970 001D15D0 48 00 3C 9D */ bl func_801D960C
+/* 801D5974 001D15D4 80 01 00 54 */ lwz r0, 0x54(r1)
+/* 801D5978 001D15D8 38 60 00 00 */ li r3, 0
+/* 801D597C 001D15DC 83 E1 00 4C */ lwz r31, 0x4c(r1)
+/* 801D5980 001D15E0 83 C1 00 48 */ lwz r30, 0x48(r1)
+/* 801D5984 001D15E4 7C 08 03 A6 */ mtlr r0
+/* 801D5988 001D15E8 38 21 00 50 */ addi r1, r1, 0x50
+/* 801D598C 001D15EC 4E 80 00 20 */ blr
+
+.global TRKDoStop
+TRKDoStop:
+/* 801D5990 001D15F0 94 21 FF B0 */ stwu r1, -0x50(r1)
+/* 801D5994 001D15F4 7C 08 02 A6 */ mflr r0
+/* 801D5998 001D15F8 90 01 00 54 */ stw r0, 0x54(r1)
+/* 801D599C 001D15FC 93 E1 00 4C */ stw r31, 0x4c(r1)
+/* 801D59A0 001D1600 48 00 1C 5D */ bl TRKTargetStop
+/* 801D59A4 001D1604 2C 03 07 04 */ cmpwi r3, 0x704
+/* 801D59A8 001D1608 41 82 00 2C */ beq lbl_801D59D4
+/* 801D59AC 001D160C 40 80 00 10 */ bge lbl_801D59BC
+/* 801D59B0 001D1610 2C 03 00 00 */ cmpwi r3, 0
+/* 801D59B4 001D1614 41 82 00 18 */ beq lbl_801D59CC
+/* 801D59B8 001D1618 48 00 00 34 */ b lbl_801D59EC
+lbl_801D59BC:
+/* 801D59BC 001D161C 2C 03 07 06 */ cmpwi r3, 0x706
+/* 801D59C0 001D1620 41 82 00 24 */ beq lbl_801D59E4
+/* 801D59C4 001D1624 40 80 00 28 */ bge lbl_801D59EC
+/* 801D59C8 001D1628 48 00 00 14 */ b lbl_801D59DC
+lbl_801D59CC:
+/* 801D59CC 001D162C 3B E0 00 00 */ li r31, 0
+/* 801D59D0 001D1630 48 00 00 20 */ b lbl_801D59F0
+lbl_801D59D4:
+/* 801D59D4 001D1634 3B E0 00 21 */ li r31, 0x21
+/* 801D59D8 001D1638 48 00 00 18 */ b lbl_801D59F0
+lbl_801D59DC:
+/* 801D59DC 001D163C 3B E0 00 22 */ li r31, 0x22
+/* 801D59E0 001D1640 48 00 00 10 */ b lbl_801D59F0
+lbl_801D59E4:
+/* 801D59E4 001D1644 3B E0 00 20 */ li r31, 0x20
+/* 801D59E8 001D1648 48 00 00 08 */ b lbl_801D59F0
+lbl_801D59EC:
+/* 801D59EC 001D164C 3B E0 00 01 */ li r31, 1
+lbl_801D59F0:
+/* 801D59F0 001D1650 38 61 00 08 */ addi r3, r1, 8
+/* 801D59F4 001D1654 38 80 00 00 */ li r4, 0
+/* 801D59F8 001D1658 38 A0 00 40 */ li r5, 0x40
+/* 801D59FC 001D165C 4B E2 E7 39 */ bl TRK_memset
+/* 801D5A00 001D1660 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5A04 001D1664 38 00 00 80 */ li r0, 0x80
+/* 801D5A08 001D1668 39 03 07 E8 */ addi r8, r3, lbl_804907E8@l
+/* 801D5A0C 001D166C 38 A0 00 40 */ li r5, 0x40
+/* 801D5A10 001D1670 80 E8 00 00 */ lwz r7, 0(r8)
+/* 801D5A14 001D1674 38 61 00 08 */ addi r3, r1, 8
+/* 801D5A18 001D1678 98 01 00 0C */ stb r0, 0xc(r1)
+/* 801D5A1C 001D167C 38 80 00 40 */ li r4, 0x40
+/* 801D5A20 001D1680 38 C7 00 01 */ addi r6, r7, 1
+/* 801D5A24 001D1684 90 E1 00 14 */ stw r7, 0x14(r1)
+/* 801D5A28 001D1688 38 06 00 01 */ addi r0, r6, 1
+/* 801D5A2C 001D168C 90 C8 00 00 */ stw r6, 0(r8)
+/* 801D5A30 001D1690 90 A1 00 08 */ stw r5, 8(r1)
+/* 801D5A34 001D1694 9B E1 00 10 */ stb r31, 0x10(r1)
+/* 801D5A38 001D1698 90 08 00 00 */ stw r0, 0(r8)
+/* 801D5A3C 001D169C 90 C1 00 14 */ stw r6, 0x14(r1)
+/* 801D5A40 001D16A0 48 00 3B CD */ bl func_801D960C
+/* 801D5A44 001D16A4 80 01 00 54 */ lwz r0, 0x54(r1)
+/* 801D5A48 001D16A8 38 60 00 00 */ li r3, 0
+/* 801D5A4C 001D16AC 83 E1 00 4C */ lwz r31, 0x4c(r1)
+/* 801D5A50 001D16B0 7C 08 03 A6 */ mtlr r0
+/* 801D5A54 001D16B4 38 21 00 50 */ addi r1, r1, 0x50
+/* 801D5A58 001D16B8 4E 80 00 20 */ blr
+
+.global TRKDoStep
+TRKDoStep:
+/* 801D5A5C 001D16BC 94 21 FE A0 */ stwu r1, -0x160(r1)
+/* 801D5A60 001D16C0 7C 08 02 A6 */ mflr r0
+/* 801D5A64 001D16C4 38 80 00 00 */ li r4, 0
+/* 801D5A68 001D16C8 90 01 01 64 */ stw r0, 0x164(r1)
+/* 801D5A6C 001D16CC BF 61 01 4C */ stmw r27, 0x14c(r1)
+/* 801D5A70 001D16D0 7C 7B 1B 78 */ mr r27, r3
+/* 801D5A74 001D16D4 4B FF F8 95 */ bl TRKSetBufferPosition
+/* 801D5A78 001D16D8 8B FB 00 18 */ lbz r31, 0x18(r27)
+/* 801D5A7C 001D16DC 83 BB 00 20 */ lwz r29, 0x20(r27)
+/* 801D5A80 001D16E0 2C 1F 00 10 */ cmpwi r31, 0x10
+/* 801D5A84 001D16E4 83 9B 00 24 */ lwz r28, 0x24(r27)
+/* 801D5A88 001D16E8 41 82 00 2C */ beq lbl_801D5AB4
+/* 801D5A8C 001D16EC 40 80 00 1C */ bge lbl_801D5AA8
+/* 801D5A90 001D16F0 2C 1F 00 01 */ cmpwi r31, 1
+/* 801D5A94 001D16F4 41 82 00 8C */ beq lbl_801D5B20
+/* 801D5A98 001D16F8 40 80 00 FC */ bge lbl_801D5B94
+/* 801D5A9C 001D16FC 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D5AA0 001D1700 40 80 00 14 */ bge lbl_801D5AB4
+/* 801D5AA4 001D1704 48 00 00 F0 */ b lbl_801D5B94
+lbl_801D5AA8:
+/* 801D5AA8 001D1708 2C 1F 00 12 */ cmpwi r31, 0x12
+/* 801D5AAC 001D170C 40 80 00 E8 */ bge lbl_801D5B94
+/* 801D5AB0 001D1710 48 00 00 70 */ b lbl_801D5B20
+lbl_801D5AB4:
+/* 801D5AB4 001D1714 8B DB 00 1C */ lbz r30, 0x1c(r27)
+/* 801D5AB8 001D1718 28 1E 00 01 */ cmplwi r30, 1
+/* 801D5ABC 001D171C 40 80 01 38 */ bge lbl_801D5BF4
+/* 801D5AC0 001D1720 38 61 01 08 */ addi r3, r1, 0x108
+/* 801D5AC4 001D1724 38 80 00 00 */ li r4, 0
+/* 801D5AC8 001D1728 38 A0 00 40 */ li r5, 0x40
+/* 801D5ACC 001D172C 4B E2 E6 69 */ bl TRK_memset
+/* 801D5AD0 001D1730 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5AD4 001D1734 38 00 00 80 */ li r0, 0x80
+/* 801D5AD8 001D1738 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D5ADC 001D173C 38 C0 00 40 */ li r6, 0x40
+/* 801D5AE0 001D1740 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D5AE4 001D1744 38 A0 00 11 */ li r5, 0x11
+/* 801D5AE8 001D1748 98 01 01 0C */ stb r0, 0x10c(r1)
+/* 801D5AEC 001D174C 38 61 01 08 */ addi r3, r1, 0x108
+/* 801D5AF0 001D1750 38 E8 00 01 */ addi r7, r8, 1
+/* 801D5AF4 001D1754 38 80 00 40 */ li r4, 0x40
+/* 801D5AF8 001D1758 91 01 01 14 */ stw r8, 0x114(r1)
+/* 801D5AFC 001D175C 38 07 00 01 */ addi r0, r7, 1
+/* 801D5B00 001D1760 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D5B04 001D1764 90 C1 01 08 */ stw r6, 0x108(r1)
+/* 801D5B08 001D1768 98 A1 01 10 */ stb r5, 0x110(r1)
+/* 801D5B0C 001D176C 90 09 00 00 */ stw r0, 0(r9)
+/* 801D5B10 001D1770 90 E1 01 14 */ stw r7, 0x114(r1)
+/* 801D5B14 001D1774 48 00 3A F9 */ bl func_801D960C
+/* 801D5B18 001D1778 38 60 00 00 */ li r3, 0
+/* 801D5B1C 001D177C 48 00 02 00 */ b lbl_801D5D1C
+lbl_801D5B20:
+/* 801D5B20 001D1780 48 00 1D 15 */ bl TRKTargetGetPC
+/* 801D5B24 001D1784 7C 03 E8 40 */ cmplw r3, r29
+/* 801D5B28 001D1788 41 80 00 0C */ blt lbl_801D5B34
+/* 801D5B2C 001D178C 7C 03 E0 40 */ cmplw r3, r28
+/* 801D5B30 001D1790 40 81 00 C4 */ ble lbl_801D5BF4
+lbl_801D5B34:
+/* 801D5B34 001D1794 38 61 00 C8 */ addi r3, r1, 0xc8
+/* 801D5B38 001D1798 38 80 00 00 */ li r4, 0
+/* 801D5B3C 001D179C 38 A0 00 40 */ li r5, 0x40
+/* 801D5B40 001D17A0 4B E2 E5 F5 */ bl TRK_memset
+/* 801D5B44 001D17A4 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5B48 001D17A8 38 00 00 80 */ li r0, 0x80
+/* 801D5B4C 001D17AC 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D5B50 001D17B0 38 C0 00 40 */ li r6, 0x40
+/* 801D5B54 001D17B4 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D5B58 001D17B8 38 A0 00 11 */ li r5, 0x11
+/* 801D5B5C 001D17BC 98 01 00 CC */ stb r0, 0xcc(r1)
+/* 801D5B60 001D17C0 38 61 00 C8 */ addi r3, r1, 0xc8
+/* 801D5B64 001D17C4 38 E8 00 01 */ addi r7, r8, 1
+/* 801D5B68 001D17C8 38 80 00 40 */ li r4, 0x40
+/* 801D5B6C 001D17CC 91 01 00 D4 */ stw r8, 0xd4(r1)
+/* 801D5B70 001D17D0 38 07 00 01 */ addi r0, r7, 1
+/* 801D5B74 001D17D4 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D5B78 001D17D8 90 C1 00 C8 */ stw r6, 0xc8(r1)
+/* 801D5B7C 001D17DC 98 A1 00 D0 */ stb r5, 0xd0(r1)
+/* 801D5B80 001D17E0 90 09 00 00 */ stw r0, 0(r9)
+/* 801D5B84 001D17E4 90 E1 00 D4 */ stw r7, 0xd4(r1)
+/* 801D5B88 001D17E8 48 00 3A 85 */ bl func_801D960C
+/* 801D5B8C 001D17EC 38 60 00 00 */ li r3, 0
+/* 801D5B90 001D17F0 48 00 01 8C */ b lbl_801D5D1C
+lbl_801D5B94:
+/* 801D5B94 001D17F4 38 61 00 88 */ addi r3, r1, 0x88
+/* 801D5B98 001D17F8 38 80 00 00 */ li r4, 0
+/* 801D5B9C 001D17FC 38 A0 00 40 */ li r5, 0x40
+/* 801D5BA0 001D1800 4B E2 E5 95 */ bl TRK_memset
+/* 801D5BA4 001D1804 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5BA8 001D1808 38 00 00 80 */ li r0, 0x80
+/* 801D5BAC 001D180C 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D5BB0 001D1810 38 C0 00 40 */ li r6, 0x40
+/* 801D5BB4 001D1814 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D5BB8 001D1818 38 A0 00 12 */ li r5, 0x12
+/* 801D5BBC 001D181C 98 01 00 8C */ stb r0, 0x8c(r1)
+/* 801D5BC0 001D1820 38 61 00 88 */ addi r3, r1, 0x88
+/* 801D5BC4 001D1824 38 E8 00 01 */ addi r7, r8, 1
+/* 801D5BC8 001D1828 38 80 00 40 */ li r4, 0x40
+/* 801D5BCC 001D182C 91 01 00 94 */ stw r8, 0x94(r1)
+/* 801D5BD0 001D1830 38 07 00 01 */ addi r0, r7, 1
+/* 801D5BD4 001D1834 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D5BD8 001D1838 90 C1 00 88 */ stw r6, 0x88(r1)
+/* 801D5BDC 001D183C 98 A1 00 90 */ stb r5, 0x90(r1)
+/* 801D5BE0 001D1840 90 09 00 00 */ stw r0, 0(r9)
+/* 801D5BE4 001D1844 90 E1 00 94 */ stw r7, 0x94(r1)
+/* 801D5BE8 001D1848 48 00 3A 25 */ bl func_801D960C
+/* 801D5BEC 001D184C 38 60 00 00 */ li r3, 0
+/* 801D5BF0 001D1850 48 00 01 2C */ b lbl_801D5D1C
+lbl_801D5BF4:
+/* 801D5BF4 001D1854 48 00 1A 31 */ bl TRKTargetStopped
+/* 801D5BF8 001D1858 2C 03 00 00 */ cmpwi r3, 0
+/* 801D5BFC 001D185C 40 82 00 64 */ bne lbl_801D5C60
+/* 801D5C00 001D1860 38 61 00 48 */ addi r3, r1, 0x48
+/* 801D5C04 001D1864 38 80 00 00 */ li r4, 0
+/* 801D5C08 001D1868 38 A0 00 40 */ li r5, 0x40
+/* 801D5C0C 001D186C 4B E2 E5 29 */ bl TRK_memset
+/* 801D5C10 001D1870 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5C14 001D1874 38 00 00 80 */ li r0, 0x80
+/* 801D5C18 001D1878 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D5C1C 001D187C 38 C0 00 40 */ li r6, 0x40
+/* 801D5C20 001D1880 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D5C24 001D1884 38 A0 00 16 */ li r5, 0x16
+/* 801D5C28 001D1888 98 01 00 4C */ stb r0, 0x4c(r1)
+/* 801D5C2C 001D188C 38 61 00 48 */ addi r3, r1, 0x48
+/* 801D5C30 001D1890 38 E8 00 01 */ addi r7, r8, 1
+/* 801D5C34 001D1894 38 80 00 40 */ li r4, 0x40
+/* 801D5C38 001D1898 91 01 00 54 */ stw r8, 0x54(r1)
+/* 801D5C3C 001D189C 38 07 00 01 */ addi r0, r7, 1
+/* 801D5C40 001D18A0 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D5C44 001D18A4 90 C1 00 48 */ stw r6, 0x48(r1)
+/* 801D5C48 001D18A8 98 A1 00 50 */ stb r5, 0x50(r1)
+/* 801D5C4C 001D18AC 90 09 00 00 */ stw r0, 0(r9)
+/* 801D5C50 001D18B0 90 E1 00 54 */ stw r7, 0x54(r1)
+/* 801D5C54 001D18B4 48 00 39 B9 */ bl func_801D960C
+/* 801D5C58 001D18B8 38 60 00 00 */ li r3, 0
+/* 801D5C5C 001D18BC 48 00 00 C0 */ b lbl_801D5D1C
+lbl_801D5C60:
+/* 801D5C60 001D18C0 38 61 00 08 */ addi r3, r1, 8
+/* 801D5C64 001D18C4 38 80 00 00 */ li r4, 0
+/* 801D5C68 001D18C8 38 A0 00 40 */ li r5, 0x40
+/* 801D5C6C 001D18CC 4B E2 E4 C9 */ bl TRK_memset
+/* 801D5C70 001D18D0 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5C74 001D18D4 38 00 00 80 */ li r0, 0x80
+/* 801D5C78 001D18D8 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D5C7C 001D18DC 38 C0 00 40 */ li r6, 0x40
+/* 801D5C80 001D18E0 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D5C84 001D18E4 38 A0 00 00 */ li r5, 0
+/* 801D5C88 001D18E8 98 01 00 0C */ stb r0, 0xc(r1)
+/* 801D5C8C 001D18EC 38 61 00 08 */ addi r3, r1, 8
+/* 801D5C90 001D18F0 38 E8 00 01 */ addi r7, r8, 1
+/* 801D5C94 001D18F4 38 80 00 40 */ li r4, 0x40
+/* 801D5C98 001D18F8 91 01 00 14 */ stw r8, 0x14(r1)
+/* 801D5C9C 001D18FC 38 07 00 01 */ addi r0, r7, 1
+/* 801D5CA0 001D1900 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D5CA4 001D1904 90 C1 00 08 */ stw r6, 8(r1)
+/* 801D5CA8 001D1908 98 A1 00 10 */ stb r5, 0x10(r1)
+/* 801D5CAC 001D190C 90 09 00 00 */ stw r0, 0(r9)
+/* 801D5CB0 001D1910 90 E1 00 14 */ stw r7, 0x14(r1)
+/* 801D5CB4 001D1914 48 00 39 59 */ bl func_801D960C
+/* 801D5CB8 001D1918 2C 1F 00 10 */ cmpwi r31, 0x10
+/* 801D5CBC 001D191C 38 60 00 00 */ li r3, 0
+/* 801D5CC0 001D1920 41 82 00 2C */ beq lbl_801D5CEC
+/* 801D5CC4 001D1924 40 80 00 1C */ bge lbl_801D5CE0
+/* 801D5CC8 001D1928 2C 1F 00 01 */ cmpwi r31, 1
+/* 801D5CCC 001D192C 41 82 00 38 */ beq lbl_801D5D04
+/* 801D5CD0 001D1930 40 80 00 4C */ bge lbl_801D5D1C
+/* 801D5CD4 001D1934 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D5CD8 001D1938 40 80 00 14 */ bge lbl_801D5CEC
+/* 801D5CDC 001D193C 48 00 00 40 */ b lbl_801D5D1C
+lbl_801D5CE0:
+/* 801D5CE0 001D1940 2C 1F 00 12 */ cmpwi r31, 0x12
+/* 801D5CE4 001D1944 40 80 00 38 */ bge lbl_801D5D1C
+/* 801D5CE8 001D1948 48 00 00 1C */ b lbl_801D5D04
+lbl_801D5CEC:
+/* 801D5CEC 001D194C 20 1F 00 10 */ subfic r0, r31, 0x10
+/* 801D5CF0 001D1950 7F C3 F3 78 */ mr r3, r30
+/* 801D5CF4 001D1954 7C 00 00 34 */ cntlzw r0, r0
+/* 801D5CF8 001D1958 54 04 D9 7E */ srwi r4, r0, 5
+/* 801D5CFC 001D195C 48 00 1B C5 */ bl TRKTargetSingleStep
+/* 801D5D00 001D1960 48 00 00 1C */ b lbl_801D5D1C
+lbl_801D5D04:
+/* 801D5D04 001D1964 20 1F 00 11 */ subfic r0, r31, 0x11
+/* 801D5D08 001D1968 7F A3 EB 78 */ mr r3, r29
+/* 801D5D0C 001D196C 7C 00 00 34 */ cntlzw r0, r0
+/* 801D5D10 001D1970 7F 84 E3 78 */ mr r4, r28
+/* 801D5D14 001D1974 54 05 D9 7E */ srwi r5, r0, 5
+/* 801D5D18 001D1978 48 00 1B 2D */ bl TRKTargetStepOutOfRange
+lbl_801D5D1C:
+/* 801D5D1C 001D197C BB 61 01 4C */ lmw r27, 0x14c(r1)
+/* 801D5D20 001D1980 80 01 01 64 */ lwz r0, 0x164(r1)
+/* 801D5D24 001D1984 7C 08 03 A6 */ mtlr r0
+/* 801D5D28 001D1988 38 21 01 60 */ addi r1, r1, 0x160
+/* 801D5D2C 001D198C 4E 80 00 20 */ blr
+
+.global TRKDoContinue
+TRKDoContinue:
+/* 801D5D30 001D1990 94 21 FF 70 */ stwu r1, -0x90(r1)
+/* 801D5D34 001D1994 7C 08 02 A6 */ mflr r0
+/* 801D5D38 001D1998 90 01 00 94 */ stw r0, 0x94(r1)
+/* 801D5D3C 001D199C 48 00 18 E9 */ bl TRKTargetStopped
+/* 801D5D40 001D19A0 2C 03 00 00 */ cmpwi r3, 0
+/* 801D5D44 001D19A4 40 82 00 64 */ bne lbl_801D5DA8
+/* 801D5D48 001D19A8 38 61 00 48 */ addi r3, r1, 0x48
+/* 801D5D4C 001D19AC 38 80 00 00 */ li r4, 0
+/* 801D5D50 001D19B0 38 A0 00 40 */ li r5, 0x40
+/* 801D5D54 001D19B4 4B E2 E3 E1 */ bl TRK_memset
+/* 801D5D58 001D19B8 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5D5C 001D19BC 38 00 00 80 */ li r0, 0x80
+/* 801D5D60 001D19C0 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D5D64 001D19C4 38 C0 00 40 */ li r6, 0x40
+/* 801D5D68 001D19C8 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D5D6C 001D19CC 38 A0 00 16 */ li r5, 0x16
+/* 801D5D70 001D19D0 98 01 00 4C */ stb r0, 0x4c(r1)
+/* 801D5D74 001D19D4 38 61 00 48 */ addi r3, r1, 0x48
+/* 801D5D78 001D19D8 38 E8 00 01 */ addi r7, r8, 1
+/* 801D5D7C 001D19DC 38 80 00 40 */ li r4, 0x40
+/* 801D5D80 001D19E0 91 01 00 54 */ stw r8, 0x54(r1)
+/* 801D5D84 001D19E4 38 07 00 01 */ addi r0, r7, 1
+/* 801D5D88 001D19E8 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D5D8C 001D19EC 90 C1 00 48 */ stw r6, 0x48(r1)
+/* 801D5D90 001D19F0 98 A1 00 50 */ stb r5, 0x50(r1)
+/* 801D5D94 001D19F4 90 09 00 00 */ stw r0, 0(r9)
+/* 801D5D98 001D19F8 90 E1 00 54 */ stw r7, 0x54(r1)
+/* 801D5D9C 001D19FC 48 00 38 71 */ bl func_801D960C
+/* 801D5DA0 001D1A00 38 60 00 00 */ li r3, 0
+/* 801D5DA4 001D1A04 48 00 00 60 */ b lbl_801D5E04
+lbl_801D5DA8:
+/* 801D5DA8 001D1A08 38 61 00 08 */ addi r3, r1, 8
+/* 801D5DAC 001D1A0C 38 80 00 00 */ li r4, 0
+/* 801D5DB0 001D1A10 38 A0 00 40 */ li r5, 0x40
+/* 801D5DB4 001D1A14 4B E2 E3 81 */ bl TRK_memset
+/* 801D5DB8 001D1A18 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5DBC 001D1A1C 38 00 00 80 */ li r0, 0x80
+/* 801D5DC0 001D1A20 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D5DC4 001D1A24 38 C0 00 40 */ li r6, 0x40
+/* 801D5DC8 001D1A28 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D5DCC 001D1A2C 38 A0 00 00 */ li r5, 0
+/* 801D5DD0 001D1A30 98 01 00 0C */ stb r0, 0xc(r1)
+/* 801D5DD4 001D1A34 38 61 00 08 */ addi r3, r1, 8
+/* 801D5DD8 001D1A38 38 E8 00 01 */ addi r7, r8, 1
+/* 801D5DDC 001D1A3C 38 80 00 40 */ li r4, 0x40
+/* 801D5DE0 001D1A40 91 01 00 14 */ stw r8, 0x14(r1)
+/* 801D5DE4 001D1A44 38 07 00 01 */ addi r0, r7, 1
+/* 801D5DE8 001D1A48 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D5DEC 001D1A4C 90 C1 00 08 */ stw r6, 8(r1)
+/* 801D5DF0 001D1A50 98 A1 00 10 */ stb r5, 0x10(r1)
+/* 801D5DF4 001D1A54 90 09 00 00 */ stw r0, 0(r9)
+/* 801D5DF8 001D1A58 90 E1 00 14 */ stw r7, 0x14(r1)
+/* 801D5DFC 001D1A5C 48 00 38 11 */ bl func_801D960C
+/* 801D5E00 001D1A60 48 00 3B 59 */ bl TRKTargetContinue
+lbl_801D5E04:
+/* 801D5E04 001D1A64 80 01 00 94 */ lwz r0, 0x94(r1)
+/* 801D5E08 001D1A68 7C 08 03 A6 */ mtlr r0
+/* 801D5E0C 001D1A6C 38 21 00 90 */ addi r1, r1, 0x90
+/* 801D5E10 001D1A70 4E 80 00 20 */ blr
+
+.global TRKDoWriteRegisters
+TRKDoWriteRegisters:
+/* 801D5E14 001D1A74 94 21 FF 20 */ stwu r1, -0xe0(r1)
+/* 801D5E18 001D1A78 7C 08 02 A6 */ mflr r0
+/* 801D5E1C 001D1A7C 38 80 00 00 */ li r4, 0
+/* 801D5E20 001D1A80 90 01 00 E4 */ stw r0, 0xe4(r1)
+/* 801D5E24 001D1A84 93 E1 00 DC */ stw r31, 0xdc(r1)
+/* 801D5E28 001D1A88 93 C1 00 D8 */ stw r30, 0xd8(r1)
+/* 801D5E2C 001D1A8C 93 A1 00 D4 */ stw r29, 0xd4(r1)
+/* 801D5E30 001D1A90 93 81 00 D0 */ stw r28, 0xd0(r1)
+/* 801D5E34 001D1A94 7C 7C 1B 78 */ mr r28, r3
+/* 801D5E38 001D1A98 8B E3 00 18 */ lbz r31, 0x18(r3)
+/* 801D5E3C 001D1A9C A3 C3 00 1C */ lhz r30, 0x1c(r3)
+/* 801D5E40 001D1AA0 A3 A3 00 20 */ lhz r29, 0x20(r3)
+/* 801D5E44 001D1AA4 4B FF F4 C5 */ bl TRKSetBufferPosition
+/* 801D5E48 001D1AA8 7C 1E E8 40 */ cmplw r30, r29
+/* 801D5E4C 001D1AAC 40 81 00 64 */ ble lbl_801D5EB0
+/* 801D5E50 001D1AB0 38 61 00 4C */ addi r3, r1, 0x4c
+/* 801D5E54 001D1AB4 38 80 00 00 */ li r4, 0
+/* 801D5E58 001D1AB8 38 A0 00 40 */ li r5, 0x40
+/* 801D5E5C 001D1ABC 4B E2 E2 D9 */ bl TRK_memset
+/* 801D5E60 001D1AC0 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5E64 001D1AC4 38 00 00 80 */ li r0, 0x80
+/* 801D5E68 001D1AC8 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D5E6C 001D1ACC 38 C0 00 40 */ li r6, 0x40
+/* 801D5E70 001D1AD0 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D5E74 001D1AD4 38 A0 00 14 */ li r5, 0x14
+/* 801D5E78 001D1AD8 98 01 00 50 */ stb r0, 0x50(r1)
+/* 801D5E7C 001D1ADC 38 61 00 4C */ addi r3, r1, 0x4c
+/* 801D5E80 001D1AE0 38 E8 00 01 */ addi r7, r8, 1
+/* 801D5E84 001D1AE4 38 80 00 40 */ li r4, 0x40
+/* 801D5E88 001D1AE8 91 01 00 58 */ stw r8, 0x58(r1)
+/* 801D5E8C 001D1AEC 38 07 00 01 */ addi r0, r7, 1
+/* 801D5E90 001D1AF0 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D5E94 001D1AF4 90 C1 00 4C */ stw r6, 0x4c(r1)
+/* 801D5E98 001D1AF8 98 A1 00 54 */ stb r5, 0x54(r1)
+/* 801D5E9C 001D1AFC 90 09 00 00 */ stw r0, 0(r9)
+/* 801D5EA0 001D1B00 90 E1 00 58 */ stw r7, 0x58(r1)
+/* 801D5EA4 001D1B04 48 00 37 69 */ bl func_801D960C
+/* 801D5EA8 001D1B08 38 60 00 00 */ li r3, 0
+/* 801D5EAC 001D1B0C 48 00 02 04 */ b lbl_801D60B0
+lbl_801D5EB0:
+/* 801D5EB0 001D1B10 7F 83 E3 78 */ mr r3, r28
+/* 801D5EB4 001D1B14 38 80 00 40 */ li r4, 0x40
+/* 801D5EB8 001D1B18 4B FF F4 51 */ bl TRKSetBufferPosition
+/* 801D5EBC 001D1B1C 2C 1F 00 02 */ cmpwi r31, 2
+/* 801D5EC0 001D1B20 41 82 00 64 */ beq lbl_801D5F24
+/* 801D5EC4 001D1B24 40 80 00 14 */ bge lbl_801D5ED8
+/* 801D5EC8 001D1B28 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D5ECC 001D1B2C 41 82 00 18 */ beq lbl_801D5EE4
+/* 801D5ED0 001D1B30 40 80 00 34 */ bge lbl_801D5F04
+/* 801D5ED4 001D1B34 48 00 00 90 */ b lbl_801D5F64
+lbl_801D5ED8:
+/* 801D5ED8 001D1B38 2C 1F 00 04 */ cmpwi r31, 4
+/* 801D5EDC 001D1B3C 40 80 00 88 */ bge lbl_801D5F64
+/* 801D5EE0 001D1B40 48 00 00 64 */ b lbl_801D5F44
+lbl_801D5EE4:
+/* 801D5EE4 001D1B44 7F C3 F3 78 */ mr r3, r30
+/* 801D5EE8 001D1B48 7F A4 EB 78 */ mr r4, r29
+/* 801D5EEC 001D1B4C 7F 85 E3 78 */ mr r5, r28
+/* 801D5EF0 001D1B50 38 C1 00 08 */ addi r6, r1, 8
+/* 801D5EF4 001D1B54 38 E0 00 00 */ li r7, 0
+/* 801D5EF8 001D1B58 48 00 28 01 */ bl TRKTargetAccessDefault
+/* 801D5EFC 001D1B5C 7C 7F 1B 78 */ mr r31, r3
+/* 801D5F00 001D1B60 48 00 00 68 */ b lbl_801D5F68
+lbl_801D5F04:
+/* 801D5F04 001D1B64 7F C3 F3 78 */ mr r3, r30
+/* 801D5F08 001D1B68 7F A4 EB 78 */ mr r4, r29
+/* 801D5F0C 001D1B6C 7F 85 E3 78 */ mr r5, r28
+/* 801D5F10 001D1B70 38 C1 00 08 */ addi r6, r1, 8
+/* 801D5F14 001D1B74 38 E0 00 00 */ li r7, 0
+/* 801D5F18 001D1B78 48 00 22 D5 */ bl TRKTargetAccessFP
+/* 801D5F1C 001D1B7C 7C 7F 1B 78 */ mr r31, r3
+/* 801D5F20 001D1B80 48 00 00 48 */ b lbl_801D5F68
+lbl_801D5F24:
+/* 801D5F24 001D1B84 7F C3 F3 78 */ mr r3, r30
+/* 801D5F28 001D1B88 7F A4 EB 78 */ mr r4, r29
+/* 801D5F2C 001D1B8C 7F 85 E3 78 */ mr r5, r28
+/* 801D5F30 001D1B90 38 C1 00 08 */ addi r6, r1, 8
+/* 801D5F34 001D1B94 38 E0 00 00 */ li r7, 0
+/* 801D5F38 001D1B98 48 00 21 45 */ bl TRKTargetAccessExtended1
+/* 801D5F3C 001D1B9C 7C 7F 1B 78 */ mr r31, r3
+/* 801D5F40 001D1BA0 48 00 00 28 */ b lbl_801D5F68
+lbl_801D5F44:
+/* 801D5F44 001D1BA4 7F C3 F3 78 */ mr r3, r30
+/* 801D5F48 001D1BA8 7F A4 EB 78 */ mr r4, r29
+/* 801D5F4C 001D1BAC 7F 85 E3 78 */ mr r5, r28
+/* 801D5F50 001D1BB0 38 C1 00 08 */ addi r6, r1, 8
+/* 801D5F54 001D1BB4 38 E0 00 00 */ li r7, 0
+/* 801D5F58 001D1BB8 48 00 1C ED */ bl TRKTargetAccessExtended2
+/* 801D5F5C 001D1BBC 7C 7F 1B 78 */ mr r31, r3
+/* 801D5F60 001D1BC0 48 00 00 08 */ b lbl_801D5F68
+lbl_801D5F64:
+/* 801D5F64 001D1BC4 3B E0 07 03 */ li r31, 0x703
+lbl_801D5F68:
+/* 801D5F68 001D1BC8 7F 83 E3 78 */ mr r3, r28
+/* 801D5F6C 001D1BCC 38 80 00 00 */ li r4, 0
+/* 801D5F70 001D1BD0 4B FF F3 C9 */ bl TRKResetBuffer
+/* 801D5F74 001D1BD4 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D5F78 001D1BD8 40 82 00 54 */ bne lbl_801D5FCC
+/* 801D5F7C 001D1BDC 38 61 00 8C */ addi r3, r1, 0x8c
+/* 801D5F80 001D1BE0 38 80 00 00 */ li r4, 0
+/* 801D5F84 001D1BE4 38 A0 00 40 */ li r5, 0x40
+/* 801D5F88 001D1BE8 4B E2 E1 AD */ bl TRK_memset
+/* 801D5F8C 001D1BEC 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D5F90 001D1BF0 38 00 00 40 */ li r0, 0x40
+/* 801D5F94 001D1BF4 38 E3 07 E8 */ addi r7, r3, lbl_804907E8@l
+/* 801D5F98 001D1BF8 38 A0 00 80 */ li r5, 0x80
+/* 801D5F9C 001D1BFC 80 C7 00 00 */ lwz r6, 0(r7)
+/* 801D5FA0 001D1C00 7F 83 E3 78 */ mr r3, r28
+/* 801D5FA4 001D1C04 90 01 00 8C */ stw r0, 0x8c(r1)
+/* 801D5FA8 001D1C08 38 81 00 8C */ addi r4, r1, 0x8c
+/* 801D5FAC 001D1C0C 38 06 00 01 */ addi r0, r6, 1
+/* 801D5FB0 001D1C10 98 A1 00 90 */ stb r5, 0x90(r1)
+/* 801D5FB4 001D1C14 38 A0 00 40 */ li r5, 0x40
+/* 801D5FB8 001D1C18 9B E1 00 94 */ stb r31, 0x94(r1)
+/* 801D5FBC 001D1C1C 90 07 00 00 */ stw r0, 0(r7)
+/* 801D5FC0 001D1C20 90 C1 00 98 */ stw r6, 0x98(r1)
+/* 801D5FC4 001D1C24 4B FF F2 A1 */ bl TRKAppendBuffer
+/* 801D5FC8 001D1C28 7C 7F 1B 78 */ mr r31, r3
+lbl_801D5FCC:
+/* 801D5FCC 001D1C2C 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D5FD0 001D1C30 41 82 00 D8 */ beq lbl_801D60A8
+/* 801D5FD4 001D1C34 2C 1F 07 03 */ cmpwi r31, 0x703
+/* 801D5FD8 001D1C38 41 82 00 38 */ beq lbl_801D6010
+/* 801D5FDC 001D1C3C 40 80 00 1C */ bge lbl_801D5FF8
+/* 801D5FE0 001D1C40 2C 1F 07 01 */ cmpwi r31, 0x701
+/* 801D5FE4 001D1C44 41 82 00 34 */ beq lbl_801D6018
+/* 801D5FE8 001D1C48 40 80 00 40 */ bge lbl_801D6028
+/* 801D5FEC 001D1C4C 2C 1F 03 02 */ cmpwi r31, 0x302
+/* 801D5FF0 001D1C50 41 82 00 30 */ beq lbl_801D6020
+/* 801D5FF4 001D1C54 48 00 00 54 */ b lbl_801D6048
+lbl_801D5FF8:
+/* 801D5FF8 001D1C58 2C 1F 07 06 */ cmpwi r31, 0x706
+/* 801D5FFC 001D1C5C 41 82 00 44 */ beq lbl_801D6040
+/* 801D6000 001D1C60 40 80 00 48 */ bge lbl_801D6048
+/* 801D6004 001D1C64 2C 1F 07 05 */ cmpwi r31, 0x705
+/* 801D6008 001D1C68 40 80 00 30 */ bge lbl_801D6038
+/* 801D600C 001D1C6C 48 00 00 24 */ b lbl_801D6030
+lbl_801D6010:
+/* 801D6010 001D1C70 3B E0 00 12 */ li r31, 0x12
+/* 801D6014 001D1C74 48 00 00 38 */ b lbl_801D604C
+lbl_801D6018:
+/* 801D6018 001D1C78 3B E0 00 14 */ li r31, 0x14
+/* 801D601C 001D1C7C 48 00 00 30 */ b lbl_801D604C
+lbl_801D6020:
+/* 801D6020 001D1C80 3B E0 00 02 */ li r31, 2
+/* 801D6024 001D1C84 48 00 00 28 */ b lbl_801D604C
+lbl_801D6028:
+/* 801D6028 001D1C88 3B E0 00 15 */ li r31, 0x15
+/* 801D602C 001D1C8C 48 00 00 20 */ b lbl_801D604C
+lbl_801D6030:
+/* 801D6030 001D1C90 3B E0 00 21 */ li r31, 0x21
+/* 801D6034 001D1C94 48 00 00 18 */ b lbl_801D604C
+lbl_801D6038:
+/* 801D6038 001D1C98 3B E0 00 22 */ li r31, 0x22
+/* 801D603C 001D1C9C 48 00 00 10 */ b lbl_801D604C
+lbl_801D6040:
+/* 801D6040 001D1CA0 3B E0 00 20 */ li r31, 0x20
+/* 801D6044 001D1CA4 48 00 00 08 */ b lbl_801D604C
+lbl_801D6048:
+/* 801D6048 001D1CA8 3B E0 00 03 */ li r31, 3
+lbl_801D604C:
+/* 801D604C 001D1CAC 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D6050 001D1CB0 38 80 00 00 */ li r4, 0
+/* 801D6054 001D1CB4 38 A0 00 40 */ li r5, 0x40
+/* 801D6058 001D1CB8 4B E2 E0 DD */ bl TRK_memset
+/* 801D605C 001D1CBC 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D6060 001D1CC0 38 00 00 80 */ li r0, 0x80
+/* 801D6064 001D1CC4 39 03 07 E8 */ addi r8, r3, lbl_804907E8@l
+/* 801D6068 001D1CC8 38 A0 00 40 */ li r5, 0x40
+/* 801D606C 001D1CCC 80 E8 00 00 */ lwz r7, 0(r8)
+/* 801D6070 001D1CD0 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D6074 001D1CD4 98 01 00 10 */ stb r0, 0x10(r1)
+/* 801D6078 001D1CD8 38 80 00 40 */ li r4, 0x40
+/* 801D607C 001D1CDC 38 C7 00 01 */ addi r6, r7, 1
+/* 801D6080 001D1CE0 90 E1 00 18 */ stw r7, 0x18(r1)
+/* 801D6084 001D1CE4 38 06 00 01 */ addi r0, r6, 1
+/* 801D6088 001D1CE8 90 C8 00 00 */ stw r6, 0(r8)
+/* 801D608C 001D1CEC 90 A1 00 0C */ stw r5, 0xc(r1)
+/* 801D6090 001D1CF0 9B E1 00 14 */ stb r31, 0x14(r1)
+/* 801D6094 001D1CF4 90 08 00 00 */ stw r0, 0(r8)
+/* 801D6098 001D1CF8 90 C1 00 18 */ stw r6, 0x18(r1)
+/* 801D609C 001D1CFC 48 00 35 71 */ bl func_801D960C
+/* 801D60A0 001D1D00 38 60 00 00 */ li r3, 0
+/* 801D60A4 001D1D04 48 00 00 0C */ b lbl_801D60B0
+lbl_801D60A8:
+/* 801D60A8 001D1D08 7F 83 E3 78 */ mr r3, r28
+/* 801D60AC 001D1D0C 4B FF EC 31 */ bl TRKMessageSend
+lbl_801D60B0:
+/* 801D60B0 001D1D10 80 01 00 E4 */ lwz r0, 0xe4(r1)
+/* 801D60B4 001D1D14 83 E1 00 DC */ lwz r31, 0xdc(r1)
+/* 801D60B8 001D1D18 83 C1 00 D8 */ lwz r30, 0xd8(r1)
+/* 801D60BC 001D1D1C 83 A1 00 D4 */ lwz r29, 0xd4(r1)
+/* 801D60C0 001D1D20 83 81 00 D0 */ lwz r28, 0xd0(r1)
+/* 801D60C4 001D1D24 7C 08 03 A6 */ mtlr r0
+/* 801D60C8 001D1D28 38 21 00 E0 */ addi r1, r1, 0xe0
+/* 801D60CC 001D1D2C 4E 80 00 20 */ blr
+
+.global TRKDoReadRegisters
+TRKDoReadRegisters:
+/* 801D60D0 001D1D30 94 21 FF 20 */ stwu r1, -0xe0(r1)
+/* 801D60D4 001D1D34 7C 08 02 A6 */ mflr r0
+/* 801D60D8 001D1D38 90 01 00 E4 */ stw r0, 0xe4(r1)
+/* 801D60DC 001D1D3C 93 E1 00 DC */ stw r31, 0xdc(r1)
+/* 801D60E0 001D1D40 7C 7F 1B 78 */ mr r31, r3
+/* 801D60E4 001D1D44 A0 83 00 1C */ lhz r4, 0x1c(r3)
+/* 801D60E8 001D1D48 A0 03 00 20 */ lhz r0, 0x20(r3)
+/* 801D60EC 001D1D4C 7C 04 00 40 */ cmplw r4, r0
+/* 801D60F0 001D1D50 40 81 00 64 */ ble lbl_801D6154
+/* 801D60F4 001D1D54 38 61 00 4C */ addi r3, r1, 0x4c
+/* 801D60F8 001D1D58 38 80 00 00 */ li r4, 0
+/* 801D60FC 001D1D5C 38 A0 00 40 */ li r5, 0x40
+/* 801D6100 001D1D60 4B E2 E0 35 */ bl TRK_memset
+/* 801D6104 001D1D64 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D6108 001D1D68 38 00 00 80 */ li r0, 0x80
+/* 801D610C 001D1D6C 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D6110 001D1D70 38 C0 00 40 */ li r6, 0x40
+/* 801D6114 001D1D74 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D6118 001D1D78 38 A0 00 14 */ li r5, 0x14
+/* 801D611C 001D1D7C 98 01 00 50 */ stb r0, 0x50(r1)
+/* 801D6120 001D1D80 38 61 00 4C */ addi r3, r1, 0x4c
+/* 801D6124 001D1D84 38 E8 00 01 */ addi r7, r8, 1
+/* 801D6128 001D1D88 38 80 00 40 */ li r4, 0x40
+/* 801D612C 001D1D8C 91 01 00 58 */ stw r8, 0x58(r1)
+/* 801D6130 001D1D90 38 07 00 01 */ addi r0, r7, 1
+/* 801D6134 001D1D94 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D6138 001D1D98 90 C1 00 4C */ stw r6, 0x4c(r1)
+/* 801D613C 001D1D9C 98 A1 00 54 */ stb r5, 0x54(r1)
+/* 801D6140 001D1DA0 90 09 00 00 */ stw r0, 0(r9)
+/* 801D6144 001D1DA4 90 E1 00 58 */ stw r7, 0x58(r1)
+/* 801D6148 001D1DA8 48 00 34 C5 */ bl func_801D960C
+/* 801D614C 001D1DAC 38 60 00 00 */ li r3, 0
+/* 801D6150 001D1DB0 48 00 01 90 */ b lbl_801D62E0
+lbl_801D6154:
+/* 801D6154 001D1DB4 3C 80 80 49 */ lis r4, lbl_804907E8@ha
+/* 801D6158 001D1DB8 38 00 00 80 */ li r0, 0x80
+/* 801D615C 001D1DBC 38 C4 07 E8 */ addi r6, r4, lbl_804907E8@l
+/* 801D6160 001D1DC0 38 E0 04 68 */ li r7, 0x468
+/* 801D6164 001D1DC4 80 A6 00 00 */ lwz r5, 0(r6)
+/* 801D6168 001D1DC8 38 80 00 00 */ li r4, 0
+/* 801D616C 001D1DCC 98 01 00 90 */ stb r0, 0x90(r1)
+/* 801D6170 001D1DD0 38 05 00 01 */ addi r0, r5, 1
+/* 801D6174 001D1DD4 90 E1 00 8C */ stw r7, 0x8c(r1)
+/* 801D6178 001D1DD8 90 06 00 00 */ stw r0, 0(r6)
+/* 801D617C 001D1DDC 90 A1 00 98 */ stw r5, 0x98(r1)
+/* 801D6180 001D1DE0 4B FF F1 B9 */ bl TRKResetBuffer
+/* 801D6184 001D1DE4 7F E3 FB 78 */ mr r3, r31
+/* 801D6188 001D1DE8 38 81 00 8C */ addi r4, r1, 0x8c
+/* 801D618C 001D1DEC 38 A0 00 40 */ li r5, 0x40
+/* 801D6190 001D1DF0 4B FF EE E5 */ bl TRKAppendBuffer_ui8
+/* 801D6194 001D1DF4 7F E5 FB 78 */ mr r5, r31
+/* 801D6198 001D1DF8 38 C1 00 08 */ addi r6, r1, 8
+/* 801D619C 001D1DFC 38 60 00 00 */ li r3, 0
+/* 801D61A0 001D1E00 38 80 00 24 */ li r4, 0x24
+/* 801D61A4 001D1E04 38 E0 00 01 */ li r7, 1
+/* 801D61A8 001D1E08 48 00 25 51 */ bl TRKTargetAccessDefault
+/* 801D61AC 001D1E0C 2C 03 00 00 */ cmpwi r3, 0
+/* 801D61B0 001D1E10 40 82 00 1C */ bne lbl_801D61CC
+/* 801D61B4 001D1E14 7F E5 FB 78 */ mr r5, r31
+/* 801D61B8 001D1E18 38 C1 00 08 */ addi r6, r1, 8
+/* 801D61BC 001D1E1C 38 60 00 00 */ li r3, 0
+/* 801D61C0 001D1E20 38 80 00 21 */ li r4, 0x21
+/* 801D61C4 001D1E24 38 E0 00 01 */ li r7, 1
+/* 801D61C8 001D1E28 48 00 20 25 */ bl TRKTargetAccessFP
+lbl_801D61CC:
+/* 801D61CC 001D1E2C 2C 03 00 00 */ cmpwi r3, 0
+/* 801D61D0 001D1E30 40 82 00 1C */ bne lbl_801D61EC
+/* 801D61D4 001D1E34 7F E5 FB 78 */ mr r5, r31
+/* 801D61D8 001D1E38 38 C1 00 08 */ addi r6, r1, 8
+/* 801D61DC 001D1E3C 38 60 00 00 */ li r3, 0
+/* 801D61E0 001D1E40 38 80 00 60 */ li r4, 0x60
+/* 801D61E4 001D1E44 38 E0 00 01 */ li r7, 1
+/* 801D61E8 001D1E48 48 00 1E 95 */ bl TRKTargetAccessExtended1
+lbl_801D61EC:
+/* 801D61EC 001D1E4C 2C 03 00 00 */ cmpwi r3, 0
+/* 801D61F0 001D1E50 40 82 00 1C */ bne lbl_801D620C
+/* 801D61F4 001D1E54 7F E5 FB 78 */ mr r5, r31
+/* 801D61F8 001D1E58 38 C1 00 08 */ addi r6, r1, 8
+/* 801D61FC 001D1E5C 38 60 00 00 */ li r3, 0
+/* 801D6200 001D1E60 38 80 00 1F */ li r4, 0x1f
+/* 801D6204 001D1E64 38 E0 00 01 */ li r7, 1
+/* 801D6208 001D1E68 48 00 1A 3D */ bl TRKTargetAccessExtended2
+lbl_801D620C:
+/* 801D620C 001D1E6C 2C 03 00 00 */ cmpwi r3, 0
+/* 801D6210 001D1E70 41 82 00 C8 */ beq lbl_801D62D8
+/* 801D6214 001D1E74 2C 03 07 04 */ cmpwi r3, 0x704
+/* 801D6218 001D1E78 41 82 00 48 */ beq lbl_801D6260
+/* 801D621C 001D1E7C 40 80 00 1C */ bge lbl_801D6238
+/* 801D6220 001D1E80 2C 03 07 02 */ cmpwi r3, 0x702
+/* 801D6224 001D1E84 41 82 00 34 */ beq lbl_801D6258
+/* 801D6228 001D1E88 40 80 00 20 */ bge lbl_801D6248
+/* 801D622C 001D1E8C 2C 03 07 01 */ cmpwi r3, 0x701
+/* 801D6230 001D1E90 40 80 00 20 */ bge lbl_801D6250
+/* 801D6234 001D1E94 48 00 00 44 */ b lbl_801D6278
+lbl_801D6238:
+/* 801D6238 001D1E98 2C 03 07 06 */ cmpwi r3, 0x706
+/* 801D623C 001D1E9C 41 82 00 34 */ beq lbl_801D6270
+/* 801D6240 001D1EA0 40 80 00 38 */ bge lbl_801D6278
+/* 801D6244 001D1EA4 48 00 00 24 */ b lbl_801D6268
+lbl_801D6248:
+/* 801D6248 001D1EA8 3B E0 00 12 */ li r31, 0x12
+/* 801D624C 001D1EAC 48 00 00 30 */ b lbl_801D627C
+lbl_801D6250:
+/* 801D6250 001D1EB0 3B E0 00 14 */ li r31, 0x14
+/* 801D6254 001D1EB4 48 00 00 28 */ b lbl_801D627C
+lbl_801D6258:
+/* 801D6258 001D1EB8 3B E0 00 15 */ li r31, 0x15
+/* 801D625C 001D1EBC 48 00 00 20 */ b lbl_801D627C
+lbl_801D6260:
+/* 801D6260 001D1EC0 3B E0 00 21 */ li r31, 0x21
+/* 801D6264 001D1EC4 48 00 00 18 */ b lbl_801D627C
+lbl_801D6268:
+/* 801D6268 001D1EC8 3B E0 00 22 */ li r31, 0x22
+/* 801D626C 001D1ECC 48 00 00 10 */ b lbl_801D627C
+lbl_801D6270:
+/* 801D6270 001D1ED0 3B E0 00 20 */ li r31, 0x20
+/* 801D6274 001D1ED4 48 00 00 08 */ b lbl_801D627C
+lbl_801D6278:
+/* 801D6278 001D1ED8 3B E0 00 03 */ li r31, 3
+lbl_801D627C:
+/* 801D627C 001D1EDC 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D6280 001D1EE0 38 80 00 00 */ li r4, 0
+/* 801D6284 001D1EE4 38 A0 00 40 */ li r5, 0x40
+/* 801D6288 001D1EE8 4B E2 DE AD */ bl TRK_memset
+/* 801D628C 001D1EEC 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D6290 001D1EF0 38 00 00 80 */ li r0, 0x80
+/* 801D6294 001D1EF4 39 03 07 E8 */ addi r8, r3, lbl_804907E8@l
+/* 801D6298 001D1EF8 38 A0 00 40 */ li r5, 0x40
+/* 801D629C 001D1EFC 80 E8 00 00 */ lwz r7, 0(r8)
+/* 801D62A0 001D1F00 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D62A4 001D1F04 98 01 00 10 */ stb r0, 0x10(r1)
+/* 801D62A8 001D1F08 38 80 00 40 */ li r4, 0x40
+/* 801D62AC 001D1F0C 38 C7 00 01 */ addi r6, r7, 1
+/* 801D62B0 001D1F10 90 E1 00 18 */ stw r7, 0x18(r1)
+/* 801D62B4 001D1F14 38 06 00 01 */ addi r0, r6, 1
+/* 801D62B8 001D1F18 90 C8 00 00 */ stw r6, 0(r8)
+/* 801D62BC 001D1F1C 90 A1 00 0C */ stw r5, 0xc(r1)
+/* 801D62C0 001D1F20 9B E1 00 14 */ stb r31, 0x14(r1)
+/* 801D62C4 001D1F24 90 08 00 00 */ stw r0, 0(r8)
+/* 801D62C8 001D1F28 90 C1 00 18 */ stw r6, 0x18(r1)
+/* 801D62CC 001D1F2C 48 00 33 41 */ bl func_801D960C
+/* 801D62D0 001D1F30 38 60 00 00 */ li r3, 0
+/* 801D62D4 001D1F34 48 00 00 0C */ b lbl_801D62E0
+lbl_801D62D8:
+/* 801D62D8 001D1F38 7F E3 FB 78 */ mr r3, r31
+/* 801D62DC 001D1F3C 4B FF EA 01 */ bl TRKMessageSend
+lbl_801D62E0:
+/* 801D62E0 001D1F40 80 01 00 E4 */ lwz r0, 0xe4(r1)
+/* 801D62E4 001D1F44 83 E1 00 DC */ lwz r31, 0xdc(r1)
+/* 801D62E8 001D1F48 7C 08 03 A6 */ mtlr r0
+/* 801D62EC 001D1F4C 38 21 00 E0 */ addi r1, r1, 0xe0
+/* 801D62F0 001D1F50 4E 80 00 20 */ blr
+
+.global TRKDoWriteMemory
+TRKDoWriteMemory:
+/* 801D62F4 001D1F54 54 2B 06 FE */ clrlwi r11, r1, 0x1b
+/* 801D62F8 001D1F58 7C 2C 0B 78 */ mr r12, r1
+/* 801D62FC 001D1F5C 21 6B F6 C0 */ subfic r11, r11, -2368
+/* 801D6300 001D1F60 7C 21 59 6E */ stwux r1, r1, r11
+/* 801D6304 001D1F64 7C 08 02 A6 */ mflr r0
+/* 801D6308 001D1F68 90 0C 00 04 */ stw r0, 4(r12)
+/* 801D630C 001D1F6C 93 EC FF FC */ stw r31, -4(r12)
+/* 801D6310 001D1F70 93 CC FF F8 */ stw r30, -8(r12)
+/* 801D6314 001D1F74 93 AC FF F4 */ stw r29, -0xc(r12)
+/* 801D6318 001D1F78 7C 7D 1B 78 */ mr r29, r3
+/* 801D631C 001D1F7C 8B E3 00 18 */ lbz r31, 0x18(r3)
+/* 801D6320 001D1F80 83 C3 00 20 */ lwz r30, 0x20(r3)
+/* 801D6324 001D1F84 57 E0 07 BD */ rlwinm. r0, r31, 0, 0x1e, 0x1e
+/* 801D6328 001D1F88 A0 83 00 1C */ lhz r4, 0x1c(r3)
+/* 801D632C 001D1F8C 41 82 00 64 */ beq lbl_801D6390
+/* 801D6330 001D1F90 38 61 00 64 */ addi r3, r1, 0x64
+/* 801D6334 001D1F94 38 80 00 00 */ li r4, 0
+/* 801D6338 001D1F98 38 A0 00 40 */ li r5, 0x40
+/* 801D633C 001D1F9C 4B E2 DD F9 */ bl TRK_memset
+/* 801D6340 001D1FA0 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D6344 001D1FA4 38 00 00 80 */ li r0, 0x80
+/* 801D6348 001D1FA8 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D634C 001D1FAC 38 C0 00 40 */ li r6, 0x40
+/* 801D6350 001D1FB0 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D6354 001D1FB4 38 A0 00 12 */ li r5, 0x12
+/* 801D6358 001D1FB8 98 01 00 68 */ stb r0, 0x68(r1)
+/* 801D635C 001D1FBC 38 61 00 64 */ addi r3, r1, 0x64
+/* 801D6360 001D1FC0 38 E8 00 01 */ addi r7, r8, 1
+/* 801D6364 001D1FC4 38 80 00 40 */ li r4, 0x40
+/* 801D6368 001D1FC8 91 01 00 70 */ stw r8, 0x70(r1)
+/* 801D636C 001D1FCC 38 07 00 01 */ addi r0, r7, 1
+/* 801D6370 001D1FD0 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D6374 001D1FD4 90 C1 00 64 */ stw r6, 0x64(r1)
+/* 801D6378 001D1FD8 98 A1 00 6C */ stb r5, 0x6c(r1)
+/* 801D637C 001D1FDC 90 09 00 00 */ stw r0, 0(r9)
+/* 801D6380 001D1FE0 90 E1 00 70 */ stw r7, 0x70(r1)
+/* 801D6384 001D1FE4 48 00 32 89 */ bl func_801D960C
+/* 801D6388 001D1FE8 38 60 00 00 */ li r3, 0
+/* 801D638C 001D1FEC 48 00 01 64 */ b lbl_801D64F0
+lbl_801D6390:
+/* 801D6390 001D1FF0 90 81 00 20 */ stw r4, 0x20(r1)
+/* 801D6394 001D1FF4 38 80 00 40 */ li r4, 0x40
+/* 801D6398 001D1FF8 4B FF EF 71 */ bl TRKSetBufferPosition
+/* 801D639C 001D1FFC 80 A1 00 20 */ lwz r5, 0x20(r1)
+/* 801D63A0 001D2000 7F A3 EB 78 */ mr r3, r29
+/* 801D63A4 001D2004 38 81 01 00 */ addi r4, r1, 0x100
+/* 801D63A8 001D2008 4B FF EE 31 */ bl TRKReadBuffer
+/* 801D63AC 001D200C 57 E0 EF FE */ rlwinm r0, r31, 0x1d, 0x1f, 0x1f
+/* 801D63B0 001D2010 7F C4 F3 78 */ mr r4, r30
+/* 801D63B4 001D2014 38 61 01 00 */ addi r3, r1, 0x100
+/* 801D63B8 001D2018 38 A1 00 20 */ addi r5, r1, 0x20
+/* 801D63BC 001D201C 68 06 00 01 */ xori r6, r0, 1
+/* 801D63C0 001D2020 38 E0 00 00 */ li r7, 0
+/* 801D63C4 001D2024 48 00 24 75 */ bl TRKTargetAccessMemory
+/* 801D63C8 001D2028 7C 60 1B 78 */ mr r0, r3
+/* 801D63CC 001D202C 7F A3 EB 78 */ mr r3, r29
+/* 801D63D0 001D2030 7C 1F 03 78 */ mr r31, r0
+/* 801D63D4 001D2034 38 80 00 00 */ li r4, 0
+/* 801D63D8 001D2038 4B FF EF 61 */ bl TRKResetBuffer
+/* 801D63DC 001D203C 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D63E0 001D2040 40 82 00 54 */ bne lbl_801D6434
+/* 801D63E4 001D2044 38 61 00 A4 */ addi r3, r1, 0xa4
+/* 801D63E8 001D2048 38 80 00 00 */ li r4, 0
+/* 801D63EC 001D204C 38 A0 00 40 */ li r5, 0x40
+/* 801D63F0 001D2050 4B E2 DD 45 */ bl TRK_memset
+/* 801D63F4 001D2054 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D63F8 001D2058 38 00 00 40 */ li r0, 0x40
+/* 801D63FC 001D205C 38 E3 07 E8 */ addi r7, r3, lbl_804907E8@l
+/* 801D6400 001D2060 38 A0 00 80 */ li r5, 0x80
+/* 801D6404 001D2064 80 C7 00 00 */ lwz r6, 0(r7)
+/* 801D6408 001D2068 7F A3 EB 78 */ mr r3, r29
+/* 801D640C 001D206C 90 01 00 A4 */ stw r0, 0xa4(r1)
+/* 801D6410 001D2070 38 81 00 A4 */ addi r4, r1, 0xa4
+/* 801D6414 001D2074 38 06 00 01 */ addi r0, r6, 1
+/* 801D6418 001D2078 98 A1 00 A8 */ stb r5, 0xa8(r1)
+/* 801D641C 001D207C 38 A0 00 40 */ li r5, 0x40
+/* 801D6420 001D2080 9B E1 00 AC */ stb r31, 0xac(r1)
+/* 801D6424 001D2084 90 07 00 00 */ stw r0, 0(r7)
+/* 801D6428 001D2088 90 C1 00 B0 */ stw r6, 0xb0(r1)
+/* 801D642C 001D208C 4B FF EE 39 */ bl TRKAppendBuffer
+/* 801D6430 001D2090 7C 7F 1B 78 */ mr r31, r3
+lbl_801D6434:
+/* 801D6434 001D2094 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D6438 001D2098 41 82 00 B0 */ beq lbl_801D64E8
+/* 801D643C 001D209C 38 1F F9 00 */ addi r0, r31, -1792
+/* 801D6440 001D20A0 28 00 00 06 */ cmplwi r0, 6
+/* 801D6444 001D20A4 41 81 00 44 */ bgt lbl_801D6488
+/* 801D6448 001D20A8 3C 60 80 42 */ lis r3, lbl_804231F8@ha
+/* 801D644C 001D20AC 54 00 10 3A */ slwi r0, r0, 2
+/* 801D6450 001D20B0 38 63 31 F8 */ addi r3, r3, lbl_804231F8@l
+/* 801D6454 001D20B4 7C 03 00 2E */ lwzx r0, r3, r0
+/* 801D6458 001D20B8 7C 09 03 A6 */ mtctr r0
+/* 801D645C 001D20BC 4E 80 04 20 */ bctr
+/* 801D6460 001D20C0 3B E0 00 15 */ li r31, 0x15
+/* 801D6464 001D20C4 48 00 00 28 */ b lbl_801D648C
+/* 801D6468 001D20C8 3B E0 00 13 */ li r31, 0x13
+/* 801D646C 001D20CC 48 00 00 20 */ b lbl_801D648C
+/* 801D6470 001D20D0 3B E0 00 21 */ li r31, 0x21
+/* 801D6474 001D20D4 48 00 00 18 */ b lbl_801D648C
+/* 801D6478 001D20D8 3B E0 00 22 */ li r31, 0x22
+/* 801D647C 001D20DC 48 00 00 10 */ b lbl_801D648C
+/* 801D6480 001D20E0 3B E0 00 20 */ li r31, 0x20
+/* 801D6484 001D20E4 48 00 00 08 */ b lbl_801D648C
+lbl_801D6488:
+/* 801D6488 001D20E8 3B E0 00 03 */ li r31, 3
+lbl_801D648C:
+/* 801D648C 001D20EC 38 61 00 24 */ addi r3, r1, 0x24
+/* 801D6490 001D20F0 38 80 00 00 */ li r4, 0
+/* 801D6494 001D20F4 38 A0 00 40 */ li r5, 0x40
+/* 801D6498 001D20F8 4B E2 DC 9D */ bl TRK_memset
+/* 801D649C 001D20FC 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D64A0 001D2100 38 00 00 80 */ li r0, 0x80
+/* 801D64A4 001D2104 39 03 07 E8 */ addi r8, r3, lbl_804907E8@l
+/* 801D64A8 001D2108 38 A0 00 40 */ li r5, 0x40
+/* 801D64AC 001D210C 80 E8 00 00 */ lwz r7, 0(r8)
+/* 801D64B0 001D2110 38 61 00 24 */ addi r3, r1, 0x24
+/* 801D64B4 001D2114 98 01 00 28 */ stb r0, 0x28(r1)
+/* 801D64B8 001D2118 38 80 00 40 */ li r4, 0x40
+/* 801D64BC 001D211C 38 C7 00 01 */ addi r6, r7, 1
+/* 801D64C0 001D2120 90 E1 00 30 */ stw r7, 0x30(r1)
+/* 801D64C4 001D2124 38 06 00 01 */ addi r0, r6, 1
+/* 801D64C8 001D2128 90 C8 00 00 */ stw r6, 0(r8)
+/* 801D64CC 001D212C 90 A1 00 24 */ stw r5, 0x24(r1)
+/* 801D64D0 001D2130 9B E1 00 2C */ stb r31, 0x2c(r1)
+/* 801D64D4 001D2134 90 08 00 00 */ stw r0, 0(r8)
+/* 801D64D8 001D2138 90 C1 00 30 */ stw r6, 0x30(r1)
+/* 801D64DC 001D213C 48 00 31 31 */ bl func_801D960C
+/* 801D64E0 001D2140 38 60 00 00 */ li r3, 0
+/* 801D64E4 001D2144 48 00 00 0C */ b lbl_801D64F0
+lbl_801D64E8:
+/* 801D64E8 001D2148 7F A3 EB 78 */ mr r3, r29
+/* 801D64EC 001D214C 4B FF E7 F1 */ bl TRKMessageSend
+lbl_801D64F0:
+/* 801D64F0 001D2150 81 41 00 00 */ lwz r10, 0(r1)
+/* 801D64F4 001D2154 80 0A 00 04 */ lwz r0, 4(r10)
+/* 801D64F8 001D2158 83 EA FF FC */ lwz r31, -4(r10)
+/* 801D64FC 001D215C 83 CA FF F8 */ lwz r30, -8(r10)
+/* 801D6500 001D2160 83 AA FF F4 */ lwz r29, -0xc(r10)
+/* 801D6504 001D2164 7C 08 03 A6 */ mtlr r0
+/* 801D6508 001D2168 7D 41 53 78 */ mr r1, r10
+/* 801D650C 001D216C 4E 80 00 20 */ blr
+
+.global TRKDoReadMemory
+TRKDoReadMemory:
+/* 801D6510 001D2170 54 2B 06 FE */ clrlwi r11, r1, 0x1b
+/* 801D6514 001D2174 7C 2C 0B 78 */ mr r12, r1
+/* 801D6518 001D2178 21 6B F6 C0 */ subfic r11, r11, -2368
+/* 801D651C 001D217C 7C 21 59 6E */ stwux r1, r1, r11
+/* 801D6520 001D2180 7C 08 02 A6 */ mflr r0
+/* 801D6524 001D2184 90 0C 00 04 */ stw r0, 4(r12)
+/* 801D6528 001D2188 93 EC FF FC */ stw r31, -4(r12)
+/* 801D652C 001D218C 7C 7F 1B 78 */ mr r31, r3
+/* 801D6530 001D2190 93 CC FF F8 */ stw r30, -8(r12)
+/* 801D6534 001D2194 93 AC FF F4 */ stw r29, -0xc(r12)
+/* 801D6538 001D2198 93 8C FF F0 */ stw r28, -0x10(r12)
+/* 801D653C 001D219C 8B C3 00 18 */ lbz r30, 0x18(r3)
+/* 801D6540 001D21A0 83 83 00 20 */ lwz r28, 0x20(r3)
+/* 801D6544 001D21A4 57 C0 07 BD */ rlwinm. r0, r30, 0, 0x1e, 0x1e
+/* 801D6548 001D21A8 A0 63 00 1C */ lhz r3, 0x1c(r3)
+/* 801D654C 001D21AC 41 82 00 64 */ beq lbl_801D65B0
+/* 801D6550 001D21B0 38 61 00 64 */ addi r3, r1, 0x64
+/* 801D6554 001D21B4 38 80 00 00 */ li r4, 0
+/* 801D6558 001D21B8 38 A0 00 40 */ li r5, 0x40
+/* 801D655C 001D21BC 4B E2 DB D9 */ bl TRK_memset
+/* 801D6560 001D21C0 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D6564 001D21C4 38 00 00 80 */ li r0, 0x80
+/* 801D6568 001D21C8 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D656C 001D21CC 38 C0 00 40 */ li r6, 0x40
+/* 801D6570 001D21D0 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D6574 001D21D4 38 A0 00 12 */ li r5, 0x12
+/* 801D6578 001D21D8 98 01 00 68 */ stb r0, 0x68(r1)
+/* 801D657C 001D21DC 38 61 00 64 */ addi r3, r1, 0x64
+/* 801D6580 001D21E0 38 E8 00 01 */ addi r7, r8, 1
+/* 801D6584 001D21E4 38 80 00 40 */ li r4, 0x40
+/* 801D6588 001D21E8 91 01 00 70 */ stw r8, 0x70(r1)
+/* 801D658C 001D21EC 38 07 00 01 */ addi r0, r7, 1
+/* 801D6590 001D21F0 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D6594 001D21F4 90 C1 00 64 */ stw r6, 0x64(r1)
+/* 801D6598 001D21F8 98 A1 00 6C */ stb r5, 0x6c(r1)
+/* 801D659C 001D21FC 90 09 00 00 */ stw r0, 0(r9)
+/* 801D65A0 001D2200 90 E1 00 70 */ stw r7, 0x70(r1)
+/* 801D65A4 001D2204 48 00 30 69 */ bl func_801D960C
+/* 801D65A8 001D2208 38 60 00 00 */ li r3, 0
+/* 801D65AC 001D220C 48 00 01 88 */ b lbl_801D6734
+lbl_801D65B0:
+/* 801D65B0 001D2210 57 C0 EF FE */ rlwinm r0, r30, 0x1d, 0x1f, 0x1f
+/* 801D65B4 001D2214 90 61 00 20 */ stw r3, 0x20(r1)
+/* 801D65B8 001D2218 7F 84 E3 78 */ mr r4, r28
+/* 801D65BC 001D221C 38 61 01 00 */ addi r3, r1, 0x100
+/* 801D65C0 001D2220 38 A1 00 20 */ addi r5, r1, 0x20
+/* 801D65C4 001D2224 68 06 00 01 */ xori r6, r0, 1
+/* 801D65C8 001D2228 38 E0 00 01 */ li r7, 1
+/* 801D65CC 001D222C 48 00 22 6D */ bl TRKTargetAccessMemory
+/* 801D65D0 001D2230 7C 60 1B 78 */ mr r0, r3
+/* 801D65D4 001D2234 7F E3 FB 78 */ mr r3, r31
+/* 801D65D8 001D2238 7C 1D 03 78 */ mr r29, r0
+/* 801D65DC 001D223C 38 80 00 00 */ li r4, 0
+/* 801D65E0 001D2240 4B FF ED 59 */ bl TRKResetBuffer
+/* 801D65E4 001D2244 2C 1D 00 00 */ cmpwi r29, 0
+/* 801D65E8 001D2248 40 82 00 90 */ bne lbl_801D6678
+/* 801D65EC 001D224C 38 61 00 A4 */ addi r3, r1, 0xa4
+/* 801D65F0 001D2250 38 80 00 00 */ li r4, 0
+/* 801D65F4 001D2254 38 A0 00 40 */ li r5, 0x40
+/* 801D65F8 001D2258 4B E2 DB 3D */ bl TRK_memset
+/* 801D65FC 001D225C 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D6600 001D2260 80 81 00 20 */ lwz r4, 0x20(r1)
+/* 801D6604 001D2264 38 E3 07 E8 */ addi r7, r3, lbl_804907E8@l
+/* 801D6608 001D2268 39 00 00 80 */ li r8, 0x80
+/* 801D660C 001D226C 80 C7 00 00 */ lwz r6, 0(r7)
+/* 801D6610 001D2270 38 04 00 40 */ addi r0, r4, 0x40
+/* 801D6614 001D2274 90 01 00 A4 */ stw r0, 0xa4(r1)
+/* 801D6618 001D2278 7F E3 FB 78 */ mr r3, r31
+/* 801D661C 001D227C 38 06 00 01 */ addi r0, r6, 1
+/* 801D6620 001D2280 38 81 00 A4 */ addi r4, r1, 0xa4
+/* 801D6624 001D2284 9B A1 00 AC */ stb r29, 0xac(r1)
+/* 801D6628 001D2288 38 A0 00 40 */ li r5, 0x40
+/* 801D662C 001D228C 99 01 00 A8 */ stb r8, 0xa8(r1)
+/* 801D6630 001D2290 90 07 00 00 */ stw r0, 0(r7)
+/* 801D6634 001D2294 90 C1 00 B0 */ stw r6, 0xb0(r1)
+/* 801D6638 001D2298 4B FF EC 2D */ bl TRKAppendBuffer
+/* 801D663C 001D229C 57 C0 06 73 */ rlwinm. r0, r30, 0, 0x19, 0x19
+/* 801D6640 001D22A0 41 82 00 24 */ beq lbl_801D6664
+/* 801D6644 001D22A4 57 80 06 FE */ clrlwi r0, r28, 0x1b
+/* 801D6648 001D22A8 38 81 01 00 */ addi r4, r1, 0x100
+/* 801D664C 001D22AC 80 A1 00 20 */ lwz r5, 0x20(r1)
+/* 801D6650 001D22B0 7F E3 FB 78 */ mr r3, r31
+/* 801D6654 001D22B4 7C 84 02 14 */ add r4, r4, r0
+/* 801D6658 001D22B8 4B FF EC 0D */ bl TRKAppendBuffer
+/* 801D665C 001D22BC 7C 7D 1B 78 */ mr r29, r3
+/* 801D6660 001D22C0 48 00 00 18 */ b lbl_801D6678
+lbl_801D6664:
+/* 801D6664 001D22C4 80 A1 00 20 */ lwz r5, 0x20(r1)
+/* 801D6668 001D22C8 7F E3 FB 78 */ mr r3, r31
+/* 801D666C 001D22CC 38 81 01 00 */ addi r4, r1, 0x100
+/* 801D6670 001D22D0 4B FF EB F5 */ bl TRKAppendBuffer
+/* 801D6674 001D22D4 7C 7D 1B 78 */ mr r29, r3
+lbl_801D6678:
+/* 801D6678 001D22D8 2C 1D 00 00 */ cmpwi r29, 0
+/* 801D667C 001D22DC 41 82 00 B0 */ beq lbl_801D672C
+/* 801D6680 001D22E0 38 1D F9 00 */ addi r0, r29, -1792
+/* 801D6684 001D22E4 28 00 00 06 */ cmplwi r0, 6
+/* 801D6688 001D22E8 41 81 00 44 */ bgt lbl_801D66CC
+/* 801D668C 001D22EC 3C 60 80 42 */ lis r3, lbl_80423214@ha
+/* 801D6690 001D22F0 54 00 10 3A */ slwi r0, r0, 2
+/* 801D6694 001D22F4 38 63 32 14 */ addi r3, r3, lbl_80423214@l
+/* 801D6698 001D22F8 7C 03 00 2E */ lwzx r0, r3, r0
+/* 801D669C 001D22FC 7C 09 03 A6 */ mtctr r0
+/* 801D66A0 001D2300 4E 80 04 20 */ bctr
+/* 801D66A4 001D2304 3B A0 00 15 */ li r29, 0x15
+/* 801D66A8 001D2308 48 00 00 28 */ b lbl_801D66D0
+/* 801D66AC 001D230C 3B A0 00 13 */ li r29, 0x13
+/* 801D66B0 001D2310 48 00 00 20 */ b lbl_801D66D0
+/* 801D66B4 001D2314 3B A0 00 21 */ li r29, 0x21
+/* 801D66B8 001D2318 48 00 00 18 */ b lbl_801D66D0
+/* 801D66BC 001D231C 3B A0 00 22 */ li r29, 0x22
+/* 801D66C0 001D2320 48 00 00 10 */ b lbl_801D66D0
+/* 801D66C4 001D2324 3B A0 00 20 */ li r29, 0x20
+/* 801D66C8 001D2328 48 00 00 08 */ b lbl_801D66D0
+lbl_801D66CC:
+/* 801D66CC 001D232C 3B A0 00 03 */ li r29, 3
+lbl_801D66D0:
+/* 801D66D0 001D2330 38 61 00 24 */ addi r3, r1, 0x24
+/* 801D66D4 001D2334 38 80 00 00 */ li r4, 0
+/* 801D66D8 001D2338 38 A0 00 40 */ li r5, 0x40
+/* 801D66DC 001D233C 4B E2 DA 59 */ bl TRK_memset
+/* 801D66E0 001D2340 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D66E4 001D2344 38 00 00 80 */ li r0, 0x80
+/* 801D66E8 001D2348 39 03 07 E8 */ addi r8, r3, lbl_804907E8@l
+/* 801D66EC 001D234C 38 A0 00 40 */ li r5, 0x40
+/* 801D66F0 001D2350 80 E8 00 00 */ lwz r7, 0(r8)
+/* 801D66F4 001D2354 38 61 00 24 */ addi r3, r1, 0x24
+/* 801D66F8 001D2358 98 01 00 28 */ stb r0, 0x28(r1)
+/* 801D66FC 001D235C 38 80 00 40 */ li r4, 0x40
+/* 801D6700 001D2360 38 C7 00 01 */ addi r6, r7, 1
+/* 801D6704 001D2364 90 E1 00 30 */ stw r7, 0x30(r1)
+/* 801D6708 001D2368 38 06 00 01 */ addi r0, r6, 1
+/* 801D670C 001D236C 90 C8 00 00 */ stw r6, 0(r8)
+/* 801D6710 001D2370 90 A1 00 24 */ stw r5, 0x24(r1)
+/* 801D6714 001D2374 9B A1 00 2C */ stb r29, 0x2c(r1)
+/* 801D6718 001D2378 90 08 00 00 */ stw r0, 0(r8)
+/* 801D671C 001D237C 90 C1 00 30 */ stw r6, 0x30(r1)
+/* 801D6720 001D2380 48 00 2E ED */ bl func_801D960C
+/* 801D6724 001D2384 38 60 00 00 */ li r3, 0
+/* 801D6728 001D2388 48 00 00 0C */ b lbl_801D6734
+lbl_801D672C:
+/* 801D672C 001D238C 7F E3 FB 78 */ mr r3, r31
+/* 801D6730 001D2390 4B FF E5 AD */ bl TRKMessageSend
+lbl_801D6734:
+/* 801D6734 001D2394 81 41 00 00 */ lwz r10, 0(r1)
+/* 801D6738 001D2398 80 0A 00 04 */ lwz r0, 4(r10)
+/* 801D673C 001D239C 83 EA FF FC */ lwz r31, -4(r10)
+/* 801D6740 001D23A0 83 CA FF F8 */ lwz r30, -8(r10)
+/* 801D6744 001D23A4 83 AA FF F4 */ lwz r29, -0xc(r10)
+/* 801D6748 001D23A8 83 8A FF F0 */ lwz r28, -0x10(r10)
+/* 801D674C 001D23AC 7C 08 03 A6 */ mtlr r0
+/* 801D6750 001D23B0 7D 41 53 78 */ mr r1, r10
+/* 801D6754 001D23B4 4E 80 00 20 */ blr
+
+.global TRKDoSupportMask
+TRKDoSupportMask:
+/* 801D6758 001D23B8 38 60 00 00 */ li r3, 0
+/* 801D675C 001D23BC 4E 80 00 20 */ blr
+
+.global TRKDoVersions
+TRKDoVersions:
+/* 801D6760 001D23C0 38 60 00 00 */ li r3, 0
+/* 801D6764 001D23C4 4E 80 00 20 */ blr
+
+.global TRKDoOverride
+TRKDoOverride:
+/* 801D6768 001D23C8 94 21 FF B0 */ stwu r1, -0x50(r1)
+/* 801D676C 001D23CC 7C 08 02 A6 */ mflr r0
+/* 801D6770 001D23D0 38 80 00 00 */ li r4, 0
+/* 801D6774 001D23D4 38 A0 00 40 */ li r5, 0x40
+/* 801D6778 001D23D8 90 01 00 54 */ stw r0, 0x54(r1)
+/* 801D677C 001D23DC 38 61 00 08 */ addi r3, r1, 8
+/* 801D6780 001D23E0 4B E2 D9 B5 */ bl TRK_memset
+/* 801D6784 001D23E4 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D6788 001D23E8 38 00 00 80 */ li r0, 0x80
+/* 801D678C 001D23EC 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D6790 001D23F0 38 C0 00 40 */ li r6, 0x40
+/* 801D6794 001D23F4 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D6798 001D23F8 38 A0 00 00 */ li r5, 0
+/* 801D679C 001D23FC 98 01 00 0C */ stb r0, 0xc(r1)
+/* 801D67A0 001D2400 38 61 00 08 */ addi r3, r1, 8
+/* 801D67A4 001D2404 38 E8 00 01 */ addi r7, r8, 1
+/* 801D67A8 001D2408 38 80 00 40 */ li r4, 0x40
+/* 801D67AC 001D240C 91 01 00 14 */ stw r8, 0x14(r1)
+/* 801D67B0 001D2410 38 07 00 01 */ addi r0, r7, 1
+/* 801D67B4 001D2414 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D67B8 001D2418 90 C1 00 08 */ stw r6, 8(r1)
+/* 801D67BC 001D241C 98 A1 00 10 */ stb r5, 0x10(r1)
+/* 801D67C0 001D2420 90 09 00 00 */ stw r0, 0(r9)
+/* 801D67C4 001D2424 90 E1 00 14 */ stw r7, 0x14(r1)
+/* 801D67C8 001D2428 48 00 2E 45 */ bl func_801D960C
+/* 801D67CC 001D242C 48 00 2A E5 */ bl __TRK_copy_vectors
+/* 801D67D0 001D2430 80 01 00 54 */ lwz r0, 0x54(r1)
+/* 801D67D4 001D2434 38 60 00 00 */ li r3, 0
+/* 801D67D8 001D2438 7C 08 03 A6 */ mtlr r0
+/* 801D67DC 001D243C 38 21 00 50 */ addi r1, r1, 0x50
+/* 801D67E0 001D2440 4E 80 00 20 */ blr
+
+.global TRKDoReset
+TRKDoReset:
+/* 801D67E4 001D2444 94 21 FF B0 */ stwu r1, -0x50(r1)
+/* 801D67E8 001D2448 7C 08 02 A6 */ mflr r0
+/* 801D67EC 001D244C 38 80 00 00 */ li r4, 0
+/* 801D67F0 001D2450 38 A0 00 40 */ li r5, 0x40
+/* 801D67F4 001D2454 90 01 00 54 */ stw r0, 0x54(r1)
+/* 801D67F8 001D2458 38 61 00 08 */ addi r3, r1, 8
+/* 801D67FC 001D245C 4B E2 D9 39 */ bl TRK_memset
+/* 801D6800 001D2460 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D6804 001D2464 38 00 00 80 */ li r0, 0x80
+/* 801D6808 001D2468 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D680C 001D246C 38 C0 00 40 */ li r6, 0x40
+/* 801D6810 001D2470 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D6814 001D2474 38 A0 00 00 */ li r5, 0
+/* 801D6818 001D2478 98 01 00 0C */ stb r0, 0xc(r1)
+/* 801D681C 001D247C 38 61 00 08 */ addi r3, r1, 8
+/* 801D6820 001D2480 38 E8 00 01 */ addi r7, r8, 1
+/* 801D6824 001D2484 38 80 00 40 */ li r4, 0x40
+/* 801D6828 001D2488 91 01 00 14 */ stw r8, 0x14(r1)
+/* 801D682C 001D248C 38 07 00 01 */ addi r0, r7, 1
+/* 801D6830 001D2490 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D6834 001D2494 90 C1 00 08 */ stw r6, 8(r1)
+/* 801D6838 001D2498 98 A1 00 10 */ stb r5, 0x10(r1)
+/* 801D683C 001D249C 90 09 00 00 */ stw r0, 0(r9)
+/* 801D6840 001D24A0 90 E1 00 14 */ stw r7, 0x14(r1)
+/* 801D6844 001D24A4 48 00 2D C9 */ bl func_801D960C
+/* 801D6848 001D24A8 4B E2 F8 75 */ bl __TRK_reset
+/* 801D684C 001D24AC 80 01 00 54 */ lwz r0, 0x54(r1)
+/* 801D6850 001D24B0 38 60 00 00 */ li r3, 0
+/* 801D6854 001D24B4 7C 08 03 A6 */ mtlr r0
+/* 801D6858 001D24B8 38 21 00 50 */ addi r1, r1, 0x50
+/* 801D685C 001D24BC 4E 80 00 20 */ blr
+
+.global TRKDoDisconnect
+TRKDoDisconnect:
+/* 801D6860 001D24C0 94 21 FF A0 */ stwu r1, -0x60(r1)
+/* 801D6864 001D24C4 7C 08 02 A6 */ mflr r0
+/* 801D6868 001D24C8 3C 60 80 49 */ lis r3, lbl_804907EC@ha
+/* 801D686C 001D24CC 38 A0 00 40 */ li r5, 0x40
+/* 801D6870 001D24D0 90 01 00 64 */ stw r0, 0x64(r1)
+/* 801D6874 001D24D4 38 83 07 EC */ addi r4, r3, lbl_804907EC@l
+/* 801D6878 001D24D8 38 00 00 00 */ li r0, 0
+/* 801D687C 001D24DC 38 61 00 14 */ addi r3, r1, 0x14
+/* 801D6880 001D24E0 90 04 00 00 */ stw r0, 0(r4)
+/* 801D6884 001D24E4 38 80 00 00 */ li r4, 0
+/* 801D6888 001D24E8 4B E2 D8 AD */ bl TRK_memset
+/* 801D688C 001D24EC 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D6890 001D24F0 38 00 00 80 */ li r0, 0x80
+/* 801D6894 001D24F4 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D6898 001D24F8 38 C0 00 40 */ li r6, 0x40
+/* 801D689C 001D24FC 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D68A0 001D2500 38 A0 00 00 */ li r5, 0
+/* 801D68A4 001D2504 98 01 00 18 */ stb r0, 0x18(r1)
+/* 801D68A8 001D2508 38 61 00 14 */ addi r3, r1, 0x14
+/* 801D68AC 001D250C 38 E8 00 01 */ addi r7, r8, 1
+/* 801D68B0 001D2510 38 80 00 40 */ li r4, 0x40
+/* 801D68B4 001D2514 91 01 00 20 */ stw r8, 0x20(r1)
+/* 801D68B8 001D2518 38 07 00 01 */ addi r0, r7, 1
+/* 801D68BC 001D251C 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D68C0 001D2520 90 C1 00 14 */ stw r6, 0x14(r1)
+/* 801D68C4 001D2524 98 A1 00 1C */ stb r5, 0x1c(r1)
+/* 801D68C8 001D2528 90 09 00 00 */ stw r0, 0(r9)
+/* 801D68CC 001D252C 90 E1 00 20 */ stw r7, 0x20(r1)
+/* 801D68D0 001D2530 48 00 2D 3D */ bl func_801D960C
+/* 801D68D4 001D2534 38 61 00 08 */ addi r3, r1, 8
+/* 801D68D8 001D2538 38 80 00 01 */ li r4, 1
+/* 801D68DC 001D253C 4B FF E0 79 */ bl TRKConstructEvent
+/* 801D68E0 001D2540 38 61 00 08 */ addi r3, r1, 8
+/* 801D68E4 001D2544 4B FF E0 89 */ bl TRKPostEvent
+/* 801D68E8 001D2548 80 01 00 64 */ lwz r0, 0x64(r1)
+/* 801D68EC 001D254C 38 60 00 00 */ li r3, 0
+/* 801D68F0 001D2550 7C 08 03 A6 */ mtlr r0
+/* 801D68F4 001D2554 38 21 00 60 */ addi r1, r1, 0x60
+/* 801D68F8 001D2558 4E 80 00 20 */ blr
+
+.global TRKDoConnect
+TRKDoConnect:
+/* 801D68FC 001D255C 94 21 FF B0 */ stwu r1, -0x50(r1)
+/* 801D6900 001D2560 7C 08 02 A6 */ mflr r0
+/* 801D6904 001D2564 3C 60 80 49 */ lis r3, lbl_804907EC@ha
+/* 801D6908 001D2568 38 A0 00 40 */ li r5, 0x40
+/* 801D690C 001D256C 90 01 00 54 */ stw r0, 0x54(r1)
+/* 801D6910 001D2570 38 83 07 EC */ addi r4, r3, lbl_804907EC@l
+/* 801D6914 001D2574 38 00 00 01 */ li r0, 1
+/* 801D6918 001D2578 38 61 00 08 */ addi r3, r1, 8
+/* 801D691C 001D257C 90 04 00 00 */ stw r0, 0(r4)
+/* 801D6920 001D2580 38 80 00 00 */ li r4, 0
+/* 801D6924 001D2584 4B E2 D8 11 */ bl TRK_memset
+/* 801D6928 001D2588 3C 60 80 49 */ lis r3, lbl_804907E8@ha
+/* 801D692C 001D258C 38 00 00 80 */ li r0, 0x80
+/* 801D6930 001D2590 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l
+/* 801D6934 001D2594 38 C0 00 40 */ li r6, 0x40
+/* 801D6938 001D2598 81 09 00 00 */ lwz r8, 0(r9)
+/* 801D693C 001D259C 38 A0 00 00 */ li r5, 0
+/* 801D6940 001D25A0 98 01 00 0C */ stb r0, 0xc(r1)
+/* 801D6944 001D25A4 38 61 00 08 */ addi r3, r1, 8
+/* 801D6948 001D25A8 38 E8 00 01 */ addi r7, r8, 1
+/* 801D694C 001D25AC 38 80 00 40 */ li r4, 0x40
+/* 801D6950 001D25B0 91 01 00 14 */ stw r8, 0x14(r1)
+/* 801D6954 001D25B4 38 07 00 01 */ addi r0, r7, 1
+/* 801D6958 001D25B8 90 E9 00 00 */ stw r7, 0(r9)
+/* 801D695C 001D25BC 90 C1 00 08 */ stw r6, 8(r1)
+/* 801D6960 001D25C0 98 A1 00 10 */ stb r5, 0x10(r1)
+/* 801D6964 001D25C4 90 09 00 00 */ stw r0, 0(r9)
+/* 801D6968 001D25C8 90 E1 00 14 */ stw r7, 0x14(r1)
+/* 801D696C 001D25CC 48 00 2C A1 */ bl func_801D960C
+/* 801D6970 001D25D0 80 01 00 54 */ lwz r0, 0x54(r1)
+/* 801D6974 001D25D4 38 60 00 00 */ li r3, 0
+/* 801D6978 001D25D8 7C 08 03 A6 */ mtlr r0
+/* 801D697C 001D25DC 38 21 00 50 */ addi r1, r1, 0x50
+/* 801D6980 001D25E0 4E 80 00 20 */ blr
+
+.global SetTRKConnected
+SetTRKConnected:
+/* 801D6984 001D25E4 3C 80 80 49 */ lis r4, lbl_804907EC@ha
+/* 801D6988 001D25E8 90 64 07 EC */ stw r3, lbl_804907EC@l(r4)
+/* 801D698C 001D25EC 4E 80 00 20 */ blr
+
+.global GetTRKConnected
+GetTRKConnected:
+/* 801D6990 001D25F0 3C 60 80 49 */ lis r3, lbl_804907EC@ha
+/* 801D6994 001D25F4 38 63 07 EC */ addi r3, r3, lbl_804907EC@l
+/* 801D6998 001D25F8 80 63 00 00 */ lwz r3, 0(r3)
+/* 801D699C 001D25FC 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/mutex_TRK.s b/asm/MetroTRK/mutex_TRK.s new file mode 100644 index 0000000..47edac7 --- /dev/null +++ b/asm/MetroTRK/mutex_TRK.s @@ -0,0 +1,18 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKReleaseMutex
+TRKReleaseMutex:
+/* 801D7054 001D2CB4 38 60 00 00 */ li r3, 0
+/* 801D7058 001D2CB8 4E 80 00 20 */ blr
+
+.global TRKAcquireMutex
+TRKAcquireMutex:
+/* 801D705C 001D2CBC 38 60 00 00 */ li r3, 0
+/* 801D7060 001D2CC0 4E 80 00 20 */ blr
+
+.global TRKInitializeMutex
+TRKInitializeMutex:
+/* 801D7064 001D2CC4 38 60 00 00 */ li r3, 0
+/* 801D7068 001D2CC8 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/notify.s b/asm/MetroTRK/notify.s new file mode 100644 index 0000000..944d25a --- /dev/null +++ b/asm/MetroTRK/notify.s @@ -0,0 +1,48 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKDoNotifyStopped
+TRKDoNotifyStopped:
+/* 801D706C 001D2CCC 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D7070 001D2CD0 7C 08 02 A6 */ mflr r0
+/* 801D7074 001D2CD4 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D7078 001D2CD8 38 81 00 08 */ addi r4, r1, 8
+/* 801D707C 001D2CDC 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D7080 001D2CE0 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D7084 001D2CE4 7C 7E 1B 78 */ mr r30, r3
+/* 801D7088 001D2CE8 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D708C 001D2CEC 4B FF E3 7D */ bl TRKGetFreeBuffer
+/* 801D7090 001D2CF0 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D7094 001D2CF4 40 82 00 54 */ bne lbl_801D70E8
+/* 801D7098 001D2CF8 40 82 00 20 */ bne lbl_801D70B8
+/* 801D709C 001D2CFC 2C 1E 00 90 */ cmpwi r30, 0x90
+/* 801D70A0 001D2D00 40 82 00 10 */ bne lbl_801D70B0
+/* 801D70A4 001D2D04 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D70A8 001D2D08 48 00 09 09 */ bl TRKTargetAddStopInfo
+/* 801D70AC 001D2D0C 48 00 00 0C */ b lbl_801D70B8
+lbl_801D70B0:
+/* 801D70B0 001D2D10 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D70B4 001D2D14 48 00 08 79 */ bl TRKTargetAddExceptionInfo
+lbl_801D70B8:
+/* 801D70B8 001D2D18 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D70BC 001D2D1C 38 81 00 10 */ addi r4, r1, 0x10
+/* 801D70C0 001D2D20 38 A0 00 02 */ li r5, 2
+/* 801D70C4 001D2D24 38 C0 00 03 */ li r6, 3
+/* 801D70C8 001D2D28 38 E0 00 01 */ li r7, 1
+/* 801D70CC 001D2D2C 4B FF FB E9 */ bl TRKRequestSend
+/* 801D70D0 001D2D30 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D70D4 001D2D34 40 82 00 0C */ bne lbl_801D70E0
+/* 801D70D8 001D2D38 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D70DC 001D2D3C 4B FF E2 9D */ bl TRKReleaseBuffer
+lbl_801D70E0:
+/* 801D70E0 001D2D40 80 61 00 0C */ lwz r3, 0xc(r1)
+/* 801D70E4 001D2D44 4B FF E2 95 */ bl TRKReleaseBuffer
+lbl_801D70E8:
+/* 801D70E8 001D2D48 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D70EC 001D2D4C 7F E3 FB 78 */ mr r3, r31
+/* 801D70F0 001D2D50 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D70F4 001D2D54 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D70F8 001D2D58 7C 08 03 A6 */ mtlr r0
+/* 801D70FC 001D2D5C 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D7100 001D2D60 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/nubevent.s b/asm/MetroTRK/nubevent.s new file mode 100644 index 0000000..b0fb0b0 --- /dev/null +++ b/asm/MetroTRK/nubevent.s @@ -0,0 +1,161 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKDestructEvent
+TRKDestructEvent:
+/* 801D4930 001D0590 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 801D4934 001D0594 7C 08 02 A6 */ mflr r0
+/* 801D4938 001D0598 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D493C 001D059C 80 63 00 08 */ lwz r3, 8(r3)
+/* 801D4940 001D05A0 48 00 0A 39 */ bl TRKReleaseBuffer
+/* 801D4944 001D05A4 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D4948 001D05A8 7C 08 03 A6 */ mtlr r0
+/* 801D494C 001D05AC 38 21 00 10 */ addi r1, r1, 0x10
+/* 801D4950 001D05B0 4E 80 00 20 */ blr
+
+.global TRKConstructEvent
+TRKConstructEvent:
+/* 801D4954 001D05B4 90 83 00 00 */ stw r4, 0(r3)
+/* 801D4958 001D05B8 38 80 00 00 */ li r4, 0
+/* 801D495C 001D05BC 38 00 FF FF */ li r0, -1
+/* 801D4960 001D05C0 90 83 00 04 */ stw r4, 4(r3)
+/* 801D4964 001D05C4 90 03 00 08 */ stw r0, 8(r3)
+/* 801D4968 001D05C8 4E 80 00 20 */ blr
+
+.global TRKPostEvent
+TRKPostEvent:
+/* 801D496C 001D05CC 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D4970 001D05D0 7C 08 02 A6 */ mflr r0
+/* 801D4974 001D05D4 3C 80 80 49 */ lis r4, lbl_8048EDF0@ha
+/* 801D4978 001D05D8 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D497C 001D05DC 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D4980 001D05E0 3B E0 00 00 */ li r31, 0
+/* 801D4984 001D05E4 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D4988 001D05E8 93 A1 00 14 */ stw r29, 0x14(r1)
+/* 801D498C 001D05EC 7C 7D 1B 78 */ mr r29, r3
+/* 801D4990 001D05F0 38 64 ED F0 */ addi r3, r4, lbl_8048EDF0@l
+/* 801D4994 001D05F4 48 00 26 C9 */ bl TRKAcquireMutex
+/* 801D4998 001D05F8 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
+/* 801D499C 001D05FC 3B C3 ED F0 */ addi r30, r3, lbl_8048EDF0@l
+/* 801D49A0 001D0600 80 7E 00 04 */ lwz r3, 4(r30)
+/* 801D49A4 001D0604 2C 03 00 02 */ cmpwi r3, 2
+/* 801D49A8 001D0608 40 82 00 0C */ bne lbl_801D49B4
+/* 801D49AC 001D060C 3B E0 01 00 */ li r31, 0x100
+/* 801D49B0 001D0610 48 00 00 70 */ b lbl_801D4A20
+lbl_801D49B4:
+/* 801D49B4 001D0614 80 1E 00 08 */ lwz r0, 8(r30)
+/* 801D49B8 001D0618 7F A4 EB 78 */ mr r4, r29
+/* 801D49BC 001D061C 38 A0 00 0C */ li r5, 0xc
+/* 801D49C0 001D0620 7C 00 1A 14 */ add r0, r0, r3
+/* 801D49C4 001D0624 54 03 0F FE */ srwi r3, r0, 0x1f
+/* 801D49C8 001D0628 54 00 07 FE */ clrlwi r0, r0, 0x1f
+/* 801D49CC 001D062C 7C 00 1A 78 */ xor r0, r0, r3
+/* 801D49D0 001D0630 7C 03 00 50 */ subf r0, r3, r0
+/* 801D49D4 001D0634 1F A0 00 0C */ mulli r29, r0, 0xc
+/* 801D49D8 001D0638 7C 7E EA 14 */ add r3, r30, r29
+/* 801D49DC 001D063C 38 63 00 0C */ addi r3, r3, 0xc
+/* 801D49E0 001D0640 4B E2 F7 85 */ bl TRK_memcpy
+/* 801D49E4 001D0644 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
+/* 801D49E8 001D0648 38 83 ED F0 */ addi r4, r3, lbl_8048EDF0@l
+/* 801D49EC 001D064C 80 04 00 24 */ lwz r0, 0x24(r4)
+/* 801D49F0 001D0650 7C 64 EA 14 */ add r3, r4, r29
+/* 801D49F4 001D0654 90 03 00 10 */ stw r0, 0x10(r3)
+/* 801D49F8 001D0658 80 64 00 24 */ lwz r3, 0x24(r4)
+/* 801D49FC 001D065C 38 03 00 01 */ addi r0, r3, 1
+/* 801D4A00 001D0660 28 00 01 00 */ cmplwi r0, 0x100
+/* 801D4A04 001D0664 90 04 00 24 */ stw r0, 0x24(r4)
+/* 801D4A08 001D0668 40 80 00 0C */ bge lbl_801D4A14
+/* 801D4A0C 001D066C 38 00 01 00 */ li r0, 0x100
+/* 801D4A10 001D0670 90 04 00 24 */ stw r0, 0x24(r4)
+lbl_801D4A14:
+/* 801D4A14 001D0674 80 7E 00 04 */ lwz r3, 4(r30)
+/* 801D4A18 001D0678 38 03 00 01 */ addi r0, r3, 1
+/* 801D4A1C 001D067C 90 1E 00 04 */ stw r0, 4(r30)
+lbl_801D4A20:
+/* 801D4A20 001D0680 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
+/* 801D4A24 001D0684 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
+/* 801D4A28 001D0688 48 00 26 2D */ bl TRKReleaseMutex
+/* 801D4A2C 001D068C 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D4A30 001D0690 7F E3 FB 78 */ mr r3, r31
+/* 801D4A34 001D0694 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D4A38 001D0698 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D4A3C 001D069C 83 A1 00 14 */ lwz r29, 0x14(r1)
+/* 801D4A40 001D06A0 7C 08 03 A6 */ mtlr r0
+/* 801D4A44 001D06A4 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D4A48 001D06A8 4E 80 00 20 */ blr
+
+.global TRKGetNextEvent
+TRKGetNextEvent:
+/* 801D4A4C 001D06AC 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D4A50 001D06B0 7C 08 02 A6 */ mflr r0
+/* 801D4A54 001D06B4 3C 80 80 49 */ lis r4, lbl_8048EDF0@ha
+/* 801D4A58 001D06B8 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D4A5C 001D06BC 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D4A60 001D06C0 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D4A64 001D06C4 3B C0 00 00 */ li r30, 0
+/* 801D4A68 001D06C8 93 A1 00 14 */ stw r29, 0x14(r1)
+/* 801D4A6C 001D06CC 7C 7D 1B 78 */ mr r29, r3
+/* 801D4A70 001D06D0 38 64 ED F0 */ addi r3, r4, lbl_8048EDF0@l
+/* 801D4A74 001D06D4 48 00 25 E9 */ bl TRKAcquireMutex
+/* 801D4A78 001D06D8 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
+/* 801D4A7C 001D06DC 3B E3 ED F0 */ addi r31, r3, lbl_8048EDF0@l
+/* 801D4A80 001D06E0 80 1F 00 04 */ lwz r0, 4(r31)
+/* 801D4A84 001D06E4 2C 00 00 00 */ cmpwi r0, 0
+/* 801D4A88 001D06E8 40 81 00 4C */ ble lbl_801D4AD4
+/* 801D4A8C 001D06EC 80 1F 00 08 */ lwz r0, 8(r31)
+/* 801D4A90 001D06F0 7F A3 EB 78 */ mr r3, r29
+/* 801D4A94 001D06F4 38 A0 00 0C */ li r5, 0xc
+/* 801D4A98 001D06F8 1C 00 00 0C */ mulli r0, r0, 0xc
+/* 801D4A9C 001D06FC 7C 9F 02 14 */ add r4, r31, r0
+/* 801D4AA0 001D0700 38 84 00 0C */ addi r4, r4, 0xc
+/* 801D4AA4 001D0704 4B E2 F6 C1 */ bl TRK_memcpy
+/* 801D4AA8 001D0708 80 7F 00 08 */ lwz r3, 8(r31)
+/* 801D4AAC 001D070C 80 9F 00 04 */ lwz r4, 4(r31)
+/* 801D4AB0 001D0710 38 03 00 01 */ addi r0, r3, 1
+/* 801D4AB4 001D0714 38 64 FF FF */ addi r3, r4, -1
+/* 801D4AB8 001D0718 90 1F 00 08 */ stw r0, 8(r31)
+/* 801D4ABC 001D071C 2C 00 00 02 */ cmpwi r0, 2
+/* 801D4AC0 001D0720 90 7F 00 04 */ stw r3, 4(r31)
+/* 801D4AC4 001D0724 40 82 00 0C */ bne lbl_801D4AD0
+/* 801D4AC8 001D0728 38 00 00 00 */ li r0, 0
+/* 801D4ACC 001D072C 90 1F 00 08 */ stw r0, 8(r31)
+lbl_801D4AD0:
+/* 801D4AD0 001D0730 3B C0 00 01 */ li r30, 1
+lbl_801D4AD4:
+/* 801D4AD4 001D0734 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
+/* 801D4AD8 001D0738 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
+/* 801D4ADC 001D073C 48 00 25 79 */ bl TRKReleaseMutex
+/* 801D4AE0 001D0740 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D4AE4 001D0744 7F C3 F3 78 */ mr r3, r30
+/* 801D4AE8 001D0748 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D4AEC 001D074C 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D4AF0 001D0750 83 A1 00 14 */ lwz r29, 0x14(r1)
+/* 801D4AF4 001D0754 7C 08 03 A6 */ mtlr r0
+/* 801D4AF8 001D0758 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D4AFC 001D075C 4E 80 00 20 */ blr
+
+.global TRKInitializeEventQueue
+TRKInitializeEventQueue:
+/* 801D4B00 001D0760 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 801D4B04 001D0764 7C 08 02 A6 */ mflr r0
+/* 801D4B08 001D0768 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
+/* 801D4B0C 001D076C 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D4B10 001D0770 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
+/* 801D4B14 001D0774 48 00 25 51 */ bl TRKInitializeMutex
+/* 801D4B18 001D0778 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
+/* 801D4B1C 001D077C 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
+/* 801D4B20 001D0780 48 00 25 3D */ bl TRKAcquireMutex
+/* 801D4B24 001D0784 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
+/* 801D4B28 001D0788 38 80 00 00 */ li r4, 0
+/* 801D4B2C 001D078C 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
+/* 801D4B30 001D0790 38 00 01 00 */ li r0, 0x100
+/* 801D4B34 001D0794 90 83 00 04 */ stw r4, 4(r3)
+/* 801D4B38 001D0798 90 83 00 08 */ stw r4, 8(r3)
+/* 801D4B3C 001D079C 90 03 00 24 */ stw r0, 0x24(r3)
+/* 801D4B40 001D07A0 48 00 25 15 */ bl TRKReleaseMutex
+/* 801D4B44 001D07A4 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D4B48 001D07A8 38 60 00 00 */ li r3, 0
+/* 801D4B4C 001D07AC 7C 08 03 A6 */ mtlr r0
+/* 801D4B50 001D07B0 38 21 00 10 */ addi r1, r1, 0x10
+/* 801D4B54 001D07B4 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/nubinit.s b/asm/MetroTRK/nubinit.s new file mode 100644 index 0000000..f826dfe --- /dev/null +++ b/asm/MetroTRK/nubinit.s @@ -0,0 +1,119 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKNubWelcome
+TRKNubWelcome:
+/* 801D4B58 001D07B8 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 801D4B5C 001D07BC 7C 08 02 A6 */ mflr r0
+/* 801D4B60 001D07C0 3C 60 80 40 */ lis r3, lbl_803FD640@ha
+/* 801D4B64 001D07C4 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D4B68 001D07C8 38 63 D6 40 */ addi r3, r3, lbl_803FD640@l
+/* 801D4B6C 001D07CC 48 00 4A 11 */ bl TRK_board_display
+/* 801D4B70 001D07D0 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D4B74 001D07D4 7C 08 03 A6 */ mtlr r0
+/* 801D4B78 001D07D8 38 21 00 10 */ addi r1, r1, 0x10
+/* 801D4B7C 001D07DC 4E 80 00 20 */ blr
+
+.global TRKTerminateNub
+TRKTerminateNub:
+/* 801D4B80 001D07E0 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 801D4B84 001D07E4 7C 08 02 A6 */ mflr r0
+/* 801D4B88 001D07E8 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D4B8C 001D07EC 48 00 09 B9 */ bl TRKTerminateSerialHandler
+/* 801D4B90 001D07F0 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D4B94 001D07F4 38 60 00 00 */ li r3, 0
+/* 801D4B98 001D07F8 7C 08 03 A6 */ mtlr r0
+/* 801D4B9C 001D07FC 38 21 00 10 */ addi r1, r1, 0x10
+/* 801D4BA0 001D0800 4E 80 00 20 */ blr
+
+.global TRKInitializeNub
+TRKInitializeNub:
+/* 801D4BA4 001D0804 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D4BA8 001D0808 7C 08 02 A6 */ mflr r0
+/* 801D4BAC 001D080C 38 A0 00 12 */ li r5, 0x12
+/* 801D4BB0 001D0810 38 80 00 34 */ li r4, 0x34
+/* 801D4BB4 001D0814 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D4BB8 001D0818 38 60 00 56 */ li r3, 0x56
+/* 801D4BBC 001D081C 38 00 00 78 */ li r0, 0x78
+/* 801D4BC0 001D0820 38 C0 00 01 */ li r6, 1
+/* 801D4BC4 001D0824 98 A1 00 08 */ stb r5, 8(r1)
+/* 801D4BC8 001D0828 3C A0 80 49 */ lis r5, lbl_8048EE18@ha
+/* 801D4BCC 001D082C 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D4BD0 001D0830 3B E0 00 00 */ li r31, 0
+/* 801D4BD4 001D0834 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D4BD8 001D0838 98 81 00 09 */ stb r4, 9(r1)
+/* 801D4BDC 001D083C 98 61 00 0A */ stb r3, 0xa(r1)
+/* 801D4BE0 001D0840 98 01 00 0B */ stb r0, 0xb(r1)
+/* 801D4BE4 001D0844 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D4BE8 001D0848 94 C5 EE 18 */ stwu r6, lbl_8048EE18@l(r5)
+/* 801D4BEC 001D084C 3C 03 ED CC */ addis r0, r3, 0xedcc
+/* 801D4BF0 001D0850 28 00 56 78 */ cmplwi r0, 0x5678
+/* 801D4BF4 001D0854 40 82 00 0C */ bne lbl_801D4C00
+/* 801D4BF8 001D0858 90 C5 00 00 */ stw r6, 0(r5)
+/* 801D4BFC 001D085C 48 00 00 1C */ b lbl_801D4C18
+lbl_801D4C00:
+/* 801D4C00 001D0860 3C 03 87 AA */ addis r0, r3, 0x87aa
+/* 801D4C04 001D0864 28 00 34 12 */ cmplwi r0, 0x3412
+/* 801D4C08 001D0868 40 82 00 0C */ bne lbl_801D4C14
+/* 801D4C0C 001D086C 93 E5 00 00 */ stw r31, 0(r5)
+/* 801D4C10 001D0870 48 00 00 08 */ b lbl_801D4C18
+lbl_801D4C14:
+/* 801D4C14 001D0874 7C DF 33 78 */ mr r31, r6
+lbl_801D4C18:
+/* 801D4C18 001D0878 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D4C1C 001D087C 40 82 00 08 */ bne lbl_801D4C24
+/* 801D4C20 001D0880 48 00 0A D1 */ bl usr_put_initialize
+lbl_801D4C24:
+/* 801D4C24 001D0884 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D4C28 001D0888 40 82 00 0C */ bne lbl_801D4C34
+/* 801D4C2C 001D088C 4B FF FE D5 */ bl TRKInitializeEventQueue
+/* 801D4C30 001D0890 7C 7F 1B 78 */ mr r31, r3
+lbl_801D4C34:
+/* 801D4C34 001D0894 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D4C38 001D0898 40 82 00 0C */ bne lbl_801D4C44
+/* 801D4C3C 001D089C 48 00 08 95 */ bl TRKInitializeMessageBuffers
+/* 801D4C40 001D08A0 7C 7F 1B 78 */ mr r31, r3
+lbl_801D4C44:
+/* 801D4C44 001D08A4 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D4C48 001D08A8 40 82 00 0C */ bne lbl_801D4C54
+/* 801D4C4C 001D08AC 48 00 0C 71 */ bl TRKInitializeDispatcher
+/* 801D4C50 001D08B0 7C 7F 1B 78 */ mr r31, r3
+lbl_801D4C54:
+/* 801D4C54 001D08B4 48 00 48 D1 */ bl InitializeProgramEndTrap
+/* 801D4C58 001D08B8 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D4C5C 001D08BC 40 82 00 0C */ bne lbl_801D4C68
+/* 801D4C60 001D08C0 48 00 08 ED */ bl TRKInitializeSerialHandler
+/* 801D4C64 001D08C4 7C 7F 1B 78 */ mr r31, r3
+lbl_801D4C68:
+/* 801D4C68 001D08C8 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D4C6C 001D08CC 40 82 00 0C */ bne lbl_801D4C78
+/* 801D4C70 001D08D0 48 00 45 F5 */ bl TRKInitializeTarget
+/* 801D4C74 001D08D4 7C 7F 1B 78 */ mr r31, r3
+lbl_801D4C78:
+/* 801D4C78 001D08D8 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D4C7C 001D08DC 40 82 00 44 */ bne lbl_801D4CC0
+/* 801D4C80 001D08E0 3C 60 80 64 */ lis r3, lbl_8063F2A0@ha
+/* 801D4C84 001D08E4 3C A0 00 01 */ lis r5, 0x0000E100@ha
+/* 801D4C88 001D08E8 38 C3 F2 A0 */ addi r6, r3, lbl_8063F2A0@l
+/* 801D4C8C 001D08EC 38 80 00 01 */ li r4, 1
+/* 801D4C90 001D08F0 38 65 E1 00 */ addi r3, r5, 0x0000E100@l
+/* 801D4C94 001D08F4 38 A0 00 00 */ li r5, 0
+/* 801D4C98 001D08F8 48 00 4A 65 */ bl TRKInitializeIntDrivenUART
+/* 801D4C9C 001D08FC 3C 80 80 64 */ lis r4, lbl_8063F2A0@ha
+/* 801D4CA0 001D0900 7C 60 1B 78 */ mr r0, r3
+/* 801D4CA4 001D0904 38 64 F2 A0 */ addi r3, r4, lbl_8063F2A0@l
+/* 801D4CA8 001D0908 80 63 00 00 */ lwz r3, 0(r3)
+/* 801D4CAC 001D090C 7C 1E 03 78 */ mr r30, r0
+/* 801D4CB0 001D0910 48 00 29 3D */ bl TRKTargetSetInputPendingPtr
+/* 801D4CB4 001D0914 2C 1E 00 00 */ cmpwi r30, 0
+/* 801D4CB8 001D0918 41 82 00 08 */ beq lbl_801D4CC0
+/* 801D4CBC 001D091C 7F DF F3 78 */ mr r31, r30
+lbl_801D4CC0:
+/* 801D4CC0 001D0920 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D4CC4 001D0924 7F E3 FB 78 */ mr r3, r31
+/* 801D4CC8 001D0928 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D4CCC 001D092C 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D4CD0 001D0930 7C 08 03 A6 */ mtlr r0
+/* 801D4CD4 001D0934 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D4CD8 001D0938 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/serpoll.s b/asm/MetroTRK/serpoll.s new file mode 100644 index 0000000..5aa893b --- /dev/null +++ b/asm/MetroTRK/serpoll.s @@ -0,0 +1,131 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKTerminateSerialHandler
+TRKTerminateSerialHandler:
+/* 801D5544 001D11A4 38 60 00 00 */ li r3, 0
+/* 801D5548 001D11A8 4E 80 00 20 */ blr
+
+.global TRKInitializeSerialHandler
+TRKInitializeSerialHandler:
+/* 801D554C 001D11AC 3C 60 80 49 */ lis r3, lbl_804907D0@ha
+/* 801D5550 001D11B0 38 A0 FF FF */ li r5, -1
+/* 801D5554 001D11B4 38 83 07 D0 */ addi r4, r3, lbl_804907D0@l
+/* 801D5558 001D11B8 38 00 00 00 */ li r0, 0
+/* 801D555C 001D11BC 90 A4 00 00 */ stw r5, 0(r4)
+/* 801D5560 001D11C0 38 60 00 00 */ li r3, 0
+/* 801D5564 001D11C4 90 04 00 08 */ stw r0, 8(r4)
+/* 801D5568 001D11C8 90 04 00 0C */ stw r0, 0xc(r4)
+/* 801D556C 001D11CC 4E 80 00 20 */ blr
+
+.global TRKProcessInput
+TRKProcessInput:
+/* 801D5570 001D11D0 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D5574 001D11D4 7C 08 02 A6 */ mflr r0
+/* 801D5578 001D11D8 38 80 00 02 */ li r4, 2
+/* 801D557C 001D11DC 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D5580 001D11E0 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D5584 001D11E4 7C 7F 1B 78 */ mr r31, r3
+/* 801D5588 001D11E8 38 61 00 08 */ addi r3, r1, 8
+/* 801D558C 001D11EC 4B FF F3 C9 */ bl TRKConstructEvent
+/* 801D5590 001D11F0 3C 60 80 49 */ lis r3, lbl_804907D0@ha
+/* 801D5594 001D11F4 38 00 FF FF */ li r0, -1
+/* 801D5598 001D11F8 38 83 07 D0 */ addi r4, r3, lbl_804907D0@l
+/* 801D559C 001D11FC 93 E1 00 10 */ stw r31, 0x10(r1)
+/* 801D55A0 001D1200 38 61 00 08 */ addi r3, r1, 8
+/* 801D55A4 001D1204 90 04 00 00 */ stw r0, 0(r4)
+/* 801D55A8 001D1208 4B FF F3 C5 */ bl TRKPostEvent
+/* 801D55AC 001D120C 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D55B0 001D1210 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D55B4 001D1214 7C 08 03 A6 */ mtlr r0
+/* 801D55B8 001D1218 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D55BC 001D121C 4E 80 00 20 */ blr
+
+.global TRKGetInput
+TRKGetInput:
+/* 801D55C0 001D1220 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D55C4 001D1224 7C 08 02 A6 */ mflr r0
+/* 801D55C8 001D1228 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D55CC 001D122C 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D55D0 001D1230 48 00 00 51 */ bl TRKTestForPacket
+/* 801D55D4 001D1234 7C 7F 1B 78 */ mr r31, r3
+/* 801D55D8 001D1238 2C 1F FF FF */ cmpwi r31, -1
+/* 801D55DC 001D123C 41 82 00 30 */ beq lbl_801D560C
+/* 801D55E0 001D1240 4B FF FD FD */ bl TRKGetBuffer
+/* 801D55E4 001D1244 38 61 00 08 */ addi r3, r1, 8
+/* 801D55E8 001D1248 38 80 00 02 */ li r4, 2
+/* 801D55EC 001D124C 4B FF F3 69 */ bl TRKConstructEvent
+/* 801D55F0 001D1250 3C 60 80 49 */ lis r3, lbl_804907D0@ha
+/* 801D55F4 001D1254 38 00 FF FF */ li r0, -1
+/* 801D55F8 001D1258 38 83 07 D0 */ addi r4, r3, lbl_804907D0@l
+/* 801D55FC 001D125C 93 E1 00 10 */ stw r31, 0x10(r1)
+/* 801D5600 001D1260 38 61 00 08 */ addi r3, r1, 8
+/* 801D5604 001D1264 90 04 00 00 */ stw r0, 0(r4)
+/* 801D5608 001D1268 4B FF F3 65 */ bl TRKPostEvent
+lbl_801D560C:
+/* 801D560C 001D126C 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D5610 001D1270 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D5614 001D1274 7C 08 03 A6 */ mtlr r0
+/* 801D5618 001D1278 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D561C 001D127C 4E 80 00 20 */ blr
+
+.global TRKTestForPacket
+TRKTestForPacket:
+/* 801D5620 001D1280 94 21 F7 20 */ stwu r1, -0x8e0(r1)
+/* 801D5624 001D1284 7C 08 02 A6 */ mflr r0
+/* 801D5628 001D1288 90 01 08 E4 */ stw r0, 0x8e4(r1)
+/* 801D562C 001D128C 93 E1 08 DC */ stw r31, 0x8dc(r1)
+/* 801D5630 001D1290 48 00 40 55 */ bl func_801D9684
+/* 801D5634 001D1294 2C 03 00 00 */ cmpwi r3, 0
+/* 801D5638 001D1298 41 81 00 0C */ bgt lbl_801D5644
+/* 801D563C 001D129C 38 60 FF FF */ li r3, -1
+/* 801D5640 001D12A0 48 00 00 9C */ b lbl_801D56DC
+lbl_801D5644:
+/* 801D5644 001D12A4 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D5648 001D12A8 38 81 00 08 */ addi r4, r1, 8
+/* 801D564C 001D12AC 4B FF FD BD */ bl TRKGetFreeBuffer
+/* 801D5650 001D12B0 7C 60 1B 78 */ mr r0, r3
+/* 801D5654 001D12B4 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D5658 001D12B8 7C 1F 03 78 */ mr r31, r0
+/* 801D565C 001D12BC 38 80 00 00 */ li r4, 0
+/* 801D5660 001D12C0 4B FF FC A9 */ bl TRKSetBufferPosition
+/* 801D5664 001D12C4 38 61 00 10 */ addi r3, r1, 0x10
+/* 801D5668 001D12C8 38 80 00 40 */ li r4, 0x40
+/* 801D566C 001D12CC 48 00 3F DD */ bl TRKWriteUARTN
+/* 801D5670 001D12D0 2C 03 00 00 */ cmpwi r3, 0
+/* 801D5674 001D12D4 40 82 00 58 */ bne lbl_801D56CC
+/* 801D5678 001D12D8 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D567C 001D12DC 38 81 00 10 */ addi r4, r1, 0x10
+/* 801D5680 001D12E0 38 A0 00 40 */ li r5, 0x40
+/* 801D5684 001D12E4 4B FF F9 F1 */ bl TRKAppendBuffer_ui8
+/* 801D5688 001D12E8 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D568C 001D12EC 83 E1 00 0C */ lwz r31, 0xc(r1)
+/* 801D5690 001D12F0 34 83 FF C0 */ addic. r4, r3, -64
+/* 801D5694 001D12F4 40 81 00 44 */ ble lbl_801D56D8
+/* 801D5698 001D12F8 38 61 00 50 */ addi r3, r1, 0x50
+/* 801D569C 001D12FC 48 00 3F AD */ bl TRKWriteUARTN
+/* 801D56A0 001D1300 2C 03 00 00 */ cmpwi r3, 0
+/* 801D56A4 001D1304 40 82 00 18 */ bne lbl_801D56BC
+/* 801D56A8 001D1308 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D56AC 001D130C 38 81 00 50 */ addi r4, r1, 0x50
+/* 801D56B0 001D1310 80 A1 00 10 */ lwz r5, 0x10(r1)
+/* 801D56B4 001D1314 4B FF F9 C1 */ bl TRKAppendBuffer_ui8
+/* 801D56B8 001D1318 48 00 00 20 */ b lbl_801D56D8
+lbl_801D56BC:
+/* 801D56BC 001D131C 7F E3 FB 78 */ mr r3, r31
+/* 801D56C0 001D1320 4B FF FC B9 */ bl TRKReleaseBuffer
+/* 801D56C4 001D1324 3B E0 FF FF */ li r31, -1
+/* 801D56C8 001D1328 48 00 00 10 */ b lbl_801D56D8
+lbl_801D56CC:
+/* 801D56CC 001D132C 7F E3 FB 78 */ mr r3, r31
+/* 801D56D0 001D1330 4B FF FC A9 */ bl TRKReleaseBuffer
+/* 801D56D4 001D1334 3B E0 FF FF */ li r31, -1
+lbl_801D56D8:
+/* 801D56D8 001D1338 7F E3 FB 78 */ mr r3, r31
+lbl_801D56DC:
+/* 801D56DC 001D133C 80 01 08 E4 */ lwz r0, 0x8e4(r1)
+/* 801D56E0 001D1340 83 E1 08 DC */ lwz r31, 0x8dc(r1)
+/* 801D56E4 001D1344 7C 08 03 A6 */ mtlr r0
+/* 801D56E8 001D1348 38 21 08 E0 */ addi r1, r1, 0x8e0
+/* 801D56EC 001D134C 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/string_TRK.s b/asm/MetroTRK/string_TRK.s new file mode 100644 index 0000000..95625a9 --- /dev/null +++ b/asm/MetroTRK/string_TRK.s @@ -0,0 +1,14 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRK_strlen
+TRK_strlen:
+/* 801D71F4 001D2E54 38 83 FF FF */ addi r4, r3, -1
+/* 801D71F8 001D2E58 38 60 FF FF */ li r3, -1
+lbl_801D71FC:
+/* 801D71FC 001D2E5C 8C 04 00 01 */ lbzu r0, 1(r4)
+/* 801D7200 001D2E60 38 63 00 01 */ addi r3, r3, 1
+/* 801D7204 001D2E64 28 00 00 00 */ cmplwi r0, 0
+/* 801D7208 001D2E68 40 82 FF F4 */ bne lbl_801D71FC
+/* 801D720C 001D2E6C 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/support.s b/asm/MetroTRK/support.s new file mode 100644 index 0000000..d58dcbe --- /dev/null +++ b/asm/MetroTRK/support.s @@ -0,0 +1,486 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global HandlePositionFileSupportRequest
+HandlePositionFileSupportRequest:
+/* 801D69A0 001D2600 94 21 FF 90 */ stwu r1, -0x70(r1)
+/* 801D69A4 001D2604 7C 08 02 A6 */ mflr r0
+/* 801D69A8 001D2608 90 01 00 74 */ stw r0, 0x74(r1)
+/* 801D69AC 001D260C 93 E1 00 6C */ stw r31, 0x6c(r1)
+/* 801D69B0 001D2610 7C BF 2B 78 */ mr r31, r5
+/* 801D69B4 001D2614 38 A0 00 40 */ li r5, 0x40
+/* 801D69B8 001D2618 93 C1 00 68 */ stw r30, 0x68(r1)
+/* 801D69BC 001D261C 7C DE 33 78 */ mr r30, r6
+/* 801D69C0 001D2620 93 A1 00 64 */ stw r29, 0x64(r1)
+/* 801D69C4 001D2624 7C 9D 23 78 */ mr r29, r4
+/* 801D69C8 001D2628 38 80 00 00 */ li r4, 0
+/* 801D69CC 001D262C 93 81 00 60 */ stw r28, 0x60(r1)
+/* 801D69D0 001D2630 7C 7C 1B 78 */ mr r28, r3
+/* 801D69D4 001D2634 38 61 00 14 */ addi r3, r1, 0x14
+/* 801D69D8 001D2638 4B E2 D7 5D */ bl TRK_memset
+/* 801D69DC 001D263C 38 60 00 D4 */ li r3, 0xd4
+/* 801D69E0 001D2640 38 00 00 40 */ li r0, 0x40
+/* 801D69E4 001D2644 98 61 00 18 */ stb r3, 0x18(r1)
+/* 801D69E8 001D2648 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D69EC 001D264C 38 81 00 08 */ addi r4, r1, 8
+/* 801D69F0 001D2650 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D69F4 001D2654 93 81 00 1C */ stw r28, 0x1c(r1)
+/* 801D69F8 001D2658 80 1D 00 00 */ lwz r0, 0(r29)
+/* 801D69FC 001D265C 90 01 00 20 */ stw r0, 0x20(r1)
+/* 801D6A00 001D2660 9B E1 00 24 */ stb r31, 0x24(r1)
+/* 801D6A04 001D2664 4B FF EA 05 */ bl TRKGetFreeBuffer
+/* 801D6A08 001D2668 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D6A0C 001D266C 40 82 00 18 */ bne lbl_801D6A24
+/* 801D6A10 001D2670 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6A14 001D2674 38 81 00 14 */ addi r4, r1, 0x14
+/* 801D6A18 001D2678 38 A0 00 40 */ li r5, 0x40
+/* 801D6A1C 001D267C 4B FF E6 59 */ bl TRKAppendBuffer_ui8
+/* 801D6A20 001D2680 7C 7F 1B 78 */ mr r31, r3
+lbl_801D6A24:
+/* 801D6A24 001D2684 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D6A28 001D2688 40 82 00 5C */ bne lbl_801D6A84
+/* 801D6A2C 001D268C 38 60 00 00 */ li r3, 0
+/* 801D6A30 001D2690 38 00 FF FF */ li r0, -1
+/* 801D6A34 001D2694 90 7E 00 00 */ stw r3, 0(r30)
+/* 801D6A38 001D2698 38 81 00 10 */ addi r4, r1, 0x10
+/* 801D6A3C 001D269C 38 A0 00 03 */ li r5, 3
+/* 801D6A40 001D26A0 38 C0 00 03 */ li r6, 3
+/* 801D6A44 001D26A4 90 1D 00 00 */ stw r0, 0(r29)
+/* 801D6A48 001D26A8 38 E0 00 00 */ li r7, 0
+/* 801D6A4C 001D26AC 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6A50 001D26B0 48 00 02 65 */ bl TRKRequestSend
+/* 801D6A54 001D26B4 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D6A58 001D26B8 40 82 00 24 */ bne lbl_801D6A7C
+/* 801D6A5C 001D26BC 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D6A60 001D26C0 4B FF E9 7D */ bl TRKGetBuffer
+/* 801D6A64 001D26C4 28 03 00 00 */ cmplwi r3, 0
+/* 801D6A68 001D26C8 41 82 00 14 */ beq lbl_801D6A7C
+/* 801D6A6C 001D26CC 80 03 00 20 */ lwz r0, 0x20(r3)
+/* 801D6A70 001D26D0 90 1E 00 00 */ stw r0, 0(r30)
+/* 801D6A74 001D26D4 80 03 00 28 */ lwz r0, 0x28(r3)
+/* 801D6A78 001D26D8 90 1D 00 00 */ stw r0, 0(r29)
+lbl_801D6A7C:
+/* 801D6A7C 001D26DC 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D6A80 001D26E0 4B FF E8 F9 */ bl TRKReleaseBuffer
+lbl_801D6A84:
+/* 801D6A84 001D26E4 80 61 00 0C */ lwz r3, 0xc(r1)
+/* 801D6A88 001D26E8 4B FF E8 F1 */ bl TRKReleaseBuffer
+/* 801D6A8C 001D26EC 80 01 00 74 */ lwz r0, 0x74(r1)
+/* 801D6A90 001D26F0 7F E3 FB 78 */ mr r3, r31
+/* 801D6A94 001D26F4 83 E1 00 6C */ lwz r31, 0x6c(r1)
+/* 801D6A98 001D26F8 83 C1 00 68 */ lwz r30, 0x68(r1)
+/* 801D6A9C 001D26FC 83 A1 00 64 */ lwz r29, 0x64(r1)
+/* 801D6AA0 001D2700 83 81 00 60 */ lwz r28, 0x60(r1)
+/* 801D6AA4 001D2704 7C 08 03 A6 */ mtlr r0
+/* 801D6AA8 001D2708 38 21 00 70 */ addi r1, r1, 0x70
+/* 801D6AAC 001D270C 4E 80 00 20 */ blr
+
+.global HandleCloseFileSupportRequest
+HandleCloseFileSupportRequest:
+/* 801D6AB0 001D2710 94 21 FF 90 */ stwu r1, -0x70(r1)
+/* 801D6AB4 001D2714 7C 08 02 A6 */ mflr r0
+/* 801D6AB8 001D2718 38 A0 00 40 */ li r5, 0x40
+/* 801D6ABC 001D271C 90 01 00 74 */ stw r0, 0x74(r1)
+/* 801D6AC0 001D2720 93 E1 00 6C */ stw r31, 0x6c(r1)
+/* 801D6AC4 001D2724 7C 7F 1B 78 */ mr r31, r3
+/* 801D6AC8 001D2728 38 61 00 14 */ addi r3, r1, 0x14
+/* 801D6ACC 001D272C 93 C1 00 68 */ stw r30, 0x68(r1)
+/* 801D6AD0 001D2730 93 A1 00 64 */ stw r29, 0x64(r1)
+/* 801D6AD4 001D2734 7C 9D 23 78 */ mr r29, r4
+/* 801D6AD8 001D2738 38 80 00 00 */ li r4, 0
+/* 801D6ADC 001D273C 4B E2 D6 59 */ bl TRK_memset
+/* 801D6AE0 001D2740 38 60 00 D3 */ li r3, 0xd3
+/* 801D6AE4 001D2744 38 00 00 40 */ li r0, 0x40
+/* 801D6AE8 001D2748 98 61 00 18 */ stb r3, 0x18(r1)
+/* 801D6AEC 001D274C 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D6AF0 001D2750 38 81 00 08 */ addi r4, r1, 8
+/* 801D6AF4 001D2754 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D6AF8 001D2758 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D6AFC 001D275C 4B FF E9 0D */ bl TRKGetFreeBuffer
+/* 801D6B00 001D2760 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D6B04 001D2764 40 82 00 18 */ bne lbl_801D6B1C
+/* 801D6B08 001D2768 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6B0C 001D276C 38 81 00 14 */ addi r4, r1, 0x14
+/* 801D6B10 001D2770 38 A0 00 40 */ li r5, 0x40
+/* 801D6B14 001D2774 4B FF E5 61 */ bl TRKAppendBuffer_ui8
+/* 801D6B18 001D2778 7C 7F 1B 78 */ mr r31, r3
+lbl_801D6B1C:
+/* 801D6B1C 001D277C 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D6B20 001D2780 40 82 00 50 */ bne lbl_801D6B70
+/* 801D6B24 001D2784 38 00 00 00 */ li r0, 0
+/* 801D6B28 001D2788 38 81 00 10 */ addi r4, r1, 0x10
+/* 801D6B2C 001D278C 90 1D 00 00 */ stw r0, 0(r29)
+/* 801D6B30 001D2790 38 A0 00 03 */ li r5, 3
+/* 801D6B34 001D2794 38 C0 00 03 */ li r6, 3
+/* 801D6B38 001D2798 38 E0 00 00 */ li r7, 0
+/* 801D6B3C 001D279C 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6B40 001D27A0 48 00 01 75 */ bl TRKRequestSend
+/* 801D6B44 001D27A4 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D6B48 001D27A8 40 82 00 10 */ bne lbl_801D6B58
+/* 801D6B4C 001D27AC 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D6B50 001D27B0 4B FF E8 8D */ bl TRKGetBuffer
+/* 801D6B54 001D27B4 7C 7E 1B 78 */ mr r30, r3
+lbl_801D6B58:
+/* 801D6B58 001D27B8 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D6B5C 001D27BC 40 82 00 0C */ bne lbl_801D6B68
+/* 801D6B60 001D27C0 80 1E 00 20 */ lwz r0, 0x20(r30)
+/* 801D6B64 001D27C4 90 1D 00 00 */ stw r0, 0(r29)
+lbl_801D6B68:
+/* 801D6B68 001D27C8 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D6B6C 001D27CC 4B FF E8 0D */ bl TRKReleaseBuffer
+lbl_801D6B70:
+/* 801D6B70 001D27D0 80 61 00 0C */ lwz r3, 0xc(r1)
+/* 801D6B74 001D27D4 4B FF E8 05 */ bl TRKReleaseBuffer
+/* 801D6B78 001D27D8 80 01 00 74 */ lwz r0, 0x74(r1)
+/* 801D6B7C 001D27DC 7F E3 FB 78 */ mr r3, r31
+/* 801D6B80 001D27E0 83 E1 00 6C */ lwz r31, 0x6c(r1)
+/* 801D6B84 001D27E4 83 C1 00 68 */ lwz r30, 0x68(r1)
+/* 801D6B88 001D27E8 83 A1 00 64 */ lwz r29, 0x64(r1)
+/* 801D6B8C 001D27EC 7C 08 03 A6 */ mtlr r0
+/* 801D6B90 001D27F0 38 21 00 70 */ addi r1, r1, 0x70
+/* 801D6B94 001D27F4 4E 80 00 20 */ blr
+
+.global HandleOpenFileSupportRequest
+HandleOpenFileSupportRequest:
+/* 801D6B98 001D27F8 94 21 FF 90 */ stwu r1, -0x70(r1)
+/* 801D6B9C 001D27FC 7C 08 02 A6 */ mflr r0
+/* 801D6BA0 001D2800 90 01 00 74 */ stw r0, 0x74(r1)
+/* 801D6BA4 001D2804 BF 61 00 5C */ stmw r27, 0x5c(r1)
+/* 801D6BA8 001D2808 7C 7B 1B 78 */ mr r27, r3
+/* 801D6BAC 001D280C 7C 9F 23 78 */ mr r31, r4
+/* 801D6BB0 001D2810 7C BC 2B 78 */ mr r28, r5
+/* 801D6BB4 001D2814 7C DD 33 78 */ mr r29, r6
+/* 801D6BB8 001D2818 38 61 00 14 */ addi r3, r1, 0x14
+/* 801D6BBC 001D281C 38 80 00 00 */ li r4, 0
+/* 801D6BC0 001D2820 38 A0 00 40 */ li r5, 0x40
+/* 801D6BC4 001D2824 4B E2 D5 71 */ bl TRK_memset
+/* 801D6BC8 001D2828 38 60 00 00 */ li r3, 0
+/* 801D6BCC 001D282C 38 00 00 D2 */ li r0, 0xd2
+/* 801D6BD0 001D2830 90 7C 00 00 */ stw r3, 0(r28)
+/* 801D6BD4 001D2834 7F 63 DB 78 */ mr r3, r27
+/* 801D6BD8 001D2838 98 01 00 18 */ stb r0, 0x18(r1)
+/* 801D6BDC 001D283C 48 00 06 19 */ bl TRK_strlen
+/* 801D6BE0 001D2840 38 03 00 41 */ addi r0, r3, 0x41
+/* 801D6BE4 001D2844 9B E1 00 1C */ stb r31, 0x1c(r1)
+/* 801D6BE8 001D2848 7F 63 DB 78 */ mr r3, r27
+/* 801D6BEC 001D284C 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D6BF0 001D2850 48 00 06 05 */ bl TRK_strlen
+/* 801D6BF4 001D2854 38 03 00 01 */ addi r0, r3, 1
+/* 801D6BF8 001D2858 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D6BFC 001D285C B0 01 00 20 */ sth r0, 0x20(r1)
+/* 801D6C00 001D2860 38 81 00 08 */ addi r4, r1, 8
+/* 801D6C04 001D2864 4B FF E8 05 */ bl TRKGetFreeBuffer
+/* 801D6C08 001D2868 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6C0C 001D286C 38 81 00 14 */ addi r4, r1, 0x14
+/* 801D6C10 001D2870 38 A0 00 40 */ li r5, 0x40
+/* 801D6C14 001D2874 4B FF E4 61 */ bl TRKAppendBuffer_ui8
+/* 801D6C18 001D2878 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D6C1C 001D287C 40 82 00 24 */ bne lbl_801D6C40
+/* 801D6C20 001D2880 7F 63 DB 78 */ mr r3, r27
+/* 801D6C24 001D2884 48 00 05 D1 */ bl TRK_strlen
+/* 801D6C28 001D2888 7C 65 1B 78 */ mr r5, r3
+/* 801D6C2C 001D288C 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6C30 001D2890 7F 64 DB 78 */ mr r4, r27
+/* 801D6C34 001D2894 38 A5 00 01 */ addi r5, r5, 1
+/* 801D6C38 001D2898 4B FF E4 3D */ bl TRKAppendBuffer_ui8
+/* 801D6C3C 001D289C 7C 7F 1B 78 */ mr r31, r3
+lbl_801D6C40:
+/* 801D6C40 001D28A0 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D6C44 001D28A4 40 82 00 50 */ bne lbl_801D6C94
+/* 801D6C48 001D28A8 38 00 00 00 */ li r0, 0
+/* 801D6C4C 001D28AC 38 81 00 10 */ addi r4, r1, 0x10
+/* 801D6C50 001D28B0 90 1D 00 00 */ stw r0, 0(r29)
+/* 801D6C54 001D28B4 38 A0 00 07 */ li r5, 7
+/* 801D6C58 001D28B8 38 C0 00 03 */ li r6, 3
+/* 801D6C5C 001D28BC 38 E0 00 00 */ li r7, 0
+/* 801D6C60 001D28C0 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6C64 001D28C4 48 00 00 51 */ bl TRKRequestSend
+/* 801D6C68 001D28C8 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D6C6C 001D28CC 40 82 00 10 */ bne lbl_801D6C7C
+/* 801D6C70 001D28D0 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D6C74 001D28D4 4B FF E7 69 */ bl TRKGetBuffer
+/* 801D6C78 001D28D8 7C 7E 1B 78 */ mr r30, r3
+lbl_801D6C7C:
+/* 801D6C7C 001D28DC 80 1E 00 20 */ lwz r0, 0x20(r30)
+/* 801D6C80 001D28E0 90 1D 00 00 */ stw r0, 0(r29)
+/* 801D6C84 001D28E4 80 1E 00 18 */ lwz r0, 0x18(r30)
+/* 801D6C88 001D28E8 90 1C 00 00 */ stw r0, 0(r28)
+/* 801D6C8C 001D28EC 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D6C90 001D28F0 4B FF E6 E9 */ bl TRKReleaseBuffer
+lbl_801D6C94:
+/* 801D6C94 001D28F4 80 61 00 0C */ lwz r3, 0xc(r1)
+/* 801D6C98 001D28F8 4B FF E6 E1 */ bl TRKReleaseBuffer
+/* 801D6C9C 001D28FC 7F E3 FB 78 */ mr r3, r31
+/* 801D6CA0 001D2900 BB 61 00 5C */ lmw r27, 0x5c(r1)
+/* 801D6CA4 001D2904 80 01 00 74 */ lwz r0, 0x74(r1)
+/* 801D6CA8 001D2908 7C 08 03 A6 */ mtlr r0
+/* 801D6CAC 001D290C 38 21 00 70 */ addi r1, r1, 0x70
+/* 801D6CB0 001D2910 4E 80 00 20 */ blr
+
+.global TRKRequestSend
+TRKRequestSend:
+/* 801D6CB4 001D2914 94 21 FF D0 */ stwu r1, -0x30(r1)
+/* 801D6CB8 001D2918 7C 08 02 A6 */ mflr r0
+/* 801D6CBC 001D291C 90 01 00 34 */ stw r0, 0x34(r1)
+/* 801D6CC0 001D2920 38 00 FF FF */ li r0, -1
+/* 801D6CC4 001D2924 BE C1 00 08 */ stmw r22, 8(r1)
+/* 801D6CC8 001D2928 7C 97 23 78 */ mr r23, r4
+/* 801D6CCC 001D292C 7C 76 1B 78 */ mr r22, r3
+/* 801D6CD0 001D2930 7C F8 3B 78 */ mr r24, r7
+/* 801D6CD4 001D2934 3B 86 00 01 */ addi r28, r6, 1
+/* 801D6CD8 001D2938 3B E0 00 00 */ li r31, 0
+/* 801D6CDC 001D293C 3B 20 00 01 */ li r25, 1
+/* 801D6CE0 001D2940 90 04 00 00 */ stw r0, 0(r4)
+/* 801D6CE4 001D2944 48 00 01 0C */ b lbl_801D6DF0
+lbl_801D6CE8:
+/* 801D6CE8 001D2948 7E C3 B3 78 */ mr r3, r22
+/* 801D6CEC 001D294C 4B FF DF F1 */ bl TRKMessageSend
+/* 801D6CF0 001D2950 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D6CF4 001D2954 40 82 00 F8 */ bne lbl_801D6DEC
+/* 801D6CF8 001D2958 2C 18 00 00 */ cmpwi r24, 0
+/* 801D6CFC 001D295C 41 82 00 08 */ beq lbl_801D6D04
+/* 801D6D00 001D2960 3B A0 00 00 */ li r29, 0
+lbl_801D6D04:
+/* 801D6D04 001D2964 4B FF E9 1D */ bl TRKTestForPacket
+/* 801D6D08 001D2968 90 77 00 00 */ stw r3, 0(r23)
+/* 801D6D0C 001D296C 80 77 00 00 */ lwz r3, 0(r23)
+/* 801D6D10 001D2970 2C 03 FF FF */ cmpwi r3, -1
+/* 801D6D14 001D2974 40 82 00 20 */ bne lbl_801D6D34
+/* 801D6D18 001D2978 2C 18 00 00 */ cmpwi r24, 0
+/* 801D6D1C 001D297C 41 82 FF E8 */ beq lbl_801D6D04
+/* 801D6D20 001D2980 3C 80 04 C5 */ lis r4, 0x04C4B3EC@ha
+/* 801D6D24 001D2984 3B BD 00 01 */ addi r29, r29, 1
+/* 801D6D28 001D2988 38 04 B3 EC */ addi r0, r4, 0x04C4B3EC@l
+/* 801D6D2C 001D298C 7C 1D 00 40 */ cmplw r29, r0
+/* 801D6D30 001D2990 41 80 FF D4 */ blt lbl_801D6D04
+lbl_801D6D34:
+/* 801D6D34 001D2994 2C 03 FF FF */ cmpwi r3, -1
+/* 801D6D38 001D2998 41 82 00 44 */ beq lbl_801D6D7C
+/* 801D6D3C 001D299C 3B 20 00 00 */ li r25, 0
+/* 801D6D40 001D29A0 4B FF E6 9D */ bl TRKGetBuffer
+/* 801D6D44 001D29A4 38 80 00 00 */ li r4, 0
+/* 801D6D48 001D29A8 7C 7E 1B 78 */ mr r30, r3
+/* 801D6D4C 001D29AC 4B FF E5 BD */ bl TRKSetBufferPosition
+/* 801D6D50 001D29B0 80 9E 00 08 */ lwz r4, 8(r30)
+/* 801D6D54 001D29B4 38 7E 00 10 */ addi r3, r30, 0x10
+/* 801D6D58 001D29B8 48 00 2F 0D */ bl func_801D9C64
+/* 801D6D5C 001D29BC 8B 7E 00 14 */ lbz r27, 0x14(r30)
+/* 801D6D60 001D29C0 28 1B 00 80 */ cmplwi r27, 0x80
+/* 801D6D64 001D29C4 40 80 00 18 */ bge lbl_801D6D7C
+/* 801D6D68 001D29C8 80 77 00 00 */ lwz r3, 0(r23)
+/* 801D6D6C 001D29CC 4B FF E8 05 */ bl TRKProcessInput
+/* 801D6D70 001D29D0 38 00 FF FF */ li r0, -1
+/* 801D6D74 001D29D4 90 17 00 00 */ stw r0, 0(r23)
+/* 801D6D78 001D29D8 4B FF FF 8C */ b lbl_801D6D04
+lbl_801D6D7C:
+/* 801D6D7C 001D29DC 80 77 00 00 */ lwz r3, 0(r23)
+/* 801D6D80 001D29E0 2C 03 FF FF */ cmpwi r3, -1
+/* 801D6D84 001D29E4 41 82 00 68 */ beq lbl_801D6DEC
+/* 801D6D88 001D29E8 80 1E 00 08 */ lwz r0, 8(r30)
+/* 801D6D8C 001D29EC 28 00 00 40 */ cmplwi r0, 0x40
+/* 801D6D90 001D29F0 40 80 00 08 */ bge lbl_801D6D98
+/* 801D6D94 001D29F4 3B 20 00 01 */ li r25, 1
+lbl_801D6D98:
+/* 801D6D98 001D29F8 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D6D9C 001D29FC 40 82 00 10 */ bne lbl_801D6DAC
+/* 801D6DA0 001D2A00 2C 19 00 00 */ cmpwi r25, 0
+/* 801D6DA4 001D2A04 40 82 00 08 */ bne lbl_801D6DAC
+/* 801D6DA8 001D2A08 8B 5E 00 18 */ lbz r26, 0x18(r30)
+lbl_801D6DAC:
+/* 801D6DAC 001D2A0C 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D6DB0 001D2A10 40 82 00 20 */ bne lbl_801D6DD0
+/* 801D6DB4 001D2A14 2C 19 00 00 */ cmpwi r25, 0
+/* 801D6DB8 001D2A18 40 82 00 18 */ bne lbl_801D6DD0
+/* 801D6DBC 001D2A1C 2C 1B 00 80 */ cmpwi r27, 0x80
+/* 801D6DC0 001D2A20 40 82 00 0C */ bne lbl_801D6DCC
+/* 801D6DC4 001D2A24 2C 1A 00 00 */ cmpwi r26, 0
+/* 801D6DC8 001D2A28 41 82 00 08 */ beq lbl_801D6DD0
+lbl_801D6DCC:
+/* 801D6DCC 001D2A2C 3B 20 00 01 */ li r25, 1
+lbl_801D6DD0:
+/* 801D6DD0 001D2A30 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D6DD4 001D2A34 40 82 00 0C */ bne lbl_801D6DE0
+/* 801D6DD8 001D2A38 2C 19 00 00 */ cmpwi r25, 0
+/* 801D6DDC 001D2A3C 41 82 00 10 */ beq lbl_801D6DEC
+lbl_801D6DE0:
+/* 801D6DE0 001D2A40 4B FF E5 99 */ bl TRKReleaseBuffer
+/* 801D6DE4 001D2A44 38 00 FF FF */ li r0, -1
+/* 801D6DE8 001D2A48 90 17 00 00 */ stw r0, 0(r23)
+lbl_801D6DEC:
+/* 801D6DEC 001D2A4C 3B 9C FF FF */ addi r28, r28, -1
+lbl_801D6DF0:
+/* 801D6DF0 001D2A50 2C 1C 00 00 */ cmpwi r28, 0
+/* 801D6DF4 001D2A54 41 82 00 18 */ beq lbl_801D6E0C
+/* 801D6DF8 001D2A58 80 17 00 00 */ lwz r0, 0(r23)
+/* 801D6DFC 001D2A5C 2C 00 FF FF */ cmpwi r0, -1
+/* 801D6E00 001D2A60 40 82 00 0C */ bne lbl_801D6E0C
+/* 801D6E04 001D2A64 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D6E08 001D2A68 41 82 FE E0 */ beq lbl_801D6CE8
+lbl_801D6E0C:
+/* 801D6E0C 001D2A6C 80 17 00 00 */ lwz r0, 0(r23)
+/* 801D6E10 001D2A70 2C 00 FF FF */ cmpwi r0, -1
+/* 801D6E14 001D2A74 40 82 00 08 */ bne lbl_801D6E1C
+/* 801D6E18 001D2A78 3B E0 08 00 */ li r31, 0x800
+lbl_801D6E1C:
+/* 801D6E1C 001D2A7C 7F E3 FB 78 */ mr r3, r31
+/* 801D6E20 001D2A80 BA C1 00 08 */ lmw r22, 8(r1)
+/* 801D6E24 001D2A84 80 01 00 34 */ lwz r0, 0x34(r1)
+/* 801D6E28 001D2A88 7C 08 03 A6 */ mtlr r0
+/* 801D6E2C 001D2A8C 38 21 00 30 */ addi r1, r1, 0x30
+/* 801D6E30 001D2A90 4E 80 00 20 */ blr
+
+.global TRKSuppAccessFile
+TRKSuppAccessFile:
+/* 801D6E34 001D2A94 94 21 FF 70 */ stwu r1, -0x90(r1)
+/* 801D6E38 001D2A98 7C 08 02 A6 */ mflr r0
+/* 801D6E3C 001D2A9C 90 01 00 94 */ stw r0, 0x94(r1)
+/* 801D6E40 001D2AA0 BE 61 00 5C */ stmw r19, 0x5c(r1)
+/* 801D6E44 001D2AA4 7C 98 23 79 */ or. r24, r4, r4
+/* 801D6E48 001D2AA8 7C 77 1B 78 */ mr r23, r3
+/* 801D6E4C 001D2AAC 7C B9 2B 78 */ mr r25, r5
+/* 801D6E50 001D2AB0 7C DA 33 78 */ mr r26, r6
+/* 801D6E54 001D2AB4 7C FB 3B 78 */ mr r27, r7
+/* 801D6E58 001D2AB8 7D 1C 43 78 */ mr r28, r8
+/* 801D6E5C 001D2ABC 41 82 00 10 */ beq lbl_801D6E6C
+/* 801D6E60 001D2AC0 80 19 00 00 */ lwz r0, 0(r25)
+/* 801D6E64 001D2AC4 28 00 00 00 */ cmplwi r0, 0
+/* 801D6E68 001D2AC8 40 82 00 0C */ bne lbl_801D6E74
+lbl_801D6E6C:
+/* 801D6E6C 001D2ACC 38 60 00 02 */ li r3, 2
+/* 801D6E70 001D2AD0 48 00 01 D0 */ b lbl_801D7040
+lbl_801D6E74:
+/* 801D6E74 001D2AD4 38 00 00 00 */ li r0, 0
+/* 801D6E78 001D2AD8 3B A0 00 00 */ li r29, 0
+/* 801D6E7C 001D2ADC 90 1A 00 00 */ stw r0, 0(r26)
+/* 801D6E80 001D2AE0 3B C0 00 00 */ li r30, 0
+/* 801D6E84 001D2AE4 3A A0 00 00 */ li r21, 0
+/* 801D6E88 001D2AE8 48 00 01 88 */ b lbl_801D7010
+lbl_801D6E8C:
+/* 801D6E8C 001D2AEC 38 61 00 14 */ addi r3, r1, 0x14
+/* 801D6E90 001D2AF0 38 80 00 00 */ li r4, 0
+/* 801D6E94 001D2AF4 38 A0 00 40 */ li r5, 0x40
+/* 801D6E98 001D2AF8 4B E2 D2 9D */ bl TRK_memset
+/* 801D6E9C 001D2AFC 80 19 00 00 */ lwz r0, 0(r25)
+/* 801D6EA0 001D2B00 38 60 08 00 */ li r3, 0x800
+/* 801D6EA4 001D2B04 7C 1E 00 50 */ subf r0, r30, r0
+/* 801D6EA8 001D2B08 28 00 08 00 */ cmplwi r0, 0x800
+/* 801D6EAC 001D2B0C 41 81 00 08 */ bgt lbl_801D6EB4
+/* 801D6EB0 001D2B10 7C 03 03 78 */ mr r3, r0
+lbl_801D6EB4:
+/* 801D6EB4 001D2B14 2C 1C 00 00 */ cmpwi r28, 0
+/* 801D6EB8 001D2B18 7C 7F 1B 78 */ mr r31, r3
+/* 801D6EBC 001D2B1C 38 00 00 D0 */ li r0, 0xd0
+/* 801D6EC0 001D2B20 41 82 00 08 */ beq lbl_801D6EC8
+/* 801D6EC4 001D2B24 38 00 00 D1 */ li r0, 0xd1
+lbl_801D6EC8:
+/* 801D6EC8 001D2B28 2C 1C 00 00 */ cmpwi r28, 0
+/* 801D6ECC 001D2B2C 98 01 00 18 */ stb r0, 0x18(r1)
+/* 801D6ED0 001D2B30 38 00 00 40 */ li r0, 0x40
+/* 801D6ED4 001D2B34 40 82 00 08 */ bne lbl_801D6EDC
+/* 801D6ED8 001D2B38 38 1F 00 40 */ addi r0, r31, 0x40
+lbl_801D6EDC:
+/* 801D6EDC 001D2B3C 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D6EE0 001D2B40 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D6EE4 001D2B44 38 81 00 08 */ addi r4, r1, 8
+/* 801D6EE8 001D2B48 92 E1 00 1C */ stw r23, 0x1c(r1)
+/* 801D6EEC 001D2B4C B3 E1 00 20 */ sth r31, 0x20(r1)
+/* 801D6EF0 001D2B50 4B FF E5 19 */ bl TRKGetFreeBuffer
+/* 801D6EF4 001D2B54 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6EF8 001D2B58 38 81 00 14 */ addi r4, r1, 0x14
+/* 801D6EFC 001D2B5C 38 A0 00 40 */ li r5, 0x40
+/* 801D6F00 001D2B60 4B FF E1 75 */ bl TRKAppendBuffer_ui8
+/* 801D6F04 001D2B64 2C 1C 00 00 */ cmpwi r28, 0
+/* 801D6F08 001D2B68 7C 75 1B 78 */ mr r21, r3
+/* 801D6F0C 001D2B6C 40 82 00 20 */ bne lbl_801D6F2C
+/* 801D6F10 001D2B70 2C 15 00 00 */ cmpwi r21, 0
+/* 801D6F14 001D2B74 40 82 00 18 */ bne lbl_801D6F2C
+/* 801D6F18 001D2B78 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6F1C 001D2B7C 7F E5 FB 78 */ mr r5, r31
+/* 801D6F20 001D2B80 7C 98 F2 14 */ add r4, r24, r30
+/* 801D6F24 001D2B84 4B FF E1 51 */ bl TRKAppendBuffer_ui8
+/* 801D6F28 001D2B88 7C 75 1B 78 */ mr r21, r3
+lbl_801D6F2C:
+/* 801D6F2C 001D2B8C 2C 15 00 00 */ cmpwi r21, 0
+/* 801D6F30 001D2B90 40 82 00 D4 */ bne lbl_801D7004
+/* 801D6F34 001D2B94 2C 1B 00 00 */ cmpwi r27, 0
+/* 801D6F38 001D2B98 41 82 00 C0 */ beq lbl_801D6FF8
+/* 801D6F3C 001D2B9C 2C 1C 00 00 */ cmpwi r28, 0
+/* 801D6F40 001D2BA0 38 00 00 00 */ li r0, 0
+/* 801D6F44 001D2BA4 41 82 00 10 */ beq lbl_801D6F54
+/* 801D6F48 001D2BA8 28 17 00 00 */ cmplwi r23, 0
+/* 801D6F4C 001D2BAC 40 82 00 08 */ bne lbl_801D6F54
+/* 801D6F50 001D2BB0 38 00 00 01 */ li r0, 1
+lbl_801D6F54:
+/* 801D6F54 001D2BB4 2C 1C 00 00 */ cmpwi r28, 0
+/* 801D6F58 001D2BB8 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6F5C 001D2BBC 38 81 00 10 */ addi r4, r1, 0x10
+/* 801D6F60 001D2BC0 38 A0 00 05 */ li r5, 5
+/* 801D6F64 001D2BC4 7C 00 00 34 */ cntlzw r0, r0
+/* 801D6F68 001D2BC8 38 C0 00 03 */ li r6, 3
+/* 801D6F6C 001D2BCC 54 07 D9 7E */ srwi r7, r0, 5
+/* 801D6F70 001D2BD0 4B FF FD 45 */ bl TRKRequestSend
+/* 801D6F74 001D2BD4 7C 75 1B 79 */ or. r21, r3, r3
+/* 801D6F78 001D2BD8 40 82 00 10 */ bne lbl_801D6F88
+/* 801D6F7C 001D2BDC 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D6F80 001D2BE0 4B FF E4 5D */ bl TRKGetBuffer
+/* 801D6F84 001D2BE4 7C 76 1B 78 */ mr r22, r3
+lbl_801D6F88:
+/* 801D6F88 001D2BE8 80 16 00 20 */ lwz r0, 0x20(r22)
+/* 801D6F8C 001D2BEC 2C 1C 00 00 */ cmpwi r28, 0
+/* 801D6F90 001D2BF0 A2 76 00 24 */ lhz r19, 0x24(r22)
+/* 801D6F94 001D2BF4 54 14 06 3E */ clrlwi r20, r0, 0x18
+/* 801D6F98 001D2BF8 41 82 00 40 */ beq lbl_801D6FD8
+/* 801D6F9C 001D2BFC 2C 15 00 00 */ cmpwi r21, 0
+/* 801D6FA0 001D2C00 40 82 00 38 */ bne lbl_801D6FD8
+/* 801D6FA4 001D2C04 7C 13 F8 40 */ cmplw r19, r31
+/* 801D6FA8 001D2C08 41 81 00 30 */ bgt lbl_801D6FD8
+/* 801D6FAC 001D2C0C 7E C3 B3 78 */ mr r3, r22
+/* 801D6FB0 001D2C10 38 80 00 40 */ li r4, 0x40
+/* 801D6FB4 001D2C14 4B FF E3 55 */ bl TRKSetBufferPosition
+/* 801D6FB8 001D2C18 7E C3 B3 78 */ mr r3, r22
+/* 801D6FBC 001D2C1C 7E 65 9B 78 */ mr r5, r19
+/* 801D6FC0 001D2C20 7C 98 F2 14 */ add r4, r24, r30
+/* 801D6FC4 001D2C24 4B FF DE 35 */ bl TRKReadBuffer_ui8
+/* 801D6FC8 001D2C28 7C 75 1B 78 */ mr r21, r3
+/* 801D6FCC 001D2C2C 2C 15 03 02 */ cmpwi r21, 0x302
+/* 801D6FD0 001D2C30 40 82 00 08 */ bne lbl_801D6FD8
+/* 801D6FD4 001D2C34 3A A0 00 00 */ li r21, 0
+lbl_801D6FD8:
+/* 801D6FD8 001D2C38 7C 13 F8 40 */ cmplw r19, r31
+/* 801D6FDC 001D2C3C 41 82 00 0C */ beq lbl_801D6FE8
+/* 801D6FE0 001D2C40 7E 7F 9B 78 */ mr r31, r19
+/* 801D6FE4 001D2C44 3B A0 00 01 */ li r29, 1
+lbl_801D6FE8:
+/* 801D6FE8 001D2C48 92 9A 00 00 */ stw r20, 0(r26)
+/* 801D6FEC 001D2C4C 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D6FF0 001D2C50 4B FF E3 89 */ bl TRKReleaseBuffer
+/* 801D6FF4 001D2C54 48 00 00 10 */ b lbl_801D7004
+lbl_801D6FF8:
+/* 801D6FF8 001D2C58 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D6FFC 001D2C5C 4B FF DC E1 */ bl TRKMessageSend
+/* 801D7000 001D2C60 7C 75 1B 78 */ mr r21, r3
+lbl_801D7004:
+/* 801D7004 001D2C64 80 61 00 0C */ lwz r3, 0xc(r1)
+/* 801D7008 001D2C68 4B FF E3 71 */ bl TRKReleaseBuffer
+/* 801D700C 001D2C6C 7F DE FA 14 */ add r30, r30, r31
+lbl_801D7010:
+/* 801D7010 001D2C70 2C 1D 00 00 */ cmpwi r29, 0
+/* 801D7014 001D2C74 40 82 00 24 */ bne lbl_801D7038
+/* 801D7018 001D2C78 80 19 00 00 */ lwz r0, 0(r25)
+/* 801D701C 001D2C7C 7C 1E 00 40 */ cmplw r30, r0
+/* 801D7020 001D2C80 40 80 00 18 */ bge lbl_801D7038
+/* 801D7024 001D2C84 2C 15 00 00 */ cmpwi r21, 0
+/* 801D7028 001D2C88 40 82 00 10 */ bne lbl_801D7038
+/* 801D702C 001D2C8C 80 1A 00 00 */ lwz r0, 0(r26)
+/* 801D7030 001D2C90 2C 00 00 00 */ cmpwi r0, 0
+/* 801D7034 001D2C94 41 82 FE 58 */ beq lbl_801D6E8C
+lbl_801D7038:
+/* 801D7038 001D2C98 93 D9 00 00 */ stw r30, 0(r25)
+/* 801D703C 001D2C9C 7E A3 AB 78 */ mr r3, r21
+lbl_801D7040:
+/* 801D7040 001D2CA0 BA 61 00 5C */ lmw r19, 0x5c(r1)
+/* 801D7044 001D2CA4 80 01 00 94 */ lwz r0, 0x94(r1)
+/* 801D7048 001D2CA8 7C 08 03 A6 */ mtlr r0
+/* 801D704C 001D2CAC 38 21 00 90 */ addi r1, r1, 0x90
+/* 801D7050 001D2CB0 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/targimpl.s b/asm/MetroTRK/targimpl.s new file mode 100644 index 0000000..5355556 --- /dev/null +++ b/asm/MetroTRK/targimpl.s @@ -0,0 +1,1869 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global __TRK_get_MSR
+__TRK_get_MSR:
+/* 801D7210 001D2E70 7C 60 00 A6 */ mfmsr r3
+/* 801D7214 001D2E74 4E 80 00 20 */ blr
+
+.global __TRK_set_MSR
+__TRK_set_MSR:
+/* 801D7218 001D2E78 7C 60 01 24 */ mtmsr r3
+/* 801D721C 001D2E7C 4E 80 00 20 */ blr
+
+.global TRK_ppc_memcpy
+TRK_ppc_memcpy:
+/* 801D7220 001D2E80 7D 00 00 A6 */ mfmsr r8
+/* 801D7224 001D2E84 39 40 00 00 */ li r10, 0
+lbl_801D7228:
+/* 801D7228 001D2E88 7C 0A 28 00 */ cmpw r10, r5
+/* 801D722C 001D2E8C 41 82 00 24 */ beq lbl_801D7250
+/* 801D7230 001D2E90 7C E0 01 24 */ mtmsr r7
+/* 801D7234 001D2E94 7C 00 04 AC */ sync 0
+/* 801D7238 001D2E98 7D 2A 20 AE */ lbzx r9, r10, r4
+/* 801D723C 001D2E9C 7C C0 01 24 */ mtmsr r6
+/* 801D7240 001D2EA0 7C 00 04 AC */ sync 0
+/* 801D7244 001D2EA4 7D 2A 19 AE */ stbx r9, r10, r3
+/* 801D7248 001D2EA8 39 4A 00 01 */ addi r10, r10, 1
+/* 801D724C 001D2EAC 4B FF FF DC */ b lbl_801D7228
+lbl_801D7250:
+/* 801D7250 001D2EB0 7D 00 01 24 */ mtmsr r8
+/* 801D7254 001D2EB4 7C 00 04 AC */ sync 0
+/* 801D7258 001D2EB8 4E 80 00 20 */ blr
+
+.global TRKInterruptHandler
+TRKInterruptHandler:
+/* 801D725C 001D2EBC 7C 5A 03 A6 */ mtspr 0x1a, r2
+/* 801D7260 001D2EC0 7C 9B 03 A6 */ mtspr 0x1b, r4
+/* 801D7264 001D2EC4 7C 93 42 A6 */ mfspr r4, 0x113
+/* 801D7268 001D2EC8 7C 40 00 26 */ mfcr r2
+/* 801D726C 001D2ECC 7C 53 43 A6 */ mtspr 0x113, r2
+/* 801D7270 001D2ED0 3C 40 80 49 */ lis r2, lbl_804907F4@h
+/* 801D7274 001D2ED4 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l
+/* 801D7278 001D2ED8 80 42 00 8C */ lwz r2, 0x8c(r2)
+/* 801D727C 001D2EDC 60 42 80 02 */ ori r2, r2, 0x8002
+/* 801D7280 001D2EE0 68 42 80 02 */ xori r2, r2, 0x8002
+/* 801D7284 001D2EE4 7C 00 04 AC */ sync 0
+/* 801D7288 001D2EE8 7C 40 01 24 */ mtmsr r2
+/* 801D728C 001D2EEC 7C 00 04 AC */ sync 0
+/* 801D7290 001D2EF0 3C 40 80 49 */ lis r2, lbl_804907F0@h
+/* 801D7294 001D2EF4 60 42 07 F0 */ ori r2, r2, lbl_804907F0@l
+/* 801D7298 001D2EF8 B0 62 00 00 */ sth r3, 0(r2)
+/* 801D729C 001D2EFC 2C 03 05 00 */ cmpwi r3, 0x500
+/* 801D72A0 001D2F00 40 82 00 84 */ bne lbl_801D7324
+/* 801D72A4 001D2F04 3C 40 80 49 */ lis r2, lbl_80490898@h
+/* 801D72A8 001D2F08 60 42 08 98 */ ori r2, r2, lbl_80490898@l
+/* 801D72AC 001D2F0C 7C 68 02 A6 */ mflr r3
+/* 801D72B0 001D2F10 90 62 04 2C */ stw r3, 0x42c(r2)
+/* 801D72B4 001D2F14 48 00 22 6D */ bl func_801D9520
+/* 801D72B8 001D2F18 3C 40 80 49 */ lis r2, lbl_80490898@h
+/* 801D72BC 001D2F1C 60 42 08 98 */ ori r2, r2, lbl_80490898@l
+/* 801D72C0 001D2F20 80 62 04 2C */ lwz r3, 0x42c(r2)
+/* 801D72C4 001D2F24 7C 68 03 A6 */ mtlr r3
+/* 801D72C8 001D2F28 3C 40 80 49 */ lis r2, lbl_804907F4@h
+/* 801D72CC 001D2F2C 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l
+/* 801D72D0 001D2F30 80 42 00 A0 */ lwz r2, 0xa0(r2)
+/* 801D72D4 001D2F34 88 42 00 00 */ lbz r2, 0(r2)
+/* 801D72D8 001D2F38 2C 02 00 00 */ cmpwi r2, 0
+/* 801D72DC 001D2F3C 41 82 00 2C */ beq lbl_801D7308
+/* 801D72E0 001D2F40 3C 40 80 42 */ lis r2, lbl_8042323C@h
+/* 801D72E4 001D2F44 60 42 32 3C */ ori r2, r2, lbl_8042323C@l
+/* 801D72E8 001D2F48 88 42 00 0C */ lbz r2, 0xc(r2)
+/* 801D72EC 001D2F4C 2C 02 00 01 */ cmpwi r2, 1
+/* 801D72F0 001D2F50 41 82 00 18 */ beq lbl_801D7308
+/* 801D72F4 001D2F54 3C 40 80 49 */ lis r2, lbl_804907F4@h
+/* 801D72F8 001D2F58 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l
+/* 801D72FC 001D2F5C 38 60 00 01 */ li r3, 1
+/* 801D7300 001D2F60 98 62 00 9C */ stb r3, 0x9c(r2)
+/* 801D7304 001D2F64 48 00 00 20 */ b lbl_801D7324
+lbl_801D7308:
+/* 801D7308 001D2F68 3C 40 80 49 */ lis r2, lbl_80490CC8@h
+/* 801D730C 001D2F6C 60 42 0C C8 */ ori r2, r2, lbl_80490CC8@l
+/* 801D7310 001D2F70 80 62 00 88 */ lwz r3, 0x88(r2)
+/* 801D7314 001D2F74 7C 6F F1 20 */ mtcrf 0xff, r3
+/* 801D7318 001D2F78 80 62 00 0C */ lwz r3, 0xc(r2)
+/* 801D731C 001D2F7C 80 42 00 08 */ lwz r2, 8(r2)
+/* 801D7320 001D2F80 4C 00 00 64 */ rfi
+lbl_801D7324:
+/* 801D7324 001D2F84 3C 40 80 49 */ lis r2, lbl_804907F0@h
+/* 801D7328 001D2F88 60 42 07 F0 */ ori r2, r2, lbl_804907F0@l
+/* 801D732C 001D2F8C A0 62 00 00 */ lhz r3, 0(r2)
+/* 801D7330 001D2F90 3C 40 80 42 */ lis r2, lbl_8042323C@h
+/* 801D7334 001D2F94 60 42 32 3C */ ori r2, r2, lbl_8042323C@l
+/* 801D7338 001D2F98 88 42 00 0C */ lbz r2, 0xc(r2)
+/* 801D733C 001D2F9C 2C 02 00 00 */ cmpwi r2, 0
+/* 801D7340 001D2FA0 40 82 00 B0 */ bne TRKExceptionHandler
+/* 801D7344 001D2FA4 3C 40 80 49 */ lis r2, lbl_80490898@h
+/* 801D7348 001D2FA8 60 42 08 98 */ ori r2, r2, lbl_80490898@l
+/* 801D734C 001D2FAC 90 02 00 00 */ stw r0, 0(r2)
+/* 801D7350 001D2FB0 90 22 00 04 */ stw r1, 4(r2)
+/* 801D7354 001D2FB4 7C 11 42 A6 */ mfspr r0, 0x111
+/* 801D7358 001D2FB8 90 02 00 08 */ stw r0, 8(r2)
+/* 801D735C 001D2FBC B0 62 02 F8 */ sth r3, 0x2f8(r2)
+/* 801D7360 001D2FC0 B0 62 02 FA */ sth r3, 0x2fa(r2)
+/* 801D7364 001D2FC4 7C 12 42 A6 */ mfspr r0, 0x112
+/* 801D7368 001D2FC8 90 02 00 0C */ stw r0, 0xc(r2)
+/* 801D736C 001D2FCC BC 82 00 10 */ stmw r4, 0x10(r2)
+/* 801D7370 001D2FD0 7F 7A 02 A6 */ mfspr r27, 0x1a
+/* 801D7374 001D2FD4 7F 88 02 A6 */ mflr r28
+/* 801D7378 001D2FD8 7F B3 42 A6 */ mfspr r29, 0x113
+/* 801D737C 001D2FDC 7F C9 02 A6 */ mfctr r30
+/* 801D7380 001D2FE0 7F E1 02 A6 */ mfxer r31
+/* 801D7384 001D2FE4 BF 62 00 80 */ stmw r27, 0x80(r2)
+/* 801D7388 001D2FE8 48 00 18 C9 */ bl TRKSaveExtended1Block
+/* 801D738C 001D2FEC 3C 40 80 42 */ lis r2, lbl_8042323C@h
+/* 801D7390 001D2FF0 60 42 32 3C */ ori r2, r2, lbl_8042323C@l
+/* 801D7394 001D2FF4 38 60 00 01 */ li r3, 1
+/* 801D7398 001D2FF8 98 62 00 0C */ stb r3, 0xc(r2)
+/* 801D739C 001D2FFC 3C 40 80 49 */ lis r2, lbl_804907F4@h
+/* 801D73A0 001D3000 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l
+/* 801D73A4 001D3004 80 02 00 8C */ lwz r0, 0x8c(r2)
+/* 801D73A8 001D3008 7C 00 04 AC */ sync 0
+/* 801D73AC 001D300C 7C 00 01 24 */ mtmsr r0
+/* 801D73B0 001D3010 7C 00 04 AC */ sync 0
+/* 801D73B4 001D3014 80 02 00 80 */ lwz r0, 0x80(r2)
+/* 801D73B8 001D3018 7C 08 03 A6 */ mtlr r0
+/* 801D73BC 001D301C 80 02 00 84 */ lwz r0, 0x84(r2)
+/* 801D73C0 001D3020 7C 09 03 A6 */ mtctr r0
+/* 801D73C4 001D3024 80 02 00 88 */ lwz r0, 0x88(r2)
+/* 801D73C8 001D3028 7C 01 03 A6 */ mtxer r0
+/* 801D73CC 001D302C 80 02 00 94 */ lwz r0, 0x94(r2)
+/* 801D73D0 001D3030 7C 12 03 A6 */ mtdsisr r0
+/* 801D73D4 001D3034 80 02 00 90 */ lwz r0, 0x90(r2)
+/* 801D73D8 001D3038 7C 13 03 A6 */ mtdar r0
+/* 801D73DC 001D303C B8 62 00 0C */ lmw r3, 0xc(r2)
+/* 801D73E0 001D3040 80 02 00 00 */ lwz r0, 0(r2)
+/* 801D73E4 001D3044 80 22 00 04 */ lwz r1, 4(r2)
+/* 801D73E8 001D3048 80 42 00 08 */ lwz r2, 8(r2)
+/* 801D73EC 001D304C 48 00 07 AC */ b TRKPostInterruptEvent
+
+.global TRKExceptionHandler
+TRKExceptionHandler:
+/* 801D73F0 001D3050 3C 40 80 42 */ lis r2, lbl_8042323C@h
+/* 801D73F4 001D3054 60 42 32 3C */ ori r2, r2, lbl_8042323C@l
+/* 801D73F8 001D3058 B0 62 00 08 */ sth r3, 8(r2)
+/* 801D73FC 001D305C 7C 7A 02 A6 */ mfspr r3, 0x1a
+/* 801D7400 001D3060 90 62 00 00 */ stw r3, 0(r2)
+/* 801D7404 001D3064 A0 62 00 08 */ lhz r3, 8(r2)
+/* 801D7408 001D3068 2C 03 02 00 */ cmpwi r3, 0x200
+/* 801D740C 001D306C 41 82 00 50 */ beq lbl_801D745C
+/* 801D7410 001D3070 2C 03 03 00 */ cmpwi r3, 0x300
+/* 801D7414 001D3074 41 82 00 48 */ beq lbl_801D745C
+/* 801D7418 001D3078 2C 03 04 00 */ cmpwi r3, 0x400
+/* 801D741C 001D307C 41 82 00 40 */ beq lbl_801D745C
+/* 801D7420 001D3080 2C 03 06 00 */ cmpwi r3, 0x600
+/* 801D7424 001D3084 41 82 00 38 */ beq lbl_801D745C
+/* 801D7428 001D3088 2C 03 07 00 */ cmpwi r3, 0x700
+/* 801D742C 001D308C 41 82 00 30 */ beq lbl_801D745C
+/* 801D7430 001D3090 2C 03 08 00 */ cmpwi r3, 0x800
+/* 801D7434 001D3094 41 82 00 28 */ beq lbl_801D745C
+/* 801D7438 001D3098 2C 03 10 00 */ cmpwi r3, 0x1000
+/* 801D743C 001D309C 41 82 00 20 */ beq lbl_801D745C
+/* 801D7440 001D30A0 2C 03 11 00 */ cmpwi r3, 0x1100
+/* 801D7444 001D30A4 41 82 00 18 */ beq lbl_801D745C
+/* 801D7448 001D30A8 2C 03 12 00 */ cmpwi r3, 0x1200
+/* 801D744C 001D30AC 41 82 00 10 */ beq lbl_801D745C
+/* 801D7450 001D30B0 2C 03 13 00 */ cmpwi r3, 0x1300
+/* 801D7454 001D30B4 41 82 00 08 */ beq lbl_801D745C
+/* 801D7458 001D30B8 48 00 00 10 */ b lbl_801D7468
+lbl_801D745C:
+/* 801D745C 001D30BC 7C 7A 02 A6 */ mfspr r3, 0x1a
+/* 801D7460 001D30C0 38 63 00 04 */ addi r3, r3, 4
+/* 801D7464 001D30C4 7C 7A 03 A6 */ mtspr 0x1a, r3
+lbl_801D7468:
+/* 801D7468 001D30C8 3C 40 80 42 */ lis r2, lbl_8042323C@h
+/* 801D746C 001D30CC 60 42 32 3C */ ori r2, r2, lbl_8042323C@l
+/* 801D7470 001D30D0 38 60 00 01 */ li r3, 1
+/* 801D7474 001D30D4 98 62 00 0D */ stb r3, 0xd(r2)
+/* 801D7478 001D30D8 7C 73 42 A6 */ mfspr r3, 0x113
+/* 801D747C 001D30DC 7C 6F F1 20 */ mtcrf 0xff, r3
+/* 801D7480 001D30E0 7C 51 42 A6 */ mfspr r2, 0x111
+/* 801D7484 001D30E4 7C 72 42 A6 */ mfspr r3, 0x112
+/* 801D7488 001D30E8 4C 00 00 64 */ rfi
+
+.global TRKSwapAndGo
+TRKSwapAndGo:
+/* 801D748C 001D30EC 3C 60 80 49 */ lis r3, lbl_804907F4@h
+/* 801D7490 001D30F0 60 63 07 F4 */ ori r3, r3, lbl_804907F4@l
+/* 801D7494 001D30F4 BC 03 00 00 */ stmw r0, 0(r3)
+/* 801D7498 001D30F8 7C 00 00 A6 */ mfmsr r0
+/* 801D749C 001D30FC 90 03 00 8C */ stw r0, 0x8c(r3)
+/* 801D74A0 001D3100 7C 08 02 A6 */ mflr r0
+/* 801D74A4 001D3104 90 03 00 80 */ stw r0, 0x80(r3)
+/* 801D74A8 001D3108 7C 09 02 A6 */ mfctr r0
+/* 801D74AC 001D310C 90 03 00 84 */ stw r0, 0x84(r3)
+/* 801D74B0 001D3110 7C 01 02 A6 */ mfxer r0
+/* 801D74B4 001D3114 90 03 00 88 */ stw r0, 0x88(r3)
+/* 801D74B8 001D3118 7C 12 02 A6 */ mfdsisr r0
+/* 801D74BC 001D311C 90 03 00 94 */ stw r0, 0x94(r3)
+/* 801D74C0 001D3120 7C 13 02 A6 */ mfdar r0
+/* 801D74C4 001D3124 90 03 00 90 */ stw r0, 0x90(r3)
+/* 801D74C8 001D3128 38 20 80 02 */ li r1, -32766
+/* 801D74CC 001D312C 7C 21 08 F8 */ nor r1, r1, r1
+/* 801D74D0 001D3130 7C 60 00 A6 */ mfmsr r3
+/* 801D74D4 001D3134 7C 63 08 38 */ and r3, r3, r1
+/* 801D74D8 001D3138 7C 60 01 24 */ mtmsr r3
+/* 801D74DC 001D313C 3C 40 80 49 */ lis r2, lbl_804907F4@h
+/* 801D74E0 001D3140 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l
+/* 801D74E4 001D3144 80 42 00 A0 */ lwz r2, 0xa0(r2)
+/* 801D74E8 001D3148 88 42 00 00 */ lbz r2, 0(r2)
+/* 801D74EC 001D314C 2C 02 00 00 */ cmpwi r2, 0
+/* 801D74F0 001D3150 41 82 00 18 */ beq lbl_801D7508
+/* 801D74F4 001D3154 3C 40 80 49 */ lis r2, lbl_804907F4@h
+/* 801D74F8 001D3158 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l
+/* 801D74FC 001D315C 38 60 00 01 */ li r3, 1
+/* 801D7500 001D3160 98 62 00 9C */ stb r3, 0x9c(r2)
+/* 801D7504 001D3164 48 00 00 4C */ b TRKInterruptHandlerEnableInterrupts
+lbl_801D7508:
+/* 801D7508 001D3168 3C 40 80 42 */ lis r2, lbl_8042323C@h
+/* 801D750C 001D316C 60 42 32 3C */ ori r2, r2, lbl_8042323C@l
+/* 801D7510 001D3170 38 60 00 00 */ li r3, 0
+/* 801D7514 001D3174 98 62 00 0C */ stb r3, 0xc(r2)
+/* 801D7518 001D3178 48 00 18 F1 */ bl TRKRestoreExtended1Block
+/* 801D751C 001D317C 3C 40 80 49 */ lis r2, lbl_80490898@h
+/* 801D7520 001D3180 60 42 08 98 */ ori r2, r2, lbl_80490898@l
+/* 801D7524 001D3184 BB 62 00 80 */ lmw r27, 0x80(r2)
+/* 801D7528 001D3188 7F 7A 03 A6 */ mtspr 0x1a, r27
+/* 801D752C 001D318C 7F 88 03 A6 */ mtlr r28
+/* 801D7530 001D3190 7F AF F1 20 */ mtcrf 0xff, r29
+/* 801D7534 001D3194 7F C9 03 A6 */ mtctr r30
+/* 801D7538 001D3198 7F E1 03 A6 */ mtxer r31
+/* 801D753C 001D319C B8 62 00 0C */ lmw r3, 0xc(r2)
+/* 801D7540 001D31A0 80 02 00 00 */ lwz r0, 0(r2)
+/* 801D7544 001D31A4 80 22 00 04 */ lwz r1, 4(r2)
+/* 801D7548 001D31A8 80 42 00 08 */ lwz r2, 8(r2)
+/* 801D754C 001D31AC 4C 00 00 64 */ rfi
+
+.global TRKInterruptHandlerEnableInterrupts
+TRKInterruptHandlerEnableInterrupts:
+/* 801D7550 001D31B0 3C 40 80 49 */ lis r2, lbl_804907F4@h
+/* 801D7554 001D31B4 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l
+/* 801D7558 001D31B8 80 02 00 8C */ lwz r0, 0x8c(r2)
+/* 801D755C 001D31BC 7C 00 04 AC */ sync 0
+/* 801D7560 001D31C0 7C 00 01 24 */ mtmsr r0
+/* 801D7564 001D31C4 7C 00 04 AC */ sync 0
+/* 801D7568 001D31C8 80 02 00 80 */ lwz r0, 0x80(r2)
+/* 801D756C 001D31CC 7C 08 03 A6 */ mtlr r0
+/* 801D7570 001D31D0 80 02 00 84 */ lwz r0, 0x84(r2)
+/* 801D7574 001D31D4 7C 09 03 A6 */ mtctr r0
+/* 801D7578 001D31D8 80 02 00 88 */ lwz r0, 0x88(r2)
+/* 801D757C 001D31DC 7C 01 03 A6 */ mtxer r0
+/* 801D7580 001D31E0 80 02 00 94 */ lwz r0, 0x94(r2)
+/* 801D7584 001D31E4 7C 12 03 A6 */ mtdsisr r0
+/* 801D7588 001D31E8 80 02 00 90 */ lwz r0, 0x90(r2)
+/* 801D758C 001D31EC 7C 13 03 A6 */ mtdar r0
+/* 801D7590 001D31F0 B8 62 00 0C */ lmw r3, 0xc(r2)
+/* 801D7594 001D31F4 80 02 00 00 */ lwz r0, 0(r2)
+/* 801D7598 001D31F8 80 22 00 04 */ lwz r1, 4(r2)
+/* 801D759C 001D31FC 80 42 00 08 */ lwz r2, 8(r2)
+/* 801D75A0 001D3200 48 00 05 F8 */ b TRKPostInterruptEvent
+
+.global ReadFPSCR
+ReadFPSCR:
+/* 801D75A4 001D3204 94 21 FF C0 */ stwu r1, -0x40(r1)
+/* 801D75A8 001D3208 DB E1 00 10 */ stfd f31, 0x10(r1)
+/* 801D75AC 001D320C F3 E1 00 20 */ psq_st f31, 32(r1), 0, qr0
+/* 801D75B0 001D3210 FF E0 04 8E */ mffs f31
+/* 801D75B4 001D3214 DB E3 00 00 */ stfd f31, 0(r3)
+/* 801D75B8 001D3218 E3 E1 00 20 */ psq_l f31, 32(r1), 0, qr0
+/* 801D75BC 001D321C CB E1 00 10 */ lfd f31, 0x10(r1)
+/* 801D75C0 001D3220 38 21 00 40 */ addi r1, r1, 0x40
+/* 801D75C4 001D3224 4E 80 00 20 */ blr
+
+.global WriteFPSCR
+WriteFPSCR:
+/* 801D75C8 001D3228 94 21 FF C0 */ stwu r1, -0x40(r1)
+/* 801D75CC 001D322C DB E1 00 10 */ stfd f31, 0x10(r1)
+/* 801D75D0 001D3230 F3 E1 00 20 */ psq_st f31, 32(r1), 0, qr0
+/* 801D75D4 001D3234 CB E3 00 00 */ lfd f31, 0(r3)
+/* 801D75D8 001D3238 FD FE FD 8E */ mtfsf 0xff, f31
+/* 801D75DC 001D323C E3 E1 00 20 */ psq_l f31, 32(r1), 0, qr0
+/* 801D75E0 001D3240 CB E1 00 10 */ lfd f31, 0x10(r1)
+/* 801D75E4 001D3244 38 21 00 40 */ addi r1, r1, 0x40
+/* 801D75E8 001D3248 4E 80 00 20 */ blr
+
+.global TRKTargetSetInputPendingPtr
+TRKTargetSetInputPendingPtr:
+/* 801D75EC 001D324C 3C 80 80 49 */ lis r4, lbl_804907F4@ha
+/* 801D75F0 001D3250 38 84 07 F4 */ addi r4, r4, lbl_804907F4@l
+/* 801D75F4 001D3254 90 64 00 A0 */ stw r3, 0xa0(r4)
+/* 801D75F8 001D3258 4E 80 00 20 */ blr
+
+.global TRKTargetStop
+TRKTargetStop:
+/* 801D75FC 001D325C 3C 60 80 49 */ lis r3, lbl_804907F4@ha
+/* 801D7600 001D3260 38 00 00 01 */ li r0, 1
+/* 801D7604 001D3264 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l
+/* 801D7608 001D3268 38 60 00 00 */ li r3, 0
+/* 801D760C 001D326C 90 04 00 98 */ stw r0, 0x98(r4)
+/* 801D7610 001D3270 4E 80 00 20 */ blr
+
+.global TRKTargetSetStopped
+TRKTargetSetStopped:
+/* 801D7614 001D3274 3C 80 80 49 */ lis r4, lbl_804907F4@ha
+/* 801D7618 001D3278 38 84 07 F4 */ addi r4, r4, lbl_804907F4@l
+/* 801D761C 001D327C 90 64 00 98 */ stw r3, 0x98(r4)
+/* 801D7620 001D3280 4E 80 00 20 */ blr
+
+.global TRKTargetStopped
+TRKTargetStopped:
+/* 801D7624 001D3284 3C 60 80 49 */ lis r3, lbl_804907F4@ha
+/* 801D7628 001D3288 38 63 07 F4 */ addi r3, r3, lbl_804907F4@l
+/* 801D762C 001D328C 80 63 00 98 */ lwz r3, 0x98(r3)
+/* 801D7630 001D3290 4E 80 00 20 */ blr
+
+.global TRKTargetSupportRequest
+TRKTargetSupportRequest:
+/* 801D7634 001D3294 94 21 FF C0 */ stwu r1, -0x40(r1)
+/* 801D7638 001D3298 7C 08 02 A6 */ mflr r0
+/* 801D763C 001D329C 3C 60 80 49 */ lis r3, lbl_80490898@ha
+/* 801D7640 001D32A0 90 01 00 44 */ stw r0, 0x44(r1)
+/* 801D7644 001D32A4 BF 61 00 2C */ stmw r27, 0x2c(r1)
+/* 801D7648 001D32A8 3B E3 08 98 */ addi r31, r3, lbl_80490898@l
+/* 801D764C 001D32AC 83 7F 00 0C */ lwz r27, 0xc(r31)
+/* 801D7650 001D32B0 2C 1B 00 D1 */ cmpwi r27, 0xd1
+/* 801D7654 001D32B4 41 82 00 40 */ beq lbl_801D7694
+/* 801D7658 001D32B8 2C 1B 00 D0 */ cmpwi r27, 0xd0
+/* 801D765C 001D32BC 41 82 00 38 */ beq lbl_801D7694
+/* 801D7660 001D32C0 2C 1B 00 D2 */ cmpwi r27, 0xd2
+/* 801D7664 001D32C4 41 82 00 30 */ beq lbl_801D7694
+/* 801D7668 001D32C8 2C 1B 00 D3 */ cmpwi r27, 0xd3
+/* 801D766C 001D32CC 41 82 00 28 */ beq lbl_801D7694
+/* 801D7670 001D32D0 2C 1B 00 D4 */ cmpwi r27, 0xd4
+/* 801D7674 001D32D4 41 82 00 20 */ beq lbl_801D7694
+/* 801D7678 001D32D8 38 61 00 10 */ addi r3, r1, 0x10
+/* 801D767C 001D32DC 38 80 00 04 */ li r4, 4
+/* 801D7680 001D32E0 4B FF D2 D5 */ bl TRKConstructEvent
+/* 801D7684 001D32E4 38 61 00 10 */ addi r3, r1, 0x10
+/* 801D7688 001D32E8 4B FF D2 E5 */ bl TRKPostEvent
+/* 801D768C 001D32EC 38 60 00 00 */ li r3, 0
+/* 801D7690 001D32F0 48 00 01 90 */ b lbl_801D7820
+lbl_801D7694:
+/* 801D7694 001D32F4 2C 1B 00 D2 */ cmpwi r27, 0xd2
+/* 801D7698 001D32F8 40 82 00 50 */ bne lbl_801D76E8
+/* 801D769C 001D32FC 3C 60 80 49 */ lis r3, lbl_80490898@ha
+/* 801D76A0 001D3300 38 C1 00 0C */ addi r6, r1, 0xc
+/* 801D76A4 001D3304 38 83 08 98 */ addi r4, r3, lbl_80490898@l
+/* 801D76A8 001D3308 80 04 00 14 */ lwz r0, 0x14(r4)
+/* 801D76AC 001D330C 80 64 00 10 */ lwz r3, 0x10(r4)
+/* 801D76B0 001D3310 80 A4 00 18 */ lwz r5, 0x18(r4)
+/* 801D76B4 001D3314 54 04 06 3E */ clrlwi r4, r0, 0x18
+/* 801D76B8 001D3318 4B FF F4 E1 */ bl HandleOpenFileSupportRequest
+/* 801D76BC 001D331C 80 01 00 0C */ lwz r0, 0xc(r1)
+/* 801D76C0 001D3320 7C 7E 1B 78 */ mr r30, r3
+/* 801D76C4 001D3324 2C 00 00 00 */ cmpwi r0, 0
+/* 801D76C8 001D3328 40 82 00 14 */ bne lbl_801D76DC
+/* 801D76CC 001D332C 2C 1E 00 00 */ cmpwi r30, 0
+/* 801D76D0 001D3330 41 82 00 0C */ beq lbl_801D76DC
+/* 801D76D4 001D3334 38 00 00 01 */ li r0, 1
+/* 801D76D8 001D3338 90 01 00 0C */ stw r0, 0xc(r1)
+lbl_801D76DC:
+/* 801D76DC 001D333C 80 01 00 0C */ lwz r0, 0xc(r1)
+/* 801D76E0 001D3340 90 1F 00 0C */ stw r0, 0xc(r31)
+/* 801D76E4 001D3344 48 00 01 24 */ b lbl_801D7808
+lbl_801D76E8:
+/* 801D76E8 001D3348 2C 1B 00 D3 */ cmpwi r27, 0xd3
+/* 801D76EC 001D334C 40 82 00 44 */ bne lbl_801D7730
+/* 801D76F0 001D3350 3C 60 80 49 */ lis r3, lbl_80490898@ha
+/* 801D76F4 001D3354 38 81 00 0C */ addi r4, r1, 0xc
+/* 801D76F8 001D3358 38 63 08 98 */ addi r3, r3, lbl_80490898@l
+/* 801D76FC 001D335C 80 63 00 10 */ lwz r3, 0x10(r3)
+/* 801D7700 001D3360 4B FF F3 B1 */ bl HandleCloseFileSupportRequest
+/* 801D7704 001D3364 80 01 00 0C */ lwz r0, 0xc(r1)
+/* 801D7708 001D3368 7C 7E 1B 78 */ mr r30, r3
+/* 801D770C 001D336C 2C 00 00 00 */ cmpwi r0, 0
+/* 801D7710 001D3370 40 82 00 14 */ bne lbl_801D7724
+/* 801D7714 001D3374 2C 1E 00 00 */ cmpwi r30, 0
+/* 801D7718 001D3378 41 82 00 0C */ beq lbl_801D7724
+/* 801D771C 001D337C 38 00 00 01 */ li r0, 1
+/* 801D7720 001D3380 90 01 00 0C */ stw r0, 0xc(r1)
+lbl_801D7724:
+/* 801D7724 001D3384 80 01 00 0C */ lwz r0, 0xc(r1)
+/* 801D7728 001D3388 90 1F 00 0C */ stw r0, 0xc(r31)
+/* 801D772C 001D338C 48 00 00 DC */ b lbl_801D7808
+lbl_801D7730:
+/* 801D7730 001D3390 2C 1B 00 D4 */ cmpwi r27, 0xd4
+/* 801D7734 001D3394 40 82 00 68 */ bne lbl_801D779C
+/* 801D7738 001D3398 3C 60 80 49 */ lis r3, lbl_80490898@ha
+/* 801D773C 001D339C 38 81 00 08 */ addi r4, r1, 8
+/* 801D7740 001D33A0 3B A3 08 98 */ addi r29, r3, lbl_80490898@l
+/* 801D7744 001D33A4 38 C1 00 0C */ addi r6, r1, 0xc
+/* 801D7748 001D33A8 80 7D 00 14 */ lwz r3, 0x14(r29)
+/* 801D774C 001D33AC 80 1D 00 18 */ lwz r0, 0x18(r29)
+/* 801D7750 001D33B0 80 E3 00 00 */ lwz r7, 0(r3)
+/* 801D7754 001D33B4 80 7D 00 10 */ lwz r3, 0x10(r29)
+/* 801D7758 001D33B8 54 05 06 3E */ clrlwi r5, r0, 0x18
+/* 801D775C 001D33BC 90 E1 00 08 */ stw r7, 8(r1)
+/* 801D7760 001D33C0 4B FF F2 41 */ bl HandlePositionFileSupportRequest
+/* 801D7764 001D33C4 80 01 00 0C */ lwz r0, 0xc(r1)
+/* 801D7768 001D33C8 7C 7E 1B 78 */ mr r30, r3
+/* 801D776C 001D33CC 2C 00 00 00 */ cmpwi r0, 0
+/* 801D7770 001D33D0 40 82 00 14 */ bne lbl_801D7784
+/* 801D7774 001D33D4 2C 1E 00 00 */ cmpwi r30, 0
+/* 801D7778 001D33D8 41 82 00 0C */ beq lbl_801D7784
+/* 801D777C 001D33DC 38 00 00 01 */ li r0, 1
+/* 801D7780 001D33E0 90 01 00 0C */ stw r0, 0xc(r1)
+lbl_801D7784:
+/* 801D7784 001D33E4 80 61 00 0C */ lwz r3, 0xc(r1)
+/* 801D7788 001D33E8 80 01 00 08 */ lwz r0, 8(r1)
+/* 801D778C 001D33EC 90 7F 00 0C */ stw r3, 0xc(r31)
+/* 801D7790 001D33F0 80 7D 00 14 */ lwz r3, 0x14(r29)
+/* 801D7794 001D33F4 90 03 00 00 */ stw r0, 0(r3)
+/* 801D7798 001D33F8 48 00 00 70 */ b lbl_801D7808
+lbl_801D779C:
+/* 801D779C 001D33FC 3C 60 80 49 */ lis r3, lbl_80490898@ha
+/* 801D77A0 001D3400 20 1B 00 D1 */ subfic r0, r27, 0xd1
+/* 801D77A4 001D3404 3B A3 08 98 */ addi r29, r3, lbl_80490898@l
+/* 801D77A8 001D3408 38 C1 00 0C */ addi r6, r1, 0xc
+/* 801D77AC 001D340C 83 9D 00 14 */ lwz r28, 0x14(r29)
+/* 801D77B0 001D3410 7C 00 00 34 */ cntlzw r0, r0
+/* 801D77B4 001D3414 80 7D 00 10 */ lwz r3, 0x10(r29)
+/* 801D77B8 001D3418 54 08 D9 7E */ srwi r8, r0, 5
+/* 801D77BC 001D341C 80 9D 00 18 */ lwz r4, 0x18(r29)
+/* 801D77C0 001D3420 7F 85 E3 78 */ mr r5, r28
+/* 801D77C4 001D3424 38 E0 00 01 */ li r7, 1
+/* 801D77C8 001D3428 4B FF F6 6D */ bl TRKSuppAccessFile
+/* 801D77CC 001D342C 80 01 00 0C */ lwz r0, 0xc(r1)
+/* 801D77D0 001D3430 7C 7E 1B 78 */ mr r30, r3
+/* 801D77D4 001D3434 2C 00 00 00 */ cmpwi r0, 0
+/* 801D77D8 001D3438 40 82 00 14 */ bne lbl_801D77EC
+/* 801D77DC 001D343C 2C 1E 00 00 */ cmpwi r30, 0
+/* 801D77E0 001D3440 41 82 00 0C */ beq lbl_801D77EC
+/* 801D77E4 001D3444 38 00 00 01 */ li r0, 1
+/* 801D77E8 001D3448 90 01 00 0C */ stw r0, 0xc(r1)
+lbl_801D77EC:
+/* 801D77EC 001D344C 80 01 00 0C */ lwz r0, 0xc(r1)
+/* 801D77F0 001D3450 2C 1B 00 D1 */ cmpwi r27, 0xd1
+/* 801D77F4 001D3454 90 1F 00 0C */ stw r0, 0xc(r31)
+/* 801D77F8 001D3458 40 82 00 10 */ bne lbl_801D7808
+/* 801D77FC 001D345C 80 7D 00 18 */ lwz r3, 0x18(r29)
+/* 801D7800 001D3460 80 9C 00 00 */ lwz r4, 0(r28)
+/* 801D7804 001D3464 4B FF F9 01 */ bl TRK_flush_cache
+lbl_801D7808:
+/* 801D7808 001D3468 3C 80 80 49 */ lis r4, lbl_80490898@ha
+/* 801D780C 001D346C 7F C3 F3 78 */ mr r3, r30
+/* 801D7810 001D3470 38 A4 08 98 */ addi r5, r4, lbl_80490898@l
+/* 801D7814 001D3474 80 85 00 80 */ lwz r4, 0x80(r5)
+/* 801D7818 001D3478 38 04 00 04 */ addi r0, r4, 4
+/* 801D781C 001D347C 90 05 00 80 */ stw r0, 0x80(r5)
+lbl_801D7820:
+/* 801D7820 001D3480 BB 61 00 2C */ lmw r27, 0x2c(r1)
+/* 801D7824 001D3484 80 01 00 44 */ lwz r0, 0x44(r1)
+/* 801D7828 001D3488 7C 08 03 A6 */ mtlr r0
+/* 801D782C 001D348C 38 21 00 40 */ addi r1, r1, 0x40
+/* 801D7830 001D3490 4E 80 00 20 */ blr
+
+.global TRKTargetGetPC
+TRKTargetGetPC:
+/* 801D7834 001D3494 3C 60 80 49 */ lis r3, lbl_80490898@ha
+/* 801D7838 001D3498 38 63 08 98 */ addi r3, r3, lbl_80490898@l
+/* 801D783C 001D349C 80 63 00 80 */ lwz r3, 0x80(r3)
+/* 801D7840 001D34A0 4E 80 00 20 */ blr
+
+.global TRKTargetStepOutOfRange
+TRKTargetStepOutOfRange:
+/* 801D7844 001D34A4 2C 05 00 00 */ cmpwi r5, 0
+/* 801D7848 001D34A8 41 82 00 0C */ beq lbl_801D7854
+/* 801D784C 001D34AC 38 60 07 03 */ li r3, 0x703
+/* 801D7850 001D34B0 4E 80 00 20 */ blr
+lbl_801D7854:
+/* 801D7854 001D34B4 3C A0 80 49 */ lis r5, lbl_80490898@ha
+/* 801D7858 001D34B8 38 E0 00 01 */ li r7, 1
+/* 801D785C 001D34BC 38 A5 08 98 */ addi r5, r5, lbl_80490898@l
+/* 801D7860 001D34C0 3C C0 80 42 */ lis r6, lbl_8042324C@ha
+/* 801D7864 001D34C4 80 05 01 F8 */ lwz r0, 0x1f8(r5)
+/* 801D7868 001D34C8 38 C6 32 4C */ addi r6, r6, lbl_8042324C@l
+/* 801D786C 001D34CC 2C 07 00 00 */ cmpwi r7, 0
+/* 801D7870 001D34D0 90 E6 00 04 */ stw r7, 4(r6)
+/* 801D7874 001D34D4 60 00 04 00 */ ori r0, r0, 0x400
+/* 801D7878 001D34D8 90 66 00 0C */ stw r3, 0xc(r6)
+/* 801D787C 001D34DC 90 86 00 10 */ stw r4, 0x10(r6)
+/* 801D7880 001D34E0 90 E6 00 00 */ stw r7, 0(r6)
+/* 801D7884 001D34E4 90 05 01 F8 */ stw r0, 0x1f8(r5)
+/* 801D7888 001D34E8 41 82 00 0C */ beq lbl_801D7894
+/* 801D788C 001D34EC 2C 07 00 10 */ cmpwi r7, 0x10
+/* 801D7890 001D34F0 40 82 00 18 */ bne lbl_801D78A8
+lbl_801D7894:
+/* 801D7894 001D34F4 3C 60 80 42 */ lis r3, lbl_8042324C@ha
+/* 801D7898 001D34F8 38 83 32 4C */ addi r4, r3, lbl_8042324C@l
+/* 801D789C 001D34FC 80 64 00 08 */ lwz r3, 8(r4)
+/* 801D78A0 001D3500 38 03 FF FF */ addi r0, r3, -1
+/* 801D78A4 001D3504 90 04 00 08 */ stw r0, 8(r4)
+lbl_801D78A8:
+/* 801D78A8 001D3508 3C 60 80 49 */ lis r3, lbl_804907F4@ha
+/* 801D78AC 001D350C 38 00 00 00 */ li r0, 0
+/* 801D78B0 001D3510 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l
+/* 801D78B4 001D3514 38 60 00 00 */ li r3, 0
+/* 801D78B8 001D3518 90 04 00 98 */ stw r0, 0x98(r4)
+/* 801D78BC 001D351C 4E 80 00 20 */ blr
+
+.global TRKTargetSingleStep
+TRKTargetSingleStep:
+/* 801D78C0 001D3520 2C 04 00 00 */ cmpwi r4, 0
+/* 801D78C4 001D3524 41 82 00 0C */ beq lbl_801D78D0
+/* 801D78C8 001D3528 38 60 07 03 */ li r3, 0x703
+/* 801D78CC 001D352C 4E 80 00 20 */ blr
+lbl_801D78D0:
+/* 801D78D0 001D3530 3C 80 80 49 */ lis r4, lbl_80490898@ha
+/* 801D78D4 001D3534 3C A0 80 42 */ lis r5, lbl_8042324C@ha
+/* 801D78D8 001D3538 38 84 08 98 */ addi r4, r4, lbl_80490898@l
+/* 801D78DC 001D353C 38 E0 00 00 */ li r7, 0
+/* 801D78E0 001D3540 80 04 01 F8 */ lwz r0, 0x1f8(r4)
+/* 801D78E4 001D3544 38 C5 32 4C */ addi r6, r5, lbl_8042324C@l
+/* 801D78E8 001D3548 38 A0 00 01 */ li r5, 1
+/* 801D78EC 001D354C 90 E6 00 04 */ stw r7, 4(r6)
+/* 801D78F0 001D3550 60 00 04 00 */ ori r0, r0, 0x400
+/* 801D78F4 001D3554 90 66 00 08 */ stw r3, 8(r6)
+/* 801D78F8 001D3558 90 A6 00 00 */ stw r5, 0(r6)
+/* 801D78FC 001D355C 90 04 01 F8 */ stw r0, 0x1f8(r4)
+/* 801D7900 001D3560 48 00 00 08 */ b lbl_801D7908
+/* 801D7904 001D3564 40 82 00 10 */ bne lbl_801D7914
+lbl_801D7908:
+/* 801D7908 001D3568 80 66 00 08 */ lwz r3, 8(r6)
+/* 801D790C 001D356C 38 03 FF FF */ addi r0, r3, -1
+/* 801D7910 001D3570 90 06 00 08 */ stw r0, 8(r6)
+lbl_801D7914:
+/* 801D7914 001D3574 3C 60 80 49 */ lis r3, lbl_804907F4@ha
+/* 801D7918 001D3578 38 00 00 00 */ li r0, 0
+/* 801D791C 001D357C 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l
+/* 801D7920 001D3580 38 60 00 00 */ li r3, 0
+/* 801D7924 001D3584 90 04 00 98 */ stw r0, 0x98(r4)
+/* 801D7928 001D3588 4E 80 00 20 */ blr
+
+.global TRKTargetAddExceptionInfo
+TRKTargetAddExceptionInfo:
+/* 801D792C 001D358C 94 21 FF A0 */ stwu r1, -0x60(r1)
+/* 801D7930 001D3590 7C 08 02 A6 */ mflr r0
+/* 801D7934 001D3594 38 80 00 00 */ li r4, 0
+/* 801D7938 001D3598 38 A0 00 40 */ li r5, 0x40
+/* 801D793C 001D359C 90 01 00 64 */ stw r0, 0x64(r1)
+/* 801D7940 001D35A0 93 E1 00 5C */ stw r31, 0x5c(r1)
+/* 801D7944 001D35A4 7C 7F 1B 78 */ mr r31, r3
+/* 801D7948 001D35A8 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D794C 001D35AC 4B E2 C7 E9 */ bl TRK_memset
+/* 801D7950 001D35B0 3C 60 80 42 */ lis r3, lbl_8042323C@ha
+/* 801D7954 001D35B4 38 A0 00 40 */ li r5, 0x40
+/* 801D7958 001D35B8 80 83 32 3C */ lwz r4, lbl_8042323C@l(r3)
+/* 801D795C 001D35BC 38 00 00 91 */ li r0, 0x91
+/* 801D7960 001D35C0 90 A1 00 0C */ stw r5, 0xc(r1)
+/* 801D7964 001D35C4 38 61 00 08 */ addi r3, r1, 8
+/* 801D7968 001D35C8 98 01 00 10 */ stb r0, 0x10(r1)
+/* 801D796C 001D35CC 90 81 00 14 */ stw r4, 0x14(r1)
+/* 801D7970 001D35D0 48 00 0E 7D */ bl TRKTargetReadInstruction
+/* 801D7974 001D35D4 3C 60 80 42 */ lis r3, lbl_8042323C@ha
+/* 801D7978 001D35D8 80 A1 00 08 */ lwz r5, 8(r1)
+/* 801D797C 001D35DC 38 83 32 3C */ addi r4, r3, lbl_8042323C@l
+/* 801D7980 001D35E0 7F E3 FB 78 */ mr r3, r31
+/* 801D7984 001D35E4 A0 04 00 08 */ lhz r0, 8(r4)
+/* 801D7988 001D35E8 38 81 00 0C */ addi r4, r1, 0xc
+/* 801D798C 001D35EC 90 A1 00 18 */ stw r5, 0x18(r1)
+/* 801D7990 001D35F0 38 A0 00 40 */ li r5, 0x40
+/* 801D7994 001D35F4 90 01 00 1C */ stw r0, 0x1c(r1)
+/* 801D7998 001D35F8 4B FF D6 DD */ bl TRKAppendBuffer_ui8
+/* 801D799C 001D35FC 80 01 00 64 */ lwz r0, 0x64(r1)
+/* 801D79A0 001D3600 83 E1 00 5C */ lwz r31, 0x5c(r1)
+/* 801D79A4 001D3604 7C 08 03 A6 */ mtlr r0
+/* 801D79A8 001D3608 38 21 00 60 */ addi r1, r1, 0x60
+/* 801D79AC 001D360C 4E 80 00 20 */ blr
+
+.global TRKTargetAddStopInfo
+TRKTargetAddStopInfo:
+/* 801D79B0 001D3610 94 21 FF A0 */ stwu r1, -0x60(r1)
+/* 801D79B4 001D3614 7C 08 02 A6 */ mflr r0
+/* 801D79B8 001D3618 38 80 00 00 */ li r4, 0
+/* 801D79BC 001D361C 38 A0 00 40 */ li r5, 0x40
+/* 801D79C0 001D3620 90 01 00 64 */ stw r0, 0x64(r1)
+/* 801D79C4 001D3624 93 E1 00 5C */ stw r31, 0x5c(r1)
+/* 801D79C8 001D3628 7C 7F 1B 78 */ mr r31, r3
+/* 801D79CC 001D362C 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D79D0 001D3630 4B E2 C7 65 */ bl TRK_memset
+/* 801D79D4 001D3634 3C 60 80 49 */ lis r3, lbl_80490898@ha
+/* 801D79D8 001D3638 38 A0 00 40 */ li r5, 0x40
+/* 801D79DC 001D363C 38 63 08 98 */ addi r3, r3, lbl_80490898@l
+/* 801D79E0 001D3640 38 00 00 90 */ li r0, 0x90
+/* 801D79E4 001D3644 80 83 00 80 */ lwz r4, 0x80(r3)
+/* 801D79E8 001D3648 38 61 00 08 */ addi r3, r1, 8
+/* 801D79EC 001D364C 90 A1 00 0C */ stw r5, 0xc(r1)
+/* 801D79F0 001D3650 98 01 00 10 */ stb r0, 0x10(r1)
+/* 801D79F4 001D3654 90 81 00 14 */ stw r4, 0x14(r1)
+/* 801D79F8 001D3658 48 00 0D F5 */ bl TRKTargetReadInstruction
+/* 801D79FC 001D365C 3C 60 80 49 */ lis r3, lbl_80490898@ha
+/* 801D7A00 001D3660 80 A1 00 08 */ lwz r5, 8(r1)
+/* 801D7A04 001D3664 38 83 08 98 */ addi r4, r3, lbl_80490898@l
+/* 801D7A08 001D3668 7F E3 FB 78 */ mr r3, r31
+/* 801D7A0C 001D366C 80 04 02 F8 */ lwz r0, 0x2f8(r4)
+/* 801D7A10 001D3670 38 81 00 0C */ addi r4, r1, 0xc
+/* 801D7A14 001D3674 90 A1 00 18 */ stw r5, 0x18(r1)
+/* 801D7A18 001D3678 38 A0 00 40 */ li r5, 0x40
+/* 801D7A1C 001D367C 54 00 04 3E */ clrlwi r0, r0, 0x10
+/* 801D7A20 001D3680 90 01 00 1C */ stw r0, 0x1c(r1)
+/* 801D7A24 001D3684 4B FF D6 51 */ bl TRKAppendBuffer_ui8
+/* 801D7A28 001D3688 80 01 00 64 */ lwz r0, 0x64(r1)
+/* 801D7A2C 001D368C 83 E1 00 5C */ lwz r31, 0x5c(r1)
+/* 801D7A30 001D3690 7C 08 03 A6 */ mtlr r0
+/* 801D7A34 001D3694 38 21 00 60 */ addi r1, r1, 0x60
+/* 801D7A38 001D3698 4E 80 00 20 */ blr
+
+.global TRKTargetInterrupt
+TRKTargetInterrupt:
+/* 801D7A3C 001D369C 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 801D7A40 001D36A0 7C 08 02 A6 */ mflr r0
+/* 801D7A44 001D36A4 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D7A48 001D36A8 80 03 00 00 */ lwz r0, 0(r3)
+/* 801D7A4C 001D36AC 38 60 00 00 */ li r3, 0
+/* 801D7A50 001D36B0 2C 00 00 05 */ cmpwi r0, 5
+/* 801D7A54 001D36B4 40 80 01 34 */ bge lbl_801D7B88
+/* 801D7A58 001D36B8 2C 00 00 03 */ cmpwi r0, 3
+/* 801D7A5C 001D36BC 40 80 00 08 */ bge lbl_801D7A64
+/* 801D7A60 001D36C0 48 00 01 28 */ b lbl_801D7B88
+lbl_801D7A64:
+/* 801D7A64 001D36C4 3C 80 80 42 */ lis r4, lbl_8042324C@ha
+/* 801D7A68 001D36C8 38 A4 32 4C */ addi r5, r4, lbl_8042324C@l
+/* 801D7A6C 001D36CC 80 05 00 00 */ lwz r0, 0(r5)
+/* 801D7A70 001D36D0 2C 00 00 00 */ cmpwi r0, 0
+/* 801D7A74 001D36D4 41 82 00 EC */ beq lbl_801D7B60
+/* 801D7A78 001D36D8 3C 80 80 49 */ lis r4, lbl_80490898@ha
+/* 801D7A7C 001D36DC 38 E0 00 01 */ li r7, 1
+/* 801D7A80 001D36E0 38 C4 08 98 */ addi r6, r4, lbl_80490898@l
+/* 801D7A84 001D36E4 80 06 01 F8 */ lwz r0, 0x1f8(r6)
+/* 801D7A88 001D36E8 54 00 05 A8 */ rlwinm r0, r0, 0, 0x16, 0x14
+/* 801D7A8C 001D36EC 90 06 01 F8 */ stw r0, 0x1f8(r6)
+/* 801D7A90 001D36F0 41 82 00 64 */ beq lbl_801D7AF4
+/* 801D7A94 001D36F4 80 06 02 F8 */ lwz r0, 0x2f8(r6)
+/* 801D7A98 001D36F8 54 00 04 3E */ clrlwi r0, r0, 0x10
+/* 801D7A9C 001D36FC 28 00 0D 00 */ cmplwi r0, 0xd00
+/* 801D7AA0 001D3700 40 82 00 54 */ bne lbl_801D7AF4
+/* 801D7AA4 001D3704 80 05 00 04 */ lwz r0, 4(r5)
+/* 801D7AA8 001D3708 2C 00 00 01 */ cmpwi r0, 1
+/* 801D7AAC 001D370C 41 82 00 28 */ beq lbl_801D7AD4
+/* 801D7AB0 001D3710 40 80 00 44 */ bge lbl_801D7AF4
+/* 801D7AB4 001D3714 2C 00 00 00 */ cmpwi r0, 0
+/* 801D7AB8 001D3718 40 80 00 08 */ bge lbl_801D7AC0
+/* 801D7ABC 001D371C 48 00 00 38 */ b lbl_801D7AF4
+lbl_801D7AC0:
+/* 801D7AC0 001D3720 80 05 00 08 */ lwz r0, 8(r5)
+/* 801D7AC4 001D3724 28 00 00 00 */ cmplwi r0, 0
+/* 801D7AC8 001D3728 41 82 00 2C */ beq lbl_801D7AF4
+/* 801D7ACC 001D372C 38 E0 00 00 */ li r7, 0
+/* 801D7AD0 001D3730 48 00 00 24 */ b lbl_801D7AF4
+lbl_801D7AD4:
+/* 801D7AD4 001D3734 80 86 00 80 */ lwz r4, 0x80(r6)
+/* 801D7AD8 001D3738 80 05 00 0C */ lwz r0, 0xc(r5)
+/* 801D7ADC 001D373C 7C 04 00 40 */ cmplw r4, r0
+/* 801D7AE0 001D3740 41 80 00 14 */ blt lbl_801D7AF4
+/* 801D7AE4 001D3744 80 05 00 10 */ lwz r0, 0x10(r5)
+/* 801D7AE8 001D3748 7C 04 00 40 */ cmplw r4, r0
+/* 801D7AEC 001D374C 41 81 00 08 */ bgt lbl_801D7AF4
+/* 801D7AF0 001D3750 38 E0 00 00 */ li r7, 0
+lbl_801D7AF4:
+/* 801D7AF4 001D3754 2C 07 00 00 */ cmpwi r7, 0
+/* 801D7AF8 001D3758 41 82 00 14 */ beq lbl_801D7B0C
+/* 801D7AFC 001D375C 3C 80 80 42 */ lis r4, lbl_8042324C@ha
+/* 801D7B00 001D3760 38 00 00 00 */ li r0, 0
+/* 801D7B04 001D3764 90 04 32 4C */ stw r0, lbl_8042324C@l(r4)
+/* 801D7B08 001D3768 48 00 00 58 */ b lbl_801D7B60
+lbl_801D7B0C:
+/* 801D7B0C 001D376C 3C 80 80 42 */ lis r4, lbl_8042324C@ha
+/* 801D7B10 001D3770 80 06 01 F8 */ lwz r0, 0x1f8(r6)
+/* 801D7B14 001D3774 38 84 32 4C */ addi r4, r4, lbl_8042324C@l
+/* 801D7B18 001D3778 38 A0 00 01 */ li r5, 1
+/* 801D7B1C 001D377C 80 E4 00 04 */ lwz r7, 4(r4)
+/* 801D7B20 001D3780 60 00 04 00 */ ori r0, r0, 0x400
+/* 801D7B24 001D3784 90 A4 00 00 */ stw r5, 0(r4)
+/* 801D7B28 001D3788 2C 07 00 00 */ cmpwi r7, 0
+/* 801D7B2C 001D378C 90 06 01 F8 */ stw r0, 0x1f8(r6)
+/* 801D7B30 001D3790 41 82 00 0C */ beq lbl_801D7B3C
+/* 801D7B34 001D3794 2C 07 00 10 */ cmpwi r7, 0x10
+/* 801D7B38 001D3798 40 82 00 18 */ bne lbl_801D7B50
+lbl_801D7B3C:
+/* 801D7B3C 001D379C 3C 80 80 42 */ lis r4, lbl_8042324C@ha
+/* 801D7B40 001D37A0 38 A4 32 4C */ addi r5, r4, lbl_8042324C@l
+/* 801D7B44 001D37A4 80 85 00 08 */ lwz r4, 8(r5)
+/* 801D7B48 001D37A8 38 04 FF FF */ addi r0, r4, -1
+/* 801D7B4C 001D37AC 90 05 00 08 */ stw r0, 8(r5)
+lbl_801D7B50:
+/* 801D7B50 001D37B0 3C 80 80 49 */ lis r4, lbl_804907F4@ha
+/* 801D7B54 001D37B4 38 00 00 00 */ li r0, 0
+/* 801D7B58 001D37B8 38 84 07 F4 */ addi r4, r4, lbl_804907F4@l
+/* 801D7B5C 001D37BC 90 04 00 98 */ stw r0, 0x98(r4)
+lbl_801D7B60:
+/* 801D7B60 001D37C0 3C 80 80 42 */ lis r4, lbl_8042324C@ha
+/* 801D7B64 001D37C4 80 04 32 4C */ lwz r0, lbl_8042324C@l(r4)
+/* 801D7B68 001D37C8 2C 00 00 00 */ cmpwi r0, 0
+/* 801D7B6C 001D37CC 40 82 00 1C */ bne lbl_801D7B88
+/* 801D7B70 001D37D0 3C 60 80 49 */ lis r3, lbl_804907F4@ha
+/* 801D7B74 001D37D4 38 00 00 01 */ li r0, 1
+/* 801D7B78 001D37D8 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l
+/* 801D7B7C 001D37DC 38 60 00 90 */ li r3, 0x90
+/* 801D7B80 001D37E0 90 04 00 98 */ stw r0, 0x98(r4)
+/* 801D7B84 001D37E4 4B FF F4 E9 */ bl TRKDoNotifyStopped
+lbl_801D7B88:
+/* 801D7B88 001D37E8 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D7B8C 001D37EC 7C 08 03 A6 */ mtlr r0
+/* 801D7B90 001D37F0 38 21 00 10 */ addi r1, r1, 0x10
+/* 801D7B94 001D37F4 4E 80 00 20 */ blr
+
+.global TRKPostInterruptEvent
+TRKPostInterruptEvent:
+/* 801D7B98 001D37F8 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D7B9C 001D37FC 7C 08 02 A6 */ mflr r0
+/* 801D7BA0 001D3800 3C 60 80 49 */ lis r3, lbl_804907F4@ha
+/* 801D7BA4 001D3804 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D7BA8 001D3808 38 63 07 F4 */ addi r3, r3, lbl_804907F4@l
+/* 801D7BAC 001D380C 80 03 00 9C */ lwz r0, 0x9c(r3)
+/* 801D7BB0 001D3810 2C 00 00 00 */ cmpwi r0, 0
+/* 801D7BB4 001D3814 41 82 00 10 */ beq lbl_801D7BC4
+/* 801D7BB8 001D3818 38 00 00 00 */ li r0, 0
+/* 801D7BBC 001D381C 90 03 00 9C */ stw r0, 0x9c(r3)
+/* 801D7BC0 001D3820 48 00 00 74 */ b lbl_801D7C34
+lbl_801D7BC4:
+/* 801D7BC4 001D3824 3C 60 80 49 */ lis r3, lbl_80490898@ha
+/* 801D7BC8 001D3828 38 63 08 98 */ addi r3, r3, lbl_80490898@l
+/* 801D7BCC 001D382C 80 03 02 F8 */ lwz r0, 0x2f8(r3)
+/* 801D7BD0 001D3830 54 00 04 3E */ clrlwi r0, r0, 0x10
+/* 801D7BD4 001D3834 2C 00 0D 00 */ cmpwi r0, 0xd00
+/* 801D7BD8 001D3838 41 82 00 14 */ beq lbl_801D7BEC
+/* 801D7BDC 001D383C 40 80 00 44 */ bge lbl_801D7C20
+/* 801D7BE0 001D3840 2C 00 07 00 */ cmpwi r0, 0x700
+/* 801D7BE4 001D3844 41 82 00 08 */ beq lbl_801D7BEC
+/* 801D7BE8 001D3848 48 00 00 38 */ b lbl_801D7C20
+lbl_801D7BEC:
+/* 801D7BEC 001D384C 3C 80 80 49 */ lis r4, lbl_80490898@ha
+/* 801D7BF0 001D3850 38 61 00 08 */ addi r3, r1, 8
+/* 801D7BF4 001D3854 38 84 08 98 */ addi r4, r4, lbl_80490898@l
+/* 801D7BF8 001D3858 80 84 00 80 */ lwz r4, 0x80(r4)
+/* 801D7BFC 001D385C 48 00 0B F1 */ bl TRKTargetReadInstruction
+/* 801D7C00 001D3860 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D7C04 001D3864 3C 03 F0 20 */ addis r0, r3, 0xf020
+/* 801D7C08 001D3868 28 00 00 00 */ cmplwi r0, 0
+/* 801D7C0C 001D386C 40 82 00 0C */ bne lbl_801D7C18
+/* 801D7C10 001D3870 38 80 00 05 */ li r4, 5
+/* 801D7C14 001D3874 48 00 00 10 */ b lbl_801D7C24
+lbl_801D7C18:
+/* 801D7C18 001D3878 38 80 00 03 */ li r4, 3
+/* 801D7C1C 001D387C 48 00 00 08 */ b lbl_801D7C24
+lbl_801D7C20:
+/* 801D7C20 001D3880 38 80 00 04 */ li r4, 4
+lbl_801D7C24:
+/* 801D7C24 001D3884 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D7C28 001D3888 4B FF CD 2D */ bl TRKConstructEvent
+/* 801D7C2C 001D388C 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D7C30 001D3890 4B FF CD 3D */ bl TRKPostEvent
+lbl_801D7C34:
+/* 801D7C34 001D3894 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D7C38 001D3898 7C 08 03 A6 */ mtlr r0
+/* 801D7C3C 001D389C 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D7C40 001D38A0 4E 80 00 20 */ blr
+
+.global TRKTargetAccessExtended2
+TRKTargetAccessExtended2:
+/* 801D7C44 001D38A4 94 21 FE D0 */ stwu r1, -0x130(r1)
+/* 801D7C48 001D38A8 7C 08 02 A6 */ mflr r0
+/* 801D7C4C 001D38AC 90 01 01 34 */ stw r0, 0x134(r1)
+/* 801D7C50 001D38B0 BE 61 00 FC */ stmw r19, 0xfc(r1)
+/* 801D7C54 001D38B4 7C 97 23 78 */ mr r23, r4
+/* 801D7C58 001D38B8 28 17 00 1F */ cmplwi r23, 0x1f
+/* 801D7C5C 001D38BC 7C 7B 1B 78 */ mr r27, r3
+/* 801D7C60 001D38C0 7C B8 2B 78 */ mr r24, r5
+/* 801D7C64 001D38C4 7C D9 33 78 */ mr r25, r6
+/* 801D7C68 001D38C8 7C FA 3B 78 */ mr r26, r7
+/* 801D7C6C 001D38CC 40 81 00 0C */ ble lbl_801D7C78
+/* 801D7C70 001D38D0 38 60 07 01 */ li r3, 0x701
+/* 801D7C74 001D38D4 48 00 03 F4 */ b lbl_801D8068
+lbl_801D7C78:
+/* 801D7C78 001D38D8 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha
+/* 801D7C7C 001D38DC 3C A0 80 42 */ lis r5, lbl_8042323C@ha
+/* 801D7C80 001D38E0 3B A3 D6 C8 */ addi r29, r3, lbl_803FD6C8@l
+/* 801D7C84 001D38E4 3C 80 7C 99 */ lis r4, 0x7C98E2A6@ha
+/* 801D7C88 001D38E8 80 1D 00 00 */ lwz r0, 0(r29)
+/* 801D7C8C 001D38EC 3B E5 32 3C */ addi r31, r5, lbl_8042323C@l
+/* 801D7C90 001D38F0 81 1D 00 04 */ lwz r8, 4(r29)
+/* 801D7C94 001D38F4 3C 60 4E 80 */ lis r3, 0x4E800020@ha
+/* 801D7C98 001D38F8 80 FD 00 24 */ lwz r7, 0x24(r29)
+/* 801D7C9C 001D38FC 38 C4 E2 A6 */ addi r6, r4, 0x7C98E2A6@l
+/* 801D7CA0 001D3900 90 01 00 C4 */ stw r0, 0xc4(r1)
+/* 801D7CA4 001D3904 38 03 00 20 */ addi r0, r3, 0x4E800020@l
+/* 801D7CA8 001D3908 82 7F 00 00 */ lwz r19, 0(r31)
+/* 801D7CAC 001D390C 3B C0 00 00 */ li r30, 0
+/* 801D7CB0 001D3910 82 DF 00 0C */ lwz r22, 0xc(r31)
+/* 801D7CB4 001D3914 3C A0 90 83 */ lis r5, 0x9083
+/* 801D7CB8 001D3918 91 01 00 C8 */ stw r8, 0xc8(r1)
+/* 801D7CBC 001D391C 38 61 00 C4 */ addi r3, r1, 0xc4
+/* 801D7CC0 001D3920 82 9F 00 04 */ lwz r20, 4(r31)
+/* 801D7CC4 001D3924 38 80 00 28 */ li r4, 0x28
+/* 801D7CC8 001D3928 90 E1 00 E8 */ stw r7, 0xe8(r1)
+/* 801D7CCC 001D392C 82 BF 00 08 */ lwz r21, 8(r31)
+/* 801D7CD0 001D3930 83 9D 00 08 */ lwz r28, 8(r29)
+/* 801D7CD4 001D3934 81 9D 00 0C */ lwz r12, 0xc(r29)
+/* 801D7CD8 001D3938 81 7D 00 10 */ lwz r11, 0x10(r29)
+/* 801D7CDC 001D393C 81 5D 00 14 */ lwz r10, 0x14(r29)
+/* 801D7CE0 001D3940 81 3D 00 18 */ lwz r9, 0x18(r29)
+/* 801D7CE4 001D3944 81 1D 00 1C */ lwz r8, 0x1c(r29)
+/* 801D7CE8 001D3948 80 FD 00 20 */ lwz r7, 0x20(r29)
+/* 801D7CEC 001D394C 92 61 00 14 */ stw r19, 0x14(r1)
+/* 801D7CF0 001D3950 92 81 00 18 */ stw r20, 0x18(r1)
+/* 801D7CF4 001D3954 92 A1 00 1C */ stw r21, 0x1c(r1)
+/* 801D7CF8 001D3958 92 C1 00 20 */ stw r22, 0x20(r1)
+/* 801D7CFC 001D395C 9B DF 00 0D */ stb r30, 0xd(r31)
+/* 801D7D00 001D3960 93 81 00 CC */ stw r28, 0xcc(r1)
+/* 801D7D04 001D3964 91 81 00 D0 */ stw r12, 0xd0(r1)
+/* 801D7D08 001D3968 91 61 00 D4 */ stw r11, 0xd4(r1)
+/* 801D7D0C 001D396C 91 41 00 D8 */ stw r10, 0xd8(r1)
+/* 801D7D10 001D3970 91 21 00 DC */ stw r9, 0xdc(r1)
+/* 801D7D14 001D3974 91 01 00 E0 */ stw r8, 0xe0(r1)
+/* 801D7D18 001D3978 90 E1 00 E4 */ stw r7, 0xe4(r1)
+/* 801D7D1C 001D397C 90 C1 00 C4 */ stw r6, 0xc4(r1)
+/* 801D7D20 001D3980 90 A1 00 C8 */ stw r5, 0xc8(r1)
+/* 801D7D24 001D3984 90 01 00 E8 */ stw r0, 0xe8(r1)
+/* 801D7D28 001D3988 4B FF F3 DD */ bl TRK_flush_cache
+/* 801D7D2C 001D398C 3C 60 80 49 */ lis r3, lbl_80490D5C@ha
+/* 801D7D30 001D3990 39 81 00 C4 */ addi r12, r1, 0xc4
+/* 801D7D34 001D3994 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l
+/* 801D7D38 001D3998 38 61 00 08 */ addi r3, r1, 8
+/* 801D7D3C 001D399C 7D 89 03 A6 */ mtctr r12
+/* 801D7D40 001D39A0 4E 80 04 21 */ bctrl
+/* 801D7D44 001D39A4 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha
+/* 801D7D48 001D39A8 80 A1 00 08 */ lwz r5, 8(r1)
+/* 801D7D4C 001D39AC 3B A3 D6 C8 */ addi r29, r3, lbl_803FD6C8@l
+/* 801D7D50 001D39B0 3C 80 7C 99 */ lis r4, 0x7C98E3A6@ha
+/* 801D7D54 001D39B4 81 1D 00 00 */ lwz r8, 0(r29)
+/* 801D7D58 001D39B8 3C 60 4E 80 */ lis r3, 0x4E800020@ha
+/* 801D7D5C 001D39BC 80 1D 00 04 */ lwz r0, 4(r29)
+/* 801D7D60 001D39C0 64 BE A0 00 */ oris r30, r5, 0xa000
+/* 801D7D64 001D39C4 80 FD 00 24 */ lwz r7, 0x24(r29)
+/* 801D7D68 001D39C8 38 A4 E3 A6 */ addi r5, r4, 0x7C98E3A6@l
+/* 801D7D6C 001D39CC 90 01 00 A0 */ stw r0, 0xa0(r1)
+/* 801D7D70 001D39D0 38 03 00 20 */ addi r0, r3, 0x4E800020@l
+/* 801D7D74 001D39D4 83 9D 00 08 */ lwz r28, 8(r29)
+/* 801D7D78 001D39D8 3C C0 80 83 */ lis r6, 0x8083
+/* 801D7D7C 001D39DC 91 01 00 9C */ stw r8, 0x9c(r1)
+/* 801D7D80 001D39E0 38 61 00 9C */ addi r3, r1, 0x9c
+/* 801D7D84 001D39E4 81 9D 00 0C */ lwz r12, 0xc(r29)
+/* 801D7D88 001D39E8 38 80 00 28 */ li r4, 0x28
+/* 801D7D8C 001D39EC 90 E1 00 C0 */ stw r7, 0xc0(r1)
+/* 801D7D90 001D39F0 81 7D 00 10 */ lwz r11, 0x10(r29)
+/* 801D7D94 001D39F4 81 5D 00 14 */ lwz r10, 0x14(r29)
+/* 801D7D98 001D39F8 81 3D 00 18 */ lwz r9, 0x18(r29)
+/* 801D7D9C 001D39FC 81 1D 00 1C */ lwz r8, 0x1c(r29)
+/* 801D7DA0 001D3A00 80 FD 00 20 */ lwz r7, 0x20(r29)
+/* 801D7DA4 001D3A04 93 C1 00 08 */ stw r30, 8(r1)
+/* 801D7DA8 001D3A08 93 81 00 A4 */ stw r28, 0xa4(r1)
+/* 801D7DAC 001D3A0C 91 81 00 A8 */ stw r12, 0xa8(r1)
+/* 801D7DB0 001D3A10 91 61 00 AC */ stw r11, 0xac(r1)
+/* 801D7DB4 001D3A14 91 41 00 B0 */ stw r10, 0xb0(r1)
+/* 801D7DB8 001D3A18 91 21 00 B4 */ stw r9, 0xb4(r1)
+/* 801D7DBC 001D3A1C 91 01 00 B8 */ stw r8, 0xb8(r1)
+/* 801D7DC0 001D3A20 90 E1 00 BC */ stw r7, 0xbc(r1)
+/* 801D7DC4 001D3A24 90 C1 00 9C */ stw r6, 0x9c(r1)
+/* 801D7DC8 001D3A28 90 A1 00 A0 */ stw r5, 0xa0(r1)
+/* 801D7DCC 001D3A2C 90 01 00 C0 */ stw r0, 0xc0(r1)
+/* 801D7DD0 001D3A30 4B FF F3 35 */ bl TRK_flush_cache
+/* 801D7DD4 001D3A34 3C 60 80 49 */ lis r3, lbl_80490D5C@ha
+/* 801D7DD8 001D3A38 39 81 00 9C */ addi r12, r1, 0x9c
+/* 801D7DDC 001D3A3C 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l
+/* 801D7DE0 001D3A40 38 61 00 08 */ addi r3, r1, 8
+/* 801D7DE4 001D3A44 7D 89 03 A6 */ mtctr r12
+/* 801D7DE8 001D3A48 4E 80 04 21 */ bctrl
+/* 801D7DEC 001D3A4C 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha
+/* 801D7DF0 001D3A50 3C 80 7C 91 */ lis r4, 0x7C90E3A6@ha
+/* 801D7DF4 001D3A54 3B A3 D6 C8 */ addi r29, r3, lbl_803FD6C8@l
+/* 801D7DF8 001D3A58 3C 60 4E 80 */ lis r3, 0x4E800020@ha
+/* 801D7DFC 001D3A5C 81 1D 00 00 */ lwz r8, 0(r29)
+/* 801D7E00 001D3A60 3B C0 00 00 */ li r30, 0
+/* 801D7E04 001D3A64 80 DD 00 04 */ lwz r6, 4(r29)
+/* 801D7E08 001D3A68 38 A4 E3 A6 */ addi r5, r4, 0x7C90E3A6@l
+/* 801D7E0C 001D3A6C 80 FD 00 24 */ lwz r7, 0x24(r29)
+/* 801D7E10 001D3A70 38 03 00 20 */ addi r0, r3, 0x4E800020@l
+/* 801D7E14 001D3A74 90 C1 00 78 */ stw r6, 0x78(r1)
+/* 801D7E18 001D3A78 3C C0 80 83 */ lis r6, 0x8083
+/* 801D7E1C 001D3A7C 83 9D 00 08 */ lwz r28, 8(r29)
+/* 801D7E20 001D3A80 38 61 00 74 */ addi r3, r1, 0x74
+/* 801D7E24 001D3A84 91 01 00 74 */ stw r8, 0x74(r1)
+/* 801D7E28 001D3A88 38 80 00 28 */ li r4, 0x28
+/* 801D7E2C 001D3A8C 81 9D 00 0C */ lwz r12, 0xc(r29)
+/* 801D7E30 001D3A90 90 E1 00 98 */ stw r7, 0x98(r1)
+/* 801D7E34 001D3A94 81 7D 00 10 */ lwz r11, 0x10(r29)
+/* 801D7E38 001D3A98 81 5D 00 14 */ lwz r10, 0x14(r29)
+/* 801D7E3C 001D3A9C 81 3D 00 18 */ lwz r9, 0x18(r29)
+/* 801D7E40 001D3AA0 81 1D 00 1C */ lwz r8, 0x1c(r29)
+/* 801D7E44 001D3AA4 80 FD 00 20 */ lwz r7, 0x20(r29)
+/* 801D7E48 001D3AA8 93 C1 00 08 */ stw r30, 8(r1)
+/* 801D7E4C 001D3AAC 93 81 00 7C */ stw r28, 0x7c(r1)
+/* 801D7E50 001D3AB0 91 81 00 80 */ stw r12, 0x80(r1)
+/* 801D7E54 001D3AB4 91 61 00 84 */ stw r11, 0x84(r1)
+/* 801D7E58 001D3AB8 91 41 00 88 */ stw r10, 0x88(r1)
+/* 801D7E5C 001D3ABC 91 21 00 8C */ stw r9, 0x8c(r1)
+/* 801D7E60 001D3AC0 91 01 00 90 */ stw r8, 0x90(r1)
+/* 801D7E64 001D3AC4 90 E1 00 94 */ stw r7, 0x94(r1)
+/* 801D7E68 001D3AC8 90 C1 00 74 */ stw r6, 0x74(r1)
+/* 801D7E6C 001D3ACC 90 A1 00 78 */ stw r5, 0x78(r1)
+/* 801D7E70 001D3AD0 90 01 00 98 */ stw r0, 0x98(r1)
+/* 801D7E74 001D3AD4 4B FF F2 91 */ bl TRK_flush_cache
+/* 801D7E78 001D3AD8 3C 60 80 49 */ lis r3, lbl_80490D5C@ha
+/* 801D7E7C 001D3ADC 39 81 00 74 */ addi r12, r1, 0x74
+/* 801D7E80 001D3AE0 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l
+/* 801D7E84 001D3AE4 38 61 00 08 */ addi r3, r1, 8
+/* 801D7E88 001D3AE8 7D 89 03 A6 */ mtctr r12
+/* 801D7E8C 001D3AEC 4E 80 04 21 */ bctrl
+/* 801D7E90 001D3AF0 38 00 00 00 */ li r0, 0
+/* 801D7E94 001D3AF4 57 7E A8 14 */ slwi r30, r27, 0x15
+/* 801D7E98 001D3AF8 90 19 00 00 */ stw r0, 0(r25)
+/* 801D7E9C 001D3AFC 3B A1 00 4C */ addi r29, r1, 0x4c
+/* 801D7EA0 001D3B00 3B 81 00 24 */ addi r28, r1, 0x24
+/* 801D7EA4 001D3B04 38 60 00 00 */ li r3, 0
+/* 801D7EA8 001D3B08 48 00 01 70 */ b lbl_801D8018
+lbl_801D7EAC:
+/* 801D7EAC 001D3B0C 2C 1A 00 00 */ cmpwi r26, 0
+/* 801D7EB0 001D3B10 41 82 00 AC */ beq lbl_801D7F5C
+/* 801D7EB4 001D3B14 3C 60 80 40 */ lis r3, lbl_80400004@ha
+/* 801D7EB8 001D3B18 85 83 D6 F0 */ lwzu r12, -0x2910(r3)
+/* 801D7EBC 001D3B1C 67 C0 E0 03 */ oris r0, r30, 0xe003
+/* 801D7EC0 001D3B20 81 63 00 04 */ lwz r11, lbl_80400004@l(r3)
+/* 801D7EC4 001D3B24 81 43 00 08 */ lwz r10, 8(r3)
+/* 801D7EC8 001D3B28 81 23 00 0C */ lwz r9, 0xc(r3)
+/* 801D7ECC 001D3B2C 81 03 00 10 */ lwz r8, 0x10(r3)
+/* 801D7ED0 001D3B30 80 E3 00 14 */ lwz r7, 0x14(r3)
+/* 801D7ED4 001D3B34 80 C3 00 18 */ lwz r6, 0x18(r3)
+/* 801D7ED8 001D3B38 80 A3 00 1C */ lwz r5, 0x1c(r3)
+/* 801D7EDC 001D3B3C 80 83 00 20 */ lwz r4, 0x20(r3)
+/* 801D7EE0 001D3B40 80 63 00 24 */ lwz r3, 0x24(r3)
+/* 801D7EE4 001D3B44 91 81 00 4C */ stw r12, 0x4c(r1)
+/* 801D7EE8 001D3B48 91 61 00 50 */ stw r11, 0x50(r1)
+/* 801D7EEC 001D3B4C 91 41 00 54 */ stw r10, 0x54(r1)
+/* 801D7EF0 001D3B50 91 21 00 58 */ stw r9, 0x58(r1)
+/* 801D7EF4 001D3B54 91 01 00 5C */ stw r8, 0x5c(r1)
+/* 801D7EF8 001D3B58 90 E1 00 60 */ stw r7, 0x60(r1)
+/* 801D7EFC 001D3B5C 90 C1 00 64 */ stw r6, 0x64(r1)
+/* 801D7F00 001D3B60 90 A1 00 68 */ stw r5, 0x68(r1)
+/* 801D7F04 001D3B64 90 81 00 6C */ stw r4, 0x6c(r1)
+/* 801D7F08 001D3B68 90 61 00 70 */ stw r3, 0x70(r1)
+/* 801D7F0C 001D3B6C 41 82 00 08 */ beq lbl_801D7F14
+/* 801D7F10 001D3B70 67 C0 F0 03 */ oris r0, r30, 0xf003
+lbl_801D7F14:
+/* 801D7F14 001D3B74 3C 60 4E 80 */ lis r3, 0x4E800020@ha
+/* 801D7F18 001D3B78 90 01 00 4C */ stw r0, 0x4c(r1)
+/* 801D7F1C 001D3B7C 38 03 00 20 */ addi r0, r3, 0x4E800020@l
+/* 801D7F20 001D3B80 7F A3 EB 78 */ mr r3, r29
+/* 801D7F24 001D3B84 90 01 00 70 */ stw r0, 0x70(r1)
+/* 801D7F28 001D3B88 38 80 00 28 */ li r4, 0x28
+/* 801D7F2C 001D3B8C 4B FF F1 D9 */ bl TRK_flush_cache
+/* 801D7F30 001D3B90 3C 60 80 49 */ lis r3, lbl_80490D5C@ha
+/* 801D7F34 001D3B94 39 81 00 4C */ addi r12, r1, 0x4c
+/* 801D7F38 001D3B98 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l
+/* 801D7F3C 001D3B9C 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D7F40 001D3BA0 7D 89 03 A6 */ mtctr r12
+/* 801D7F44 001D3BA4 4E 80 04 21 */ bctrl
+/* 801D7F48 001D3BA8 80 A1 00 0C */ lwz r5, 0xc(r1)
+/* 801D7F4C 001D3BAC 7F 03 C3 78 */ mr r3, r24
+/* 801D7F50 001D3BB0 80 C1 00 10 */ lwz r6, 0x10(r1)
+/* 801D7F54 001D3BB4 4B FF D1 89 */ bl TRKAppendBuffer1_ui64
+/* 801D7F58 001D3BB8 48 00 00 AC */ b lbl_801D8004
+lbl_801D7F5C:
+/* 801D7F5C 001D3BBC 7F 03 C3 78 */ mr r3, r24
+/* 801D7F60 001D3BC0 38 81 00 0C */ addi r4, r1, 0xc
+/* 801D7F64 001D3BC4 4B FF CF 2D */ bl TRKReadBuffer1_ui64
+/* 801D7F68 001D3BC8 3C 60 80 40 */ lis r3, lbl_80400004@ha
+/* 801D7F6C 001D3BCC 85 83 D6 F0 */ lwzu r12, -0x2910(r3)
+/* 801D7F70 001D3BD0 2C 1A 00 00 */ cmpwi r26, 0
+/* 801D7F74 001D3BD4 67 C0 E0 03 */ oris r0, r30, 0xe003
+/* 801D7F78 001D3BD8 81 63 00 04 */ lwz r11, lbl_80400004@l(r3)
+/* 801D7F7C 001D3BDC 81 43 00 08 */ lwz r10, 8(r3)
+/* 801D7F80 001D3BE0 81 23 00 0C */ lwz r9, 0xc(r3)
+/* 801D7F84 001D3BE4 81 03 00 10 */ lwz r8, 0x10(r3)
+/* 801D7F88 001D3BE8 80 E3 00 14 */ lwz r7, 0x14(r3)
+/* 801D7F8C 001D3BEC 80 C3 00 18 */ lwz r6, 0x18(r3)
+/* 801D7F90 001D3BF0 80 A3 00 1C */ lwz r5, 0x1c(r3)
+/* 801D7F94 001D3BF4 80 83 00 20 */ lwz r4, 0x20(r3)
+/* 801D7F98 001D3BF8 80 63 00 24 */ lwz r3, 0x24(r3)
+/* 801D7F9C 001D3BFC 91 81 00 24 */ stw r12, 0x24(r1)
+/* 801D7FA0 001D3C00 91 61 00 28 */ stw r11, 0x28(r1)
+/* 801D7FA4 001D3C04 91 41 00 2C */ stw r10, 0x2c(r1)
+/* 801D7FA8 001D3C08 91 21 00 30 */ stw r9, 0x30(r1)
+/* 801D7FAC 001D3C0C 91 01 00 34 */ stw r8, 0x34(r1)
+/* 801D7FB0 001D3C10 90 E1 00 38 */ stw r7, 0x38(r1)
+/* 801D7FB4 001D3C14 90 C1 00 3C */ stw r6, 0x3c(r1)
+/* 801D7FB8 001D3C18 90 A1 00 40 */ stw r5, 0x40(r1)
+/* 801D7FBC 001D3C1C 90 81 00 44 */ stw r4, 0x44(r1)
+/* 801D7FC0 001D3C20 90 61 00 48 */ stw r3, 0x48(r1)
+/* 801D7FC4 001D3C24 41 82 00 08 */ beq lbl_801D7FCC
+/* 801D7FC8 001D3C28 67 C0 F0 03 */ oris r0, r30, 0xf003
+lbl_801D7FCC:
+/* 801D7FCC 001D3C2C 3C 60 4E 80 */ lis r3, 0x4E800020@ha
+/* 801D7FD0 001D3C30 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D7FD4 001D3C34 38 03 00 20 */ addi r0, r3, 0x4E800020@l
+/* 801D7FD8 001D3C38 7F 83 E3 78 */ mr r3, r28
+/* 801D7FDC 001D3C3C 90 01 00 48 */ stw r0, 0x48(r1)
+/* 801D7FE0 001D3C40 38 80 00 28 */ li r4, 0x28
+/* 801D7FE4 001D3C44 4B FF F1 21 */ bl TRK_flush_cache
+/* 801D7FE8 001D3C48 3C 60 80 49 */ lis r3, lbl_80490D5C@ha
+/* 801D7FEC 001D3C4C 39 81 00 24 */ addi r12, r1, 0x24
+/* 801D7FF0 001D3C50 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l
+/* 801D7FF4 001D3C54 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D7FF8 001D3C58 7D 89 03 A6 */ mtctr r12
+/* 801D7FFC 001D3C5C 4E 80 04 21 */ bctrl
+/* 801D8000 001D3C60 38 60 00 00 */ li r3, 0
+lbl_801D8004:
+/* 801D8004 001D3C64 80 99 00 00 */ lwz r4, 0(r25)
+/* 801D8008 001D3C68 3F DE 00 20 */ addis r30, r30, 0x20
+/* 801D800C 001D3C6C 3B 7B 00 01 */ addi r27, r27, 1
+/* 801D8010 001D3C70 38 04 00 08 */ addi r0, r4, 8
+/* 801D8014 001D3C74 90 19 00 00 */ stw r0, 0(r25)
+lbl_801D8018:
+/* 801D8018 001D3C78 7C 1B B8 40 */ cmplw r27, r23
+/* 801D801C 001D3C7C 41 81 00 0C */ bgt lbl_801D8028
+/* 801D8020 001D3C80 2C 03 00 00 */ cmpwi r3, 0
+/* 801D8024 001D3C84 41 82 FE 88 */ beq lbl_801D7EAC
+lbl_801D8028:
+/* 801D8028 001D3C88 88 1F 00 0D */ lbz r0, 0xd(r31)
+/* 801D802C 001D3C8C 28 00 00 00 */ cmplwi r0, 0
+/* 801D8030 001D3C90 41 82 00 10 */ beq lbl_801D8040
+/* 801D8034 001D3C94 38 00 00 00 */ li r0, 0
+/* 801D8038 001D3C98 38 60 07 02 */ li r3, 0x702
+/* 801D803C 001D3C9C 90 19 00 00 */ stw r0, 0(r25)
+lbl_801D8040:
+/* 801D8040 001D3CA0 3C 80 80 42 */ lis r4, lbl_8042323C@ha
+/* 801D8044 001D3CA4 80 C1 00 14 */ lwz r6, 0x14(r1)
+/* 801D8048 001D3CA8 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l
+/* 801D804C 001D3CAC 80 A1 00 18 */ lwz r5, 0x18(r1)
+/* 801D8050 001D3CB0 80 81 00 1C */ lwz r4, 0x1c(r1)
+/* 801D8054 001D3CB4 80 01 00 20 */ lwz r0, 0x20(r1)
+/* 801D8058 001D3CB8 90 C7 00 00 */ stw r6, 0(r7)
+/* 801D805C 001D3CBC 90 A7 00 04 */ stw r5, 4(r7)
+/* 801D8060 001D3CC0 90 87 00 08 */ stw r4, 8(r7)
+/* 801D8064 001D3CC4 90 07 00 0C */ stw r0, 0xc(r7)
+lbl_801D8068:
+/* 801D8068 001D3CC8 BA 61 00 FC */ lmw r19, 0xfc(r1)
+/* 801D806C 001D3CCC 80 01 01 34 */ lwz r0, 0x134(r1)
+/* 801D8070 001D3CD0 7C 08 03 A6 */ mtlr r0
+/* 801D8074 001D3CD4 38 21 01 30 */ addi r1, r1, 0x130
+/* 801D8078 001D3CD8 4E 80 00 20 */ blr
+
+.global TRKTargetAccessExtended1
+TRKTargetAccessExtended1:
+/* 801D807C 001D3CDC 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D8080 001D3CE0 7C 08 02 A6 */ mflr r0
+/* 801D8084 001D3CE4 28 04 00 60 */ cmplwi r4, 0x60
+/* 801D8088 001D3CE8 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D808C 001D3CEC 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D8090 001D3CF0 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D8094 001D3CF4 7C DE 33 78 */ mr r30, r6
+/* 801D8098 001D3CF8 40 81 00 0C */ ble lbl_801D80A4
+/* 801D809C 001D3CFC 38 60 07 01 */ li r3, 0x701
+/* 801D80A0 001D3D00 48 00 01 34 */ b lbl_801D81D4
+lbl_801D80A4:
+/* 801D80A4 001D3D04 3C C0 80 42 */ lis r6, lbl_8042323C@ha
+/* 801D80A8 001D3D08 38 00 00 00 */ li r0, 0
+/* 801D80AC 001D3D0C 3B E6 32 3C */ addi r31, r6, lbl_8042323C@l
+/* 801D80B0 001D3D10 7C 03 20 40 */ cmplw r3, r4
+/* 801D80B4 001D3D14 80 DF 00 0C */ lwz r6, 0xc(r31)
+/* 801D80B8 001D3D18 81 5F 00 00 */ lwz r10, 0(r31)
+/* 801D80BC 001D3D1C 81 3F 00 04 */ lwz r9, 4(r31)
+/* 801D80C0 001D3D20 81 1F 00 08 */ lwz r8, 8(r31)
+/* 801D80C4 001D3D24 98 1F 00 0D */ stb r0, 0xd(r31)
+/* 801D80C8 001D3D28 91 41 00 08 */ stw r10, 8(r1)
+/* 801D80CC 001D3D2C 91 21 00 0C */ stw r9, 0xc(r1)
+/* 801D80D0 001D3D30 91 01 00 10 */ stw r8, 0x10(r1)
+/* 801D80D4 001D3D34 90 C1 00 14 */ stw r6, 0x14(r1)
+/* 801D80D8 001D3D38 90 1E 00 00 */ stw r0, 0(r30)
+/* 801D80DC 001D3D3C 41 81 00 B8 */ bgt lbl_801D8194
+/* 801D80E0 001D3D40 7C 83 20 50 */ subf r4, r3, r4
+/* 801D80E4 001D3D44 3D 00 80 49 */ lis r8, lbl_80490898@ha
+/* 801D80E8 001D3D48 38 04 00 01 */ addi r0, r4, 1
+/* 801D80EC 001D3D4C 80 9E 00 00 */ lwz r4, 0(r30)
+/* 801D80F0 001D3D50 54 06 10 3A */ slwi r6, r0, 2
+/* 801D80F4 001D3D54 2C 07 00 00 */ cmpwi r7, 0
+/* 801D80F8 001D3D58 7C 84 32 14 */ add r4, r4, r6
+/* 801D80FC 001D3D5C 38 E8 08 98 */ addi r7, r8, lbl_80490898@l
+/* 801D8100 001D3D60 54 63 10 3A */ slwi r3, r3, 2
+/* 801D8104 001D3D64 90 9E 00 00 */ stw r4, 0(r30)
+/* 801D8108 001D3D68 7C 87 1A 14 */ add r4, r7, r3
+/* 801D810C 001D3D6C 38 84 01 A8 */ addi r4, r4, 0x1a8
+/* 801D8110 001D3D70 41 82 00 14 */ beq lbl_801D8124
+/* 801D8114 001D3D74 7C A3 2B 78 */ mr r3, r5
+/* 801D8118 001D3D78 7C 05 03 78 */ mr r5, r0
+/* 801D811C 001D3D7C 4B FF CE 5D */ bl TRKAppendBuffer_ui32
+/* 801D8120 001D3D80 48 00 00 74 */ b lbl_801D8194
+lbl_801D8124:
+/* 801D8124 001D3D84 38 67 01 EC */ addi r3, r7, 0x1ec
+/* 801D8128 001D3D88 7C 04 18 40 */ cmplw r4, r3
+/* 801D812C 001D3D8C 41 81 00 24 */ bgt lbl_801D8150
+/* 801D8130 001D3D90 38 C6 FF FC */ addi r6, r6, -4
+/* 801D8134 001D3D94 38 67 01 E8 */ addi r3, r7, 0x1e8
+/* 801D8138 001D3D98 7C C4 32 14 */ add r6, r4, r6
+/* 801D813C 001D3D9C 7C 06 18 40 */ cmplw r6, r3
+/* 801D8140 001D3DA0 41 80 00 10 */ blt lbl_801D8150
+/* 801D8144 001D3DA4 3C 60 80 42 */ lis r3, lbl_80423230@ha
+/* 801D8148 001D3DA8 38 C0 00 01 */ li r6, 1
+/* 801D814C 001D3DAC 98 C3 32 30 */ stb r6, lbl_80423230@l(r3)
+lbl_801D8150:
+/* 801D8150 001D3DB0 3C 60 80 49 */ lis r3, lbl_80490898@ha
+/* 801D8154 001D3DB4 38 63 08 98 */ addi r3, r3, lbl_80490898@l
+/* 801D8158 001D3DB8 38 C3 02 78 */ addi r6, r3, 0x278
+/* 801D815C 001D3DBC 7C 04 30 40 */ cmplw r4, r6
+/* 801D8160 001D3DC0 41 81 00 28 */ bgt lbl_801D8188
+/* 801D8164 001D3DC4 54 03 10 3A */ slwi r3, r0, 2
+/* 801D8168 001D3DC8 38 63 FF FC */ addi r3, r3, -4
+/* 801D816C 001D3DCC 7C 64 1A 14 */ add r3, r4, r3
+/* 801D8170 001D3DD0 7C 03 30 40 */ cmplw r3, r6
+/* 801D8174 001D3DD4 41 80 00 14 */ blt lbl_801D8188
+/* 801D8178 001D3DD8 3C 60 80 42 */ lis r3, lbl_80423230@ha
+/* 801D817C 001D3DDC 38 C0 00 01 */ li r6, 1
+/* 801D8180 001D3DE0 38 63 32 30 */ addi r3, r3, lbl_80423230@l
+/* 801D8184 001D3DE4 98 C3 00 01 */ stb r6, 1(r3)
+lbl_801D8188:
+/* 801D8188 001D3DE8 7C A3 2B 78 */ mr r3, r5
+/* 801D818C 001D3DEC 7C 05 03 78 */ mr r5, r0
+/* 801D8190 001D3DF0 4B FF CB 79 */ bl TRKReadBuffer_ui32
+lbl_801D8194:
+/* 801D8194 001D3DF4 88 1F 00 0D */ lbz r0, 0xd(r31)
+/* 801D8198 001D3DF8 28 00 00 00 */ cmplwi r0, 0
+/* 801D819C 001D3DFC 41 82 00 10 */ beq lbl_801D81AC
+/* 801D81A0 001D3E00 38 00 00 00 */ li r0, 0
+/* 801D81A4 001D3E04 38 60 07 02 */ li r3, 0x702
+/* 801D81A8 001D3E08 90 1E 00 00 */ stw r0, 0(r30)
+lbl_801D81AC:
+/* 801D81AC 001D3E0C 3C 80 80 42 */ lis r4, lbl_8042323C@ha
+/* 801D81B0 001D3E10 80 C1 00 08 */ lwz r6, 8(r1)
+/* 801D81B4 001D3E14 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l
+/* 801D81B8 001D3E18 80 A1 00 0C */ lwz r5, 0xc(r1)
+/* 801D81BC 001D3E1C 80 81 00 10 */ lwz r4, 0x10(r1)
+/* 801D81C0 001D3E20 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D81C4 001D3E24 90 C7 00 00 */ stw r6, 0(r7)
+/* 801D81C8 001D3E28 90 A7 00 04 */ stw r5, 4(r7)
+/* 801D81CC 001D3E2C 90 87 00 08 */ stw r4, 8(r7)
+/* 801D81D0 001D3E30 90 07 00 0C */ stw r0, 0xc(r7)
+lbl_801D81D4:
+/* 801D81D4 001D3E34 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D81D8 001D3E38 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D81DC 001D3E3C 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D81E0 001D3E40 7C 08 03 A6 */ mtlr r0
+/* 801D81E4 001D3E44 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D81E8 001D3E48 4E 80 00 20 */ blr
+
+.global TRKTargetAccessFP
+TRKTargetAccessFP:
+/* 801D81EC 001D3E4C 94 21 FF 10 */ stwu r1, -0xf0(r1)
+/* 801D81F0 001D3E50 7C 08 02 A6 */ mflr r0
+/* 801D81F4 001D3E54 90 01 00 F4 */ stw r0, 0xf4(r1)
+/* 801D81F8 001D3E58 BE 81 00 C0 */ stmw r20, 0xc0(r1)
+/* 801D81FC 001D3E5C 7C 9C 23 78 */ mr r28, r4
+/* 801D8200 001D3E60 28 1C 00 21 */ cmplwi r28, 0x21
+/* 801D8204 001D3E64 7C 74 1B 78 */ mr r20, r3
+/* 801D8208 001D3E68 7C BD 2B 78 */ mr r29, r5
+/* 801D820C 001D3E6C 7C DE 33 78 */ mr r30, r6
+/* 801D8210 001D3E70 7C FF 3B 78 */ mr r31, r7
+/* 801D8214 001D3E74 40 81 00 0C */ ble lbl_801D8220
+/* 801D8218 001D3E78 38 60 07 01 */ li r3, 0x701
+/* 801D821C 001D3E7C 48 00 04 C8 */ b lbl_801D86E4
+lbl_801D8220:
+/* 801D8220 001D3E80 3C 60 80 42 */ lis r3, lbl_8042323C@ha
+/* 801D8224 001D3E84 38 00 00 00 */ li r0, 0
+/* 801D8228 001D3E88 3B 63 32 3C */ addi r27, r3, lbl_8042323C@l
+/* 801D822C 001D3E8C 80 7B 00 0C */ lwz r3, 0xc(r27)
+/* 801D8230 001D3E90 80 DB 00 00 */ lwz r6, 0(r27)
+/* 801D8234 001D3E94 80 BB 00 04 */ lwz r5, 4(r27)
+/* 801D8238 001D3E98 80 9B 00 08 */ lwz r4, 8(r27)
+/* 801D823C 001D3E9C 90 C1 00 10 */ stw r6, 0x10(r1)
+/* 801D8240 001D3EA0 90 A1 00 14 */ stw r5, 0x14(r1)
+/* 801D8244 001D3EA4 90 81 00 18 */ stw r4, 0x18(r1)
+/* 801D8248 001D3EA8 90 61 00 1C */ stw r3, 0x1c(r1)
+/* 801D824C 001D3EAC 98 1B 00 0D */ stb r0, 0xd(r27)
+/* 801D8250 001D3EB0 4B FF EF C1 */ bl __TRK_get_MSR
+/* 801D8254 001D3EB4 60 63 20 00 */ ori r3, r3, 0x2000
+/* 801D8258 001D3EB8 4B FF EF C1 */ bl __TRK_set_MSR
+/* 801D825C 001D3EBC 38 00 00 00 */ li r0, 0
+/* 801D8260 001D3EC0 7E 95 A3 78 */ mr r21, r20
+/* 801D8264 001D3EC4 90 1E 00 00 */ stw r0, 0(r30)
+/* 801D8268 001D3EC8 56 9A A8 14 */ slwi r26, r20, 0x15
+/* 801D826C 001D3ECC 3B 21 00 98 */ addi r25, r1, 0x98
+/* 801D8270 001D3ED0 3B 01 00 48 */ addi r24, r1, 0x48
+/* 801D8274 001D3ED4 3A E1 00 70 */ addi r23, r1, 0x70
+/* 801D8278 001D3ED8 3A C1 00 20 */ addi r22, r1, 0x20
+/* 801D827C 001D3EDC 38 60 00 00 */ li r3, 0
+/* 801D8280 001D3EE0 48 00 04 14 */ b lbl_801D8694
+lbl_801D8284:
+/* 801D8284 001D3EE4 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D8288 001D3EE8 41 82 01 FC */ beq lbl_801D8484
+/* 801D828C 001D3EEC 3C 60 80 40 */ lis r3, lbl_803FD718@ha
+/* 801D8290 001D3EF0 28 15 00 20 */ cmplwi r21, 0x20
+/* 801D8294 001D3EF4 39 83 D7 18 */ addi r12, r3, lbl_803FD718@l
+/* 801D8298 001D3EF8 81 6C 00 00 */ lwz r11, 0(r12)
+/* 801D829C 001D3EFC 81 4C 00 04 */ lwz r10, 4(r12)
+/* 801D82A0 001D3F00 81 2C 00 08 */ lwz r9, 8(r12)
+/* 801D82A4 001D3F04 81 0C 00 0C */ lwz r8, 0xc(r12)
+/* 801D82A8 001D3F08 80 EC 00 10 */ lwz r7, 0x10(r12)
+/* 801D82AC 001D3F0C 80 CC 00 14 */ lwz r6, 0x14(r12)
+/* 801D82B0 001D3F10 80 AC 00 18 */ lwz r5, 0x18(r12)
+/* 801D82B4 001D3F14 80 8C 00 1C */ lwz r4, 0x1c(r12)
+/* 801D82B8 001D3F18 80 6C 00 20 */ lwz r3, 0x20(r12)
+/* 801D82BC 001D3F1C 80 0C 00 24 */ lwz r0, 0x24(r12)
+/* 801D82C0 001D3F20 91 61 00 98 */ stw r11, 0x98(r1)
+/* 801D82C4 001D3F24 91 41 00 9C */ stw r10, 0x9c(r1)
+/* 801D82C8 001D3F28 91 21 00 A0 */ stw r9, 0xa0(r1)
+/* 801D82CC 001D3F2C 91 01 00 A4 */ stw r8, 0xa4(r1)
+/* 801D82D0 001D3F30 90 E1 00 A8 */ stw r7, 0xa8(r1)
+/* 801D82D4 001D3F34 90 C1 00 AC */ stw r6, 0xac(r1)
+/* 801D82D8 001D3F38 90 A1 00 B0 */ stw r5, 0xb0(r1)
+/* 801D82DC 001D3F3C 90 81 00 B4 */ stw r4, 0xb4(r1)
+/* 801D82E0 001D3F40 90 61 00 B8 */ stw r3, 0xb8(r1)
+/* 801D82E4 001D3F44 90 01 00 BC */ stw r0, 0xbc(r1)
+/* 801D82E8 001D3F48 40 80 00 4C */ bge lbl_801D8334
+/* 801D82EC 001D3F4C 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D82F0 001D3F50 67 40 C8 03 */ oris r0, r26, 0xc803
+/* 801D82F4 001D3F54 41 82 00 08 */ beq lbl_801D82FC
+/* 801D82F8 001D3F58 67 40 D8 03 */ oris r0, r26, 0xd803
+lbl_801D82FC:
+/* 801D82FC 001D3F5C 3C 60 4E 80 */ lis r3, 0x4E800020@ha
+/* 801D8300 001D3F60 90 01 00 98 */ stw r0, 0x98(r1)
+/* 801D8304 001D3F64 38 03 00 20 */ addi r0, r3, 0x4E800020@l
+/* 801D8308 001D3F68 7F 23 CB 78 */ mr r3, r25
+/* 801D830C 001D3F6C 90 01 00 BC */ stw r0, 0xbc(r1)
+/* 801D8310 001D3F70 38 80 00 28 */ li r4, 0x28
+/* 801D8314 001D3F74 4B FF ED F1 */ bl TRK_flush_cache
+/* 801D8318 001D3F78 3C 60 80 49 */ lis r3, lbl_80490D5C@ha
+/* 801D831C 001D3F7C 39 81 00 98 */ addi r12, r1, 0x98
+/* 801D8320 001D3F80 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l
+/* 801D8324 001D3F84 38 61 00 08 */ addi r3, r1, 8
+/* 801D8328 001D3F88 7D 89 03 A6 */ mtctr r12
+/* 801D832C 001D3F8C 4E 80 04 21 */ bctrl
+/* 801D8330 001D3F90 48 00 01 40 */ b lbl_801D8470
+lbl_801D8334:
+/* 801D8334 001D3F94 40 82 00 44 */ bne lbl_801D8378
+/* 801D8338 001D3F98 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D833C 001D3F9C 41 82 00 10 */ beq lbl_801D834C
+/* 801D8340 001D3FA0 38 61 00 08 */ addi r3, r1, 8
+/* 801D8344 001D3FA4 4B FF F2 61 */ bl ReadFPSCR
+/* 801D8348 001D3FA8 48 00 00 0C */ b lbl_801D8354
+lbl_801D834C:
+/* 801D834C 001D3FAC 38 61 00 08 */ addi r3, r1, 8
+/* 801D8350 001D3FB0 4B FF F2 79 */ bl WriteFPSCR
+lbl_801D8354:
+/* 801D8354 001D3FB4 80 81 00 08 */ lwz r4, 8(r1)
+/* 801D8358 001D3FB8 38 00 00 00 */ li r0, 0
+/* 801D835C 001D3FBC 80 A1 00 0C */ lwz r5, 0xc(r1)
+/* 801D8360 001D3FC0 38 60 FF FF */ li r3, -1
+/* 801D8364 001D3FC4 7C 80 00 38 */ and r0, r4, r0
+/* 801D8368 001D3FC8 7C A3 18 38 */ and r3, r5, r3
+/* 801D836C 001D3FCC 90 01 00 08 */ stw r0, 8(r1)
+/* 801D8370 001D3FD0 90 61 00 0C */ stw r3, 0xc(r1)
+/* 801D8374 001D3FD4 48 00 00 FC */ b lbl_801D8470
+lbl_801D8378:
+/* 801D8378 001D3FD8 28 15 00 21 */ cmplwi r21, 0x21
+/* 801D837C 001D3FDC 40 82 00 F4 */ bne lbl_801D8470
+/* 801D8380 001D3FE0 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D8384 001D3FE4 40 82 00 0C */ bne lbl_801D8390
+/* 801D8388 001D3FE8 80 01 00 0C */ lwz r0, 0xc(r1)
+/* 801D838C 001D3FEC 90 01 00 08 */ stw r0, 8(r1)
+lbl_801D8390:
+/* 801D8390 001D3FF0 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha
+/* 801D8394 001D3FF4 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D8398 001D3FF8 39 83 D6 C8 */ addi r12, r3, lbl_803FD6C8@l
+/* 801D839C 001D3FFC 81 6C 00 00 */ lwz r11, 0(r12)
+/* 801D83A0 001D4000 81 4C 00 04 */ lwz r10, 4(r12)
+/* 801D83A4 001D4004 81 2C 00 08 */ lwz r9, 8(r12)
+/* 801D83A8 001D4008 81 0C 00 0C */ lwz r8, 0xc(r12)
+/* 801D83AC 001D400C 80 EC 00 10 */ lwz r7, 0x10(r12)
+/* 801D83B0 001D4010 80 CC 00 14 */ lwz r6, 0x14(r12)
+/* 801D83B4 001D4014 80 AC 00 18 */ lwz r5, 0x18(r12)
+/* 801D83B8 001D4018 80 8C 00 1C */ lwz r4, 0x1c(r12)
+/* 801D83BC 001D401C 80 6C 00 20 */ lwz r3, 0x20(r12)
+/* 801D83C0 001D4020 80 0C 00 24 */ lwz r0, 0x24(r12)
+/* 801D83C4 001D4024 91 61 00 48 */ stw r11, 0x48(r1)
+/* 801D83C8 001D4028 91 41 00 4C */ stw r10, 0x4c(r1)
+/* 801D83CC 001D402C 91 21 00 50 */ stw r9, 0x50(r1)
+/* 801D83D0 001D4030 91 01 00 54 */ stw r8, 0x54(r1)
+/* 801D83D4 001D4034 90 E1 00 58 */ stw r7, 0x58(r1)
+/* 801D83D8 001D4038 90 C1 00 5C */ stw r6, 0x5c(r1)
+/* 801D83DC 001D403C 90 A1 00 60 */ stw r5, 0x60(r1)
+/* 801D83E0 001D4040 90 81 00 64 */ stw r4, 0x64(r1)
+/* 801D83E4 001D4044 90 61 00 68 */ stw r3, 0x68(r1)
+/* 801D83E8 001D4048 90 01 00 6C */ stw r0, 0x6c(r1)
+/* 801D83EC 001D404C 41 82 00 1C */ beq lbl_801D8408
+/* 801D83F0 001D4050 3C 60 7C 9F */ lis r3, 0x7C9EFAA6@ha
+/* 801D83F4 001D4054 3C 00 90 83 */ lis r0, 0x9083
+/* 801D83F8 001D4058 38 63 FA A6 */ addi r3, r3, 0x7C9EFAA6@l
+/* 801D83FC 001D405C 90 01 00 4C */ stw r0, 0x4c(r1)
+/* 801D8400 001D4060 90 61 00 48 */ stw r3, 0x48(r1)
+/* 801D8404 001D4064 48 00 00 18 */ b lbl_801D841C
+lbl_801D8408:
+/* 801D8408 001D4068 3C 60 7C 9F */ lis r3, 0x7C9EFBA6@ha
+/* 801D840C 001D406C 3C 80 80 83 */ lis r4, 0x8083
+/* 801D8410 001D4070 38 03 FB A6 */ addi r0, r3, 0x7C9EFBA6@l
+/* 801D8414 001D4074 90 81 00 48 */ stw r4, 0x48(r1)
+/* 801D8418 001D4078 90 01 00 4C */ stw r0, 0x4c(r1)
+lbl_801D841C:
+/* 801D841C 001D407C 3C 80 4E 80 */ lis r4, 0x4E800020@ha
+/* 801D8420 001D4080 7F 03 C3 78 */ mr r3, r24
+/* 801D8424 001D4084 38 04 00 20 */ addi r0, r4, 0x4E800020@l
+/* 801D8428 001D4088 38 80 00 28 */ li r4, 0x28
+/* 801D842C 001D408C 90 01 00 6C */ stw r0, 0x6c(r1)
+/* 801D8430 001D4090 4B FF EC D5 */ bl TRK_flush_cache
+/* 801D8434 001D4094 3C 60 80 49 */ lis r3, lbl_80490D5C@ha
+/* 801D8438 001D4098 39 81 00 48 */ addi r12, r1, 0x48
+/* 801D843C 001D409C 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l
+/* 801D8440 001D40A0 38 61 00 08 */ addi r3, r1, 8
+/* 801D8444 001D40A4 7D 89 03 A6 */ mtctr r12
+/* 801D8448 001D40A8 4E 80 04 21 */ bctrl
+/* 801D844C 001D40AC 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D8450 001D40B0 41 82 00 20 */ beq lbl_801D8470
+/* 801D8454 001D40B4 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D8458 001D40B8 38 80 00 00 */ li r4, 0
+/* 801D845C 001D40BC 38 00 FF FF */ li r0, -1
+/* 801D8460 001D40C0 7C 63 00 38 */ and r3, r3, r0
+/* 801D8464 001D40C4 7C 80 20 38 */ and r0, r4, r4
+/* 801D8468 001D40C8 90 61 00 0C */ stw r3, 0xc(r1)
+/* 801D846C 001D40CC 90 01 00 08 */ stw r0, 8(r1)
+lbl_801D8470:
+/* 801D8470 001D40D0 80 A1 00 08 */ lwz r5, 8(r1)
+/* 801D8474 001D40D4 7F A3 EB 78 */ mr r3, r29
+/* 801D8478 001D40D8 80 C1 00 0C */ lwz r6, 0xc(r1)
+/* 801D847C 001D40DC 4B FF CC 61 */ bl TRKAppendBuffer1_ui64
+/* 801D8480 001D40E0 48 00 02 00 */ b lbl_801D8680
+lbl_801D8484:
+/* 801D8484 001D40E4 7F A3 EB 78 */ mr r3, r29
+/* 801D8488 001D40E8 38 81 00 08 */ addi r4, r1, 8
+/* 801D848C 001D40EC 4B FF CA 05 */ bl TRKReadBuffer1_ui64
+/* 801D8490 001D40F0 3C 60 80 40 */ lis r3, lbl_803FD718@ha
+/* 801D8494 001D40F4 28 15 00 20 */ cmplwi r21, 0x20
+/* 801D8498 001D40F8 39 83 D7 18 */ addi r12, r3, lbl_803FD718@l
+/* 801D849C 001D40FC 3A 80 00 00 */ li r20, 0
+/* 801D84A0 001D4100 81 6C 00 00 */ lwz r11, 0(r12)
+/* 801D84A4 001D4104 81 4C 00 04 */ lwz r10, 4(r12)
+/* 801D84A8 001D4108 81 2C 00 08 */ lwz r9, 8(r12)
+/* 801D84AC 001D410C 81 0C 00 0C */ lwz r8, 0xc(r12)
+/* 801D84B0 001D4110 80 EC 00 10 */ lwz r7, 0x10(r12)
+/* 801D84B4 001D4114 80 CC 00 14 */ lwz r6, 0x14(r12)
+/* 801D84B8 001D4118 80 AC 00 18 */ lwz r5, 0x18(r12)
+/* 801D84BC 001D411C 80 8C 00 1C */ lwz r4, 0x1c(r12)
+/* 801D84C0 001D4120 80 6C 00 20 */ lwz r3, 0x20(r12)
+/* 801D84C4 001D4124 80 0C 00 24 */ lwz r0, 0x24(r12)
+/* 801D84C8 001D4128 91 61 00 70 */ stw r11, 0x70(r1)
+/* 801D84CC 001D412C 91 41 00 74 */ stw r10, 0x74(r1)
+/* 801D84D0 001D4130 91 21 00 78 */ stw r9, 0x78(r1)
+/* 801D84D4 001D4134 91 01 00 7C */ stw r8, 0x7c(r1)
+/* 801D84D8 001D4138 90 E1 00 80 */ stw r7, 0x80(r1)
+/* 801D84DC 001D413C 90 C1 00 84 */ stw r6, 0x84(r1)
+/* 801D84E0 001D4140 90 A1 00 88 */ stw r5, 0x88(r1)
+/* 801D84E4 001D4144 90 81 00 8C */ stw r4, 0x8c(r1)
+/* 801D84E8 001D4148 90 61 00 90 */ stw r3, 0x90(r1)
+/* 801D84EC 001D414C 90 01 00 94 */ stw r0, 0x94(r1)
+/* 801D84F0 001D4150 40 80 00 50 */ bge lbl_801D8540
+/* 801D84F4 001D4154 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D84F8 001D4158 67 40 C8 03 */ oris r0, r26, 0xc803
+/* 801D84FC 001D415C 41 82 00 08 */ beq lbl_801D8504
+/* 801D8500 001D4160 67 40 D8 03 */ oris r0, r26, 0xd803
+lbl_801D8504:
+/* 801D8504 001D4164 3C 60 4E 80 */ lis r3, 0x4E800020@ha
+/* 801D8508 001D4168 90 01 00 70 */ stw r0, 0x70(r1)
+/* 801D850C 001D416C 38 03 00 20 */ addi r0, r3, 0x4E800020@l
+/* 801D8510 001D4170 7E E3 BB 78 */ mr r3, r23
+/* 801D8514 001D4174 90 01 00 94 */ stw r0, 0x94(r1)
+/* 801D8518 001D4178 38 80 00 28 */ li r4, 0x28
+/* 801D851C 001D417C 4B FF EB E9 */ bl TRK_flush_cache
+/* 801D8520 001D4180 3C 60 80 49 */ lis r3, lbl_80490D5C@ha
+/* 801D8524 001D4184 39 81 00 70 */ addi r12, r1, 0x70
+/* 801D8528 001D4188 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l
+/* 801D852C 001D418C 38 61 00 08 */ addi r3, r1, 8
+/* 801D8530 001D4190 7D 89 03 A6 */ mtctr r12
+/* 801D8534 001D4194 4E 80 04 21 */ bctrl
+/* 801D8538 001D4198 3A 80 00 00 */ li r20, 0
+/* 801D853C 001D419C 48 00 01 40 */ b lbl_801D867C
+lbl_801D8540:
+/* 801D8540 001D41A0 40 82 00 44 */ bne lbl_801D8584
+/* 801D8544 001D41A4 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D8548 001D41A8 41 82 00 10 */ beq lbl_801D8558
+/* 801D854C 001D41AC 38 61 00 08 */ addi r3, r1, 8
+/* 801D8550 001D41B0 4B FF F0 55 */ bl ReadFPSCR
+/* 801D8554 001D41B4 48 00 00 0C */ b lbl_801D8560
+lbl_801D8558:
+/* 801D8558 001D41B8 38 61 00 08 */ addi r3, r1, 8
+/* 801D855C 001D41BC 4B FF F0 6D */ bl WriteFPSCR
+lbl_801D8560:
+/* 801D8560 001D41C0 80 81 00 08 */ lwz r4, 8(r1)
+/* 801D8564 001D41C4 38 00 00 00 */ li r0, 0
+/* 801D8568 001D41C8 80 A1 00 0C */ lwz r5, 0xc(r1)
+/* 801D856C 001D41CC 38 60 FF FF */ li r3, -1
+/* 801D8570 001D41D0 7C 80 00 38 */ and r0, r4, r0
+/* 801D8574 001D41D4 7C A3 18 38 */ and r3, r5, r3
+/* 801D8578 001D41D8 90 01 00 08 */ stw r0, 8(r1)
+/* 801D857C 001D41DC 90 61 00 0C */ stw r3, 0xc(r1)
+/* 801D8580 001D41E0 48 00 00 FC */ b lbl_801D867C
+lbl_801D8584:
+/* 801D8584 001D41E4 28 15 00 21 */ cmplwi r21, 0x21
+/* 801D8588 001D41E8 40 82 00 F4 */ bne lbl_801D867C
+/* 801D858C 001D41EC 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D8590 001D41F0 40 82 00 0C */ bne lbl_801D859C
+/* 801D8594 001D41F4 80 01 00 0C */ lwz r0, 0xc(r1)
+/* 801D8598 001D41F8 90 01 00 08 */ stw r0, 8(r1)
+lbl_801D859C:
+/* 801D859C 001D41FC 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha
+/* 801D85A0 001D4200 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D85A4 001D4204 39 83 D6 C8 */ addi r12, r3, lbl_803FD6C8@l
+/* 801D85A8 001D4208 81 6C 00 00 */ lwz r11, 0(r12)
+/* 801D85AC 001D420C 81 4C 00 04 */ lwz r10, 4(r12)
+/* 801D85B0 001D4210 81 2C 00 08 */ lwz r9, 8(r12)
+/* 801D85B4 001D4214 81 0C 00 0C */ lwz r8, 0xc(r12)
+/* 801D85B8 001D4218 80 EC 00 10 */ lwz r7, 0x10(r12)
+/* 801D85BC 001D421C 80 CC 00 14 */ lwz r6, 0x14(r12)
+/* 801D85C0 001D4220 80 AC 00 18 */ lwz r5, 0x18(r12)
+/* 801D85C4 001D4224 80 8C 00 1C */ lwz r4, 0x1c(r12)
+/* 801D85C8 001D4228 80 6C 00 20 */ lwz r3, 0x20(r12)
+/* 801D85CC 001D422C 80 0C 00 24 */ lwz r0, 0x24(r12)
+/* 801D85D0 001D4230 91 61 00 20 */ stw r11, 0x20(r1)
+/* 801D85D4 001D4234 91 41 00 24 */ stw r10, 0x24(r1)
+/* 801D85D8 001D4238 91 21 00 28 */ stw r9, 0x28(r1)
+/* 801D85DC 001D423C 91 01 00 2C */ stw r8, 0x2c(r1)
+/* 801D85E0 001D4240 90 E1 00 30 */ stw r7, 0x30(r1)
+/* 801D85E4 001D4244 90 C1 00 34 */ stw r6, 0x34(r1)
+/* 801D85E8 001D4248 90 A1 00 38 */ stw r5, 0x38(r1)
+/* 801D85EC 001D424C 90 81 00 3C */ stw r4, 0x3c(r1)
+/* 801D85F0 001D4250 90 61 00 40 */ stw r3, 0x40(r1)
+/* 801D85F4 001D4254 90 01 00 44 */ stw r0, 0x44(r1)
+/* 801D85F8 001D4258 41 82 00 1C */ beq lbl_801D8614
+/* 801D85FC 001D425C 3C 60 7C 9F */ lis r3, 0x7C9EFAA6@ha
+/* 801D8600 001D4260 3C 00 90 83 */ lis r0, 0x9083
+/* 801D8604 001D4264 38 63 FA A6 */ addi r3, r3, 0x7C9EFAA6@l
+/* 801D8608 001D4268 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D860C 001D426C 90 61 00 20 */ stw r3, 0x20(r1)
+/* 801D8610 001D4270 48 00 00 18 */ b lbl_801D8628
+lbl_801D8614:
+/* 801D8614 001D4274 3C 60 7C 9F */ lis r3, 0x7C9EFBA6@ha
+/* 801D8618 001D4278 3C 80 80 83 */ lis r4, 0x8083
+/* 801D861C 001D427C 38 03 FB A6 */ addi r0, r3, 0x7C9EFBA6@l
+/* 801D8620 001D4280 90 81 00 20 */ stw r4, 0x20(r1)
+/* 801D8624 001D4284 90 01 00 24 */ stw r0, 0x24(r1)
+lbl_801D8628:
+/* 801D8628 001D4288 3C 80 4E 80 */ lis r4, 0x4E800020@ha
+/* 801D862C 001D428C 7E C3 B3 78 */ mr r3, r22
+/* 801D8630 001D4290 38 04 00 20 */ addi r0, r4, 0x4E800020@l
+/* 801D8634 001D4294 38 80 00 28 */ li r4, 0x28
+/* 801D8638 001D4298 90 01 00 44 */ stw r0, 0x44(r1)
+/* 801D863C 001D429C 4B FF EA C9 */ bl TRK_flush_cache
+/* 801D8640 001D42A0 3C 60 80 49 */ lis r3, lbl_80490D5C@ha
+/* 801D8644 001D42A4 39 81 00 20 */ addi r12, r1, 0x20
+/* 801D8648 001D42A8 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l
+/* 801D864C 001D42AC 38 61 00 08 */ addi r3, r1, 8
+/* 801D8650 001D42B0 7D 89 03 A6 */ mtctr r12
+/* 801D8654 001D42B4 4E 80 04 21 */ bctrl
+/* 801D8658 001D42B8 2C 1F 00 00 */ cmpwi r31, 0
+/* 801D865C 001D42BC 3A 80 00 00 */ li r20, 0
+/* 801D8660 001D42C0 41 82 00 1C */ beq lbl_801D867C
+/* 801D8664 001D42C4 80 81 00 08 */ lwz r4, 8(r1)
+/* 801D8668 001D42C8 38 60 FF FF */ li r3, -1
+/* 801D866C 001D42CC 7E 80 A0 38 */ and r0, r20, r20
+/* 801D8670 001D42D0 7C 83 18 38 */ and r3, r4, r3
+/* 801D8674 001D42D4 90 01 00 08 */ stw r0, 8(r1)
+/* 801D8678 001D42D8 90 61 00 0C */ stw r3, 0xc(r1)
+lbl_801D867C:
+/* 801D867C 001D42DC 7E 83 A3 78 */ mr r3, r20
+lbl_801D8680:
+/* 801D8680 001D42E0 80 9E 00 00 */ lwz r4, 0(r30)
+/* 801D8684 001D42E4 3F 5A 00 20 */ addis r26, r26, 0x20
+/* 801D8688 001D42E8 3A B5 00 01 */ addi r21, r21, 1
+/* 801D868C 001D42EC 38 04 00 08 */ addi r0, r4, 8
+/* 801D8690 001D42F0 90 1E 00 00 */ stw r0, 0(r30)
+lbl_801D8694:
+/* 801D8694 001D42F4 7C 15 E0 40 */ cmplw r21, r28
+/* 801D8698 001D42F8 41 81 00 0C */ bgt lbl_801D86A4
+/* 801D869C 001D42FC 2C 03 00 00 */ cmpwi r3, 0
+/* 801D86A0 001D4300 41 82 FB E4 */ beq lbl_801D8284
+lbl_801D86A4:
+/* 801D86A4 001D4304 88 1B 00 0D */ lbz r0, 0xd(r27)
+/* 801D86A8 001D4308 28 00 00 00 */ cmplwi r0, 0
+/* 801D86AC 001D430C 41 82 00 10 */ beq lbl_801D86BC
+/* 801D86B0 001D4310 38 00 00 00 */ li r0, 0
+/* 801D86B4 001D4314 38 60 07 02 */ li r3, 0x702
+/* 801D86B8 001D4318 90 1E 00 00 */ stw r0, 0(r30)
+lbl_801D86BC:
+/* 801D86BC 001D431C 3C 80 80 42 */ lis r4, lbl_8042323C@ha
+/* 801D86C0 001D4320 80 C1 00 10 */ lwz r6, 0x10(r1)
+/* 801D86C4 001D4324 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l
+/* 801D86C8 001D4328 80 A1 00 14 */ lwz r5, 0x14(r1)
+/* 801D86CC 001D432C 80 81 00 18 */ lwz r4, 0x18(r1)
+/* 801D86D0 001D4330 80 01 00 1C */ lwz r0, 0x1c(r1)
+/* 801D86D4 001D4334 90 C7 00 00 */ stw r6, 0(r7)
+/* 801D86D8 001D4338 90 A7 00 04 */ stw r5, 4(r7)
+/* 801D86DC 001D433C 90 87 00 08 */ stw r4, 8(r7)
+/* 801D86E0 001D4340 90 07 00 0C */ stw r0, 0xc(r7)
+lbl_801D86E4:
+/* 801D86E4 001D4344 BA 81 00 C0 */ lmw r20, 0xc0(r1)
+/* 801D86E8 001D4348 80 01 00 F4 */ lwz r0, 0xf4(r1)
+/* 801D86EC 001D434C 7C 08 03 A6 */ mtlr r0
+/* 801D86F0 001D4350 38 21 00 F0 */ addi r1, r1, 0xf0
+/* 801D86F4 001D4354 4E 80 00 20 */ blr
+
+.global TRKTargetAccessDefault
+TRKTargetAccessDefault:
+/* 801D86F8 001D4358 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D86FC 001D435C 7C 08 02 A6 */ mflr r0
+/* 801D8700 001D4360 28 04 00 24 */ cmplwi r4, 0x24
+/* 801D8704 001D4364 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D8708 001D4368 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D870C 001D436C 7C DF 33 78 */ mr r31, r6
+/* 801D8710 001D4370 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D8714 001D4374 40 81 00 0C */ ble lbl_801D8720
+/* 801D8718 001D4378 38 60 07 01 */ li r3, 0x701
+/* 801D871C 001D437C 48 00 00 B8 */ b lbl_801D87D4
+lbl_801D8720:
+/* 801D8720 001D4380 3C C0 80 42 */ lis r6, lbl_8042323C@ha
+/* 801D8724 001D4384 7C 83 20 50 */ subf r4, r3, r4
+/* 801D8728 001D4388 3B C6 32 3C */ addi r30, r6, lbl_8042323C@l
+/* 801D872C 001D438C 3C C0 80 49 */ lis r6, lbl_80490898@ha
+/* 801D8730 001D4390 81 3E 00 0C */ lwz r9, 0xc(r30)
+/* 801D8734 001D4394 39 00 00 00 */ li r8, 0
+/* 801D8738 001D4398 39 84 00 01 */ addi r12, r4, 1
+/* 801D873C 001D439C 81 7E 00 00 */ lwz r11, 0(r30)
+/* 801D8740 001D43A0 81 5E 00 04 */ lwz r10, 4(r30)
+/* 801D8744 001D43A4 2C 07 00 00 */ cmpwi r7, 0
+/* 801D8748 001D43A8 80 FE 00 08 */ lwz r7, 8(r30)
+/* 801D874C 001D43AC 55 80 10 3A */ slwi r0, r12, 2
+/* 801D8750 001D43B0 99 1E 00 0D */ stb r8, 0xd(r30)
+/* 801D8754 001D43B4 54 64 10 3A */ slwi r4, r3, 2
+/* 801D8758 001D43B8 38 66 08 98 */ addi r3, r6, lbl_80490898@l
+/* 801D875C 001D43BC 91 61 00 08 */ stw r11, 8(r1)
+/* 801D8760 001D43C0 7C 83 22 14 */ add r4, r3, r4
+/* 801D8764 001D43C4 91 41 00 0C */ stw r10, 0xc(r1)
+/* 801D8768 001D43C8 90 E1 00 10 */ stw r7, 0x10(r1)
+/* 801D876C 001D43CC 91 21 00 14 */ stw r9, 0x14(r1)
+/* 801D8770 001D43D0 90 1F 00 00 */ stw r0, 0(r31)
+/* 801D8774 001D43D4 41 82 00 14 */ beq lbl_801D8788
+/* 801D8778 001D43D8 7C A3 2B 78 */ mr r3, r5
+/* 801D877C 001D43DC 7D 85 63 78 */ mr r5, r12
+/* 801D8780 001D43E0 4B FF C7 F9 */ bl TRKAppendBuffer_ui32
+/* 801D8784 001D43E4 48 00 00 10 */ b lbl_801D8794
+lbl_801D8788:
+/* 801D8788 001D43E8 7C A3 2B 78 */ mr r3, r5
+/* 801D878C 001D43EC 7D 85 63 78 */ mr r5, r12
+/* 801D8790 001D43F0 4B FF C5 79 */ bl TRKReadBuffer_ui32
+lbl_801D8794:
+/* 801D8794 001D43F4 88 1E 00 0D */ lbz r0, 0xd(r30)
+/* 801D8798 001D43F8 28 00 00 00 */ cmplwi r0, 0
+/* 801D879C 001D43FC 41 82 00 10 */ beq lbl_801D87AC
+/* 801D87A0 001D4400 38 00 00 00 */ li r0, 0
+/* 801D87A4 001D4404 38 60 07 02 */ li r3, 0x702
+/* 801D87A8 001D4408 90 1F 00 00 */ stw r0, 0(r31)
+lbl_801D87AC:
+/* 801D87AC 001D440C 3C 80 80 42 */ lis r4, lbl_8042323C@ha
+/* 801D87B0 001D4410 80 C1 00 08 */ lwz r6, 8(r1)
+/* 801D87B4 001D4414 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l
+/* 801D87B8 001D4418 80 A1 00 0C */ lwz r5, 0xc(r1)
+/* 801D87BC 001D441C 80 81 00 10 */ lwz r4, 0x10(r1)
+/* 801D87C0 001D4420 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D87C4 001D4424 90 C7 00 00 */ stw r6, 0(r7)
+/* 801D87C8 001D4428 90 A7 00 04 */ stw r5, 4(r7)
+/* 801D87CC 001D442C 90 87 00 08 */ stw r4, 8(r7)
+/* 801D87D0 001D4430 90 07 00 0C */ stw r0, 0xc(r7)
+lbl_801D87D4:
+/* 801D87D4 001D4434 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D87D8 001D4438 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D87DC 001D443C 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D87E0 001D4440 7C 08 03 A6 */ mtlr r0
+/* 801D87E4 001D4444 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D87E8 001D4448 4E 80 00 20 */ blr
+
+.global TRKTargetReadInstruction
+TRKTargetReadInstruction:
+/* 801D87EC 001D444C 94 21 FF F0 */ stwu r1, -0x10(r1)
+/* 801D87F0 001D4450 7C 08 02 A6 */ mflr r0
+/* 801D87F4 001D4454 38 C0 00 00 */ li r6, 0
+/* 801D87F8 001D4458 38 E0 00 01 */ li r7, 1
+/* 801D87FC 001D445C 90 01 00 14 */ stw r0, 0x14(r1)
+/* 801D8800 001D4460 38 00 00 04 */ li r0, 4
+/* 801D8804 001D4464 38 A1 00 08 */ addi r5, r1, 8
+/* 801D8808 001D4468 90 01 00 08 */ stw r0, 8(r1)
+/* 801D880C 001D446C 48 00 00 2D */ bl TRKTargetAccessMemory
+/* 801D8810 001D4470 2C 03 00 00 */ cmpwi r3, 0
+/* 801D8814 001D4474 40 82 00 14 */ bne lbl_801D8828
+/* 801D8818 001D4478 80 01 00 08 */ lwz r0, 8(r1)
+/* 801D881C 001D447C 28 00 00 04 */ cmplwi r0, 4
+/* 801D8820 001D4480 41 82 00 08 */ beq lbl_801D8828
+/* 801D8824 001D4484 38 60 07 00 */ li r3, 0x700
+lbl_801D8828:
+/* 801D8828 001D4488 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D882C 001D448C 7C 08 03 A6 */ mtlr r0
+/* 801D8830 001D4490 38 21 00 10 */ addi r1, r1, 0x10
+/* 801D8834 001D4494 4E 80 00 20 */ blr
+
+.global TRKTargetAccessMemory
+TRKTargetAccessMemory:
+/* 801D8838 001D4498 94 21 FF C0 */ stwu r1, -0x40(r1)
+/* 801D883C 001D449C 7C 08 02 A6 */ mflr r0
+/* 801D8840 001D44A0 3C C0 80 42 */ lis r6, lbl_8042323C@ha
+/* 801D8844 001D44A4 90 01 00 44 */ stw r0, 0x44(r1)
+/* 801D8848 001D44A8 38 00 00 00 */ li r0, 0
+/* 801D884C 001D44AC BF 21 00 24 */ stmw r25, 0x24(r1)
+/* 801D8850 001D44B0 3B E6 32 3C */ addi r31, r6, lbl_8042323C@l
+/* 801D8854 001D44B4 7C 9B 23 78 */ mr r27, r4
+/* 801D8858 001D44B8 7C BC 2B 78 */ mr r28, r5
+/* 801D885C 001D44BC 7C 7A 1B 78 */ mr r26, r3
+/* 801D8860 001D44C0 7C FD 3B 78 */ mr r29, r7
+/* 801D8864 001D44C4 7F 63 DB 78 */ mr r3, r27
+/* 801D8868 001D44C8 80 9F 00 0C */ lwz r4, 0xc(r31)
+/* 801D886C 001D44CC 81 1F 00 00 */ lwz r8, 0(r31)
+/* 801D8870 001D44D0 80 DF 00 04 */ lwz r6, 4(r31)
+/* 801D8874 001D44D4 80 BF 00 08 */ lwz r5, 8(r31)
+/* 801D8878 001D44D8 91 01 00 08 */ stw r8, 8(r1)
+/* 801D887C 001D44DC 90 C1 00 0C */ stw r6, 0xc(r1)
+/* 801D8880 001D44E0 90 A1 00 10 */ stw r5, 0x10(r1)
+/* 801D8884 001D44E4 90 81 00 14 */ stw r4, 0x14(r1)
+/* 801D8888 001D44E8 98 1F 00 0D */ stb r0, 0xd(r31)
+/* 801D888C 001D44EC 48 00 0B 51 */ bl TRKTargetTranslate
+/* 801D8890 001D44F0 7F A0 00 34 */ cntlzw r0, r29
+/* 801D8894 001D44F4 80 9C 00 00 */ lwz r4, 0(r28)
+/* 801D8898 001D44F8 7C 79 1B 78 */ mr r25, r3
+/* 801D889C 001D44FC 54 05 D9 7E */ srwi r5, r0, 5
+/* 801D88A0 001D4500 48 00 00 E5 */ bl TRKValidMemory32
+/* 801D88A4 001D4504 7C 7E 1B 79 */ or. r30, r3, r3
+/* 801D88A8 001D4508 41 82 00 10 */ beq lbl_801D88B8
+/* 801D88AC 001D450C 38 00 00 00 */ li r0, 0
+/* 801D88B0 001D4510 90 1C 00 00 */ stw r0, 0(r28)
+/* 801D88B4 001D4514 48 00 00 78 */ b lbl_801D892C
+lbl_801D88B8:
+/* 801D88B8 001D4518 4B FF E9 59 */ bl __TRK_get_MSR
+/* 801D88BC 001D451C 3C 80 80 49 */ lis r4, lbl_80490898@ha
+/* 801D88C0 001D4520 2C 1D 00 00 */ cmpwi r29, 0
+/* 801D88C4 001D4524 38 84 08 98 */ addi r4, r4, lbl_80490898@l
+/* 801D88C8 001D4528 7C 68 1B 78 */ mr r8, r3
+/* 801D88CC 001D452C 80 04 01 F8 */ lwz r0, 0x1f8(r4)
+/* 801D88D0 001D4530 54 00 06 F6 */ rlwinm r0, r0, 0, 0x1b, 0x1b
+/* 801D88D4 001D4534 7D 07 03 78 */ or r7, r8, r0
+/* 801D88D8 001D4538 41 82 00 1C */ beq lbl_801D88F4
+/* 801D88DC 001D453C 80 BC 00 00 */ lwz r5, 0(r28)
+/* 801D88E0 001D4540 7F 43 D3 78 */ mr r3, r26
+/* 801D88E4 001D4544 7F 24 CB 78 */ mr r4, r25
+/* 801D88E8 001D4548 7D 06 43 78 */ mr r6, r8
+/* 801D88EC 001D454C 4B FF E9 35 */ bl TRK_ppc_memcpy
+/* 801D88F0 001D4550 48 00 00 3C */ b lbl_801D892C
+lbl_801D88F4:
+/* 801D88F4 001D4554 80 BC 00 00 */ lwz r5, 0(r28)
+/* 801D88F8 001D4558 7F 23 CB 78 */ mr r3, r25
+/* 801D88FC 001D455C 7F 44 D3 78 */ mr r4, r26
+/* 801D8900 001D4560 7C E6 3B 78 */ mr r6, r7
+/* 801D8904 001D4564 7D 07 43 78 */ mr r7, r8
+/* 801D8908 001D4568 4B FF E9 19 */ bl TRK_ppc_memcpy
+/* 801D890C 001D456C 80 9C 00 00 */ lwz r4, 0(r28)
+/* 801D8910 001D4570 7F 23 CB 78 */ mr r3, r25
+/* 801D8914 001D4574 4B FF E7 F1 */ bl TRK_flush_cache
+/* 801D8918 001D4578 7C 1B C8 40 */ cmplw r27, r25
+/* 801D891C 001D457C 41 82 00 10 */ beq lbl_801D892C
+/* 801D8920 001D4580 80 9C 00 00 */ lwz r4, 0(r28)
+/* 801D8924 001D4584 7F 63 DB 78 */ mr r3, r27
+/* 801D8928 001D4588 4B FF E7 DD */ bl TRK_flush_cache
+lbl_801D892C:
+/* 801D892C 001D458C 88 1F 00 0D */ lbz r0, 0xd(r31)
+/* 801D8930 001D4590 28 00 00 00 */ cmplwi r0, 0
+/* 801D8934 001D4594 41 82 00 10 */ beq lbl_801D8944
+/* 801D8938 001D4598 38 00 00 00 */ li r0, 0
+/* 801D893C 001D459C 3B C0 07 02 */ li r30, 0x702
+/* 801D8940 001D45A0 90 1C 00 00 */ stw r0, 0(r28)
+lbl_801D8944:
+/* 801D8944 001D45A4 3C 60 80 42 */ lis r3, lbl_8042323C@ha
+/* 801D8948 001D45A8 80 C1 00 08 */ lwz r6, 8(r1)
+/* 801D894C 001D45AC 38 E3 32 3C */ addi r7, r3, lbl_8042323C@l
+/* 801D8950 001D45B0 80 A1 00 0C */ lwz r5, 0xc(r1)
+/* 801D8954 001D45B4 80 81 00 10 */ lwz r4, 0x10(r1)
+/* 801D8958 001D45B8 7F C3 F3 78 */ mr r3, r30
+/* 801D895C 001D45BC 80 01 00 14 */ lwz r0, 0x14(r1)
+/* 801D8960 001D45C0 90 C7 00 00 */ stw r6, 0(r7)
+/* 801D8964 001D45C4 90 A7 00 04 */ stw r5, 4(r7)
+/* 801D8968 001D45C8 90 87 00 08 */ stw r4, 8(r7)
+/* 801D896C 001D45CC 90 07 00 0C */ stw r0, 0xc(r7)
+/* 801D8970 001D45D0 BB 21 00 24 */ lmw r25, 0x24(r1)
+/* 801D8974 001D45D4 80 01 00 44 */ lwz r0, 0x44(r1)
+/* 801D8978 001D45D8 7C 08 03 A6 */ mtlr r0
+/* 801D897C 001D45DC 38 21 00 40 */ addi r1, r1, 0x40
+/* 801D8980 001D45E0 4E 80 00 20 */ blr
+
+.global TRKValidMemory32
+TRKValidMemory32:
+/* 801D8984 001D45E4 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D8988 001D45E8 7C 08 02 A6 */ mflr r0
+/* 801D898C 001D45EC 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D8990 001D45F0 BF 41 00 08 */ stmw r26, 8(r1)
+/* 801D8994 001D45F4 7F 64 1A 14 */ add r27, r4, r3
+/* 801D8998 001D45F8 3B 7B FF FF */ addi r27, r27, -1
+/* 801D899C 001D45FC 7C BA 2B 78 */ mr r26, r5
+/* 801D89A0 001D4600 7C 1B 18 40 */ cmplw r27, r3
+/* 801D89A4 001D4604 38 A0 07 00 */ li r5, 0x700
+/* 801D89A8 001D4608 40 80 00 0C */ bge lbl_801D89B4
+/* 801D89AC 001D460C 38 60 07 00 */ li r3, 0x700
+/* 801D89B0 001D4610 48 00 02 64 */ b lbl_801D8C14
+lbl_801D89B4:
+/* 801D89B4 001D4614 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha
+/* 801D89B8 001D4618 38 C0 00 00 */ li r6, 0
+/* 801D89BC 001D461C 3B E4 D6 B8 */ addi r31, r4, lbl_803FD6B8@l
+/* 801D89C0 001D4620 80 1F 00 04 */ lwz r0, 4(r31)
+/* 801D89C4 001D4624 7C 03 00 40 */ cmplw r3, r0
+/* 801D89C8 001D4628 41 81 02 48 */ bgt lbl_801D8C10
+/* 801D89CC 001D462C 80 1F 00 00 */ lwz r0, 0(r31)
+/* 801D89D0 001D4630 7C 1B 00 40 */ cmplw r27, r0
+/* 801D89D4 001D4634 41 80 02 3C */ blt lbl_801D8C10
+/* 801D89D8 001D4638 2C 1A 00 00 */ cmpwi r26, 0
+/* 801D89DC 001D463C 40 82 00 18 */ bne lbl_801D89F4
+/* 801D89E0 001D4640 54 C0 20 36 */ slwi r0, r6, 4
+/* 801D89E4 001D4644 7C 9F 02 14 */ add r4, r31, r0
+/* 801D89E8 001D4648 80 04 00 08 */ lwz r0, 8(r4)
+/* 801D89EC 001D464C 2C 00 00 00 */ cmpwi r0, 0
+/* 801D89F0 001D4650 41 82 00 28 */ beq lbl_801D8A18
+lbl_801D89F4:
+/* 801D89F4 001D4654 2C 1A 00 01 */ cmpwi r26, 1
+/* 801D89F8 001D4658 40 82 00 28 */ bne lbl_801D8A20
+/* 801D89FC 001D465C 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha
+/* 801D8A00 001D4660 54 C0 20 36 */ slwi r0, r6, 4
+/* 801D8A04 001D4664 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l
+/* 801D8A08 001D4668 7C 84 02 14 */ add r4, r4, r0
+/* 801D8A0C 001D466C 80 04 00 0C */ lwz r0, 0xc(r4)
+/* 801D8A10 001D4670 2C 00 00 00 */ cmpwi r0, 0
+/* 801D8A14 001D4674 40 82 00 0C */ bne lbl_801D8A20
+lbl_801D8A18:
+/* 801D8A18 001D4678 38 A0 07 00 */ li r5, 0x700
+/* 801D8A1C 001D467C 48 00 01 F4 */ b lbl_801D8C10
+lbl_801D8A20:
+/* 801D8A20 001D4680 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha
+/* 801D8A24 001D4684 54 DD 20 36 */ slwi r29, r6, 4
+/* 801D8A28 001D4688 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l
+/* 801D8A2C 001D468C 38 A0 00 00 */ li r5, 0
+/* 801D8A30 001D4690 7C 04 E8 2E */ lwzx r0, r4, r29
+/* 801D8A34 001D4694 7C 03 00 40 */ cmplw r3, r0
+/* 801D8A38 001D4698 40 80 00 E4 */ bge lbl_801D8B1C
+/* 801D8A3C 001D469C 7C 03 00 50 */ subf r0, r3, r0
+/* 801D8A40 001D46A0 38 C0 07 00 */ li r6, 0x700
+/* 801D8A44 001D46A4 7F C0 1A 14 */ add r30, r0, r3
+/* 801D8A48 001D46A8 3B DE FF FF */ addi r30, r30, -1
+/* 801D8A4C 001D46AC 7C 1E 18 40 */ cmplw r30, r3
+/* 801D8A50 001D46B0 40 80 00 08 */ bge lbl_801D8A58
+/* 801D8A54 001D46B4 48 00 00 C4 */ b lbl_801D8B18
+lbl_801D8A58:
+/* 801D8A58 001D46B8 80 1F 00 04 */ lwz r0, 4(r31)
+/* 801D8A5C 001D46BC 38 A0 00 00 */ li r5, 0
+/* 801D8A60 001D46C0 7C 03 00 40 */ cmplw r3, r0
+/* 801D8A64 001D46C4 41 81 00 B4 */ bgt lbl_801D8B18
+/* 801D8A68 001D46C8 80 1F 00 00 */ lwz r0, 0(r31)
+/* 801D8A6C 001D46CC 7C 1E 00 40 */ cmplw r30, r0
+/* 801D8A70 001D46D0 41 80 00 A8 */ blt lbl_801D8B18
+/* 801D8A74 001D46D4 2C 1A 00 00 */ cmpwi r26, 0
+/* 801D8A78 001D46D8 40 82 00 18 */ bne lbl_801D8A90
+/* 801D8A7C 001D46DC 54 A0 20 36 */ slwi r0, r5, 4
+/* 801D8A80 001D46E0 7C 84 02 14 */ add r4, r4, r0
+/* 801D8A84 001D46E4 80 04 00 08 */ lwz r0, 8(r4)
+/* 801D8A88 001D46E8 2C 00 00 00 */ cmpwi r0, 0
+/* 801D8A8C 001D46EC 41 82 00 28 */ beq lbl_801D8AB4
+lbl_801D8A90:
+/* 801D8A90 001D46F0 2C 1A 00 01 */ cmpwi r26, 1
+/* 801D8A94 001D46F4 40 82 00 28 */ bne lbl_801D8ABC
+/* 801D8A98 001D46F8 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha
+/* 801D8A9C 001D46FC 54 A0 20 36 */ slwi r0, r5, 4
+/* 801D8AA0 001D4700 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l
+/* 801D8AA4 001D4704 7C 84 02 14 */ add r4, r4, r0
+/* 801D8AA8 001D4708 80 04 00 0C */ lwz r0, 0xc(r4)
+/* 801D8AAC 001D470C 2C 00 00 00 */ cmpwi r0, 0
+/* 801D8AB0 001D4710 40 82 00 0C */ bne lbl_801D8ABC
+lbl_801D8AB4:
+/* 801D8AB4 001D4714 38 C0 07 00 */ li r6, 0x700
+/* 801D8AB8 001D4718 48 00 00 60 */ b lbl_801D8B18
+lbl_801D8ABC:
+/* 801D8ABC 001D471C 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha
+/* 801D8AC0 001D4720 54 BC 20 36 */ slwi r28, r5, 4
+/* 801D8AC4 001D4724 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l
+/* 801D8AC8 001D4728 38 C0 00 00 */ li r6, 0
+/* 801D8ACC 001D472C 7C 04 E0 2E */ lwzx r0, r4, r28
+/* 801D8AD0 001D4730 7C 03 00 40 */ cmplw r3, r0
+/* 801D8AD4 001D4734 40 80 00 14 */ bge lbl_801D8AE8
+/* 801D8AD8 001D4738 7F 45 D3 78 */ mr r5, r26
+/* 801D8ADC 001D473C 7C 83 00 50 */ subf r4, r3, r0
+/* 801D8AE0 001D4740 4B FF FE A5 */ bl TRKValidMemory32
+/* 801D8AE4 001D4744 7C 66 1B 78 */ mr r6, r3
+lbl_801D8AE8:
+/* 801D8AE8 001D4748 2C 06 00 00 */ cmpwi r6, 0
+/* 801D8AEC 001D474C 40 82 00 2C */ bne lbl_801D8B18
+/* 801D8AF0 001D4750 3C 60 80 40 */ lis r3, lbl_803FD6B8@ha
+/* 801D8AF4 001D4754 38 03 D6 B8 */ addi r0, r3, lbl_803FD6B8@l
+/* 801D8AF8 001D4758 7C 60 E2 14 */ add r3, r0, r28
+/* 801D8AFC 001D475C 80 63 00 04 */ lwz r3, 4(r3)
+/* 801D8B00 001D4760 7C 1E 18 40 */ cmplw r30, r3
+/* 801D8B04 001D4764 40 81 00 14 */ ble lbl_801D8B18
+/* 801D8B08 001D4768 7F 45 D3 78 */ mr r5, r26
+/* 801D8B0C 001D476C 7C 83 F0 50 */ subf r4, r3, r30
+/* 801D8B10 001D4770 4B FF FE 75 */ bl TRKValidMemory32
+/* 801D8B14 001D4774 7C 66 1B 78 */ mr r6, r3
+lbl_801D8B18:
+/* 801D8B18 001D4778 7C C5 33 78 */ mr r5, r6
+lbl_801D8B1C:
+/* 801D8B1C 001D477C 2C 05 00 00 */ cmpwi r5, 0
+/* 801D8B20 001D4780 40 82 00 F0 */ bne lbl_801D8C10
+/* 801D8B24 001D4784 3C 60 80 40 */ lis r3, lbl_803FD6B8@ha
+/* 801D8B28 001D4788 38 83 D6 B8 */ addi r4, r3, lbl_803FD6B8@l
+/* 801D8B2C 001D478C 3B 84 00 04 */ addi r28, r4, 4
+/* 801D8B30 001D4790 7C 7C E8 2E */ lwzx r3, r28, r29
+/* 801D8B34 001D4794 7C 1B 18 40 */ cmplw r27, r3
+/* 801D8B38 001D4798 40 81 00 D8 */ ble lbl_801D8C10
+/* 801D8B3C 001D479C 7C 03 D8 50 */ subf r0, r3, r27
+/* 801D8B40 001D47A0 38 C0 07 00 */ li r6, 0x700
+/* 801D8B44 001D47A4 7F C0 1A 14 */ add r30, r0, r3
+/* 801D8B48 001D47A8 3B DE FF FF */ addi r30, r30, -1
+/* 801D8B4C 001D47AC 7C 1E 18 40 */ cmplw r30, r3
+/* 801D8B50 001D47B0 40 80 00 08 */ bge lbl_801D8B58
+/* 801D8B54 001D47B4 48 00 00 B8 */ b lbl_801D8C0C
+lbl_801D8B58:
+/* 801D8B58 001D47B8 80 1F 00 04 */ lwz r0, 4(r31)
+/* 801D8B5C 001D47BC 38 A0 00 00 */ li r5, 0
+/* 801D8B60 001D47C0 7C 03 00 40 */ cmplw r3, r0
+/* 801D8B64 001D47C4 41 81 00 A8 */ bgt lbl_801D8C0C
+/* 801D8B68 001D47C8 80 1F 00 00 */ lwz r0, 0(r31)
+/* 801D8B6C 001D47CC 7C 1E 00 40 */ cmplw r30, r0
+/* 801D8B70 001D47D0 41 80 00 9C */ blt lbl_801D8C0C
+/* 801D8B74 001D47D4 2C 1A 00 00 */ cmpwi r26, 0
+/* 801D8B78 001D47D8 40 82 00 18 */ bne lbl_801D8B90
+/* 801D8B7C 001D47DC 54 A0 20 36 */ slwi r0, r5, 4
+/* 801D8B80 001D47E0 7C 84 02 14 */ add r4, r4, r0
+/* 801D8B84 001D47E4 80 04 00 08 */ lwz r0, 8(r4)
+/* 801D8B88 001D47E8 2C 00 00 00 */ cmpwi r0, 0
+/* 801D8B8C 001D47EC 41 82 00 28 */ beq lbl_801D8BB4
+lbl_801D8B90:
+/* 801D8B90 001D47F0 2C 1A 00 01 */ cmpwi r26, 1
+/* 801D8B94 001D47F4 40 82 00 28 */ bne lbl_801D8BBC
+/* 801D8B98 001D47F8 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha
+/* 801D8B9C 001D47FC 54 A0 20 36 */ slwi r0, r5, 4
+/* 801D8BA0 001D4800 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l
+/* 801D8BA4 001D4804 7C 84 02 14 */ add r4, r4, r0
+/* 801D8BA8 001D4808 80 04 00 0C */ lwz r0, 0xc(r4)
+/* 801D8BAC 001D480C 2C 00 00 00 */ cmpwi r0, 0
+/* 801D8BB0 001D4810 40 82 00 0C */ bne lbl_801D8BBC
+lbl_801D8BB4:
+/* 801D8BB4 001D4814 38 C0 07 00 */ li r6, 0x700
+/* 801D8BB8 001D4818 48 00 00 54 */ b lbl_801D8C0C
+lbl_801D8BBC:
+/* 801D8BBC 001D481C 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha
+/* 801D8BC0 001D4820 54 BB 20 36 */ slwi r27, r5, 4
+/* 801D8BC4 001D4824 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l
+/* 801D8BC8 001D4828 38 C0 00 00 */ li r6, 0
+/* 801D8BCC 001D482C 7C 04 D8 2E */ lwzx r0, r4, r27
+/* 801D8BD0 001D4830 7C 03 00 40 */ cmplw r3, r0
+/* 801D8BD4 001D4834 40 80 00 14 */ bge lbl_801D8BE8
+/* 801D8BD8 001D4838 7F 45 D3 78 */ mr r5, r26
+/* 801D8BDC 001D483C 7C 83 00 50 */ subf r4, r3, r0
+/* 801D8BE0 001D4840 4B FF FD A5 */ bl TRKValidMemory32
+/* 801D8BE4 001D4844 7C 66 1B 78 */ mr r6, r3
+lbl_801D8BE8:
+/* 801D8BE8 001D4848 2C 06 00 00 */ cmpwi r6, 0
+/* 801D8BEC 001D484C 40 82 00 20 */ bne lbl_801D8C0C
+/* 801D8BF0 001D4850 7C 7C D8 2E */ lwzx r3, r28, r27
+/* 801D8BF4 001D4854 7C 1E 18 40 */ cmplw r30, r3
+/* 801D8BF8 001D4858 40 81 00 14 */ ble lbl_801D8C0C
+/* 801D8BFC 001D485C 7F 45 D3 78 */ mr r5, r26
+/* 801D8C00 001D4860 7C 83 F0 50 */ subf r4, r3, r30
+/* 801D8C04 001D4864 4B FF FD 81 */ bl TRKValidMemory32
+/* 801D8C08 001D4868 7C 66 1B 78 */ mr r6, r3
+lbl_801D8C0C:
+/* 801D8C0C 001D486C 7C C5 33 78 */ mr r5, r6
+lbl_801D8C10:
+/* 801D8C10 001D4870 7C A3 2B 78 */ mr r3, r5
+lbl_801D8C14:
+/* 801D8C14 001D4874 BB 41 00 08 */ lmw r26, 8(r1)
+/* 801D8C18 001D4878 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D8C1C 001D487C 7C 08 03 A6 */ mtlr r0
+/* 801D8C20 001D4880 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D8C24 001D4884 4E 80 00 20 */ blr
+/* 801D8C28 001D4888 00 00 00 00 */ .4byte 0x00000000 /* unknown instruction */
+/* 801D8C2C 001D488C 00 00 00 00 */ .4byte 0x00000000 /* unknown instruction */
diff --git a/asm/MetroTRK/usr_put.s b/asm/MetroTRK/usr_put.s new file mode 100644 index 0000000..3278225 --- /dev/null +++ b/asm/MetroTRK/usr_put.s @@ -0,0 +1,47 @@ +.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global usr_put_initialize
+usr_put_initialize:
+/* 801D56F0 001D1350 4E 80 00 20 */ blr
+
+.global usr_puts_serial
+usr_puts_serial:
+/* 801D56F4 001D1354 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D56F8 001D1358 7C 08 02 A6 */ mflr r0
+/* 801D56FC 001D135C 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D5700 001D1360 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D5704 001D1364 3B E0 00 00 */ li r31, 0
+/* 801D5708 001D1368 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D570C 001D136C 93 A1 00 14 */ stw r29, 0x14(r1)
+/* 801D5710 001D1370 7C 7D 1B 78 */ mr r29, r3
+/* 801D5714 001D1374 38 60 00 00 */ li r3, 0
+/* 801D5718 001D1378 48 00 00 30 */ b lbl_801D5748
+lbl_801D571C:
+/* 801D571C 001D137C 48 00 12 75 */ bl GetTRKConnected
+/* 801D5720 001D1380 9B C1 00 08 */ stb r30, 8(r1)
+/* 801D5724 001D1384 7C 7E 1B 78 */ mr r30, r3
+/* 801D5728 001D1388 38 60 00 00 */ li r3, 0
+/* 801D572C 001D138C 9B E1 00 09 */ stb r31, 9(r1)
+/* 801D5730 001D1390 48 00 12 55 */ bl SetTRKConnected
+/* 801D5734 001D1394 38 61 00 08 */ addi r3, r1, 8
+/* 801D5738 001D1398 4B E3 23 8D */ bl func_80007AC4
+/* 801D573C 001D139C 7F C3 F3 78 */ mr r3, r30
+/* 801D5740 001D13A0 48 00 12 45 */ bl SetTRKConnected
+/* 801D5744 001D13A4 38 60 00 00 */ li r3, 0
+lbl_801D5748:
+/* 801D5748 001D13A8 2C 03 00 00 */ cmpwi r3, 0
+/* 801D574C 001D13AC 40 82 00 14 */ bne lbl_801D5760
+/* 801D5750 001D13B0 88 1D 00 00 */ lbz r0, 0(r29)
+/* 801D5754 001D13B4 3B BD 00 01 */ addi r29, r29, 1
+/* 801D5758 001D13B8 7C 1E 07 75 */ extsb. r30, r0
+/* 801D575C 001D13BC 40 82 FF C0 */ bne lbl_801D571C
+lbl_801D5760:
+/* 801D5760 001D13C0 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D5764 001D13C4 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D5768 001D13C8 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D576C 001D13CC 83 A1 00 14 */ lwz r29, 0x14(r1)
+/* 801D5770 001D13D0 7C 08 03 A6 */ mtlr r0
+/* 801D5774 001D13D4 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D5778 001D13D8 4E 80 00 20 */ blr
diff --git a/asm/text_6.s b/asm/text_6.s deleted file mode 100644 index d692e4f..0000000 --- a/asm/text_6.s +++ /dev/null @@ -1,2933 +0,0 @@ -.include "macros.inc" - -.section .text, "ax" # 0x80006980 - 0x803E1E60 - -.global func_801D4930 -func_801D4930: -/* 801D4930 001D0590 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D4934 001D0594 7C 08 02 A6 */ mflr r0 -/* 801D4938 001D0598 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D493C 001D059C 80 63 00 08 */ lwz r3, 8(r3) -/* 801D4940 001D05A0 48 00 0A 39 */ bl TRKReleaseBuffer -/* 801D4944 001D05A4 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D4948 001D05A8 7C 08 03 A6 */ mtlr r0 -/* 801D494C 001D05AC 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D4950 001D05B0 4E 80 00 20 */ blr - -.global TRKConstructEvent -TRKConstructEvent: -/* 801D4954 001D05B4 90 83 00 00 */ stw r4, 0(r3) -/* 801D4958 001D05B8 38 80 00 00 */ li r4, 0 -/* 801D495C 001D05BC 38 00 FF FF */ li r0, -1 -/* 801D4960 001D05C0 90 83 00 04 */ stw r4, 4(r3) -/* 801D4964 001D05C4 90 03 00 08 */ stw r0, 8(r3) -/* 801D4968 001D05C8 4E 80 00 20 */ blr - -.global TRKPostEvent -TRKPostEvent: -/* 801D496C 001D05CC 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D4970 001D05D0 7C 08 02 A6 */ mflr r0 -/* 801D4974 001D05D4 3C 80 80 49 */ lis r4, lbl_8048EDF0@ha -/* 801D4978 001D05D8 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D497C 001D05DC 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D4980 001D05E0 3B E0 00 00 */ li r31, 0 -/* 801D4984 001D05E4 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D4988 001D05E8 93 A1 00 14 */ stw r29, 0x14(r1) -/* 801D498C 001D05EC 7C 7D 1B 78 */ mr r29, r3 -/* 801D4990 001D05F0 38 64 ED F0 */ addi r3, r4, lbl_8048EDF0@l -/* 801D4994 001D05F4 48 00 26 C9 */ bl func_801D705C -/* 801D4998 001D05F8 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha -/* 801D499C 001D05FC 3B C3 ED F0 */ addi r30, r3, lbl_8048EDF0@l -/* 801D49A0 001D0600 80 7E 00 04 */ lwz r3, 4(r30) -/* 801D49A4 001D0604 2C 03 00 02 */ cmpwi r3, 2 -/* 801D49A8 001D0608 40 82 00 0C */ bne lbl_801D49B4 -/* 801D49AC 001D060C 3B E0 01 00 */ li r31, 0x100 -/* 801D49B0 001D0610 48 00 00 70 */ b lbl_801D4A20 -lbl_801D49B4: -/* 801D49B4 001D0614 80 1E 00 08 */ lwz r0, 8(r30) -/* 801D49B8 001D0618 7F A4 EB 78 */ mr r4, r29 -/* 801D49BC 001D061C 38 A0 00 0C */ li r5, 0xc -/* 801D49C0 001D0620 7C 00 1A 14 */ add r0, r0, r3 -/* 801D49C4 001D0624 54 03 0F FE */ srwi r3, r0, 0x1f -/* 801D49C8 001D0628 54 00 07 FE */ clrlwi r0, r0, 0x1f -/* 801D49CC 001D062C 7C 00 1A 78 */ xor r0, r0, r3 -/* 801D49D0 001D0630 7C 03 00 50 */ subf r0, r3, r0 -/* 801D49D4 001D0634 1F A0 00 0C */ mulli r29, r0, 0xc -/* 801D49D8 001D0638 7C 7E EA 14 */ add r3, r30, r29 -/* 801D49DC 001D063C 38 63 00 0C */ addi r3, r3, 0xc -/* 801D49E0 001D0640 4B E2 F7 85 */ bl TRK_memcpy -/* 801D49E4 001D0644 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha -/* 801D49E8 001D0648 38 83 ED F0 */ addi r4, r3, lbl_8048EDF0@l -/* 801D49EC 001D064C 80 04 00 24 */ lwz r0, 0x24(r4) -/* 801D49F0 001D0650 7C 64 EA 14 */ add r3, r4, r29 -/* 801D49F4 001D0654 90 03 00 10 */ stw r0, 0x10(r3) -/* 801D49F8 001D0658 80 64 00 24 */ lwz r3, 0x24(r4) -/* 801D49FC 001D065C 38 03 00 01 */ addi r0, r3, 1 -/* 801D4A00 001D0660 28 00 01 00 */ cmplwi r0, 0x100 -/* 801D4A04 001D0664 90 04 00 24 */ stw r0, 0x24(r4) -/* 801D4A08 001D0668 40 80 00 0C */ bge lbl_801D4A14 -/* 801D4A0C 001D066C 38 00 01 00 */ li r0, 0x100 -/* 801D4A10 001D0670 90 04 00 24 */ stw r0, 0x24(r4) -lbl_801D4A14: -/* 801D4A14 001D0674 80 7E 00 04 */ lwz r3, 4(r30) -/* 801D4A18 001D0678 38 03 00 01 */ addi r0, r3, 1 -/* 801D4A1C 001D067C 90 1E 00 04 */ stw r0, 4(r30) -lbl_801D4A20: -/* 801D4A20 001D0680 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha -/* 801D4A24 001D0684 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l -/* 801D4A28 001D0688 48 00 26 2D */ bl func_801D7054 -/* 801D4A2C 001D068C 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D4A30 001D0690 7F E3 FB 78 */ mr r3, r31 -/* 801D4A34 001D0694 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D4A38 001D0698 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D4A3C 001D069C 83 A1 00 14 */ lwz r29, 0x14(r1) -/* 801D4A40 001D06A0 7C 08 03 A6 */ mtlr r0 -/* 801D4A44 001D06A4 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D4A48 001D06A8 4E 80 00 20 */ blr - -.global TRKGetNextEvent -TRKGetNextEvent: -/* 801D4A4C 001D06AC 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D4A50 001D06B0 7C 08 02 A6 */ mflr r0 -/* 801D4A54 001D06B4 3C 80 80 49 */ lis r4, lbl_8048EDF0@ha -/* 801D4A58 001D06B8 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D4A5C 001D06BC 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D4A60 001D06C0 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D4A64 001D06C4 3B C0 00 00 */ li r30, 0 -/* 801D4A68 001D06C8 93 A1 00 14 */ stw r29, 0x14(r1) -/* 801D4A6C 001D06CC 7C 7D 1B 78 */ mr r29, r3 -/* 801D4A70 001D06D0 38 64 ED F0 */ addi r3, r4, lbl_8048EDF0@l -/* 801D4A74 001D06D4 48 00 25 E9 */ bl func_801D705C -/* 801D4A78 001D06D8 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha -/* 801D4A7C 001D06DC 3B E3 ED F0 */ addi r31, r3, lbl_8048EDF0@l -/* 801D4A80 001D06E0 80 1F 00 04 */ lwz r0, 4(r31) -/* 801D4A84 001D06E4 2C 00 00 00 */ cmpwi r0, 0 -/* 801D4A88 001D06E8 40 81 00 4C */ ble lbl_801D4AD4 -/* 801D4A8C 001D06EC 80 1F 00 08 */ lwz r0, 8(r31) -/* 801D4A90 001D06F0 7F A3 EB 78 */ mr r3, r29 -/* 801D4A94 001D06F4 38 A0 00 0C */ li r5, 0xc -/* 801D4A98 001D06F8 1C 00 00 0C */ mulli r0, r0, 0xc -/* 801D4A9C 001D06FC 7C 9F 02 14 */ add r4, r31, r0 -/* 801D4AA0 001D0700 38 84 00 0C */ addi r4, r4, 0xc -/* 801D4AA4 001D0704 4B E2 F6 C1 */ bl TRK_memcpy -/* 801D4AA8 001D0708 80 7F 00 08 */ lwz r3, 8(r31) -/* 801D4AAC 001D070C 80 9F 00 04 */ lwz r4, 4(r31) -/* 801D4AB0 001D0710 38 03 00 01 */ addi r0, r3, 1 -/* 801D4AB4 001D0714 38 64 FF FF */ addi r3, r4, -1 -/* 801D4AB8 001D0718 90 1F 00 08 */ stw r0, 8(r31) -/* 801D4ABC 001D071C 2C 00 00 02 */ cmpwi r0, 2 -/* 801D4AC0 001D0720 90 7F 00 04 */ stw r3, 4(r31) -/* 801D4AC4 001D0724 40 82 00 0C */ bne lbl_801D4AD0 -/* 801D4AC8 001D0728 38 00 00 00 */ li r0, 0 -/* 801D4ACC 001D072C 90 1F 00 08 */ stw r0, 8(r31) -lbl_801D4AD0: -/* 801D4AD0 001D0730 3B C0 00 01 */ li r30, 1 -lbl_801D4AD4: -/* 801D4AD4 001D0734 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha -/* 801D4AD8 001D0738 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l -/* 801D4ADC 001D073C 48 00 25 79 */ bl func_801D7054 -/* 801D4AE0 001D0740 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D4AE4 001D0744 7F C3 F3 78 */ mr r3, r30 -/* 801D4AE8 001D0748 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D4AEC 001D074C 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D4AF0 001D0750 83 A1 00 14 */ lwz r29, 0x14(r1) -/* 801D4AF4 001D0754 7C 08 03 A6 */ mtlr r0 -/* 801D4AF8 001D0758 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D4AFC 001D075C 4E 80 00 20 */ blr - -.global TRKInitializeEventQueue -TRKInitializeEventQueue: -/* 801D4B00 001D0760 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D4B04 001D0764 7C 08 02 A6 */ mflr r0 -/* 801D4B08 001D0768 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha -/* 801D4B0C 001D076C 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D4B10 001D0770 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l -/* 801D4B14 001D0774 48 00 25 51 */ bl func_801D7064 -/* 801D4B18 001D0778 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha -/* 801D4B1C 001D077C 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l -/* 801D4B20 001D0780 48 00 25 3D */ bl func_801D705C -/* 801D4B24 001D0784 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha -/* 801D4B28 001D0788 38 80 00 00 */ li r4, 0 -/* 801D4B2C 001D078C 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l -/* 801D4B30 001D0790 38 00 01 00 */ li r0, 0x100 -/* 801D4B34 001D0794 90 83 00 04 */ stw r4, 4(r3) -/* 801D4B38 001D0798 90 83 00 08 */ stw r4, 8(r3) -/* 801D4B3C 001D079C 90 03 00 24 */ stw r0, 0x24(r3) -/* 801D4B40 001D07A0 48 00 25 15 */ bl func_801D7054 -/* 801D4B44 001D07A4 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D4B48 001D07A8 38 60 00 00 */ li r3, 0 -/* 801D4B4C 001D07AC 7C 08 03 A6 */ mtlr r0 -/* 801D4B50 001D07B0 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D4B54 001D07B4 4E 80 00 20 */ blr - -.global TRKNubWelcome -TRKNubWelcome: -/* 801D4B58 001D07B8 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D4B5C 001D07BC 7C 08 02 A6 */ mflr r0 -/* 801D4B60 001D07C0 3C 60 80 40 */ lis r3, lbl_803FD640@ha -/* 801D4B64 001D07C4 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D4B68 001D07C8 38 63 D6 40 */ addi r3, r3, lbl_803FD640@l -/* 801D4B6C 001D07CC 48 00 4A 11 */ bl TRK_board_display -/* 801D4B70 001D07D0 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D4B74 001D07D4 7C 08 03 A6 */ mtlr r0 -/* 801D4B78 001D07D8 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D4B7C 001D07DC 4E 80 00 20 */ blr - -.global func_801D4B80 -func_801D4B80: -/* 801D4B80 001D07E0 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D4B84 001D07E4 7C 08 02 A6 */ mflr r0 -/* 801D4B88 001D07E8 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D4B8C 001D07EC 48 00 09 B9 */ bl func_801D5544 -/* 801D4B90 001D07F0 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D4B94 001D07F4 38 60 00 00 */ li r3, 0 -/* 801D4B98 001D07F8 7C 08 03 A6 */ mtlr r0 -/* 801D4B9C 001D07FC 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D4BA0 001D0800 4E 80 00 20 */ blr - -.global func_801D4BA4 -func_801D4BA4: -/* 801D4BA4 001D0804 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D4BA8 001D0808 7C 08 02 A6 */ mflr r0 -/* 801D4BAC 001D080C 38 A0 00 12 */ li r5, 0x12 -/* 801D4BB0 001D0810 38 80 00 34 */ li r4, 0x34 -/* 801D4BB4 001D0814 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D4BB8 001D0818 38 60 00 56 */ li r3, 0x56 -/* 801D4BBC 001D081C 38 00 00 78 */ li r0, 0x78 -/* 801D4BC0 001D0820 38 C0 00 01 */ li r6, 1 -/* 801D4BC4 001D0824 98 A1 00 08 */ stb r5, 8(r1) -/* 801D4BC8 001D0828 3C A0 80 49 */ lis r5, lbl_8048EE18@ha -/* 801D4BCC 001D082C 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D4BD0 001D0830 3B E0 00 00 */ li r31, 0 -/* 801D4BD4 001D0834 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D4BD8 001D0838 98 81 00 09 */ stb r4, 9(r1) -/* 801D4BDC 001D083C 98 61 00 0A */ stb r3, 0xa(r1) -/* 801D4BE0 001D0840 98 01 00 0B */ stb r0, 0xb(r1) -/* 801D4BE4 001D0844 80 61 00 08 */ lwz r3, 8(r1) -/* 801D4BE8 001D0848 94 C5 EE 18 */ stwu r6, lbl_8048EE18@l(r5) -/* 801D4BEC 001D084C 3C 03 ED CC */ addis r0, r3, 0xedcc -/* 801D4BF0 001D0850 28 00 56 78 */ cmplwi r0, 0x5678 -/* 801D4BF4 001D0854 40 82 00 0C */ bne lbl_801D4C00 -/* 801D4BF8 001D0858 90 C5 00 00 */ stw r6, 0(r5) -/* 801D4BFC 001D085C 48 00 00 1C */ b lbl_801D4C18 -lbl_801D4C00: -/* 801D4C00 001D0860 3C 03 87 AA */ addis r0, r3, 0x87aa -/* 801D4C04 001D0864 28 00 34 12 */ cmplwi r0, 0x3412 -/* 801D4C08 001D0868 40 82 00 0C */ bne lbl_801D4C14 -/* 801D4C0C 001D086C 93 E5 00 00 */ stw r31, 0(r5) -/* 801D4C10 001D0870 48 00 00 08 */ b lbl_801D4C18 -lbl_801D4C14: -/* 801D4C14 001D0874 7C DF 33 78 */ mr r31, r6 -lbl_801D4C18: -/* 801D4C18 001D0878 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D4C1C 001D087C 40 82 00 08 */ bne lbl_801D4C24 -/* 801D4C20 001D0880 48 00 0A D1 */ bl func_801D56F0 -lbl_801D4C24: -/* 801D4C24 001D0884 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D4C28 001D0888 40 82 00 0C */ bne lbl_801D4C34 -/* 801D4C2C 001D088C 4B FF FE D5 */ bl TRKInitializeEventQueue -/* 801D4C30 001D0890 7C 7F 1B 78 */ mr r31, r3 -lbl_801D4C34: -/* 801D4C34 001D0894 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D4C38 001D0898 40 82 00 0C */ bne lbl_801D4C44 -/* 801D4C3C 001D089C 48 00 08 95 */ bl TRKInitializeMessageBuffers -/* 801D4C40 001D08A0 7C 7F 1B 78 */ mr r31, r3 -lbl_801D4C44: -/* 801D4C44 001D08A4 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D4C48 001D08A8 40 82 00 0C */ bne lbl_801D4C54 -/* 801D4C4C 001D08AC 48 00 0C 71 */ bl func_801D58BC -/* 801D4C50 001D08B0 7C 7F 1B 78 */ mr r31, r3 -lbl_801D4C54: -/* 801D4C54 001D08B4 48 00 48 D1 */ bl InitializeProgramEndTrap -/* 801D4C58 001D08B8 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D4C5C 001D08BC 40 82 00 0C */ bne lbl_801D4C68 -/* 801D4C60 001D08C0 48 00 08 ED */ bl func_801D554C -/* 801D4C64 001D08C4 7C 7F 1B 78 */ mr r31, r3 -lbl_801D4C68: -/* 801D4C68 001D08C8 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D4C6C 001D08CC 40 82 00 0C */ bne lbl_801D4C78 -/* 801D4C70 001D08D0 48 00 45 F5 */ bl TRKInitializeTarget -/* 801D4C74 001D08D4 7C 7F 1B 78 */ mr r31, r3 -lbl_801D4C78: -/* 801D4C78 001D08D8 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D4C7C 001D08DC 40 82 00 44 */ bne lbl_801D4CC0 -/* 801D4C80 001D08E0 3C 60 80 64 */ lis r3, lbl_8063F2A0@ha -/* 801D4C84 001D08E4 3C A0 00 01 */ lis r5, 0x0000E100@ha -/* 801D4C88 001D08E8 38 C3 F2 A0 */ addi r6, r3, lbl_8063F2A0@l -/* 801D4C8C 001D08EC 38 80 00 01 */ li r4, 1 -/* 801D4C90 001D08F0 38 65 E1 00 */ addi r3, r5, 0x0000E100@l -/* 801D4C94 001D08F4 38 A0 00 00 */ li r5, 0 -/* 801D4C98 001D08F8 48 00 4A 65 */ bl TRKInitializeIntDrivenUART -/* 801D4C9C 001D08FC 3C 80 80 64 */ lis r4, lbl_8063F2A0@ha -/* 801D4CA0 001D0900 7C 60 1B 78 */ mr r0, r3 -/* 801D4CA4 001D0904 38 64 F2 A0 */ addi r3, r4, lbl_8063F2A0@l -/* 801D4CA8 001D0908 80 63 00 00 */ lwz r3, 0(r3) -/* 801D4CAC 001D090C 7C 1E 03 78 */ mr r30, r0 -/* 801D4CB0 001D0910 48 00 29 3D */ bl func_801D75EC -/* 801D4CB4 001D0914 2C 1E 00 00 */ cmpwi r30, 0 -/* 801D4CB8 001D0918 41 82 00 08 */ beq lbl_801D4CC0 -/* 801D4CBC 001D091C 7F DF F3 78 */ mr r31, r30 -lbl_801D4CC0: -/* 801D4CC0 001D0920 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D4CC4 001D0924 7F E3 FB 78 */ mr r3, r31 -/* 801D4CC8 001D0928 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D4CCC 001D092C 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D4CD0 001D0930 7C 08 03 A6 */ mtlr r0 -/* 801D4CD4 001D0934 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D4CD8 001D0938 4E 80 00 20 */ blr - -.global func_801D4CDC -func_801D4CDC: -/* 801D4CDC 001D093C 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D4CE0 001D0940 7C 08 02 A6 */ mflr r0 -/* 801D4CE4 001D0944 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D4CE8 001D0948 80 83 00 08 */ lwz r4, 8(r3) -/* 801D4CEC 001D094C 38 63 00 10 */ addi r3, r3, 0x10 -/* 801D4CF0 001D0950 48 00 49 1D */ bl func_801D960C -/* 801D4CF4 001D0954 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D4CF8 001D0958 38 60 00 00 */ li r3, 0 -/* 801D4CFC 001D095C 7C 08 03 A6 */ mtlr r0 -/* 801D4D00 001D0960 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D4D04 001D0964 4E 80 00 20 */ blr - -.global TRKReadBuffer_ui32 -TRKReadBuffer_ui32: -/* 801D4D08 001D0968 94 21 FF D0 */ stwu r1, -0x30(r1) -/* 801D4D0C 001D096C 7C 08 02 A6 */ mflr r0 -/* 801D4D10 001D0970 3C C0 80 49 */ lis r6, lbl_8048EE18@ha -/* 801D4D14 001D0974 90 01 00 34 */ stw r0, 0x34(r1) -/* 801D4D18 001D0978 BF 01 00 10 */ stmw r24, 0x10(r1) -/* 801D4D1C 001D097C 7C 7C 1B 78 */ mr r28, r3 -/* 801D4D20 001D0980 7C BD 2B 78 */ mr r29, r5 -/* 801D4D24 001D0984 7C 9F 23 78 */ mr r31, r4 -/* 801D4D28 001D0988 3B 66 EE 18 */ addi r27, r6, lbl_8048EE18@l -/* 801D4D2C 001D098C 3B C0 00 00 */ li r30, 0 -/* 801D4D30 001D0990 38 60 00 00 */ li r3, 0 -/* 801D4D34 001D0994 48 00 00 A0 */ b lbl_801D4DD4 -lbl_801D4D38: -/* 801D4D38 001D0998 80 1B 00 00 */ lwz r0, 0(r27) -/* 801D4D3C 001D099C 2C 00 00 00 */ cmpwi r0, 0 -/* 801D4D40 001D09A0 41 82 00 0C */ beq lbl_801D4D4C -/* 801D4D44 001D09A4 7F F9 FB 78 */ mr r25, r31 -/* 801D4D48 001D09A8 48 00 00 08 */ b lbl_801D4D50 -lbl_801D4D4C: -/* 801D4D4C 001D09AC 3B 21 00 08 */ addi r25, r1, 8 -lbl_801D4D50: -/* 801D4D50 001D09B0 80 7C 00 0C */ lwz r3, 0xc(r28) -/* 801D4D54 001D09B4 3B 00 00 04 */ li r24, 4 -/* 801D4D58 001D09B8 80 1C 00 08 */ lwz r0, 8(r28) -/* 801D4D5C 001D09BC 3B 40 00 00 */ li r26, 0 -/* 801D4D60 001D09C0 7C 03 00 50 */ subf r0, r3, r0 -/* 801D4D64 001D09C4 7C 18 00 40 */ cmplw r24, r0 -/* 801D4D68 001D09C8 40 81 00 0C */ ble lbl_801D4D74 -/* 801D4D6C 001D09CC 3B 40 03 02 */ li r26, 0x302 -/* 801D4D70 001D09D0 7C 18 03 78 */ mr r24, r0 -lbl_801D4D74: -/* 801D4D74 001D09D4 38 83 00 10 */ addi r4, r3, 0x10 -/* 801D4D78 001D09D8 7F 23 CB 78 */ mr r3, r25 -/* 801D4D7C 001D09DC 7F 05 C3 78 */ mr r5, r24 -/* 801D4D80 001D09E0 7C 9C 22 14 */ add r4, r28, r4 -/* 801D4D84 001D09E4 4B E2 F3 E1 */ bl TRK_memcpy -/* 801D4D88 001D09E8 80 1C 00 0C */ lwz r0, 0xc(r28) -/* 801D4D8C 001D09EC 7C 00 C2 14 */ add r0, r0, r24 -/* 801D4D90 001D09F0 90 1C 00 0C */ stw r0, 0xc(r28) -/* 801D4D94 001D09F4 80 1B 00 00 */ lwz r0, 0(r27) -/* 801D4D98 001D09F8 2C 00 00 00 */ cmpwi r0, 0 -/* 801D4D9C 001D09FC 40 82 00 2C */ bne lbl_801D4DC8 -/* 801D4DA0 001D0A00 2C 1A 00 00 */ cmpwi r26, 0 -/* 801D4DA4 001D0A04 40 82 00 24 */ bne lbl_801D4DC8 -/* 801D4DA8 001D0A08 88 19 00 03 */ lbz r0, 3(r25) -/* 801D4DAC 001D0A0C 98 1F 00 00 */ stb r0, 0(r31) -/* 801D4DB0 001D0A10 88 19 00 02 */ lbz r0, 2(r25) -/* 801D4DB4 001D0A14 98 1F 00 01 */ stb r0, 1(r31) -/* 801D4DB8 001D0A18 88 19 00 01 */ lbz r0, 1(r25) -/* 801D4DBC 001D0A1C 98 1F 00 02 */ stb r0, 2(r31) -/* 801D4DC0 001D0A20 88 19 00 00 */ lbz r0, 0(r25) -/* 801D4DC4 001D0A24 98 1F 00 03 */ stb r0, 3(r31) -lbl_801D4DC8: -/* 801D4DC8 001D0A28 7F 43 D3 78 */ mr r3, r26 -/* 801D4DCC 001D0A2C 3B FF 00 04 */ addi r31, r31, 4 -/* 801D4DD0 001D0A30 3B DE 00 01 */ addi r30, r30, 1 -lbl_801D4DD4: -/* 801D4DD4 001D0A34 2C 03 00 00 */ cmpwi r3, 0 -/* 801D4DD8 001D0A38 40 82 00 0C */ bne lbl_801D4DE4 -/* 801D4DDC 001D0A3C 7C 1E E8 00 */ cmpw r30, r29 -/* 801D4DE0 001D0A40 41 80 FF 58 */ blt lbl_801D4D38 -lbl_801D4DE4: -/* 801D4DE4 001D0A44 BB 01 00 10 */ lmw r24, 0x10(r1) -/* 801D4DE8 001D0A48 80 01 00 34 */ lwz r0, 0x34(r1) -/* 801D4DEC 001D0A4C 7C 08 03 A6 */ mtlr r0 -/* 801D4DF0 001D0A50 38 21 00 30 */ addi r1, r1, 0x30 -/* 801D4DF4 001D0A54 4E 80 00 20 */ blr - -.global TRKReadBuffer_ui8 -TRKReadBuffer_ui8: -/* 801D4DF8 001D0A58 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D4DFC 001D0A5C 7C 08 02 A6 */ mflr r0 -/* 801D4E00 001D0A60 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D4E04 001D0A64 BF 41 00 08 */ stmw r26, 8(r1) -/* 801D4E08 001D0A68 7C 7A 1B 78 */ mr r26, r3 -/* 801D4E0C 001D0A6C 7C 9B 23 78 */ mr r27, r4 -/* 801D4E10 001D0A70 7C BC 2B 78 */ mr r28, r5 -/* 801D4E14 001D0A74 3B A0 00 00 */ li r29, 0 -/* 801D4E18 001D0A78 38 60 00 00 */ li r3, 0 -/* 801D4E1C 001D0A7C 48 00 00 50 */ b lbl_801D4E6C -lbl_801D4E20: -/* 801D4E20 001D0A80 80 7A 00 0C */ lwz r3, 0xc(r26) -/* 801D4E24 001D0A84 3B C0 00 01 */ li r30, 1 -/* 801D4E28 001D0A88 80 1A 00 08 */ lwz r0, 8(r26) -/* 801D4E2C 001D0A8C 3B E0 00 00 */ li r31, 0 -/* 801D4E30 001D0A90 7C 03 00 50 */ subf r0, r3, r0 -/* 801D4E34 001D0A94 7C 1E 00 40 */ cmplw r30, r0 -/* 801D4E38 001D0A98 40 81 00 0C */ ble lbl_801D4E44 -/* 801D4E3C 001D0A9C 3B E0 03 02 */ li r31, 0x302 -/* 801D4E40 001D0AA0 7C 1E 03 78 */ mr r30, r0 -lbl_801D4E44: -/* 801D4E44 001D0AA4 38 83 00 10 */ addi r4, r3, 0x10 -/* 801D4E48 001D0AA8 7F C5 F3 78 */ mr r5, r30 -/* 801D4E4C 001D0AAC 7C 7B EA 14 */ add r3, r27, r29 -/* 801D4E50 001D0AB0 7C 9A 22 14 */ add r4, r26, r4 -/* 801D4E54 001D0AB4 4B E2 F3 11 */ bl TRK_memcpy -/* 801D4E58 001D0AB8 80 1A 00 0C */ lwz r0, 0xc(r26) -/* 801D4E5C 001D0ABC 7F E3 FB 78 */ mr r3, r31 -/* 801D4E60 001D0AC0 3B BD 00 01 */ addi r29, r29, 1 -/* 801D4E64 001D0AC4 7C 00 F2 14 */ add r0, r0, r30 -/* 801D4E68 001D0AC8 90 1A 00 0C */ stw r0, 0xc(r26) -lbl_801D4E6C: -/* 801D4E6C 001D0ACC 2C 03 00 00 */ cmpwi r3, 0 -/* 801D4E70 001D0AD0 40 82 00 0C */ bne lbl_801D4E7C -/* 801D4E74 001D0AD4 7C 1D E0 00 */ cmpw r29, r28 -/* 801D4E78 001D0AD8 41 80 FF A8 */ blt lbl_801D4E20 -lbl_801D4E7C: -/* 801D4E7C 001D0ADC BB 41 00 08 */ lmw r26, 8(r1) -/* 801D4E80 001D0AE0 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D4E84 001D0AE4 7C 08 03 A6 */ mtlr r0 -/* 801D4E88 001D0AE8 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D4E8C 001D0AEC 4E 80 00 20 */ blr - -.global TRKReadBuffer1_ui64 -TRKReadBuffer1_ui64: -/* 801D4E90 001D0AF0 94 21 FF D0 */ stwu r1, -0x30(r1) -/* 801D4E94 001D0AF4 7C 08 02 A6 */ mflr r0 -/* 801D4E98 001D0AF8 3C A0 80 49 */ lis r5, lbl_8048EE18@ha -/* 801D4E9C 001D0AFC 90 01 00 34 */ stw r0, 0x34(r1) -/* 801D4EA0 001D0B00 BF 61 00 1C */ stmw r27, 0x1c(r1) -/* 801D4EA4 001D0B04 7C 7B 1B 78 */ mr r27, r3 -/* 801D4EA8 001D0B08 7C 9E 23 78 */ mr r30, r4 -/* 801D4EAC 001D0B0C 80 05 EE 18 */ lwz r0, lbl_8048EE18@l(r5) -/* 801D4EB0 001D0B10 2C 00 00 00 */ cmpwi r0, 0 -/* 801D4EB4 001D0B14 41 82 00 0C */ beq lbl_801D4EC0 -/* 801D4EB8 001D0B18 7F DF F3 78 */ mr r31, r30 -/* 801D4EBC 001D0B1C 48 00 00 08 */ b lbl_801D4EC4 -lbl_801D4EC0: -/* 801D4EC0 001D0B20 3B E1 00 08 */ addi r31, r1, 8 -lbl_801D4EC4: -/* 801D4EC4 001D0B24 80 7B 00 0C */ lwz r3, 0xc(r27) -/* 801D4EC8 001D0B28 3B 80 00 08 */ li r28, 8 -/* 801D4ECC 001D0B2C 80 1B 00 08 */ lwz r0, 8(r27) -/* 801D4ED0 001D0B30 3B A0 00 00 */ li r29, 0 -/* 801D4ED4 001D0B34 7C 03 00 50 */ subf r0, r3, r0 -/* 801D4ED8 001D0B38 7C 1C 00 40 */ cmplw r28, r0 -/* 801D4EDC 001D0B3C 40 81 00 0C */ ble lbl_801D4EE8 -/* 801D4EE0 001D0B40 3B A0 03 02 */ li r29, 0x302 -/* 801D4EE4 001D0B44 7C 1C 03 78 */ mr r28, r0 -lbl_801D4EE8: -/* 801D4EE8 001D0B48 38 83 00 10 */ addi r4, r3, 0x10 -/* 801D4EEC 001D0B4C 7F E3 FB 78 */ mr r3, r31 -/* 801D4EF0 001D0B50 7F 85 E3 78 */ mr r5, r28 -/* 801D4EF4 001D0B54 7C 9B 22 14 */ add r4, r27, r4 -/* 801D4EF8 001D0B58 4B E2 F2 6D */ bl TRK_memcpy -/* 801D4EFC 001D0B5C 80 1B 00 0C */ lwz r0, 0xc(r27) -/* 801D4F00 001D0B60 3C 60 80 49 */ lis r3, lbl_8048EE18@ha -/* 801D4F04 001D0B64 7C 00 E2 14 */ add r0, r0, r28 -/* 801D4F08 001D0B68 90 1B 00 0C */ stw r0, 0xc(r27) -/* 801D4F0C 001D0B6C 80 03 EE 18 */ lwz r0, lbl_8048EE18@l(r3) -/* 801D4F10 001D0B70 2C 00 00 00 */ cmpwi r0, 0 -/* 801D4F14 001D0B74 40 82 00 4C */ bne lbl_801D4F60 -/* 801D4F18 001D0B78 2C 1D 00 00 */ cmpwi r29, 0 -/* 801D4F1C 001D0B7C 40 82 00 44 */ bne lbl_801D4F60 -/* 801D4F20 001D0B80 88 1F 00 07 */ lbz r0, 7(r31) -/* 801D4F24 001D0B84 98 1E 00 00 */ stb r0, 0(r30) -/* 801D4F28 001D0B88 88 1F 00 06 */ lbz r0, 6(r31) -/* 801D4F2C 001D0B8C 98 1E 00 01 */ stb r0, 1(r30) -/* 801D4F30 001D0B90 88 1F 00 05 */ lbz r0, 5(r31) -/* 801D4F34 001D0B94 98 1E 00 02 */ stb r0, 2(r30) -/* 801D4F38 001D0B98 88 1F 00 04 */ lbz r0, 4(r31) -/* 801D4F3C 001D0B9C 98 1E 00 03 */ stb r0, 3(r30) -/* 801D4F40 001D0BA0 88 1F 00 03 */ lbz r0, 3(r31) -/* 801D4F44 001D0BA4 98 1E 00 04 */ stb r0, 4(r30) -/* 801D4F48 001D0BA8 88 1F 00 02 */ lbz r0, 2(r31) -/* 801D4F4C 001D0BAC 98 1E 00 05 */ stb r0, 5(r30) -/* 801D4F50 001D0BB0 88 1F 00 01 */ lbz r0, 1(r31) -/* 801D4F54 001D0BB4 98 1E 00 06 */ stb r0, 6(r30) -/* 801D4F58 001D0BB8 88 1F 00 00 */ lbz r0, 0(r31) -/* 801D4F5C 001D0BBC 98 1E 00 07 */ stb r0, 7(r30) -lbl_801D4F60: -/* 801D4F60 001D0BC0 7F A3 EB 78 */ mr r3, r29 -/* 801D4F64 001D0BC4 BB 61 00 1C */ lmw r27, 0x1c(r1) -/* 801D4F68 001D0BC8 80 01 00 34 */ lwz r0, 0x34(r1) -/* 801D4F6C 001D0BCC 7C 08 03 A6 */ mtlr r0 -/* 801D4F70 001D0BD0 38 21 00 30 */ addi r1, r1, 0x30 -/* 801D4F74 001D0BD4 4E 80 00 20 */ blr - -.global TRKAppendBuffer_ui32 -TRKAppendBuffer_ui32: -/* 801D4F78 001D0BD8 94 21 FF D0 */ stwu r1, -0x30(r1) -/* 801D4F7C 001D0BDC 7C 08 02 A6 */ mflr r0 -/* 801D4F80 001D0BE0 3C C0 80 49 */ lis r6, lbl_8048EE18@ha -/* 801D4F84 001D0BE4 90 01 00 34 */ stw r0, 0x34(r1) -/* 801D4F88 001D0BE8 BF 21 00 14 */ stmw r25, 0x14(r1) -/* 801D4F8C 001D0BEC 7C 7B 1B 78 */ mr r27, r3 -/* 801D4F90 001D0BF0 7C BC 2B 78 */ mr r28, r5 -/* 801D4F94 001D0BF4 7C 9E 23 78 */ mr r30, r4 -/* 801D4F98 001D0BF8 3B E6 EE 18 */ addi r31, r6, lbl_8048EE18@l -/* 801D4F9C 001D0BFC 3B A0 00 00 */ li r29, 0 -/* 801D4FA0 001D0C00 38 60 00 00 */ li r3, 0 -/* 801D4FA4 001D0C04 48 00 00 AC */ b lbl_801D5050 -lbl_801D4FA8: -/* 801D4FA8 001D0C08 80 1F 00 00 */ lwz r0, 0(r31) -/* 801D4FAC 001D0C0C 80 7E 00 00 */ lwz r3, 0(r30) -/* 801D4FB0 001D0C10 2C 00 00 00 */ cmpwi r0, 0 -/* 801D4FB4 001D0C14 90 61 00 08 */ stw r3, 8(r1) -/* 801D4FB8 001D0C18 41 82 00 0C */ beq lbl_801D4FC4 -/* 801D4FBC 001D0C1C 38 81 00 08 */ addi r4, r1, 8 -/* 801D4FC0 001D0C20 48 00 00 28 */ b lbl_801D4FE8 -lbl_801D4FC4: -/* 801D4FC4 001D0C24 88 C1 00 0B */ lbz r6, 0xb(r1) -/* 801D4FC8 001D0C28 38 81 00 0C */ addi r4, r1, 0xc -/* 801D4FCC 001D0C2C 88 A1 00 0A */ lbz r5, 0xa(r1) -/* 801D4FD0 001D0C30 88 61 00 09 */ lbz r3, 9(r1) -/* 801D4FD4 001D0C34 88 01 00 08 */ lbz r0, 8(r1) -/* 801D4FD8 001D0C38 98 C1 00 0C */ stb r6, 0xc(r1) -/* 801D4FDC 001D0C3C 98 A1 00 0D */ stb r5, 0xd(r1) -/* 801D4FE0 001D0C40 98 61 00 0E */ stb r3, 0xe(r1) -/* 801D4FE4 001D0C44 98 01 00 0F */ stb r0, 0xf(r1) -lbl_801D4FE8: -/* 801D4FE8 001D0C48 80 BB 00 0C */ lwz r5, 0xc(r27) -/* 801D4FEC 001D0C4C 3B 20 00 04 */ li r25, 4 -/* 801D4FF0 001D0C50 3B 40 00 00 */ li r26, 0 -/* 801D4FF4 001D0C54 20 05 08 80 */ subfic r0, r5, 0x880 -/* 801D4FF8 001D0C58 28 00 00 04 */ cmplwi r0, 4 -/* 801D4FFC 001D0C5C 40 80 00 0C */ bge lbl_801D5008 -/* 801D5000 001D0C60 3B 40 03 01 */ li r26, 0x301 -/* 801D5004 001D0C64 7C 19 03 78 */ mr r25, r0 -lbl_801D5008: -/* 801D5008 001D0C68 28 19 00 01 */ cmplwi r25, 1 -/* 801D500C 001D0C6C 40 82 00 14 */ bne lbl_801D5020 -/* 801D5010 001D0C70 88 64 00 00 */ lbz r3, 0(r4) -/* 801D5014 001D0C74 38 05 00 10 */ addi r0, r5, 0x10 -/* 801D5018 001D0C78 7C 7B 01 AE */ stbx r3, r27, r0 -/* 801D501C 001D0C7C 48 00 00 14 */ b lbl_801D5030 -lbl_801D5020: -/* 801D5020 001D0C80 38 65 00 10 */ addi r3, r5, 0x10 -/* 801D5024 001D0C84 7F 25 CB 78 */ mr r5, r25 -/* 801D5028 001D0C88 7C 7B 1A 14 */ add r3, r27, r3 -/* 801D502C 001D0C8C 4B E2 F1 39 */ bl TRK_memcpy -lbl_801D5030: -/* 801D5030 001D0C90 80 1B 00 0C */ lwz r0, 0xc(r27) -/* 801D5034 001D0C94 7F 43 D3 78 */ mr r3, r26 -/* 801D5038 001D0C98 3B DE 00 04 */ addi r30, r30, 4 -/* 801D503C 001D0C9C 3B BD 00 01 */ addi r29, r29, 1 -/* 801D5040 001D0CA0 7C 00 CA 14 */ add r0, r0, r25 -/* 801D5044 001D0CA4 90 1B 00 0C */ stw r0, 0xc(r27) -/* 801D5048 001D0CA8 80 1B 00 0C */ lwz r0, 0xc(r27) -/* 801D504C 001D0CAC 90 1B 00 08 */ stw r0, 8(r27) -lbl_801D5050: -/* 801D5050 001D0CB0 2C 03 00 00 */ cmpwi r3, 0 -/* 801D5054 001D0CB4 40 82 00 0C */ bne lbl_801D5060 -/* 801D5058 001D0CB8 7C 1D E0 00 */ cmpw r29, r28 -/* 801D505C 001D0CBC 41 80 FF 4C */ blt lbl_801D4FA8 -lbl_801D5060: -/* 801D5060 001D0CC0 BB 21 00 14 */ lmw r25, 0x14(r1) -/* 801D5064 001D0CC4 80 01 00 34 */ lwz r0, 0x34(r1) -/* 801D5068 001D0CC8 7C 08 03 A6 */ mtlr r0 -/* 801D506C 001D0CCC 38 21 00 30 */ addi r1, r1, 0x30 -/* 801D5070 001D0CD0 4E 80 00 20 */ blr - -.global TRKAppendBuffer_ui8 -TRKAppendBuffer_ui8: -/* 801D5074 001D0CD4 39 20 00 00 */ li r9, 0 -/* 801D5078 001D0CD8 38 00 00 00 */ li r0, 0 -/* 801D507C 001D0CDC 48 00 00 48 */ b lbl_801D50C4 -lbl_801D5080: -/* 801D5080 001D0CE0 80 E3 00 0C */ lwz r7, 0xc(r3) -/* 801D5084 001D0CE4 89 04 00 00 */ lbz r8, 0(r4) -/* 801D5088 001D0CE8 28 07 08 80 */ cmplwi r7, 0x880 -/* 801D508C 001D0CEC 41 80 00 0C */ blt lbl_801D5098 -/* 801D5090 001D0CF0 38 E0 03 01 */ li r7, 0x301 -/* 801D5094 001D0CF4 48 00 00 24 */ b lbl_801D50B8 -lbl_801D5098: -/* 801D5098 001D0CF8 38 C7 00 01 */ addi r6, r7, 1 -/* 801D509C 001D0CFC 38 07 00 10 */ addi r0, r7, 0x10 -/* 801D50A0 001D0D00 90 C3 00 0C */ stw r6, 0xc(r3) -/* 801D50A4 001D0D04 38 E0 00 00 */ li r7, 0 -/* 801D50A8 001D0D08 7D 03 01 AE */ stbx r8, r3, r0 -/* 801D50AC 001D0D0C 80 C3 00 08 */ lwz r6, 8(r3) -/* 801D50B0 001D0D10 38 06 00 01 */ addi r0, r6, 1 -/* 801D50B4 001D0D14 90 03 00 08 */ stw r0, 8(r3) -lbl_801D50B8: -/* 801D50B8 001D0D18 7C E0 3B 78 */ mr r0, r7 -/* 801D50BC 001D0D1C 39 29 00 01 */ addi r9, r9, 1 -/* 801D50C0 001D0D20 38 84 00 01 */ addi r4, r4, 1 -lbl_801D50C4: -/* 801D50C4 001D0D24 2C 00 00 00 */ cmpwi r0, 0 -/* 801D50C8 001D0D28 40 82 00 0C */ bne lbl_801D50D4 -/* 801D50CC 001D0D2C 7C 09 28 00 */ cmpw r9, r5 -/* 801D50D0 001D0D30 41 80 FF B0 */ blt lbl_801D5080 -lbl_801D50D4: -/* 801D50D4 001D0D34 7C 03 03 78 */ mr r3, r0 -/* 801D50D8 001D0D38 4E 80 00 20 */ blr - -.global TRKAppendBuffer1_ui64 -TRKAppendBuffer1_ui64: -/* 801D50DC 001D0D3C 94 21 FF D0 */ stwu r1, -0x30(r1) -/* 801D50E0 001D0D40 7C 08 02 A6 */ mflr r0 -/* 801D50E4 001D0D44 3C 80 80 49 */ lis r4, lbl_8048EE18@ha -/* 801D50E8 001D0D48 90 01 00 34 */ stw r0, 0x34(r1) -/* 801D50EC 001D0D4C 93 E1 00 2C */ stw r31, 0x2c(r1) -/* 801D50F0 001D0D50 7C 7F 1B 78 */ mr r31, r3 -/* 801D50F4 001D0D54 93 C1 00 28 */ stw r30, 0x28(r1) -/* 801D50F8 001D0D58 93 A1 00 24 */ stw r29, 0x24(r1) -/* 801D50FC 001D0D5C 80 04 EE 18 */ lwz r0, lbl_8048EE18@l(r4) -/* 801D5100 001D0D60 90 A1 00 08 */ stw r5, 8(r1) -/* 801D5104 001D0D64 2C 00 00 00 */ cmpwi r0, 0 -/* 801D5108 001D0D68 90 C1 00 0C */ stw r6, 0xc(r1) -/* 801D510C 001D0D6C 41 82 00 0C */ beq lbl_801D5118 -/* 801D5110 001D0D70 38 81 00 08 */ addi r4, r1, 8 -/* 801D5114 001D0D74 48 00 00 48 */ b lbl_801D515C -lbl_801D5118: -/* 801D5118 001D0D78 89 41 00 0F */ lbz r10, 0xf(r1) -/* 801D511C 001D0D7C 38 81 00 10 */ addi r4, r1, 0x10 -/* 801D5120 001D0D80 89 21 00 0E */ lbz r9, 0xe(r1) -/* 801D5124 001D0D84 89 01 00 0D */ lbz r8, 0xd(r1) -/* 801D5128 001D0D88 88 E1 00 0C */ lbz r7, 0xc(r1) -/* 801D512C 001D0D8C 88 C1 00 0B */ lbz r6, 0xb(r1) -/* 801D5130 001D0D90 88 A1 00 0A */ lbz r5, 0xa(r1) -/* 801D5134 001D0D94 88 61 00 09 */ lbz r3, 9(r1) -/* 801D5138 001D0D98 88 01 00 08 */ lbz r0, 8(r1) -/* 801D513C 001D0D9C 99 41 00 10 */ stb r10, 0x10(r1) -/* 801D5140 001D0DA0 99 21 00 11 */ stb r9, 0x11(r1) -/* 801D5144 001D0DA4 99 01 00 12 */ stb r8, 0x12(r1) -/* 801D5148 001D0DA8 98 E1 00 13 */ stb r7, 0x13(r1) -/* 801D514C 001D0DAC 98 C1 00 14 */ stb r6, 0x14(r1) -/* 801D5150 001D0DB0 98 A1 00 15 */ stb r5, 0x15(r1) -/* 801D5154 001D0DB4 98 61 00 16 */ stb r3, 0x16(r1) -/* 801D5158 001D0DB8 98 01 00 17 */ stb r0, 0x17(r1) -lbl_801D515C: -/* 801D515C 001D0DBC 80 7F 00 0C */ lwz r3, 0xc(r31) -/* 801D5160 001D0DC0 3B A0 00 08 */ li r29, 8 -/* 801D5164 001D0DC4 3B C0 00 00 */ li r30, 0 -/* 801D5168 001D0DC8 20 03 08 80 */ subfic r0, r3, 0x880 -/* 801D516C 001D0DCC 28 00 00 08 */ cmplwi r0, 8 -/* 801D5170 001D0DD0 40 80 00 0C */ bge lbl_801D517C -/* 801D5174 001D0DD4 3B C0 03 01 */ li r30, 0x301 -/* 801D5178 001D0DD8 7C 1D 03 78 */ mr r29, r0 -lbl_801D517C: -/* 801D517C 001D0DDC 28 1D 00 01 */ cmplwi r29, 1 -/* 801D5180 001D0DE0 40 82 00 14 */ bne lbl_801D5194 -/* 801D5184 001D0DE4 88 04 00 00 */ lbz r0, 0(r4) -/* 801D5188 001D0DE8 7C 7F 1A 14 */ add r3, r31, r3 -/* 801D518C 001D0DEC 98 03 00 10 */ stb r0, 0x10(r3) -/* 801D5190 001D0DF0 48 00 00 14 */ b lbl_801D51A4 -lbl_801D5194: -/* 801D5194 001D0DF4 38 63 00 10 */ addi r3, r3, 0x10 -/* 801D5198 001D0DF8 7F A5 EB 78 */ mr r5, r29 -/* 801D519C 001D0DFC 7C 7F 1A 14 */ add r3, r31, r3 -/* 801D51A0 001D0E00 4B E2 EF C5 */ bl TRK_memcpy -lbl_801D51A4: -/* 801D51A4 001D0E04 80 1F 00 0C */ lwz r0, 0xc(r31) -/* 801D51A8 001D0E08 7F C3 F3 78 */ mr r3, r30 -/* 801D51AC 001D0E0C 7C 00 EA 14 */ add r0, r0, r29 -/* 801D51B0 001D0E10 90 1F 00 0C */ stw r0, 0xc(r31) -/* 801D51B4 001D0E14 80 1F 00 0C */ lwz r0, 0xc(r31) -/* 801D51B8 001D0E18 90 1F 00 08 */ stw r0, 8(r31) -/* 801D51BC 001D0E1C 83 E1 00 2C */ lwz r31, 0x2c(r1) -/* 801D51C0 001D0E20 83 C1 00 28 */ lwz r30, 0x28(r1) -/* 801D51C4 001D0E24 83 A1 00 24 */ lwz r29, 0x24(r1) -/* 801D51C8 001D0E28 80 01 00 34 */ lwz r0, 0x34(r1) -/* 801D51CC 001D0E2C 7C 08 03 A6 */ mtlr r0 -/* 801D51D0 001D0E30 38 21 00 30 */ addi r1, r1, 0x30 -/* 801D51D4 001D0E34 4E 80 00 20 */ blr - -.global TRKReadBuffer -TRKReadBuffer: -/* 801D51D8 001D0E38 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D51DC 001D0E3C 7C 08 02 A6 */ mflr r0 -/* 801D51E0 001D0E40 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D51E4 001D0E44 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D51E8 001D0E48 3B E0 00 00 */ li r31, 0 -/* 801D51EC 001D0E4C 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D51F0 001D0E50 7C BE 2B 79 */ or. r30, r5, r5 -/* 801D51F4 001D0E54 93 A1 00 14 */ stw r29, 0x14(r1) -/* 801D51F8 001D0E58 7C 7D 1B 78 */ mr r29, r3 -/* 801D51FC 001D0E5C 7C 83 23 78 */ mr r3, r4 -/* 801D5200 001D0E60 40 82 00 0C */ bne lbl_801D520C -/* 801D5204 001D0E64 38 60 00 00 */ li r3, 0 -/* 801D5208 001D0E68 48 00 00 40 */ b lbl_801D5248 -lbl_801D520C: -/* 801D520C 001D0E6C 80 9D 00 0C */ lwz r4, 0xc(r29) -/* 801D5210 001D0E70 80 1D 00 08 */ lwz r0, 8(r29) -/* 801D5214 001D0E74 7C 04 00 50 */ subf r0, r4, r0 -/* 801D5218 001D0E78 7C 1E 00 40 */ cmplw r30, r0 -/* 801D521C 001D0E7C 40 81 00 0C */ ble lbl_801D5228 -/* 801D5220 001D0E80 3B E0 03 02 */ li r31, 0x302 -/* 801D5224 001D0E84 7C 1E 03 78 */ mr r30, r0 -lbl_801D5228: -/* 801D5228 001D0E88 38 84 00 10 */ addi r4, r4, 0x10 -/* 801D522C 001D0E8C 7F C5 F3 78 */ mr r5, r30 -/* 801D5230 001D0E90 7C 9D 22 14 */ add r4, r29, r4 -/* 801D5234 001D0E94 4B E2 EF 31 */ bl TRK_memcpy -/* 801D5238 001D0E98 80 1D 00 0C */ lwz r0, 0xc(r29) -/* 801D523C 001D0E9C 7F E3 FB 78 */ mr r3, r31 -/* 801D5240 001D0EA0 7C 00 F2 14 */ add r0, r0, r30 -/* 801D5244 001D0EA4 90 1D 00 0C */ stw r0, 0xc(r29) -lbl_801D5248: -/* 801D5248 001D0EA8 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D524C 001D0EAC 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D5250 001D0EB0 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D5254 001D0EB4 83 A1 00 14 */ lwz r29, 0x14(r1) -/* 801D5258 001D0EB8 7C 08 03 A6 */ mtlr r0 -/* 801D525C 001D0EBC 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D5260 001D0EC0 4E 80 00 20 */ blr - -.global TRKAppendBuffer -TRKAppendBuffer: -/* 801D5264 001D0EC4 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D5268 001D0EC8 7C 08 02 A6 */ mflr r0 -/* 801D526C 001D0ECC 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D5270 001D0ED0 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D5274 001D0ED4 3B E0 00 00 */ li r31, 0 -/* 801D5278 001D0ED8 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D527C 001D0EDC 7C BE 2B 79 */ or. r30, r5, r5 -/* 801D5280 001D0EE0 93 A1 00 14 */ stw r29, 0x14(r1) -/* 801D5284 001D0EE4 7C 7D 1B 78 */ mr r29, r3 -/* 801D5288 001D0EE8 40 82 00 0C */ bne lbl_801D5294 -/* 801D528C 001D0EEC 38 60 00 00 */ li r3, 0 -/* 801D5290 001D0EF0 48 00 00 5C */ b lbl_801D52EC -lbl_801D5294: -/* 801D5294 001D0EF4 80 7D 00 0C */ lwz r3, 0xc(r29) -/* 801D5298 001D0EF8 20 03 08 80 */ subfic r0, r3, 0x880 -/* 801D529C 001D0EFC 7C 00 F0 40 */ cmplw r0, r30 -/* 801D52A0 001D0F00 40 80 00 0C */ bge lbl_801D52AC -/* 801D52A4 001D0F04 3B E0 03 01 */ li r31, 0x301 -/* 801D52A8 001D0F08 7C 1E 03 78 */ mr r30, r0 -lbl_801D52AC: -/* 801D52AC 001D0F0C 28 1E 00 01 */ cmplwi r30, 1 -/* 801D52B0 001D0F10 40 82 00 14 */ bne lbl_801D52C4 -/* 801D52B4 001D0F14 88 04 00 00 */ lbz r0, 0(r4) -/* 801D52B8 001D0F18 7C 7D 1A 14 */ add r3, r29, r3 -/* 801D52BC 001D0F1C 98 03 00 10 */ stb r0, 0x10(r3) -/* 801D52C0 001D0F20 48 00 00 14 */ b lbl_801D52D4 -lbl_801D52C4: -/* 801D52C4 001D0F24 38 63 00 10 */ addi r3, r3, 0x10 -/* 801D52C8 001D0F28 7F C5 F3 78 */ mr r5, r30 -/* 801D52CC 001D0F2C 7C 7D 1A 14 */ add r3, r29, r3 -/* 801D52D0 001D0F30 4B E2 EE 95 */ bl TRK_memcpy -lbl_801D52D4: -/* 801D52D4 001D0F34 80 1D 00 0C */ lwz r0, 0xc(r29) -/* 801D52D8 001D0F38 7F E3 FB 78 */ mr r3, r31 -/* 801D52DC 001D0F3C 7C 00 F2 14 */ add r0, r0, r30 -/* 801D52E0 001D0F40 90 1D 00 0C */ stw r0, 0xc(r29) -/* 801D52E4 001D0F44 80 1D 00 0C */ lwz r0, 0xc(r29) -/* 801D52E8 001D0F48 90 1D 00 08 */ stw r0, 8(r29) -lbl_801D52EC: -/* 801D52EC 001D0F4C 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D52F0 001D0F50 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D52F4 001D0F54 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D52F8 001D0F58 83 A1 00 14 */ lwz r29, 0x14(r1) -/* 801D52FC 001D0F5C 7C 08 03 A6 */ mtlr r0 -/* 801D5300 001D0F60 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D5304 001D0F64 4E 80 00 20 */ blr - -.global TRKSetBufferPosition -TRKSetBufferPosition: -/* 801D5308 001D0F68 28 04 08 80 */ cmplwi r4, 0x880 -/* 801D530C 001D0F6C 38 A0 00 00 */ li r5, 0 -/* 801D5310 001D0F70 40 81 00 0C */ ble lbl_801D531C -/* 801D5314 001D0F74 38 A0 03 01 */ li r5, 0x301 -/* 801D5318 001D0F78 48 00 00 18 */ b lbl_801D5330 -lbl_801D531C: -/* 801D531C 001D0F7C 90 83 00 0C */ stw r4, 0xc(r3) -/* 801D5320 001D0F80 80 03 00 08 */ lwz r0, 8(r3) -/* 801D5324 001D0F84 7C 04 00 40 */ cmplw r4, r0 -/* 801D5328 001D0F88 40 81 00 08 */ ble lbl_801D5330 -/* 801D532C 001D0F8C 90 83 00 08 */ stw r4, 8(r3) -lbl_801D5330: -/* 801D5330 001D0F90 7C A3 2B 78 */ mr r3, r5 -/* 801D5334 001D0F94 4E 80 00 20 */ blr - -.global TRKResetBuffer -TRKResetBuffer: -/* 801D5338 001D0F98 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D533C 001D0F9C 7C 08 02 A6 */ mflr r0 -/* 801D5340 001D0FA0 2C 04 00 00 */ cmpwi r4, 0 -/* 801D5344 001D0FA4 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D5348 001D0FA8 38 00 00 00 */ li r0, 0 -/* 801D534C 001D0FAC 90 03 00 08 */ stw r0, 8(r3) -/* 801D5350 001D0FB0 90 03 00 0C */ stw r0, 0xc(r3) -/* 801D5354 001D0FB4 40 82 00 14 */ bne lbl_801D5368 -/* 801D5358 001D0FB8 38 63 00 10 */ addi r3, r3, 0x10 -/* 801D535C 001D0FBC 38 80 00 00 */ li r4, 0 -/* 801D5360 001D0FC0 38 A0 08 80 */ li r5, 0x880 -/* 801D5364 001D0FC4 4B E2 ED D1 */ bl TRK_memset -lbl_801D5368: -/* 801D5368 001D0FC8 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D536C 001D0FCC 7C 08 03 A6 */ mtlr r0 -/* 801D5370 001D0FD0 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D5374 001D0FD4 4E 80 00 20 */ blr - -.global TRKReleaseBuffer -TRKReleaseBuffer: -/* 801D5378 001D0FD8 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D537C 001D0FDC 7C 08 02 A6 */ mflr r0 -/* 801D5380 001D0FE0 2C 03 FF FF */ cmpwi r3, -1 -/* 801D5384 001D0FE4 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D5388 001D0FE8 93 E1 00 0C */ stw r31, 0xc(r1) -/* 801D538C 001D0FEC 41 82 00 3C */ beq lbl_801D53C8 -/* 801D5390 001D0FF0 2C 03 00 00 */ cmpwi r3, 0 -/* 801D5394 001D0FF4 41 80 00 34 */ blt lbl_801D53C8 -/* 801D5398 001D0FF8 2C 03 00 03 */ cmpwi r3, 3 -/* 801D539C 001D0FFC 40 80 00 2C */ bge lbl_801D53C8 -/* 801D53A0 001D1000 1C 83 08 90 */ mulli r4, r3, 0x890 -/* 801D53A4 001D1004 3C 60 80 49 */ lis r3, lbl_8048EE20@ha -/* 801D53A8 001D1008 38 03 EE 20 */ addi r0, r3, lbl_8048EE20@l -/* 801D53AC 001D100C 7F E0 22 14 */ add r31, r0, r4 -/* 801D53B0 001D1010 7F E3 FB 78 */ mr r3, r31 -/* 801D53B4 001D1014 48 00 1C A9 */ bl func_801D705C -/* 801D53B8 001D1018 38 00 00 00 */ li r0, 0 -/* 801D53BC 001D101C 7F E3 FB 78 */ mr r3, r31 -/* 801D53C0 001D1020 90 1F 00 04 */ stw r0, 4(r31) -/* 801D53C4 001D1024 48 00 1C 91 */ bl func_801D7054 -lbl_801D53C8: -/* 801D53C8 001D1028 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D53CC 001D102C 83 E1 00 0C */ lwz r31, 0xc(r1) -/* 801D53D0 001D1030 7C 08 03 A6 */ mtlr r0 -/* 801D53D4 001D1034 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D53D8 001D1038 4E 80 00 20 */ blr - -.global TRKGetBuffer -TRKGetBuffer: -/* 801D53DC 001D103C 2C 03 00 00 */ cmpwi r3, 0 -/* 801D53E0 001D1040 38 00 00 00 */ li r0, 0 -/* 801D53E4 001D1044 41 80 00 1C */ blt lbl_801D5400 -/* 801D53E8 001D1048 2C 03 00 03 */ cmpwi r3, 3 -/* 801D53EC 001D104C 40 80 00 14 */ bge lbl_801D5400 -/* 801D53F0 001D1050 1C 83 08 90 */ mulli r4, r3, 0x890 -/* 801D53F4 001D1054 3C 60 80 49 */ lis r3, lbl_8048EE20@ha -/* 801D53F8 001D1058 38 03 EE 20 */ addi r0, r3, lbl_8048EE20@l -/* 801D53FC 001D105C 7C 00 22 14 */ add r0, r0, r4 -lbl_801D5400: -/* 801D5400 001D1060 7C 03 03 78 */ mr r3, r0 -/* 801D5404 001D1064 4E 80 00 20 */ blr - -.global TRKGetFreeBuffer -TRKGetFreeBuffer: -/* 801D5408 001D1068 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D540C 001D106C 7C 08 02 A6 */ mflr r0 -/* 801D5410 001D1070 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D5414 001D1074 38 00 00 00 */ li r0, 0 -/* 801D5418 001D1078 BF 61 00 0C */ stmw r27, 0xc(r1) -/* 801D541C 001D107C 7C 9C 23 78 */ mr r28, r4 -/* 801D5420 001D1080 7C 7B 1B 78 */ mr r27, r3 -/* 801D5424 001D1084 3B C0 03 00 */ li r30, 0x300 -/* 801D5428 001D1088 3B A0 00 00 */ li r29, 0 -/* 801D542C 001D108C 90 04 00 00 */ stw r0, 0(r4) -/* 801D5430 001D1090 48 00 00 6C */ b lbl_801D549C -lbl_801D5434: -/* 801D5434 001D1094 2C 1D 00 00 */ cmpwi r29, 0 -/* 801D5438 001D1098 3B E0 00 00 */ li r31, 0 -/* 801D543C 001D109C 41 80 00 1C */ blt lbl_801D5458 -/* 801D5440 001D10A0 2C 1D 00 03 */ cmpwi r29, 3 -/* 801D5444 001D10A4 40 80 00 14 */ bge lbl_801D5458 -/* 801D5448 001D10A8 1C 9D 08 90 */ mulli r4, r29, 0x890 -/* 801D544C 001D10AC 3C 60 80 49 */ lis r3, lbl_8048EE20@ha -/* 801D5450 001D10B0 38 03 EE 20 */ addi r0, r3, lbl_8048EE20@l -/* 801D5454 001D10B4 7F E0 22 14 */ add r31, r0, r4 -lbl_801D5458: -/* 801D5458 001D10B8 7F E3 FB 78 */ mr r3, r31 -/* 801D545C 001D10BC 48 00 1C 01 */ bl func_801D705C -/* 801D5460 001D10C0 80 1F 00 04 */ lwz r0, 4(r31) -/* 801D5464 001D10C4 2C 00 00 00 */ cmpwi r0, 0 -/* 801D5468 001D10C8 40 82 00 28 */ bne lbl_801D5490 -/* 801D546C 001D10CC 38 60 00 00 */ li r3, 0 -/* 801D5470 001D10D0 38 00 00 01 */ li r0, 1 -/* 801D5474 001D10D4 90 7F 00 08 */ stw r3, 8(r31) -/* 801D5478 001D10D8 3B C0 00 00 */ li r30, 0 -/* 801D547C 001D10DC 90 7F 00 0C */ stw r3, 0xc(r31) -/* 801D5480 001D10E0 90 1F 00 04 */ stw r0, 4(r31) -/* 801D5484 001D10E4 93 FC 00 00 */ stw r31, 0(r28) -/* 801D5488 001D10E8 93 BB 00 00 */ stw r29, 0(r27) -/* 801D548C 001D10EC 3B A0 00 03 */ li r29, 3 -lbl_801D5490: -/* 801D5490 001D10F0 7F E3 FB 78 */ mr r3, r31 -/* 801D5494 001D10F4 48 00 1B C1 */ bl func_801D7054 -/* 801D5498 001D10F8 3B BD 00 01 */ addi r29, r29, 1 -lbl_801D549C: -/* 801D549C 001D10FC 2C 1D 00 03 */ cmpwi r29, 3 -/* 801D54A0 001D1100 41 80 FF 94 */ blt lbl_801D5434 -/* 801D54A4 001D1104 2C 1E 03 00 */ cmpwi r30, 0x300 -/* 801D54A8 001D1108 40 82 00 10 */ bne lbl_801D54B8 -/* 801D54AC 001D110C 3C 60 80 40 */ lis r3, lbl_803FD660@ha -/* 801D54B0 001D1110 38 63 D6 60 */ addi r3, r3, lbl_803FD660@l -/* 801D54B4 001D1114 48 00 02 41 */ bl usr_puts_serial -lbl_801D54B8: -/* 801D54B8 001D1118 7F C3 F3 78 */ mr r3, r30 -/* 801D54BC 001D111C BB 61 00 0C */ lmw r27, 0xc(r1) -/* 801D54C0 001D1120 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D54C4 001D1124 7C 08 03 A6 */ mtlr r0 -/* 801D54C8 001D1128 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D54CC 001D112C 4E 80 00 20 */ blr - -.global TRKInitializeMessageBuffers -TRKInitializeMessageBuffers: -/* 801D54D0 001D1130 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D54D4 001D1134 7C 08 02 A6 */ mflr r0 -/* 801D54D8 001D1138 3C 60 80 49 */ lis r3, lbl_8048EE20@ha -/* 801D54DC 001D113C 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D54E0 001D1140 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D54E4 001D1144 3B E0 00 00 */ li r31, 0 -/* 801D54E8 001D1148 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D54EC 001D114C 3B C3 EE 20 */ addi r30, r3, lbl_8048EE20@l -/* 801D54F0 001D1150 93 A1 00 14 */ stw r29, 0x14(r1) -/* 801D54F4 001D1154 3B A0 00 00 */ li r29, 0 -lbl_801D54F8: -/* 801D54F8 001D1158 7F C3 F3 78 */ mr r3, r30 -/* 801D54FC 001D115C 48 00 1B 69 */ bl func_801D7064 -/* 801D5500 001D1160 7F C3 F3 78 */ mr r3, r30 -/* 801D5504 001D1164 48 00 1B 59 */ bl func_801D705C -/* 801D5508 001D1168 93 FE 00 04 */ stw r31, 4(r30) -/* 801D550C 001D116C 7F C3 F3 78 */ mr r3, r30 -/* 801D5510 001D1170 48 00 1B 45 */ bl func_801D7054 -/* 801D5514 001D1174 3B BD 00 01 */ addi r29, r29, 1 -/* 801D5518 001D1178 3B DE 08 90 */ addi r30, r30, 0x890 -/* 801D551C 001D117C 2C 1D 00 03 */ cmpwi r29, 3 -/* 801D5520 001D1180 41 80 FF D8 */ blt lbl_801D54F8 -/* 801D5524 001D1184 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D5528 001D1188 38 60 00 00 */ li r3, 0 -/* 801D552C 001D118C 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D5530 001D1190 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D5534 001D1194 83 A1 00 14 */ lwz r29, 0x14(r1) -/* 801D5538 001D1198 7C 08 03 A6 */ mtlr r0 -/* 801D553C 001D119C 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D5540 001D11A0 4E 80 00 20 */ blr - -.global func_801D5544 -func_801D5544: -/* 801D5544 001D11A4 38 60 00 00 */ li r3, 0 -/* 801D5548 001D11A8 4E 80 00 20 */ blr - -.global func_801D554C -func_801D554C: -/* 801D554C 001D11AC 3C 60 80 49 */ lis r3, lbl_804907D0@ha -/* 801D5550 001D11B0 38 A0 FF FF */ li r5, -1 -/* 801D5554 001D11B4 38 83 07 D0 */ addi r4, r3, lbl_804907D0@l -/* 801D5558 001D11B8 38 00 00 00 */ li r0, 0 -/* 801D555C 001D11BC 90 A4 00 00 */ stw r5, 0(r4) -/* 801D5560 001D11C0 38 60 00 00 */ li r3, 0 -/* 801D5564 001D11C4 90 04 00 08 */ stw r0, 8(r4) -/* 801D5568 001D11C8 90 04 00 0C */ stw r0, 0xc(r4) -/* 801D556C 001D11CC 4E 80 00 20 */ blr - -.global TRKProcessInput -TRKProcessInput: -/* 801D5570 001D11D0 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D5574 001D11D4 7C 08 02 A6 */ mflr r0 -/* 801D5578 001D11D8 38 80 00 02 */ li r4, 2 -/* 801D557C 001D11DC 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D5580 001D11E0 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D5584 001D11E4 7C 7F 1B 78 */ mr r31, r3 -/* 801D5588 001D11E8 38 61 00 08 */ addi r3, r1, 8 -/* 801D558C 001D11EC 4B FF F3 C9 */ bl TRKConstructEvent -/* 801D5590 001D11F0 3C 60 80 49 */ lis r3, lbl_804907D0@ha -/* 801D5594 001D11F4 38 00 FF FF */ li r0, -1 -/* 801D5598 001D11F8 38 83 07 D0 */ addi r4, r3, lbl_804907D0@l -/* 801D559C 001D11FC 93 E1 00 10 */ stw r31, 0x10(r1) -/* 801D55A0 001D1200 38 61 00 08 */ addi r3, r1, 8 -/* 801D55A4 001D1204 90 04 00 00 */ stw r0, 0(r4) -/* 801D55A8 001D1208 4B FF F3 C5 */ bl TRKPostEvent -/* 801D55AC 001D120C 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D55B0 001D1210 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D55B4 001D1214 7C 08 03 A6 */ mtlr r0 -/* 801D55B8 001D1218 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D55BC 001D121C 4E 80 00 20 */ blr - -.global TRKGetInput -TRKGetInput: -/* 801D55C0 001D1220 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D55C4 001D1224 7C 08 02 A6 */ mflr r0 -/* 801D55C8 001D1228 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D55CC 001D122C 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D55D0 001D1230 48 00 00 51 */ bl func_801D5620 -/* 801D55D4 001D1234 7C 7F 1B 78 */ mr r31, r3 -/* 801D55D8 001D1238 2C 1F FF FF */ cmpwi r31, -1 -/* 801D55DC 001D123C 41 82 00 30 */ beq lbl_801D560C -/* 801D55E0 001D1240 4B FF FD FD */ bl TRKGetBuffer -/* 801D55E4 001D1244 38 61 00 08 */ addi r3, r1, 8 -/* 801D55E8 001D1248 38 80 00 02 */ li r4, 2 -/* 801D55EC 001D124C 4B FF F3 69 */ bl TRKConstructEvent -/* 801D55F0 001D1250 3C 60 80 49 */ lis r3, lbl_804907D0@ha -/* 801D55F4 001D1254 38 00 FF FF */ li r0, -1 -/* 801D55F8 001D1258 38 83 07 D0 */ addi r4, r3, lbl_804907D0@l -/* 801D55FC 001D125C 93 E1 00 10 */ stw r31, 0x10(r1) -/* 801D5600 001D1260 38 61 00 08 */ addi r3, r1, 8 -/* 801D5604 001D1264 90 04 00 00 */ stw r0, 0(r4) -/* 801D5608 001D1268 4B FF F3 65 */ bl TRKPostEvent -lbl_801D560C: -/* 801D560C 001D126C 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D5610 001D1270 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D5614 001D1274 7C 08 03 A6 */ mtlr r0 -/* 801D5618 001D1278 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D561C 001D127C 4E 80 00 20 */ blr - -.global func_801D5620 -func_801D5620: -/* 801D5620 001D1280 94 21 F7 20 */ stwu r1, -0x8e0(r1) -/* 801D5624 001D1284 7C 08 02 A6 */ mflr r0 -/* 801D5628 001D1288 90 01 08 E4 */ stw r0, 0x8e4(r1) -/* 801D562C 001D128C 93 E1 08 DC */ stw r31, 0x8dc(r1) -/* 801D5630 001D1290 48 00 40 55 */ bl func_801D9684 -/* 801D5634 001D1294 2C 03 00 00 */ cmpwi r3, 0 -/* 801D5638 001D1298 41 81 00 0C */ bgt lbl_801D5644 -/* 801D563C 001D129C 38 60 FF FF */ li r3, -1 -/* 801D5640 001D12A0 48 00 00 9C */ b lbl_801D56DC -lbl_801D5644: -/* 801D5644 001D12A4 38 61 00 0C */ addi r3, r1, 0xc -/* 801D5648 001D12A8 38 81 00 08 */ addi r4, r1, 8 -/* 801D564C 001D12AC 4B FF FD BD */ bl TRKGetFreeBuffer -/* 801D5650 001D12B0 7C 60 1B 78 */ mr r0, r3 -/* 801D5654 001D12B4 80 61 00 08 */ lwz r3, 8(r1) -/* 801D5658 001D12B8 7C 1F 03 78 */ mr r31, r0 -/* 801D565C 001D12BC 38 80 00 00 */ li r4, 0 -/* 801D5660 001D12C0 4B FF FC A9 */ bl TRKSetBufferPosition -/* 801D5664 001D12C4 38 61 00 10 */ addi r3, r1, 0x10 -/* 801D5668 001D12C8 38 80 00 40 */ li r4, 0x40 -/* 801D566C 001D12CC 48 00 3F DD */ bl TRKWriteUARTN -/* 801D5670 001D12D0 2C 03 00 00 */ cmpwi r3, 0 -/* 801D5674 001D12D4 40 82 00 58 */ bne lbl_801D56CC -/* 801D5678 001D12D8 80 61 00 08 */ lwz r3, 8(r1) -/* 801D567C 001D12DC 38 81 00 10 */ addi r4, r1, 0x10 -/* 801D5680 001D12E0 38 A0 00 40 */ li r5, 0x40 -/* 801D5684 001D12E4 4B FF F9 F1 */ bl TRKAppendBuffer_ui8 -/* 801D5688 001D12E8 80 61 00 10 */ lwz r3, 0x10(r1) -/* 801D568C 001D12EC 83 E1 00 0C */ lwz r31, 0xc(r1) -/* 801D5690 001D12F0 34 83 FF C0 */ addic. r4, r3, -64 -/* 801D5694 001D12F4 40 81 00 44 */ ble lbl_801D56D8 -/* 801D5698 001D12F8 38 61 00 50 */ addi r3, r1, 0x50 -/* 801D569C 001D12FC 48 00 3F AD */ bl TRKWriteUARTN -/* 801D56A0 001D1300 2C 03 00 00 */ cmpwi r3, 0 -/* 801D56A4 001D1304 40 82 00 18 */ bne lbl_801D56BC -/* 801D56A8 001D1308 80 61 00 08 */ lwz r3, 8(r1) -/* 801D56AC 001D130C 38 81 00 50 */ addi r4, r1, 0x50 -/* 801D56B0 001D1310 80 A1 00 10 */ lwz r5, 0x10(r1) -/* 801D56B4 001D1314 4B FF F9 C1 */ bl TRKAppendBuffer_ui8 -/* 801D56B8 001D1318 48 00 00 20 */ b lbl_801D56D8 -lbl_801D56BC: -/* 801D56BC 001D131C 7F E3 FB 78 */ mr r3, r31 -/* 801D56C0 001D1320 4B FF FC B9 */ bl TRKReleaseBuffer -/* 801D56C4 001D1324 3B E0 FF FF */ li r31, -1 -/* 801D56C8 001D1328 48 00 00 10 */ b lbl_801D56D8 -lbl_801D56CC: -/* 801D56CC 001D132C 7F E3 FB 78 */ mr r3, r31 -/* 801D56D0 001D1330 4B FF FC A9 */ bl TRKReleaseBuffer -/* 801D56D4 001D1334 3B E0 FF FF */ li r31, -1 -lbl_801D56D8: -/* 801D56D8 001D1338 7F E3 FB 78 */ mr r3, r31 -lbl_801D56DC: -/* 801D56DC 001D133C 80 01 08 E4 */ lwz r0, 0x8e4(r1) -/* 801D56E0 001D1340 83 E1 08 DC */ lwz r31, 0x8dc(r1) -/* 801D56E4 001D1344 7C 08 03 A6 */ mtlr r0 -/* 801D56E8 001D1348 38 21 08 E0 */ addi r1, r1, 0x8e0 -/* 801D56EC 001D134C 4E 80 00 20 */ blr - -.global func_801D56F0 -func_801D56F0: -/* 801D56F0 001D1350 4E 80 00 20 */ blr - -.global usr_puts_serial -usr_puts_serial: -/* 801D56F4 001D1354 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D56F8 001D1358 7C 08 02 A6 */ mflr r0 -/* 801D56FC 001D135C 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D5700 001D1360 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D5704 001D1364 3B E0 00 00 */ li r31, 0 -/* 801D5708 001D1368 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D570C 001D136C 93 A1 00 14 */ stw r29, 0x14(r1) -/* 801D5710 001D1370 7C 7D 1B 78 */ mr r29, r3 -/* 801D5714 001D1374 38 60 00 00 */ li r3, 0 -/* 801D5718 001D1378 48 00 00 30 */ b lbl_801D5748 -lbl_801D571C: -/* 801D571C 001D137C 48 00 12 75 */ bl func_801D6990 -/* 801D5720 001D1380 9B C1 00 08 */ stb r30, 8(r1) -/* 801D5724 001D1384 7C 7E 1B 78 */ mr r30, r3 -/* 801D5728 001D1388 38 60 00 00 */ li r3, 0 -/* 801D572C 001D138C 9B E1 00 09 */ stb r31, 9(r1) -/* 801D5730 001D1390 48 00 12 55 */ bl SetTRKConnected -/* 801D5734 001D1394 38 61 00 08 */ addi r3, r1, 8 -/* 801D5738 001D1398 4B E3 23 8D */ bl func_80007AC4 -/* 801D573C 001D139C 7F C3 F3 78 */ mr r3, r30 -/* 801D5740 001D13A0 48 00 12 45 */ bl SetTRKConnected -/* 801D5744 001D13A4 38 60 00 00 */ li r3, 0 -lbl_801D5748: -/* 801D5748 001D13A8 2C 03 00 00 */ cmpwi r3, 0 -/* 801D574C 001D13AC 40 82 00 14 */ bne lbl_801D5760 -/* 801D5750 001D13B0 88 1D 00 00 */ lbz r0, 0(r29) -/* 801D5754 001D13B4 3B BD 00 01 */ addi r29, r29, 1 -/* 801D5758 001D13B8 7C 1E 07 75 */ extsb. r30, r0 -/* 801D575C 001D13BC 40 82 FF C0 */ bne lbl_801D571C -lbl_801D5760: -/* 801D5760 001D13C0 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D5764 001D13C4 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D5768 001D13C8 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D576C 001D13CC 83 A1 00 14 */ lwz r29, 0x14(r1) -/* 801D5770 001D13D0 7C 08 03 A6 */ mtlr r0 -/* 801D5774 001D13D4 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D5778 001D13D8 4E 80 00 20 */ blr - -.global func_801D577C -func_801D577C: -/* 801D577C 001D13DC 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D5780 001D13E0 7C 08 02 A6 */ mflr r0 -/* 801D5784 001D13E4 38 80 00 00 */ li r4, 0 -/* 801D5788 001D13E8 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D578C 001D13EC 93 E1 00 0C */ stw r31, 0xc(r1) -/* 801D5790 001D13F0 3B E0 05 00 */ li r31, 0x500 -/* 801D5794 001D13F4 93 C1 00 08 */ stw r30, 8(r1) -/* 801D5798 001D13F8 7C 7E 1B 78 */ mr r30, r3 -/* 801D579C 001D13FC 4B FF FB 6D */ bl TRKSetBufferPosition -/* 801D57A0 001D1400 88 1E 00 14 */ lbz r0, 0x14(r30) -/* 801D57A4 001D1404 28 00 00 1A */ cmplwi r0, 0x1a -/* 801D57A8 001D1408 41 81 00 F8 */ bgt lbl_801D58A0 -/* 801D57AC 001D140C 3C 60 80 42 */ lis r3, lbl_80423188@ha -/* 801D57B0 001D1410 54 00 10 3A */ slwi r0, r0, 2 -/* 801D57B4 001D1414 38 63 31 88 */ addi r3, r3, lbl_80423188@l -/* 801D57B8 001D1418 7C 03 00 2E */ lwzx r0, r3, r0 -/* 801D57BC 001D141C 7C 09 03 A6 */ mtctr r0 -/* 801D57C0 001D1420 4E 80 04 20 */ bctr -/* 801D57C4 001D1424 7F C3 F3 78 */ mr r3, r30 -/* 801D57C8 001D1428 48 00 11 35 */ bl func_801D68FC -/* 801D57CC 001D142C 7C 7F 1B 78 */ mr r31, r3 -/* 801D57D0 001D1430 48 00 00 D0 */ b lbl_801D58A0 -/* 801D57D4 001D1434 7F C3 F3 78 */ mr r3, r30 -/* 801D57D8 001D1438 48 00 10 89 */ bl func_801D6860 -/* 801D57DC 001D143C 7C 7F 1B 78 */ mr r31, r3 -/* 801D57E0 001D1440 48 00 00 C0 */ b lbl_801D58A0 -/* 801D57E4 001D1444 7F C3 F3 78 */ mr r3, r30 -/* 801D57E8 001D1448 48 00 0F FD */ bl func_801D67E4 -/* 801D57EC 001D144C 7C 7F 1B 78 */ mr r31, r3 -/* 801D57F0 001D1450 48 00 00 B0 */ b lbl_801D58A0 -/* 801D57F4 001D1454 7F C3 F3 78 */ mr r3, r30 -/* 801D57F8 001D1458 48 00 0F 71 */ bl func_801D6768 -/* 801D57FC 001D145C 7C 7F 1B 78 */ mr r31, r3 -/* 801D5800 001D1460 48 00 00 A0 */ b lbl_801D58A0 -/* 801D5804 001D1464 7F C3 F3 78 */ mr r3, r30 -/* 801D5808 001D1468 48 00 0F 59 */ bl func_801D6760 -/* 801D580C 001D146C 7C 7F 1B 78 */ mr r31, r3 -/* 801D5810 001D1470 48 00 00 90 */ b lbl_801D58A0 -/* 801D5814 001D1474 7F C3 F3 78 */ mr r3, r30 -/* 801D5818 001D1478 48 00 0F 41 */ bl func_801D6758 -/* 801D581C 001D147C 7C 7F 1B 78 */ mr r31, r3 -/* 801D5820 001D1480 48 00 00 80 */ b lbl_801D58A0 -/* 801D5824 001D1484 7F C3 F3 78 */ mr r3, r30 -/* 801D5828 001D1488 48 00 0C E9 */ bl func_801D6510 -/* 801D582C 001D148C 7C 7F 1B 78 */ mr r31, r3 -/* 801D5830 001D1490 48 00 00 70 */ b lbl_801D58A0 -/* 801D5834 001D1494 7F C3 F3 78 */ mr r3, r30 -/* 801D5838 001D1498 48 00 0A BD */ bl func_801D62F4 -/* 801D583C 001D149C 7C 7F 1B 78 */ mr r31, r3 -/* 801D5840 001D14A0 48 00 00 60 */ b lbl_801D58A0 -/* 801D5844 001D14A4 7F C3 F3 78 */ mr r3, r30 -/* 801D5848 001D14A8 48 00 08 89 */ bl func_801D60D0 -/* 801D584C 001D14AC 7C 7F 1B 78 */ mr r31, r3 -/* 801D5850 001D14B0 48 00 00 50 */ b lbl_801D58A0 -/* 801D5854 001D14B4 7F C3 F3 78 */ mr r3, r30 -/* 801D5858 001D14B8 48 00 05 BD */ bl func_801D5E14 -/* 801D585C 001D14BC 7C 7F 1B 78 */ mr r31, r3 -/* 801D5860 001D14C0 48 00 00 40 */ b lbl_801D58A0 -/* 801D5864 001D14C4 7F C3 F3 78 */ mr r3, r30 -/* 801D5868 001D14C8 48 00 04 C9 */ bl func_801D5D30 -/* 801D586C 001D14CC 7C 7F 1B 78 */ mr r31, r3 -/* 801D5870 001D14D0 48 00 00 30 */ b lbl_801D58A0 -/* 801D5874 001D14D4 7F C3 F3 78 */ mr r3, r30 -/* 801D5878 001D14D8 48 00 01 E5 */ bl func_801D5A5C -/* 801D587C 001D14DC 7C 7F 1B 78 */ mr r31, r3 -/* 801D5880 001D14E0 48 00 00 20 */ b lbl_801D58A0 -/* 801D5884 001D14E4 7F C3 F3 78 */ mr r3, r30 -/* 801D5888 001D14E8 48 00 01 09 */ bl func_801D5990 -/* 801D588C 001D14EC 7C 7F 1B 78 */ mr r31, r3 -/* 801D5890 001D14F0 48 00 00 10 */ b lbl_801D58A0 -/* 801D5894 001D14F4 7F C3 F3 78 */ mr r3, r30 -/* 801D5898 001D14F8 48 00 00 2D */ bl func_801D58C4 -/* 801D589C 001D14FC 7C 7F 1B 78 */ mr r31, r3 -lbl_801D58A0: -/* 801D58A0 001D1500 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D58A4 001D1504 7F E3 FB 78 */ mr r3, r31 -/* 801D58A8 001D1508 83 E1 00 0C */ lwz r31, 0xc(r1) -/* 801D58AC 001D150C 83 C1 00 08 */ lwz r30, 8(r1) -/* 801D58B0 001D1510 7C 08 03 A6 */ mtlr r0 -/* 801D58B4 001D1514 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D58B8 001D1518 4E 80 00 20 */ blr - -.global func_801D58BC -func_801D58BC: -/* 801D58BC 001D151C 38 60 00 00 */ li r3, 0 -/* 801D58C0 001D1520 4E 80 00 20 */ blr - -.global func_801D58C4 -func_801D58C4: -/* 801D58C4 001D1524 94 21 FF B0 */ stwu r1, -0x50(r1) -/* 801D58C8 001D1528 7C 08 02 A6 */ mflr r0 -/* 801D58CC 001D152C 3C 80 80 40 */ lis r4, lbl_803FD680@ha -/* 801D58D0 001D1530 90 01 00 54 */ stw r0, 0x54(r1) -/* 801D58D4 001D1534 93 E1 00 4C */ stw r31, 0x4c(r1) -/* 801D58D8 001D1538 3B E4 D6 80 */ addi r31, r4, lbl_803FD680@l -/* 801D58DC 001D153C 93 C1 00 48 */ stw r30, 0x48(r1) -/* 801D58E0 001D1540 88 03 00 18 */ lbz r0, 0x18(r3) -/* 801D58E4 001D1544 8B C3 00 1C */ lbz r30, 0x1c(r3) -/* 801D58E8 001D1548 28 00 00 01 */ cmplwi r0, 1 -/* 801D58EC 001D154C 40 82 00 30 */ bne lbl_801D591C -/* 801D58F0 001D1550 38 7F 00 00 */ addi r3, r31, 0 -/* 801D58F4 001D1554 4B FF FE 01 */ bl usr_puts_serial -/* 801D58F8 001D1558 28 1E 00 00 */ cmplwi r30, 0 -/* 801D58FC 001D155C 41 82 00 10 */ beq lbl_801D590C -/* 801D5900 001D1560 38 7F 00 20 */ addi r3, r31, 0x20 -/* 801D5904 001D1564 4B FF FD F1 */ bl usr_puts_serial -/* 801D5908 001D1568 48 00 00 0C */ b lbl_801D5914 -lbl_801D590C: -/* 801D590C 001D156C 38 7F 00 28 */ addi r3, r31, 0x28 -/* 801D5910 001D1570 4B FF FD E5 */ bl usr_puts_serial -lbl_801D5914: -/* 801D5914 001D1574 7F C3 F3 78 */ mr r3, r30 -/* 801D5918 001D1578 48 00 40 85 */ bl SetUseSerialIO -lbl_801D591C: -/* 801D591C 001D157C 38 61 00 08 */ addi r3, r1, 8 -/* 801D5920 001D1580 38 80 00 00 */ li r4, 0 -/* 801D5924 001D1584 38 A0 00 40 */ li r5, 0x40 -/* 801D5928 001D1588 4B E2 E8 0D */ bl TRK_memset -/* 801D592C 001D158C 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5930 001D1590 38 00 00 80 */ li r0, 0x80 -/* 801D5934 001D1594 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D5938 001D1598 38 C0 00 40 */ li r6, 0x40 -/* 801D593C 001D159C 81 09 00 00 */ lwz r8, 0(r9) -/* 801D5940 001D15A0 38 A0 00 00 */ li r5, 0 -/* 801D5944 001D15A4 98 01 00 0C */ stb r0, 0xc(r1) -/* 801D5948 001D15A8 38 61 00 08 */ addi r3, r1, 8 -/* 801D594C 001D15AC 38 E8 00 01 */ addi r7, r8, 1 -/* 801D5950 001D15B0 38 80 00 40 */ li r4, 0x40 -/* 801D5954 001D15B4 91 01 00 14 */ stw r8, 0x14(r1) -/* 801D5958 001D15B8 38 07 00 01 */ addi r0, r7, 1 -/* 801D595C 001D15BC 90 E9 00 00 */ stw r7, 0(r9) -/* 801D5960 001D15C0 90 C1 00 08 */ stw r6, 8(r1) -/* 801D5964 001D15C4 98 A1 00 10 */ stb r5, 0x10(r1) -/* 801D5968 001D15C8 90 09 00 00 */ stw r0, 0(r9) -/* 801D596C 001D15CC 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D5970 001D15D0 48 00 3C 9D */ bl func_801D960C -/* 801D5974 001D15D4 80 01 00 54 */ lwz r0, 0x54(r1) -/* 801D5978 001D15D8 38 60 00 00 */ li r3, 0 -/* 801D597C 001D15DC 83 E1 00 4C */ lwz r31, 0x4c(r1) -/* 801D5980 001D15E0 83 C1 00 48 */ lwz r30, 0x48(r1) -/* 801D5984 001D15E4 7C 08 03 A6 */ mtlr r0 -/* 801D5988 001D15E8 38 21 00 50 */ addi r1, r1, 0x50 -/* 801D598C 001D15EC 4E 80 00 20 */ blr - -.global func_801D5990 -func_801D5990: -/* 801D5990 001D15F0 94 21 FF B0 */ stwu r1, -0x50(r1) -/* 801D5994 001D15F4 7C 08 02 A6 */ mflr r0 -/* 801D5998 001D15F8 90 01 00 54 */ stw r0, 0x54(r1) -/* 801D599C 001D15FC 93 E1 00 4C */ stw r31, 0x4c(r1) -/* 801D59A0 001D1600 48 00 1C 5D */ bl TRKTargetStop -/* 801D59A4 001D1604 2C 03 07 04 */ cmpwi r3, 0x704 -/* 801D59A8 001D1608 41 82 00 2C */ beq lbl_801D59D4 -/* 801D59AC 001D160C 40 80 00 10 */ bge lbl_801D59BC -/* 801D59B0 001D1610 2C 03 00 00 */ cmpwi r3, 0 -/* 801D59B4 001D1614 41 82 00 18 */ beq lbl_801D59CC -/* 801D59B8 001D1618 48 00 00 34 */ b lbl_801D59EC -lbl_801D59BC: -/* 801D59BC 001D161C 2C 03 07 06 */ cmpwi r3, 0x706 -/* 801D59C0 001D1620 41 82 00 24 */ beq lbl_801D59E4 -/* 801D59C4 001D1624 40 80 00 28 */ bge lbl_801D59EC -/* 801D59C8 001D1628 48 00 00 14 */ b lbl_801D59DC -lbl_801D59CC: -/* 801D59CC 001D162C 3B E0 00 00 */ li r31, 0 -/* 801D59D0 001D1630 48 00 00 20 */ b lbl_801D59F0 -lbl_801D59D4: -/* 801D59D4 001D1634 3B E0 00 21 */ li r31, 0x21 -/* 801D59D8 001D1638 48 00 00 18 */ b lbl_801D59F0 -lbl_801D59DC: -/* 801D59DC 001D163C 3B E0 00 22 */ li r31, 0x22 -/* 801D59E0 001D1640 48 00 00 10 */ b lbl_801D59F0 -lbl_801D59E4: -/* 801D59E4 001D1644 3B E0 00 20 */ li r31, 0x20 -/* 801D59E8 001D1648 48 00 00 08 */ b lbl_801D59F0 -lbl_801D59EC: -/* 801D59EC 001D164C 3B E0 00 01 */ li r31, 1 -lbl_801D59F0: -/* 801D59F0 001D1650 38 61 00 08 */ addi r3, r1, 8 -/* 801D59F4 001D1654 38 80 00 00 */ li r4, 0 -/* 801D59F8 001D1658 38 A0 00 40 */ li r5, 0x40 -/* 801D59FC 001D165C 4B E2 E7 39 */ bl TRK_memset -/* 801D5A00 001D1660 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5A04 001D1664 38 00 00 80 */ li r0, 0x80 -/* 801D5A08 001D1668 39 03 07 E8 */ addi r8, r3, lbl_804907E8@l -/* 801D5A0C 001D166C 38 A0 00 40 */ li r5, 0x40 -/* 801D5A10 001D1670 80 E8 00 00 */ lwz r7, 0(r8) -/* 801D5A14 001D1674 38 61 00 08 */ addi r3, r1, 8 -/* 801D5A18 001D1678 98 01 00 0C */ stb r0, 0xc(r1) -/* 801D5A1C 001D167C 38 80 00 40 */ li r4, 0x40 -/* 801D5A20 001D1680 38 C7 00 01 */ addi r6, r7, 1 -/* 801D5A24 001D1684 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D5A28 001D1688 38 06 00 01 */ addi r0, r6, 1 -/* 801D5A2C 001D168C 90 C8 00 00 */ stw r6, 0(r8) -/* 801D5A30 001D1690 90 A1 00 08 */ stw r5, 8(r1) -/* 801D5A34 001D1694 9B E1 00 10 */ stb r31, 0x10(r1) -/* 801D5A38 001D1698 90 08 00 00 */ stw r0, 0(r8) -/* 801D5A3C 001D169C 90 C1 00 14 */ stw r6, 0x14(r1) -/* 801D5A40 001D16A0 48 00 3B CD */ bl func_801D960C -/* 801D5A44 001D16A4 80 01 00 54 */ lwz r0, 0x54(r1) -/* 801D5A48 001D16A8 38 60 00 00 */ li r3, 0 -/* 801D5A4C 001D16AC 83 E1 00 4C */ lwz r31, 0x4c(r1) -/* 801D5A50 001D16B0 7C 08 03 A6 */ mtlr r0 -/* 801D5A54 001D16B4 38 21 00 50 */ addi r1, r1, 0x50 -/* 801D5A58 001D16B8 4E 80 00 20 */ blr - -.global func_801D5A5C -func_801D5A5C: -/* 801D5A5C 001D16BC 94 21 FE A0 */ stwu r1, -0x160(r1) -/* 801D5A60 001D16C0 7C 08 02 A6 */ mflr r0 -/* 801D5A64 001D16C4 38 80 00 00 */ li r4, 0 -/* 801D5A68 001D16C8 90 01 01 64 */ stw r0, 0x164(r1) -/* 801D5A6C 001D16CC BF 61 01 4C */ stmw r27, 0x14c(r1) -/* 801D5A70 001D16D0 7C 7B 1B 78 */ mr r27, r3 -/* 801D5A74 001D16D4 4B FF F8 95 */ bl TRKSetBufferPosition -/* 801D5A78 001D16D8 8B FB 00 18 */ lbz r31, 0x18(r27) -/* 801D5A7C 001D16DC 83 BB 00 20 */ lwz r29, 0x20(r27) -/* 801D5A80 001D16E0 2C 1F 00 10 */ cmpwi r31, 0x10 -/* 801D5A84 001D16E4 83 9B 00 24 */ lwz r28, 0x24(r27) -/* 801D5A88 001D16E8 41 82 00 2C */ beq lbl_801D5AB4 -/* 801D5A8C 001D16EC 40 80 00 1C */ bge lbl_801D5AA8 -/* 801D5A90 001D16F0 2C 1F 00 01 */ cmpwi r31, 1 -/* 801D5A94 001D16F4 41 82 00 8C */ beq lbl_801D5B20 -/* 801D5A98 001D16F8 40 80 00 FC */ bge lbl_801D5B94 -/* 801D5A9C 001D16FC 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D5AA0 001D1700 40 80 00 14 */ bge lbl_801D5AB4 -/* 801D5AA4 001D1704 48 00 00 F0 */ b lbl_801D5B94 -lbl_801D5AA8: -/* 801D5AA8 001D1708 2C 1F 00 12 */ cmpwi r31, 0x12 -/* 801D5AAC 001D170C 40 80 00 E8 */ bge lbl_801D5B94 -/* 801D5AB0 001D1710 48 00 00 70 */ b lbl_801D5B20 -lbl_801D5AB4: -/* 801D5AB4 001D1714 8B DB 00 1C */ lbz r30, 0x1c(r27) -/* 801D5AB8 001D1718 28 1E 00 01 */ cmplwi r30, 1 -/* 801D5ABC 001D171C 40 80 01 38 */ bge lbl_801D5BF4 -/* 801D5AC0 001D1720 38 61 01 08 */ addi r3, r1, 0x108 -/* 801D5AC4 001D1724 38 80 00 00 */ li r4, 0 -/* 801D5AC8 001D1728 38 A0 00 40 */ li r5, 0x40 -/* 801D5ACC 001D172C 4B E2 E6 69 */ bl TRK_memset -/* 801D5AD0 001D1730 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5AD4 001D1734 38 00 00 80 */ li r0, 0x80 -/* 801D5AD8 001D1738 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D5ADC 001D173C 38 C0 00 40 */ li r6, 0x40 -/* 801D5AE0 001D1740 81 09 00 00 */ lwz r8, 0(r9) -/* 801D5AE4 001D1744 38 A0 00 11 */ li r5, 0x11 -/* 801D5AE8 001D1748 98 01 01 0C */ stb r0, 0x10c(r1) -/* 801D5AEC 001D174C 38 61 01 08 */ addi r3, r1, 0x108 -/* 801D5AF0 001D1750 38 E8 00 01 */ addi r7, r8, 1 -/* 801D5AF4 001D1754 38 80 00 40 */ li r4, 0x40 -/* 801D5AF8 001D1758 91 01 01 14 */ stw r8, 0x114(r1) -/* 801D5AFC 001D175C 38 07 00 01 */ addi r0, r7, 1 -/* 801D5B00 001D1760 90 E9 00 00 */ stw r7, 0(r9) -/* 801D5B04 001D1764 90 C1 01 08 */ stw r6, 0x108(r1) -/* 801D5B08 001D1768 98 A1 01 10 */ stb r5, 0x110(r1) -/* 801D5B0C 001D176C 90 09 00 00 */ stw r0, 0(r9) -/* 801D5B10 001D1770 90 E1 01 14 */ stw r7, 0x114(r1) -/* 801D5B14 001D1774 48 00 3A F9 */ bl func_801D960C -/* 801D5B18 001D1778 38 60 00 00 */ li r3, 0 -/* 801D5B1C 001D177C 48 00 02 00 */ b lbl_801D5D1C -lbl_801D5B20: -/* 801D5B20 001D1780 48 00 1D 15 */ bl func_801D7834 -/* 801D5B24 001D1784 7C 03 E8 40 */ cmplw r3, r29 -/* 801D5B28 001D1788 41 80 00 0C */ blt lbl_801D5B34 -/* 801D5B2C 001D178C 7C 03 E0 40 */ cmplw r3, r28 -/* 801D5B30 001D1790 40 81 00 C4 */ ble lbl_801D5BF4 -lbl_801D5B34: -/* 801D5B34 001D1794 38 61 00 C8 */ addi r3, r1, 0xc8 -/* 801D5B38 001D1798 38 80 00 00 */ li r4, 0 -/* 801D5B3C 001D179C 38 A0 00 40 */ li r5, 0x40 -/* 801D5B40 001D17A0 4B E2 E5 F5 */ bl TRK_memset -/* 801D5B44 001D17A4 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5B48 001D17A8 38 00 00 80 */ li r0, 0x80 -/* 801D5B4C 001D17AC 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D5B50 001D17B0 38 C0 00 40 */ li r6, 0x40 -/* 801D5B54 001D17B4 81 09 00 00 */ lwz r8, 0(r9) -/* 801D5B58 001D17B8 38 A0 00 11 */ li r5, 0x11 -/* 801D5B5C 001D17BC 98 01 00 CC */ stb r0, 0xcc(r1) -/* 801D5B60 001D17C0 38 61 00 C8 */ addi r3, r1, 0xc8 -/* 801D5B64 001D17C4 38 E8 00 01 */ addi r7, r8, 1 -/* 801D5B68 001D17C8 38 80 00 40 */ li r4, 0x40 -/* 801D5B6C 001D17CC 91 01 00 D4 */ stw r8, 0xd4(r1) -/* 801D5B70 001D17D0 38 07 00 01 */ addi r0, r7, 1 -/* 801D5B74 001D17D4 90 E9 00 00 */ stw r7, 0(r9) -/* 801D5B78 001D17D8 90 C1 00 C8 */ stw r6, 0xc8(r1) -/* 801D5B7C 001D17DC 98 A1 00 D0 */ stb r5, 0xd0(r1) -/* 801D5B80 001D17E0 90 09 00 00 */ stw r0, 0(r9) -/* 801D5B84 001D17E4 90 E1 00 D4 */ stw r7, 0xd4(r1) -/* 801D5B88 001D17E8 48 00 3A 85 */ bl func_801D960C -/* 801D5B8C 001D17EC 38 60 00 00 */ li r3, 0 -/* 801D5B90 001D17F0 48 00 01 8C */ b lbl_801D5D1C -lbl_801D5B94: -/* 801D5B94 001D17F4 38 61 00 88 */ addi r3, r1, 0x88 -/* 801D5B98 001D17F8 38 80 00 00 */ li r4, 0 -/* 801D5B9C 001D17FC 38 A0 00 40 */ li r5, 0x40 -/* 801D5BA0 001D1800 4B E2 E5 95 */ bl TRK_memset -/* 801D5BA4 001D1804 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5BA8 001D1808 38 00 00 80 */ li r0, 0x80 -/* 801D5BAC 001D180C 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D5BB0 001D1810 38 C0 00 40 */ li r6, 0x40 -/* 801D5BB4 001D1814 81 09 00 00 */ lwz r8, 0(r9) -/* 801D5BB8 001D1818 38 A0 00 12 */ li r5, 0x12 -/* 801D5BBC 001D181C 98 01 00 8C */ stb r0, 0x8c(r1) -/* 801D5BC0 001D1820 38 61 00 88 */ addi r3, r1, 0x88 -/* 801D5BC4 001D1824 38 E8 00 01 */ addi r7, r8, 1 -/* 801D5BC8 001D1828 38 80 00 40 */ li r4, 0x40 -/* 801D5BCC 001D182C 91 01 00 94 */ stw r8, 0x94(r1) -/* 801D5BD0 001D1830 38 07 00 01 */ addi r0, r7, 1 -/* 801D5BD4 001D1834 90 E9 00 00 */ stw r7, 0(r9) -/* 801D5BD8 001D1838 90 C1 00 88 */ stw r6, 0x88(r1) -/* 801D5BDC 001D183C 98 A1 00 90 */ stb r5, 0x90(r1) -/* 801D5BE0 001D1840 90 09 00 00 */ stw r0, 0(r9) -/* 801D5BE4 001D1844 90 E1 00 94 */ stw r7, 0x94(r1) -/* 801D5BE8 001D1848 48 00 3A 25 */ bl func_801D960C -/* 801D5BEC 001D184C 38 60 00 00 */ li r3, 0 -/* 801D5BF0 001D1850 48 00 01 2C */ b lbl_801D5D1C -lbl_801D5BF4: -/* 801D5BF4 001D1854 48 00 1A 31 */ bl func_801D7624 -/* 801D5BF8 001D1858 2C 03 00 00 */ cmpwi r3, 0 -/* 801D5BFC 001D185C 40 82 00 64 */ bne lbl_801D5C60 -/* 801D5C00 001D1860 38 61 00 48 */ addi r3, r1, 0x48 -/* 801D5C04 001D1864 38 80 00 00 */ li r4, 0 -/* 801D5C08 001D1868 38 A0 00 40 */ li r5, 0x40 -/* 801D5C0C 001D186C 4B E2 E5 29 */ bl TRK_memset -/* 801D5C10 001D1870 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5C14 001D1874 38 00 00 80 */ li r0, 0x80 -/* 801D5C18 001D1878 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D5C1C 001D187C 38 C0 00 40 */ li r6, 0x40 -/* 801D5C20 001D1880 81 09 00 00 */ lwz r8, 0(r9) -/* 801D5C24 001D1884 38 A0 00 16 */ li r5, 0x16 -/* 801D5C28 001D1888 98 01 00 4C */ stb r0, 0x4c(r1) -/* 801D5C2C 001D188C 38 61 00 48 */ addi r3, r1, 0x48 -/* 801D5C30 001D1890 38 E8 00 01 */ addi r7, r8, 1 -/* 801D5C34 001D1894 38 80 00 40 */ li r4, 0x40 -/* 801D5C38 001D1898 91 01 00 54 */ stw r8, 0x54(r1) -/* 801D5C3C 001D189C 38 07 00 01 */ addi r0, r7, 1 -/* 801D5C40 001D18A0 90 E9 00 00 */ stw r7, 0(r9) -/* 801D5C44 001D18A4 90 C1 00 48 */ stw r6, 0x48(r1) -/* 801D5C48 001D18A8 98 A1 00 50 */ stb r5, 0x50(r1) -/* 801D5C4C 001D18AC 90 09 00 00 */ stw r0, 0(r9) -/* 801D5C50 001D18B0 90 E1 00 54 */ stw r7, 0x54(r1) -/* 801D5C54 001D18B4 48 00 39 B9 */ bl func_801D960C -/* 801D5C58 001D18B8 38 60 00 00 */ li r3, 0 -/* 801D5C5C 001D18BC 48 00 00 C0 */ b lbl_801D5D1C -lbl_801D5C60: -/* 801D5C60 001D18C0 38 61 00 08 */ addi r3, r1, 8 -/* 801D5C64 001D18C4 38 80 00 00 */ li r4, 0 -/* 801D5C68 001D18C8 38 A0 00 40 */ li r5, 0x40 -/* 801D5C6C 001D18CC 4B E2 E4 C9 */ bl TRK_memset -/* 801D5C70 001D18D0 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5C74 001D18D4 38 00 00 80 */ li r0, 0x80 -/* 801D5C78 001D18D8 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D5C7C 001D18DC 38 C0 00 40 */ li r6, 0x40 -/* 801D5C80 001D18E0 81 09 00 00 */ lwz r8, 0(r9) -/* 801D5C84 001D18E4 38 A0 00 00 */ li r5, 0 -/* 801D5C88 001D18E8 98 01 00 0C */ stb r0, 0xc(r1) -/* 801D5C8C 001D18EC 38 61 00 08 */ addi r3, r1, 8 -/* 801D5C90 001D18F0 38 E8 00 01 */ addi r7, r8, 1 -/* 801D5C94 001D18F4 38 80 00 40 */ li r4, 0x40 -/* 801D5C98 001D18F8 91 01 00 14 */ stw r8, 0x14(r1) -/* 801D5C9C 001D18FC 38 07 00 01 */ addi r0, r7, 1 -/* 801D5CA0 001D1900 90 E9 00 00 */ stw r7, 0(r9) -/* 801D5CA4 001D1904 90 C1 00 08 */ stw r6, 8(r1) -/* 801D5CA8 001D1908 98 A1 00 10 */ stb r5, 0x10(r1) -/* 801D5CAC 001D190C 90 09 00 00 */ stw r0, 0(r9) -/* 801D5CB0 001D1910 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D5CB4 001D1914 48 00 39 59 */ bl func_801D960C -/* 801D5CB8 001D1918 2C 1F 00 10 */ cmpwi r31, 0x10 -/* 801D5CBC 001D191C 38 60 00 00 */ li r3, 0 -/* 801D5CC0 001D1920 41 82 00 2C */ beq lbl_801D5CEC -/* 801D5CC4 001D1924 40 80 00 1C */ bge lbl_801D5CE0 -/* 801D5CC8 001D1928 2C 1F 00 01 */ cmpwi r31, 1 -/* 801D5CCC 001D192C 41 82 00 38 */ beq lbl_801D5D04 -/* 801D5CD0 001D1930 40 80 00 4C */ bge lbl_801D5D1C -/* 801D5CD4 001D1934 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D5CD8 001D1938 40 80 00 14 */ bge lbl_801D5CEC -/* 801D5CDC 001D193C 48 00 00 40 */ b lbl_801D5D1C -lbl_801D5CE0: -/* 801D5CE0 001D1940 2C 1F 00 12 */ cmpwi r31, 0x12 -/* 801D5CE4 001D1944 40 80 00 38 */ bge lbl_801D5D1C -/* 801D5CE8 001D1948 48 00 00 1C */ b lbl_801D5D04 -lbl_801D5CEC: -/* 801D5CEC 001D194C 20 1F 00 10 */ subfic r0, r31, 0x10 -/* 801D5CF0 001D1950 7F C3 F3 78 */ mr r3, r30 -/* 801D5CF4 001D1954 7C 00 00 34 */ cntlzw r0, r0 -/* 801D5CF8 001D1958 54 04 D9 7E */ srwi r4, r0, 5 -/* 801D5CFC 001D195C 48 00 1B C5 */ bl func_801D78C0 -/* 801D5D00 001D1960 48 00 00 1C */ b lbl_801D5D1C -lbl_801D5D04: -/* 801D5D04 001D1964 20 1F 00 11 */ subfic r0, r31, 0x11 -/* 801D5D08 001D1968 7F A3 EB 78 */ mr r3, r29 -/* 801D5D0C 001D196C 7C 00 00 34 */ cntlzw r0, r0 -/* 801D5D10 001D1970 7F 84 E3 78 */ mr r4, r28 -/* 801D5D14 001D1974 54 05 D9 7E */ srwi r5, r0, 5 -/* 801D5D18 001D1978 48 00 1B 2D */ bl func_801D7844 -lbl_801D5D1C: -/* 801D5D1C 001D197C BB 61 01 4C */ lmw r27, 0x14c(r1) -/* 801D5D20 001D1980 80 01 01 64 */ lwz r0, 0x164(r1) -/* 801D5D24 001D1984 7C 08 03 A6 */ mtlr r0 -/* 801D5D28 001D1988 38 21 01 60 */ addi r1, r1, 0x160 -/* 801D5D2C 001D198C 4E 80 00 20 */ blr - -.global func_801D5D30 -func_801D5D30: -/* 801D5D30 001D1990 94 21 FF 70 */ stwu r1, -0x90(r1) -/* 801D5D34 001D1994 7C 08 02 A6 */ mflr r0 -/* 801D5D38 001D1998 90 01 00 94 */ stw r0, 0x94(r1) -/* 801D5D3C 001D199C 48 00 18 E9 */ bl func_801D7624 -/* 801D5D40 001D19A0 2C 03 00 00 */ cmpwi r3, 0 -/* 801D5D44 001D19A4 40 82 00 64 */ bne lbl_801D5DA8 -/* 801D5D48 001D19A8 38 61 00 48 */ addi r3, r1, 0x48 -/* 801D5D4C 001D19AC 38 80 00 00 */ li r4, 0 -/* 801D5D50 001D19B0 38 A0 00 40 */ li r5, 0x40 -/* 801D5D54 001D19B4 4B E2 E3 E1 */ bl TRK_memset -/* 801D5D58 001D19B8 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5D5C 001D19BC 38 00 00 80 */ li r0, 0x80 -/* 801D5D60 001D19C0 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D5D64 001D19C4 38 C0 00 40 */ li r6, 0x40 -/* 801D5D68 001D19C8 81 09 00 00 */ lwz r8, 0(r9) -/* 801D5D6C 001D19CC 38 A0 00 16 */ li r5, 0x16 -/* 801D5D70 001D19D0 98 01 00 4C */ stb r0, 0x4c(r1) -/* 801D5D74 001D19D4 38 61 00 48 */ addi r3, r1, 0x48 -/* 801D5D78 001D19D8 38 E8 00 01 */ addi r7, r8, 1 -/* 801D5D7C 001D19DC 38 80 00 40 */ li r4, 0x40 -/* 801D5D80 001D19E0 91 01 00 54 */ stw r8, 0x54(r1) -/* 801D5D84 001D19E4 38 07 00 01 */ addi r0, r7, 1 -/* 801D5D88 001D19E8 90 E9 00 00 */ stw r7, 0(r9) -/* 801D5D8C 001D19EC 90 C1 00 48 */ stw r6, 0x48(r1) -/* 801D5D90 001D19F0 98 A1 00 50 */ stb r5, 0x50(r1) -/* 801D5D94 001D19F4 90 09 00 00 */ stw r0, 0(r9) -/* 801D5D98 001D19F8 90 E1 00 54 */ stw r7, 0x54(r1) -/* 801D5D9C 001D19FC 48 00 38 71 */ bl func_801D960C -/* 801D5DA0 001D1A00 38 60 00 00 */ li r3, 0 -/* 801D5DA4 001D1A04 48 00 00 60 */ b lbl_801D5E04 -lbl_801D5DA8: -/* 801D5DA8 001D1A08 38 61 00 08 */ addi r3, r1, 8 -/* 801D5DAC 001D1A0C 38 80 00 00 */ li r4, 0 -/* 801D5DB0 001D1A10 38 A0 00 40 */ li r5, 0x40 -/* 801D5DB4 001D1A14 4B E2 E3 81 */ bl TRK_memset -/* 801D5DB8 001D1A18 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5DBC 001D1A1C 38 00 00 80 */ li r0, 0x80 -/* 801D5DC0 001D1A20 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D5DC4 001D1A24 38 C0 00 40 */ li r6, 0x40 -/* 801D5DC8 001D1A28 81 09 00 00 */ lwz r8, 0(r9) -/* 801D5DCC 001D1A2C 38 A0 00 00 */ li r5, 0 -/* 801D5DD0 001D1A30 98 01 00 0C */ stb r0, 0xc(r1) -/* 801D5DD4 001D1A34 38 61 00 08 */ addi r3, r1, 8 -/* 801D5DD8 001D1A38 38 E8 00 01 */ addi r7, r8, 1 -/* 801D5DDC 001D1A3C 38 80 00 40 */ li r4, 0x40 -/* 801D5DE0 001D1A40 91 01 00 14 */ stw r8, 0x14(r1) -/* 801D5DE4 001D1A44 38 07 00 01 */ addi r0, r7, 1 -/* 801D5DE8 001D1A48 90 E9 00 00 */ stw r7, 0(r9) -/* 801D5DEC 001D1A4C 90 C1 00 08 */ stw r6, 8(r1) -/* 801D5DF0 001D1A50 98 A1 00 10 */ stb r5, 0x10(r1) -/* 801D5DF4 001D1A54 90 09 00 00 */ stw r0, 0(r9) -/* 801D5DF8 001D1A58 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D5DFC 001D1A5C 48 00 38 11 */ bl func_801D960C -/* 801D5E00 001D1A60 48 00 3B 59 */ bl TRKTargetContinue -lbl_801D5E04: -/* 801D5E04 001D1A64 80 01 00 94 */ lwz r0, 0x94(r1) -/* 801D5E08 001D1A68 7C 08 03 A6 */ mtlr r0 -/* 801D5E0C 001D1A6C 38 21 00 90 */ addi r1, r1, 0x90 -/* 801D5E10 001D1A70 4E 80 00 20 */ blr - -.global func_801D5E14 -func_801D5E14: -/* 801D5E14 001D1A74 94 21 FF 20 */ stwu r1, -0xe0(r1) -/* 801D5E18 001D1A78 7C 08 02 A6 */ mflr r0 -/* 801D5E1C 001D1A7C 38 80 00 00 */ li r4, 0 -/* 801D5E20 001D1A80 90 01 00 E4 */ stw r0, 0xe4(r1) -/* 801D5E24 001D1A84 93 E1 00 DC */ stw r31, 0xdc(r1) -/* 801D5E28 001D1A88 93 C1 00 D8 */ stw r30, 0xd8(r1) -/* 801D5E2C 001D1A8C 93 A1 00 D4 */ stw r29, 0xd4(r1) -/* 801D5E30 001D1A90 93 81 00 D0 */ stw r28, 0xd0(r1) -/* 801D5E34 001D1A94 7C 7C 1B 78 */ mr r28, r3 -/* 801D5E38 001D1A98 8B E3 00 18 */ lbz r31, 0x18(r3) -/* 801D5E3C 001D1A9C A3 C3 00 1C */ lhz r30, 0x1c(r3) -/* 801D5E40 001D1AA0 A3 A3 00 20 */ lhz r29, 0x20(r3) -/* 801D5E44 001D1AA4 4B FF F4 C5 */ bl TRKSetBufferPosition -/* 801D5E48 001D1AA8 7C 1E E8 40 */ cmplw r30, r29 -/* 801D5E4C 001D1AAC 40 81 00 64 */ ble lbl_801D5EB0 -/* 801D5E50 001D1AB0 38 61 00 4C */ addi r3, r1, 0x4c -/* 801D5E54 001D1AB4 38 80 00 00 */ li r4, 0 -/* 801D5E58 001D1AB8 38 A0 00 40 */ li r5, 0x40 -/* 801D5E5C 001D1ABC 4B E2 E2 D9 */ bl TRK_memset -/* 801D5E60 001D1AC0 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5E64 001D1AC4 38 00 00 80 */ li r0, 0x80 -/* 801D5E68 001D1AC8 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D5E6C 001D1ACC 38 C0 00 40 */ li r6, 0x40 -/* 801D5E70 001D1AD0 81 09 00 00 */ lwz r8, 0(r9) -/* 801D5E74 001D1AD4 38 A0 00 14 */ li r5, 0x14 -/* 801D5E78 001D1AD8 98 01 00 50 */ stb r0, 0x50(r1) -/* 801D5E7C 001D1ADC 38 61 00 4C */ addi r3, r1, 0x4c -/* 801D5E80 001D1AE0 38 E8 00 01 */ addi r7, r8, 1 -/* 801D5E84 001D1AE4 38 80 00 40 */ li r4, 0x40 -/* 801D5E88 001D1AE8 91 01 00 58 */ stw r8, 0x58(r1) -/* 801D5E8C 001D1AEC 38 07 00 01 */ addi r0, r7, 1 -/* 801D5E90 001D1AF0 90 E9 00 00 */ stw r7, 0(r9) -/* 801D5E94 001D1AF4 90 C1 00 4C */ stw r6, 0x4c(r1) -/* 801D5E98 001D1AF8 98 A1 00 54 */ stb r5, 0x54(r1) -/* 801D5E9C 001D1AFC 90 09 00 00 */ stw r0, 0(r9) -/* 801D5EA0 001D1B00 90 E1 00 58 */ stw r7, 0x58(r1) -/* 801D5EA4 001D1B04 48 00 37 69 */ bl func_801D960C -/* 801D5EA8 001D1B08 38 60 00 00 */ li r3, 0 -/* 801D5EAC 001D1B0C 48 00 02 04 */ b lbl_801D60B0 -lbl_801D5EB0: -/* 801D5EB0 001D1B10 7F 83 E3 78 */ mr r3, r28 -/* 801D5EB4 001D1B14 38 80 00 40 */ li r4, 0x40 -/* 801D5EB8 001D1B18 4B FF F4 51 */ bl TRKSetBufferPosition -/* 801D5EBC 001D1B1C 2C 1F 00 02 */ cmpwi r31, 2 -/* 801D5EC0 001D1B20 41 82 00 64 */ beq lbl_801D5F24 -/* 801D5EC4 001D1B24 40 80 00 14 */ bge lbl_801D5ED8 -/* 801D5EC8 001D1B28 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D5ECC 001D1B2C 41 82 00 18 */ beq lbl_801D5EE4 -/* 801D5ED0 001D1B30 40 80 00 34 */ bge lbl_801D5F04 -/* 801D5ED4 001D1B34 48 00 00 90 */ b lbl_801D5F64 -lbl_801D5ED8: -/* 801D5ED8 001D1B38 2C 1F 00 04 */ cmpwi r31, 4 -/* 801D5EDC 001D1B3C 40 80 00 88 */ bge lbl_801D5F64 -/* 801D5EE0 001D1B40 48 00 00 64 */ b lbl_801D5F44 -lbl_801D5EE4: -/* 801D5EE4 001D1B44 7F C3 F3 78 */ mr r3, r30 -/* 801D5EE8 001D1B48 7F A4 EB 78 */ mr r4, r29 -/* 801D5EEC 001D1B4C 7F 85 E3 78 */ mr r5, r28 -/* 801D5EF0 001D1B50 38 C1 00 08 */ addi r6, r1, 8 -/* 801D5EF4 001D1B54 38 E0 00 00 */ li r7, 0 -/* 801D5EF8 001D1B58 48 00 28 01 */ bl TRKTargetAccessDefault -/* 801D5EFC 001D1B5C 7C 7F 1B 78 */ mr r31, r3 -/* 801D5F00 001D1B60 48 00 00 68 */ b lbl_801D5F68 -lbl_801D5F04: -/* 801D5F04 001D1B64 7F C3 F3 78 */ mr r3, r30 -/* 801D5F08 001D1B68 7F A4 EB 78 */ mr r4, r29 -/* 801D5F0C 001D1B6C 7F 85 E3 78 */ mr r5, r28 -/* 801D5F10 001D1B70 38 C1 00 08 */ addi r6, r1, 8 -/* 801D5F14 001D1B74 38 E0 00 00 */ li r7, 0 -/* 801D5F18 001D1B78 48 00 22 D5 */ bl TRKTargetAccessFP -/* 801D5F1C 001D1B7C 7C 7F 1B 78 */ mr r31, r3 -/* 801D5F20 001D1B80 48 00 00 48 */ b lbl_801D5F68 -lbl_801D5F24: -/* 801D5F24 001D1B84 7F C3 F3 78 */ mr r3, r30 -/* 801D5F28 001D1B88 7F A4 EB 78 */ mr r4, r29 -/* 801D5F2C 001D1B8C 7F 85 E3 78 */ mr r5, r28 -/* 801D5F30 001D1B90 38 C1 00 08 */ addi r6, r1, 8 -/* 801D5F34 001D1B94 38 E0 00 00 */ li r7, 0 -/* 801D5F38 001D1B98 48 00 21 45 */ bl TRKTargetAccessExtended1 -/* 801D5F3C 001D1B9C 7C 7F 1B 78 */ mr r31, r3 -/* 801D5F40 001D1BA0 48 00 00 28 */ b lbl_801D5F68 -lbl_801D5F44: -/* 801D5F44 001D1BA4 7F C3 F3 78 */ mr r3, r30 -/* 801D5F48 001D1BA8 7F A4 EB 78 */ mr r4, r29 -/* 801D5F4C 001D1BAC 7F 85 E3 78 */ mr r5, r28 -/* 801D5F50 001D1BB0 38 C1 00 08 */ addi r6, r1, 8 -/* 801D5F54 001D1BB4 38 E0 00 00 */ li r7, 0 -/* 801D5F58 001D1BB8 48 00 1C ED */ bl TRKTargetAccessExtended2 -/* 801D5F5C 001D1BBC 7C 7F 1B 78 */ mr r31, r3 -/* 801D5F60 001D1BC0 48 00 00 08 */ b lbl_801D5F68 -lbl_801D5F64: -/* 801D5F64 001D1BC4 3B E0 07 03 */ li r31, 0x703 -lbl_801D5F68: -/* 801D5F68 001D1BC8 7F 83 E3 78 */ mr r3, r28 -/* 801D5F6C 001D1BCC 38 80 00 00 */ li r4, 0 -/* 801D5F70 001D1BD0 4B FF F3 C9 */ bl TRKResetBuffer -/* 801D5F74 001D1BD4 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D5F78 001D1BD8 40 82 00 54 */ bne lbl_801D5FCC -/* 801D5F7C 001D1BDC 38 61 00 8C */ addi r3, r1, 0x8c -/* 801D5F80 001D1BE0 38 80 00 00 */ li r4, 0 -/* 801D5F84 001D1BE4 38 A0 00 40 */ li r5, 0x40 -/* 801D5F88 001D1BE8 4B E2 E1 AD */ bl TRK_memset -/* 801D5F8C 001D1BEC 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D5F90 001D1BF0 38 00 00 40 */ li r0, 0x40 -/* 801D5F94 001D1BF4 38 E3 07 E8 */ addi r7, r3, lbl_804907E8@l -/* 801D5F98 001D1BF8 38 A0 00 80 */ li r5, 0x80 -/* 801D5F9C 001D1BFC 80 C7 00 00 */ lwz r6, 0(r7) -/* 801D5FA0 001D1C00 7F 83 E3 78 */ mr r3, r28 -/* 801D5FA4 001D1C04 90 01 00 8C */ stw r0, 0x8c(r1) -/* 801D5FA8 001D1C08 38 81 00 8C */ addi r4, r1, 0x8c -/* 801D5FAC 001D1C0C 38 06 00 01 */ addi r0, r6, 1 -/* 801D5FB0 001D1C10 98 A1 00 90 */ stb r5, 0x90(r1) -/* 801D5FB4 001D1C14 38 A0 00 40 */ li r5, 0x40 -/* 801D5FB8 001D1C18 9B E1 00 94 */ stb r31, 0x94(r1) -/* 801D5FBC 001D1C1C 90 07 00 00 */ stw r0, 0(r7) -/* 801D5FC0 001D1C20 90 C1 00 98 */ stw r6, 0x98(r1) -/* 801D5FC4 001D1C24 4B FF F2 A1 */ bl TRKAppendBuffer -/* 801D5FC8 001D1C28 7C 7F 1B 78 */ mr r31, r3 -lbl_801D5FCC: -/* 801D5FCC 001D1C2C 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D5FD0 001D1C30 41 82 00 D8 */ beq lbl_801D60A8 -/* 801D5FD4 001D1C34 2C 1F 07 03 */ cmpwi r31, 0x703 -/* 801D5FD8 001D1C38 41 82 00 38 */ beq lbl_801D6010 -/* 801D5FDC 001D1C3C 40 80 00 1C */ bge lbl_801D5FF8 -/* 801D5FE0 001D1C40 2C 1F 07 01 */ cmpwi r31, 0x701 -/* 801D5FE4 001D1C44 41 82 00 34 */ beq lbl_801D6018 -/* 801D5FE8 001D1C48 40 80 00 40 */ bge lbl_801D6028 -/* 801D5FEC 001D1C4C 2C 1F 03 02 */ cmpwi r31, 0x302 -/* 801D5FF0 001D1C50 41 82 00 30 */ beq lbl_801D6020 -/* 801D5FF4 001D1C54 48 00 00 54 */ b lbl_801D6048 -lbl_801D5FF8: -/* 801D5FF8 001D1C58 2C 1F 07 06 */ cmpwi r31, 0x706 -/* 801D5FFC 001D1C5C 41 82 00 44 */ beq lbl_801D6040 -/* 801D6000 001D1C60 40 80 00 48 */ bge lbl_801D6048 -/* 801D6004 001D1C64 2C 1F 07 05 */ cmpwi r31, 0x705 -/* 801D6008 001D1C68 40 80 00 30 */ bge lbl_801D6038 -/* 801D600C 001D1C6C 48 00 00 24 */ b lbl_801D6030 -lbl_801D6010: -/* 801D6010 001D1C70 3B E0 00 12 */ li r31, 0x12 -/* 801D6014 001D1C74 48 00 00 38 */ b lbl_801D604C -lbl_801D6018: -/* 801D6018 001D1C78 3B E0 00 14 */ li r31, 0x14 -/* 801D601C 001D1C7C 48 00 00 30 */ b lbl_801D604C -lbl_801D6020: -/* 801D6020 001D1C80 3B E0 00 02 */ li r31, 2 -/* 801D6024 001D1C84 48 00 00 28 */ b lbl_801D604C -lbl_801D6028: -/* 801D6028 001D1C88 3B E0 00 15 */ li r31, 0x15 -/* 801D602C 001D1C8C 48 00 00 20 */ b lbl_801D604C -lbl_801D6030: -/* 801D6030 001D1C90 3B E0 00 21 */ li r31, 0x21 -/* 801D6034 001D1C94 48 00 00 18 */ b lbl_801D604C -lbl_801D6038: -/* 801D6038 001D1C98 3B E0 00 22 */ li r31, 0x22 -/* 801D603C 001D1C9C 48 00 00 10 */ b lbl_801D604C -lbl_801D6040: -/* 801D6040 001D1CA0 3B E0 00 20 */ li r31, 0x20 -/* 801D6044 001D1CA4 48 00 00 08 */ b lbl_801D604C -lbl_801D6048: -/* 801D6048 001D1CA8 3B E0 00 03 */ li r31, 3 -lbl_801D604C: -/* 801D604C 001D1CAC 38 61 00 0C */ addi r3, r1, 0xc -/* 801D6050 001D1CB0 38 80 00 00 */ li r4, 0 -/* 801D6054 001D1CB4 38 A0 00 40 */ li r5, 0x40 -/* 801D6058 001D1CB8 4B E2 E0 DD */ bl TRK_memset -/* 801D605C 001D1CBC 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D6060 001D1CC0 38 00 00 80 */ li r0, 0x80 -/* 801D6064 001D1CC4 39 03 07 E8 */ addi r8, r3, lbl_804907E8@l -/* 801D6068 001D1CC8 38 A0 00 40 */ li r5, 0x40 -/* 801D606C 001D1CCC 80 E8 00 00 */ lwz r7, 0(r8) -/* 801D6070 001D1CD0 38 61 00 0C */ addi r3, r1, 0xc -/* 801D6074 001D1CD4 98 01 00 10 */ stb r0, 0x10(r1) -/* 801D6078 001D1CD8 38 80 00 40 */ li r4, 0x40 -/* 801D607C 001D1CDC 38 C7 00 01 */ addi r6, r7, 1 -/* 801D6080 001D1CE0 90 E1 00 18 */ stw r7, 0x18(r1) -/* 801D6084 001D1CE4 38 06 00 01 */ addi r0, r6, 1 -/* 801D6088 001D1CE8 90 C8 00 00 */ stw r6, 0(r8) -/* 801D608C 001D1CEC 90 A1 00 0C */ stw r5, 0xc(r1) -/* 801D6090 001D1CF0 9B E1 00 14 */ stb r31, 0x14(r1) -/* 801D6094 001D1CF4 90 08 00 00 */ stw r0, 0(r8) -/* 801D6098 001D1CF8 90 C1 00 18 */ stw r6, 0x18(r1) -/* 801D609C 001D1CFC 48 00 35 71 */ bl func_801D960C -/* 801D60A0 001D1D00 38 60 00 00 */ li r3, 0 -/* 801D60A4 001D1D04 48 00 00 0C */ b lbl_801D60B0 -lbl_801D60A8: -/* 801D60A8 001D1D08 7F 83 E3 78 */ mr r3, r28 -/* 801D60AC 001D1D0C 4B FF EC 31 */ bl func_801D4CDC -lbl_801D60B0: -/* 801D60B0 001D1D10 80 01 00 E4 */ lwz r0, 0xe4(r1) -/* 801D60B4 001D1D14 83 E1 00 DC */ lwz r31, 0xdc(r1) -/* 801D60B8 001D1D18 83 C1 00 D8 */ lwz r30, 0xd8(r1) -/* 801D60BC 001D1D1C 83 A1 00 D4 */ lwz r29, 0xd4(r1) -/* 801D60C0 001D1D20 83 81 00 D0 */ lwz r28, 0xd0(r1) -/* 801D60C4 001D1D24 7C 08 03 A6 */ mtlr r0 -/* 801D60C8 001D1D28 38 21 00 E0 */ addi r1, r1, 0xe0 -/* 801D60CC 001D1D2C 4E 80 00 20 */ blr - -.global func_801D60D0 -func_801D60D0: -/* 801D60D0 001D1D30 94 21 FF 20 */ stwu r1, -0xe0(r1) -/* 801D60D4 001D1D34 7C 08 02 A6 */ mflr r0 -/* 801D60D8 001D1D38 90 01 00 E4 */ stw r0, 0xe4(r1) -/* 801D60DC 001D1D3C 93 E1 00 DC */ stw r31, 0xdc(r1) -/* 801D60E0 001D1D40 7C 7F 1B 78 */ mr r31, r3 -/* 801D60E4 001D1D44 A0 83 00 1C */ lhz r4, 0x1c(r3) -/* 801D60E8 001D1D48 A0 03 00 20 */ lhz r0, 0x20(r3) -/* 801D60EC 001D1D4C 7C 04 00 40 */ cmplw r4, r0 -/* 801D60F0 001D1D50 40 81 00 64 */ ble lbl_801D6154 -/* 801D60F4 001D1D54 38 61 00 4C */ addi r3, r1, 0x4c -/* 801D60F8 001D1D58 38 80 00 00 */ li r4, 0 -/* 801D60FC 001D1D5C 38 A0 00 40 */ li r5, 0x40 -/* 801D6100 001D1D60 4B E2 E0 35 */ bl TRK_memset -/* 801D6104 001D1D64 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D6108 001D1D68 38 00 00 80 */ li r0, 0x80 -/* 801D610C 001D1D6C 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D6110 001D1D70 38 C0 00 40 */ li r6, 0x40 -/* 801D6114 001D1D74 81 09 00 00 */ lwz r8, 0(r9) -/* 801D6118 001D1D78 38 A0 00 14 */ li r5, 0x14 -/* 801D611C 001D1D7C 98 01 00 50 */ stb r0, 0x50(r1) -/* 801D6120 001D1D80 38 61 00 4C */ addi r3, r1, 0x4c -/* 801D6124 001D1D84 38 E8 00 01 */ addi r7, r8, 1 -/* 801D6128 001D1D88 38 80 00 40 */ li r4, 0x40 -/* 801D612C 001D1D8C 91 01 00 58 */ stw r8, 0x58(r1) -/* 801D6130 001D1D90 38 07 00 01 */ addi r0, r7, 1 -/* 801D6134 001D1D94 90 E9 00 00 */ stw r7, 0(r9) -/* 801D6138 001D1D98 90 C1 00 4C */ stw r6, 0x4c(r1) -/* 801D613C 001D1D9C 98 A1 00 54 */ stb r5, 0x54(r1) -/* 801D6140 001D1DA0 90 09 00 00 */ stw r0, 0(r9) -/* 801D6144 001D1DA4 90 E1 00 58 */ stw r7, 0x58(r1) -/* 801D6148 001D1DA8 48 00 34 C5 */ bl func_801D960C -/* 801D614C 001D1DAC 38 60 00 00 */ li r3, 0 -/* 801D6150 001D1DB0 48 00 01 90 */ b lbl_801D62E0 -lbl_801D6154: -/* 801D6154 001D1DB4 3C 80 80 49 */ lis r4, lbl_804907E8@ha -/* 801D6158 001D1DB8 38 00 00 80 */ li r0, 0x80 -/* 801D615C 001D1DBC 38 C4 07 E8 */ addi r6, r4, lbl_804907E8@l -/* 801D6160 001D1DC0 38 E0 04 68 */ li r7, 0x468 -/* 801D6164 001D1DC4 80 A6 00 00 */ lwz r5, 0(r6) -/* 801D6168 001D1DC8 38 80 00 00 */ li r4, 0 -/* 801D616C 001D1DCC 98 01 00 90 */ stb r0, 0x90(r1) -/* 801D6170 001D1DD0 38 05 00 01 */ addi r0, r5, 1 -/* 801D6174 001D1DD4 90 E1 00 8C */ stw r7, 0x8c(r1) -/* 801D6178 001D1DD8 90 06 00 00 */ stw r0, 0(r6) -/* 801D617C 001D1DDC 90 A1 00 98 */ stw r5, 0x98(r1) -/* 801D6180 001D1DE0 4B FF F1 B9 */ bl TRKResetBuffer -/* 801D6184 001D1DE4 7F E3 FB 78 */ mr r3, r31 -/* 801D6188 001D1DE8 38 81 00 8C */ addi r4, r1, 0x8c -/* 801D618C 001D1DEC 38 A0 00 40 */ li r5, 0x40 -/* 801D6190 001D1DF0 4B FF EE E5 */ bl TRKAppendBuffer_ui8 -/* 801D6194 001D1DF4 7F E5 FB 78 */ mr r5, r31 -/* 801D6198 001D1DF8 38 C1 00 08 */ addi r6, r1, 8 -/* 801D619C 001D1DFC 38 60 00 00 */ li r3, 0 -/* 801D61A0 001D1E00 38 80 00 24 */ li r4, 0x24 -/* 801D61A4 001D1E04 38 E0 00 01 */ li r7, 1 -/* 801D61A8 001D1E08 48 00 25 51 */ bl TRKTargetAccessDefault -/* 801D61AC 001D1E0C 2C 03 00 00 */ cmpwi r3, 0 -/* 801D61B0 001D1E10 40 82 00 1C */ bne lbl_801D61CC -/* 801D61B4 001D1E14 7F E5 FB 78 */ mr r5, r31 -/* 801D61B8 001D1E18 38 C1 00 08 */ addi r6, r1, 8 -/* 801D61BC 001D1E1C 38 60 00 00 */ li r3, 0 -/* 801D61C0 001D1E20 38 80 00 21 */ li r4, 0x21 -/* 801D61C4 001D1E24 38 E0 00 01 */ li r7, 1 -/* 801D61C8 001D1E28 48 00 20 25 */ bl TRKTargetAccessFP -lbl_801D61CC: -/* 801D61CC 001D1E2C 2C 03 00 00 */ cmpwi r3, 0 -/* 801D61D0 001D1E30 40 82 00 1C */ bne lbl_801D61EC -/* 801D61D4 001D1E34 7F E5 FB 78 */ mr r5, r31 -/* 801D61D8 001D1E38 38 C1 00 08 */ addi r6, r1, 8 -/* 801D61DC 001D1E3C 38 60 00 00 */ li r3, 0 -/* 801D61E0 001D1E40 38 80 00 60 */ li r4, 0x60 -/* 801D61E4 001D1E44 38 E0 00 01 */ li r7, 1 -/* 801D61E8 001D1E48 48 00 1E 95 */ bl TRKTargetAccessExtended1 -lbl_801D61EC: -/* 801D61EC 001D1E4C 2C 03 00 00 */ cmpwi r3, 0 -/* 801D61F0 001D1E50 40 82 00 1C */ bne lbl_801D620C -/* 801D61F4 001D1E54 7F E5 FB 78 */ mr r5, r31 -/* 801D61F8 001D1E58 38 C1 00 08 */ addi r6, r1, 8 -/* 801D61FC 001D1E5C 38 60 00 00 */ li r3, 0 -/* 801D6200 001D1E60 38 80 00 1F */ li r4, 0x1f -/* 801D6204 001D1E64 38 E0 00 01 */ li r7, 1 -/* 801D6208 001D1E68 48 00 1A 3D */ bl TRKTargetAccessExtended2 -lbl_801D620C: -/* 801D620C 001D1E6C 2C 03 00 00 */ cmpwi r3, 0 -/* 801D6210 001D1E70 41 82 00 C8 */ beq lbl_801D62D8 -/* 801D6214 001D1E74 2C 03 07 04 */ cmpwi r3, 0x704 -/* 801D6218 001D1E78 41 82 00 48 */ beq lbl_801D6260 -/* 801D621C 001D1E7C 40 80 00 1C */ bge lbl_801D6238 -/* 801D6220 001D1E80 2C 03 07 02 */ cmpwi r3, 0x702 -/* 801D6224 001D1E84 41 82 00 34 */ beq lbl_801D6258 -/* 801D6228 001D1E88 40 80 00 20 */ bge lbl_801D6248 -/* 801D622C 001D1E8C 2C 03 07 01 */ cmpwi r3, 0x701 -/* 801D6230 001D1E90 40 80 00 20 */ bge lbl_801D6250 -/* 801D6234 001D1E94 48 00 00 44 */ b lbl_801D6278 -lbl_801D6238: -/* 801D6238 001D1E98 2C 03 07 06 */ cmpwi r3, 0x706 -/* 801D623C 001D1E9C 41 82 00 34 */ beq lbl_801D6270 -/* 801D6240 001D1EA0 40 80 00 38 */ bge lbl_801D6278 -/* 801D6244 001D1EA4 48 00 00 24 */ b lbl_801D6268 -lbl_801D6248: -/* 801D6248 001D1EA8 3B E0 00 12 */ li r31, 0x12 -/* 801D624C 001D1EAC 48 00 00 30 */ b lbl_801D627C -lbl_801D6250: -/* 801D6250 001D1EB0 3B E0 00 14 */ li r31, 0x14 -/* 801D6254 001D1EB4 48 00 00 28 */ b lbl_801D627C -lbl_801D6258: -/* 801D6258 001D1EB8 3B E0 00 15 */ li r31, 0x15 -/* 801D625C 001D1EBC 48 00 00 20 */ b lbl_801D627C -lbl_801D6260: -/* 801D6260 001D1EC0 3B E0 00 21 */ li r31, 0x21 -/* 801D6264 001D1EC4 48 00 00 18 */ b lbl_801D627C -lbl_801D6268: -/* 801D6268 001D1EC8 3B E0 00 22 */ li r31, 0x22 -/* 801D626C 001D1ECC 48 00 00 10 */ b lbl_801D627C -lbl_801D6270: -/* 801D6270 001D1ED0 3B E0 00 20 */ li r31, 0x20 -/* 801D6274 001D1ED4 48 00 00 08 */ b lbl_801D627C -lbl_801D6278: -/* 801D6278 001D1ED8 3B E0 00 03 */ li r31, 3 -lbl_801D627C: -/* 801D627C 001D1EDC 38 61 00 0C */ addi r3, r1, 0xc -/* 801D6280 001D1EE0 38 80 00 00 */ li r4, 0 -/* 801D6284 001D1EE4 38 A0 00 40 */ li r5, 0x40 -/* 801D6288 001D1EE8 4B E2 DE AD */ bl TRK_memset -/* 801D628C 001D1EEC 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D6290 001D1EF0 38 00 00 80 */ li r0, 0x80 -/* 801D6294 001D1EF4 39 03 07 E8 */ addi r8, r3, lbl_804907E8@l -/* 801D6298 001D1EF8 38 A0 00 40 */ li r5, 0x40 -/* 801D629C 001D1EFC 80 E8 00 00 */ lwz r7, 0(r8) -/* 801D62A0 001D1F00 38 61 00 0C */ addi r3, r1, 0xc -/* 801D62A4 001D1F04 98 01 00 10 */ stb r0, 0x10(r1) -/* 801D62A8 001D1F08 38 80 00 40 */ li r4, 0x40 -/* 801D62AC 001D1F0C 38 C7 00 01 */ addi r6, r7, 1 -/* 801D62B0 001D1F10 90 E1 00 18 */ stw r7, 0x18(r1) -/* 801D62B4 001D1F14 38 06 00 01 */ addi r0, r6, 1 -/* 801D62B8 001D1F18 90 C8 00 00 */ stw r6, 0(r8) -/* 801D62BC 001D1F1C 90 A1 00 0C */ stw r5, 0xc(r1) -/* 801D62C0 001D1F20 9B E1 00 14 */ stb r31, 0x14(r1) -/* 801D62C4 001D1F24 90 08 00 00 */ stw r0, 0(r8) -/* 801D62C8 001D1F28 90 C1 00 18 */ stw r6, 0x18(r1) -/* 801D62CC 001D1F2C 48 00 33 41 */ bl func_801D960C -/* 801D62D0 001D1F30 38 60 00 00 */ li r3, 0 -/* 801D62D4 001D1F34 48 00 00 0C */ b lbl_801D62E0 -lbl_801D62D8: -/* 801D62D8 001D1F38 7F E3 FB 78 */ mr r3, r31 -/* 801D62DC 001D1F3C 4B FF EA 01 */ bl func_801D4CDC -lbl_801D62E0: -/* 801D62E0 001D1F40 80 01 00 E4 */ lwz r0, 0xe4(r1) -/* 801D62E4 001D1F44 83 E1 00 DC */ lwz r31, 0xdc(r1) -/* 801D62E8 001D1F48 7C 08 03 A6 */ mtlr r0 -/* 801D62EC 001D1F4C 38 21 00 E0 */ addi r1, r1, 0xe0 -/* 801D62F0 001D1F50 4E 80 00 20 */ blr - -.global func_801D62F4 -func_801D62F4: -/* 801D62F4 001D1F54 54 2B 06 FE */ clrlwi r11, r1, 0x1b -/* 801D62F8 001D1F58 7C 2C 0B 78 */ mr r12, r1 -/* 801D62FC 001D1F5C 21 6B F6 C0 */ subfic r11, r11, -2368 -/* 801D6300 001D1F60 7C 21 59 6E */ stwux r1, r1, r11 -/* 801D6304 001D1F64 7C 08 02 A6 */ mflr r0 -/* 801D6308 001D1F68 90 0C 00 04 */ stw r0, 4(r12) -/* 801D630C 001D1F6C 93 EC FF FC */ stw r31, -4(r12) -/* 801D6310 001D1F70 93 CC FF F8 */ stw r30, -8(r12) -/* 801D6314 001D1F74 93 AC FF F4 */ stw r29, -0xc(r12) -/* 801D6318 001D1F78 7C 7D 1B 78 */ mr r29, r3 -/* 801D631C 001D1F7C 8B E3 00 18 */ lbz r31, 0x18(r3) -/* 801D6320 001D1F80 83 C3 00 20 */ lwz r30, 0x20(r3) -/* 801D6324 001D1F84 57 E0 07 BD */ rlwinm. r0, r31, 0, 0x1e, 0x1e -/* 801D6328 001D1F88 A0 83 00 1C */ lhz r4, 0x1c(r3) -/* 801D632C 001D1F8C 41 82 00 64 */ beq lbl_801D6390 -/* 801D6330 001D1F90 38 61 00 64 */ addi r3, r1, 0x64 -/* 801D6334 001D1F94 38 80 00 00 */ li r4, 0 -/* 801D6338 001D1F98 38 A0 00 40 */ li r5, 0x40 -/* 801D633C 001D1F9C 4B E2 DD F9 */ bl TRK_memset -/* 801D6340 001D1FA0 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D6344 001D1FA4 38 00 00 80 */ li r0, 0x80 -/* 801D6348 001D1FA8 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D634C 001D1FAC 38 C0 00 40 */ li r6, 0x40 -/* 801D6350 001D1FB0 81 09 00 00 */ lwz r8, 0(r9) -/* 801D6354 001D1FB4 38 A0 00 12 */ li r5, 0x12 -/* 801D6358 001D1FB8 98 01 00 68 */ stb r0, 0x68(r1) -/* 801D635C 001D1FBC 38 61 00 64 */ addi r3, r1, 0x64 -/* 801D6360 001D1FC0 38 E8 00 01 */ addi r7, r8, 1 -/* 801D6364 001D1FC4 38 80 00 40 */ li r4, 0x40 -/* 801D6368 001D1FC8 91 01 00 70 */ stw r8, 0x70(r1) -/* 801D636C 001D1FCC 38 07 00 01 */ addi r0, r7, 1 -/* 801D6370 001D1FD0 90 E9 00 00 */ stw r7, 0(r9) -/* 801D6374 001D1FD4 90 C1 00 64 */ stw r6, 0x64(r1) -/* 801D6378 001D1FD8 98 A1 00 6C */ stb r5, 0x6c(r1) -/* 801D637C 001D1FDC 90 09 00 00 */ stw r0, 0(r9) -/* 801D6380 001D1FE0 90 E1 00 70 */ stw r7, 0x70(r1) -/* 801D6384 001D1FE4 48 00 32 89 */ bl func_801D960C -/* 801D6388 001D1FE8 38 60 00 00 */ li r3, 0 -/* 801D638C 001D1FEC 48 00 01 64 */ b lbl_801D64F0 -lbl_801D6390: -/* 801D6390 001D1FF0 90 81 00 20 */ stw r4, 0x20(r1) -/* 801D6394 001D1FF4 38 80 00 40 */ li r4, 0x40 -/* 801D6398 001D1FF8 4B FF EF 71 */ bl TRKSetBufferPosition -/* 801D639C 001D1FFC 80 A1 00 20 */ lwz r5, 0x20(r1) -/* 801D63A0 001D2000 7F A3 EB 78 */ mr r3, r29 -/* 801D63A4 001D2004 38 81 01 00 */ addi r4, r1, 0x100 -/* 801D63A8 001D2008 4B FF EE 31 */ bl TRKReadBuffer -/* 801D63AC 001D200C 57 E0 EF FE */ rlwinm r0, r31, 0x1d, 0x1f, 0x1f -/* 801D63B0 001D2010 7F C4 F3 78 */ mr r4, r30 -/* 801D63B4 001D2014 38 61 01 00 */ addi r3, r1, 0x100 -/* 801D63B8 001D2018 38 A1 00 20 */ addi r5, r1, 0x20 -/* 801D63BC 001D201C 68 06 00 01 */ xori r6, r0, 1 -/* 801D63C0 001D2020 38 E0 00 00 */ li r7, 0 -/* 801D63C4 001D2024 48 00 24 75 */ bl TRKTargetAccessMemory -/* 801D63C8 001D2028 7C 60 1B 78 */ mr r0, r3 -/* 801D63CC 001D202C 7F A3 EB 78 */ mr r3, r29 -/* 801D63D0 001D2030 7C 1F 03 78 */ mr r31, r0 -/* 801D63D4 001D2034 38 80 00 00 */ li r4, 0 -/* 801D63D8 001D2038 4B FF EF 61 */ bl TRKResetBuffer -/* 801D63DC 001D203C 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D63E0 001D2040 40 82 00 54 */ bne lbl_801D6434 -/* 801D63E4 001D2044 38 61 00 A4 */ addi r3, r1, 0xa4 -/* 801D63E8 001D2048 38 80 00 00 */ li r4, 0 -/* 801D63EC 001D204C 38 A0 00 40 */ li r5, 0x40 -/* 801D63F0 001D2050 4B E2 DD 45 */ bl TRK_memset -/* 801D63F4 001D2054 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D63F8 001D2058 38 00 00 40 */ li r0, 0x40 -/* 801D63FC 001D205C 38 E3 07 E8 */ addi r7, r3, lbl_804907E8@l -/* 801D6400 001D2060 38 A0 00 80 */ li r5, 0x80 -/* 801D6404 001D2064 80 C7 00 00 */ lwz r6, 0(r7) -/* 801D6408 001D2068 7F A3 EB 78 */ mr r3, r29 -/* 801D640C 001D206C 90 01 00 A4 */ stw r0, 0xa4(r1) -/* 801D6410 001D2070 38 81 00 A4 */ addi r4, r1, 0xa4 -/* 801D6414 001D2074 38 06 00 01 */ addi r0, r6, 1 -/* 801D6418 001D2078 98 A1 00 A8 */ stb r5, 0xa8(r1) -/* 801D641C 001D207C 38 A0 00 40 */ li r5, 0x40 -/* 801D6420 001D2080 9B E1 00 AC */ stb r31, 0xac(r1) -/* 801D6424 001D2084 90 07 00 00 */ stw r0, 0(r7) -/* 801D6428 001D2088 90 C1 00 B0 */ stw r6, 0xb0(r1) -/* 801D642C 001D208C 4B FF EE 39 */ bl TRKAppendBuffer -/* 801D6430 001D2090 7C 7F 1B 78 */ mr r31, r3 -lbl_801D6434: -/* 801D6434 001D2094 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D6438 001D2098 41 82 00 B0 */ beq lbl_801D64E8 -/* 801D643C 001D209C 38 1F F9 00 */ addi r0, r31, -1792 -/* 801D6440 001D20A0 28 00 00 06 */ cmplwi r0, 6 -/* 801D6444 001D20A4 41 81 00 44 */ bgt lbl_801D6488 -/* 801D6448 001D20A8 3C 60 80 42 */ lis r3, lbl_804231F8@ha -/* 801D644C 001D20AC 54 00 10 3A */ slwi r0, r0, 2 -/* 801D6450 001D20B0 38 63 31 F8 */ addi r3, r3, lbl_804231F8@l -/* 801D6454 001D20B4 7C 03 00 2E */ lwzx r0, r3, r0 -/* 801D6458 001D20B8 7C 09 03 A6 */ mtctr r0 -/* 801D645C 001D20BC 4E 80 04 20 */ bctr -/* 801D6460 001D20C0 3B E0 00 15 */ li r31, 0x15 -/* 801D6464 001D20C4 48 00 00 28 */ b lbl_801D648C -/* 801D6468 001D20C8 3B E0 00 13 */ li r31, 0x13 -/* 801D646C 001D20CC 48 00 00 20 */ b lbl_801D648C -/* 801D6470 001D20D0 3B E0 00 21 */ li r31, 0x21 -/* 801D6474 001D20D4 48 00 00 18 */ b lbl_801D648C -/* 801D6478 001D20D8 3B E0 00 22 */ li r31, 0x22 -/* 801D647C 001D20DC 48 00 00 10 */ b lbl_801D648C -/* 801D6480 001D20E0 3B E0 00 20 */ li r31, 0x20 -/* 801D6484 001D20E4 48 00 00 08 */ b lbl_801D648C -lbl_801D6488: -/* 801D6488 001D20E8 3B E0 00 03 */ li r31, 3 -lbl_801D648C: -/* 801D648C 001D20EC 38 61 00 24 */ addi r3, r1, 0x24 -/* 801D6490 001D20F0 38 80 00 00 */ li r4, 0 -/* 801D6494 001D20F4 38 A0 00 40 */ li r5, 0x40 -/* 801D6498 001D20F8 4B E2 DC 9D */ bl TRK_memset -/* 801D649C 001D20FC 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D64A0 001D2100 38 00 00 80 */ li r0, 0x80 -/* 801D64A4 001D2104 39 03 07 E8 */ addi r8, r3, lbl_804907E8@l -/* 801D64A8 001D2108 38 A0 00 40 */ li r5, 0x40 -/* 801D64AC 001D210C 80 E8 00 00 */ lwz r7, 0(r8) -/* 801D64B0 001D2110 38 61 00 24 */ addi r3, r1, 0x24 -/* 801D64B4 001D2114 98 01 00 28 */ stb r0, 0x28(r1) -/* 801D64B8 001D2118 38 80 00 40 */ li r4, 0x40 -/* 801D64BC 001D211C 38 C7 00 01 */ addi r6, r7, 1 -/* 801D64C0 001D2120 90 E1 00 30 */ stw r7, 0x30(r1) -/* 801D64C4 001D2124 38 06 00 01 */ addi r0, r6, 1 -/* 801D64C8 001D2128 90 C8 00 00 */ stw r6, 0(r8) -/* 801D64CC 001D212C 90 A1 00 24 */ stw r5, 0x24(r1) -/* 801D64D0 001D2130 9B E1 00 2C */ stb r31, 0x2c(r1) -/* 801D64D4 001D2134 90 08 00 00 */ stw r0, 0(r8) -/* 801D64D8 001D2138 90 C1 00 30 */ stw r6, 0x30(r1) -/* 801D64DC 001D213C 48 00 31 31 */ bl func_801D960C -/* 801D64E0 001D2140 38 60 00 00 */ li r3, 0 -/* 801D64E4 001D2144 48 00 00 0C */ b lbl_801D64F0 -lbl_801D64E8: -/* 801D64E8 001D2148 7F A3 EB 78 */ mr r3, r29 -/* 801D64EC 001D214C 4B FF E7 F1 */ bl func_801D4CDC -lbl_801D64F0: -/* 801D64F0 001D2150 81 41 00 00 */ lwz r10, 0(r1) -/* 801D64F4 001D2154 80 0A 00 04 */ lwz r0, 4(r10) -/* 801D64F8 001D2158 83 EA FF FC */ lwz r31, -4(r10) -/* 801D64FC 001D215C 83 CA FF F8 */ lwz r30, -8(r10) -/* 801D6500 001D2160 83 AA FF F4 */ lwz r29, -0xc(r10) -/* 801D6504 001D2164 7C 08 03 A6 */ mtlr r0 -/* 801D6508 001D2168 7D 41 53 78 */ mr r1, r10 -/* 801D650C 001D216C 4E 80 00 20 */ blr - -.global func_801D6510 -func_801D6510: -/* 801D6510 001D2170 54 2B 06 FE */ clrlwi r11, r1, 0x1b -/* 801D6514 001D2174 7C 2C 0B 78 */ mr r12, r1 -/* 801D6518 001D2178 21 6B F6 C0 */ subfic r11, r11, -2368 -/* 801D651C 001D217C 7C 21 59 6E */ stwux r1, r1, r11 -/* 801D6520 001D2180 7C 08 02 A6 */ mflr r0 -/* 801D6524 001D2184 90 0C 00 04 */ stw r0, 4(r12) -/* 801D6528 001D2188 93 EC FF FC */ stw r31, -4(r12) -/* 801D652C 001D218C 7C 7F 1B 78 */ mr r31, r3 -/* 801D6530 001D2190 93 CC FF F8 */ stw r30, -8(r12) -/* 801D6534 001D2194 93 AC FF F4 */ stw r29, -0xc(r12) -/* 801D6538 001D2198 93 8C FF F0 */ stw r28, -0x10(r12) -/* 801D653C 001D219C 8B C3 00 18 */ lbz r30, 0x18(r3) -/* 801D6540 001D21A0 83 83 00 20 */ lwz r28, 0x20(r3) -/* 801D6544 001D21A4 57 C0 07 BD */ rlwinm. r0, r30, 0, 0x1e, 0x1e -/* 801D6548 001D21A8 A0 63 00 1C */ lhz r3, 0x1c(r3) -/* 801D654C 001D21AC 41 82 00 64 */ beq lbl_801D65B0 -/* 801D6550 001D21B0 38 61 00 64 */ addi r3, r1, 0x64 -/* 801D6554 001D21B4 38 80 00 00 */ li r4, 0 -/* 801D6558 001D21B8 38 A0 00 40 */ li r5, 0x40 -/* 801D655C 001D21BC 4B E2 DB D9 */ bl TRK_memset -/* 801D6560 001D21C0 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D6564 001D21C4 38 00 00 80 */ li r0, 0x80 -/* 801D6568 001D21C8 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D656C 001D21CC 38 C0 00 40 */ li r6, 0x40 -/* 801D6570 001D21D0 81 09 00 00 */ lwz r8, 0(r9) -/* 801D6574 001D21D4 38 A0 00 12 */ li r5, 0x12 -/* 801D6578 001D21D8 98 01 00 68 */ stb r0, 0x68(r1) -/* 801D657C 001D21DC 38 61 00 64 */ addi r3, r1, 0x64 -/* 801D6580 001D21E0 38 E8 00 01 */ addi r7, r8, 1 -/* 801D6584 001D21E4 38 80 00 40 */ li r4, 0x40 -/* 801D6588 001D21E8 91 01 00 70 */ stw r8, 0x70(r1) -/* 801D658C 001D21EC 38 07 00 01 */ addi r0, r7, 1 -/* 801D6590 001D21F0 90 E9 00 00 */ stw r7, 0(r9) -/* 801D6594 001D21F4 90 C1 00 64 */ stw r6, 0x64(r1) -/* 801D6598 001D21F8 98 A1 00 6C */ stb r5, 0x6c(r1) -/* 801D659C 001D21FC 90 09 00 00 */ stw r0, 0(r9) -/* 801D65A0 001D2200 90 E1 00 70 */ stw r7, 0x70(r1) -/* 801D65A4 001D2204 48 00 30 69 */ bl func_801D960C -/* 801D65A8 001D2208 38 60 00 00 */ li r3, 0 -/* 801D65AC 001D220C 48 00 01 88 */ b lbl_801D6734 -lbl_801D65B0: -/* 801D65B0 001D2210 57 C0 EF FE */ rlwinm r0, r30, 0x1d, 0x1f, 0x1f -/* 801D65B4 001D2214 90 61 00 20 */ stw r3, 0x20(r1) -/* 801D65B8 001D2218 7F 84 E3 78 */ mr r4, r28 -/* 801D65BC 001D221C 38 61 01 00 */ addi r3, r1, 0x100 -/* 801D65C0 001D2220 38 A1 00 20 */ addi r5, r1, 0x20 -/* 801D65C4 001D2224 68 06 00 01 */ xori r6, r0, 1 -/* 801D65C8 001D2228 38 E0 00 01 */ li r7, 1 -/* 801D65CC 001D222C 48 00 22 6D */ bl TRKTargetAccessMemory -/* 801D65D0 001D2230 7C 60 1B 78 */ mr r0, r3 -/* 801D65D4 001D2234 7F E3 FB 78 */ mr r3, r31 -/* 801D65D8 001D2238 7C 1D 03 78 */ mr r29, r0 -/* 801D65DC 001D223C 38 80 00 00 */ li r4, 0 -/* 801D65E0 001D2240 4B FF ED 59 */ bl TRKResetBuffer -/* 801D65E4 001D2244 2C 1D 00 00 */ cmpwi r29, 0 -/* 801D65E8 001D2248 40 82 00 90 */ bne lbl_801D6678 -/* 801D65EC 001D224C 38 61 00 A4 */ addi r3, r1, 0xa4 -/* 801D65F0 001D2250 38 80 00 00 */ li r4, 0 -/* 801D65F4 001D2254 38 A0 00 40 */ li r5, 0x40 -/* 801D65F8 001D2258 4B E2 DB 3D */ bl TRK_memset -/* 801D65FC 001D225C 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D6600 001D2260 80 81 00 20 */ lwz r4, 0x20(r1) -/* 801D6604 001D2264 38 E3 07 E8 */ addi r7, r3, lbl_804907E8@l -/* 801D6608 001D2268 39 00 00 80 */ li r8, 0x80 -/* 801D660C 001D226C 80 C7 00 00 */ lwz r6, 0(r7) -/* 801D6610 001D2270 38 04 00 40 */ addi r0, r4, 0x40 -/* 801D6614 001D2274 90 01 00 A4 */ stw r0, 0xa4(r1) -/* 801D6618 001D2278 7F E3 FB 78 */ mr r3, r31 -/* 801D661C 001D227C 38 06 00 01 */ addi r0, r6, 1 -/* 801D6620 001D2280 38 81 00 A4 */ addi r4, r1, 0xa4 -/* 801D6624 001D2284 9B A1 00 AC */ stb r29, 0xac(r1) -/* 801D6628 001D2288 38 A0 00 40 */ li r5, 0x40 -/* 801D662C 001D228C 99 01 00 A8 */ stb r8, 0xa8(r1) -/* 801D6630 001D2290 90 07 00 00 */ stw r0, 0(r7) -/* 801D6634 001D2294 90 C1 00 B0 */ stw r6, 0xb0(r1) -/* 801D6638 001D2298 4B FF EC 2D */ bl TRKAppendBuffer -/* 801D663C 001D229C 57 C0 06 73 */ rlwinm. r0, r30, 0, 0x19, 0x19 -/* 801D6640 001D22A0 41 82 00 24 */ beq lbl_801D6664 -/* 801D6644 001D22A4 57 80 06 FE */ clrlwi r0, r28, 0x1b -/* 801D6648 001D22A8 38 81 01 00 */ addi r4, r1, 0x100 -/* 801D664C 001D22AC 80 A1 00 20 */ lwz r5, 0x20(r1) -/* 801D6650 001D22B0 7F E3 FB 78 */ mr r3, r31 -/* 801D6654 001D22B4 7C 84 02 14 */ add r4, r4, r0 -/* 801D6658 001D22B8 4B FF EC 0D */ bl TRKAppendBuffer -/* 801D665C 001D22BC 7C 7D 1B 78 */ mr r29, r3 -/* 801D6660 001D22C0 48 00 00 18 */ b lbl_801D6678 -lbl_801D6664: -/* 801D6664 001D22C4 80 A1 00 20 */ lwz r5, 0x20(r1) -/* 801D6668 001D22C8 7F E3 FB 78 */ mr r3, r31 -/* 801D666C 001D22CC 38 81 01 00 */ addi r4, r1, 0x100 -/* 801D6670 001D22D0 4B FF EB F5 */ bl TRKAppendBuffer -/* 801D6674 001D22D4 7C 7D 1B 78 */ mr r29, r3 -lbl_801D6678: -/* 801D6678 001D22D8 2C 1D 00 00 */ cmpwi r29, 0 -/* 801D667C 001D22DC 41 82 00 B0 */ beq lbl_801D672C -/* 801D6680 001D22E0 38 1D F9 00 */ addi r0, r29, -1792 -/* 801D6684 001D22E4 28 00 00 06 */ cmplwi r0, 6 -/* 801D6688 001D22E8 41 81 00 44 */ bgt lbl_801D66CC -/* 801D668C 001D22EC 3C 60 80 42 */ lis r3, lbl_80423214@ha -/* 801D6690 001D22F0 54 00 10 3A */ slwi r0, r0, 2 -/* 801D6694 001D22F4 38 63 32 14 */ addi r3, r3, lbl_80423214@l -/* 801D6698 001D22F8 7C 03 00 2E */ lwzx r0, r3, r0 -/* 801D669C 001D22FC 7C 09 03 A6 */ mtctr r0 -/* 801D66A0 001D2300 4E 80 04 20 */ bctr -/* 801D66A4 001D2304 3B A0 00 15 */ li r29, 0x15 -/* 801D66A8 001D2308 48 00 00 28 */ b lbl_801D66D0 -/* 801D66AC 001D230C 3B A0 00 13 */ li r29, 0x13 -/* 801D66B0 001D2310 48 00 00 20 */ b lbl_801D66D0 -/* 801D66B4 001D2314 3B A0 00 21 */ li r29, 0x21 -/* 801D66B8 001D2318 48 00 00 18 */ b lbl_801D66D0 -/* 801D66BC 001D231C 3B A0 00 22 */ li r29, 0x22 -/* 801D66C0 001D2320 48 00 00 10 */ b lbl_801D66D0 -/* 801D66C4 001D2324 3B A0 00 20 */ li r29, 0x20 -/* 801D66C8 001D2328 48 00 00 08 */ b lbl_801D66D0 -lbl_801D66CC: -/* 801D66CC 001D232C 3B A0 00 03 */ li r29, 3 -lbl_801D66D0: -/* 801D66D0 001D2330 38 61 00 24 */ addi r3, r1, 0x24 -/* 801D66D4 001D2334 38 80 00 00 */ li r4, 0 -/* 801D66D8 001D2338 38 A0 00 40 */ li r5, 0x40 -/* 801D66DC 001D233C 4B E2 DA 59 */ bl TRK_memset -/* 801D66E0 001D2340 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D66E4 001D2344 38 00 00 80 */ li r0, 0x80 -/* 801D66E8 001D2348 39 03 07 E8 */ addi r8, r3, lbl_804907E8@l -/* 801D66EC 001D234C 38 A0 00 40 */ li r5, 0x40 -/* 801D66F0 001D2350 80 E8 00 00 */ lwz r7, 0(r8) -/* 801D66F4 001D2354 38 61 00 24 */ addi r3, r1, 0x24 -/* 801D66F8 001D2358 98 01 00 28 */ stb r0, 0x28(r1) -/* 801D66FC 001D235C 38 80 00 40 */ li r4, 0x40 -/* 801D6700 001D2360 38 C7 00 01 */ addi r6, r7, 1 -/* 801D6704 001D2364 90 E1 00 30 */ stw r7, 0x30(r1) -/* 801D6708 001D2368 38 06 00 01 */ addi r0, r6, 1 -/* 801D670C 001D236C 90 C8 00 00 */ stw r6, 0(r8) -/* 801D6710 001D2370 90 A1 00 24 */ stw r5, 0x24(r1) -/* 801D6714 001D2374 9B A1 00 2C */ stb r29, 0x2c(r1) -/* 801D6718 001D2378 90 08 00 00 */ stw r0, 0(r8) -/* 801D671C 001D237C 90 C1 00 30 */ stw r6, 0x30(r1) -/* 801D6720 001D2380 48 00 2E ED */ bl func_801D960C -/* 801D6724 001D2384 38 60 00 00 */ li r3, 0 -/* 801D6728 001D2388 48 00 00 0C */ b lbl_801D6734 -lbl_801D672C: -/* 801D672C 001D238C 7F E3 FB 78 */ mr r3, r31 -/* 801D6730 001D2390 4B FF E5 AD */ bl func_801D4CDC -lbl_801D6734: -/* 801D6734 001D2394 81 41 00 00 */ lwz r10, 0(r1) -/* 801D6738 001D2398 80 0A 00 04 */ lwz r0, 4(r10) -/* 801D673C 001D239C 83 EA FF FC */ lwz r31, -4(r10) -/* 801D6740 001D23A0 83 CA FF F8 */ lwz r30, -8(r10) -/* 801D6744 001D23A4 83 AA FF F4 */ lwz r29, -0xc(r10) -/* 801D6748 001D23A8 83 8A FF F0 */ lwz r28, -0x10(r10) -/* 801D674C 001D23AC 7C 08 03 A6 */ mtlr r0 -/* 801D6750 001D23B0 7D 41 53 78 */ mr r1, r10 -/* 801D6754 001D23B4 4E 80 00 20 */ blr - -.global func_801D6758 -func_801D6758: -/* 801D6758 001D23B8 38 60 00 00 */ li r3, 0 -/* 801D675C 001D23BC 4E 80 00 20 */ blr - -.global func_801D6760 -func_801D6760: -/* 801D6760 001D23C0 38 60 00 00 */ li r3, 0 -/* 801D6764 001D23C4 4E 80 00 20 */ blr - -.global func_801D6768 -func_801D6768: -/* 801D6768 001D23C8 94 21 FF B0 */ stwu r1, -0x50(r1) -/* 801D676C 001D23CC 7C 08 02 A6 */ mflr r0 -/* 801D6770 001D23D0 38 80 00 00 */ li r4, 0 -/* 801D6774 001D23D4 38 A0 00 40 */ li r5, 0x40 -/* 801D6778 001D23D8 90 01 00 54 */ stw r0, 0x54(r1) -/* 801D677C 001D23DC 38 61 00 08 */ addi r3, r1, 8 -/* 801D6780 001D23E0 4B E2 D9 B5 */ bl TRK_memset -/* 801D6784 001D23E4 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D6788 001D23E8 38 00 00 80 */ li r0, 0x80 -/* 801D678C 001D23EC 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D6790 001D23F0 38 C0 00 40 */ li r6, 0x40 -/* 801D6794 001D23F4 81 09 00 00 */ lwz r8, 0(r9) -/* 801D6798 001D23F8 38 A0 00 00 */ li r5, 0 -/* 801D679C 001D23FC 98 01 00 0C */ stb r0, 0xc(r1) -/* 801D67A0 001D2400 38 61 00 08 */ addi r3, r1, 8 -/* 801D67A4 001D2404 38 E8 00 01 */ addi r7, r8, 1 -/* 801D67A8 001D2408 38 80 00 40 */ li r4, 0x40 -/* 801D67AC 001D240C 91 01 00 14 */ stw r8, 0x14(r1) -/* 801D67B0 001D2410 38 07 00 01 */ addi r0, r7, 1 -/* 801D67B4 001D2414 90 E9 00 00 */ stw r7, 0(r9) -/* 801D67B8 001D2418 90 C1 00 08 */ stw r6, 8(r1) -/* 801D67BC 001D241C 98 A1 00 10 */ stb r5, 0x10(r1) -/* 801D67C0 001D2420 90 09 00 00 */ stw r0, 0(r9) -/* 801D67C4 001D2424 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D67C8 001D2428 48 00 2E 45 */ bl func_801D960C -/* 801D67CC 001D242C 48 00 2A E5 */ bl __TRK_copy_vectors -/* 801D67D0 001D2430 80 01 00 54 */ lwz r0, 0x54(r1) -/* 801D67D4 001D2434 38 60 00 00 */ li r3, 0 -/* 801D67D8 001D2438 7C 08 03 A6 */ mtlr r0 -/* 801D67DC 001D243C 38 21 00 50 */ addi r1, r1, 0x50 -/* 801D67E0 001D2440 4E 80 00 20 */ blr - -.global func_801D67E4 -func_801D67E4: -/* 801D67E4 001D2444 94 21 FF B0 */ stwu r1, -0x50(r1) -/* 801D67E8 001D2448 7C 08 02 A6 */ mflr r0 -/* 801D67EC 001D244C 38 80 00 00 */ li r4, 0 -/* 801D67F0 001D2450 38 A0 00 40 */ li r5, 0x40 -/* 801D67F4 001D2454 90 01 00 54 */ stw r0, 0x54(r1) -/* 801D67F8 001D2458 38 61 00 08 */ addi r3, r1, 8 -/* 801D67FC 001D245C 4B E2 D9 39 */ bl TRK_memset -/* 801D6800 001D2460 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D6804 001D2464 38 00 00 80 */ li r0, 0x80 -/* 801D6808 001D2468 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D680C 001D246C 38 C0 00 40 */ li r6, 0x40 -/* 801D6810 001D2470 81 09 00 00 */ lwz r8, 0(r9) -/* 801D6814 001D2474 38 A0 00 00 */ li r5, 0 -/* 801D6818 001D2478 98 01 00 0C */ stb r0, 0xc(r1) -/* 801D681C 001D247C 38 61 00 08 */ addi r3, r1, 8 -/* 801D6820 001D2480 38 E8 00 01 */ addi r7, r8, 1 -/* 801D6824 001D2484 38 80 00 40 */ li r4, 0x40 -/* 801D6828 001D2488 91 01 00 14 */ stw r8, 0x14(r1) -/* 801D682C 001D248C 38 07 00 01 */ addi r0, r7, 1 -/* 801D6830 001D2490 90 E9 00 00 */ stw r7, 0(r9) -/* 801D6834 001D2494 90 C1 00 08 */ stw r6, 8(r1) -/* 801D6838 001D2498 98 A1 00 10 */ stb r5, 0x10(r1) -/* 801D683C 001D249C 90 09 00 00 */ stw r0, 0(r9) -/* 801D6840 001D24A0 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D6844 001D24A4 48 00 2D C9 */ bl func_801D960C -/* 801D6848 001D24A8 4B E2 F8 75 */ bl __TRK_reset -/* 801D684C 001D24AC 80 01 00 54 */ lwz r0, 0x54(r1) -/* 801D6850 001D24B0 38 60 00 00 */ li r3, 0 -/* 801D6854 001D24B4 7C 08 03 A6 */ mtlr r0 -/* 801D6858 001D24B8 38 21 00 50 */ addi r1, r1, 0x50 -/* 801D685C 001D24BC 4E 80 00 20 */ blr - -.global func_801D6860 -func_801D6860: -/* 801D6860 001D24C0 94 21 FF A0 */ stwu r1, -0x60(r1) -/* 801D6864 001D24C4 7C 08 02 A6 */ mflr r0 -/* 801D6868 001D24C8 3C 60 80 49 */ lis r3, lbl_804907EC@ha -/* 801D686C 001D24CC 38 A0 00 40 */ li r5, 0x40 -/* 801D6870 001D24D0 90 01 00 64 */ stw r0, 0x64(r1) -/* 801D6874 001D24D4 38 83 07 EC */ addi r4, r3, lbl_804907EC@l -/* 801D6878 001D24D8 38 00 00 00 */ li r0, 0 -/* 801D687C 001D24DC 38 61 00 14 */ addi r3, r1, 0x14 -/* 801D6880 001D24E0 90 04 00 00 */ stw r0, 0(r4) -/* 801D6884 001D24E4 38 80 00 00 */ li r4, 0 -/* 801D6888 001D24E8 4B E2 D8 AD */ bl TRK_memset -/* 801D688C 001D24EC 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D6890 001D24F0 38 00 00 80 */ li r0, 0x80 -/* 801D6894 001D24F4 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D6898 001D24F8 38 C0 00 40 */ li r6, 0x40 -/* 801D689C 001D24FC 81 09 00 00 */ lwz r8, 0(r9) -/* 801D68A0 001D2500 38 A0 00 00 */ li r5, 0 -/* 801D68A4 001D2504 98 01 00 18 */ stb r0, 0x18(r1) -/* 801D68A8 001D2508 38 61 00 14 */ addi r3, r1, 0x14 -/* 801D68AC 001D250C 38 E8 00 01 */ addi r7, r8, 1 -/* 801D68B0 001D2510 38 80 00 40 */ li r4, 0x40 -/* 801D68B4 001D2514 91 01 00 20 */ stw r8, 0x20(r1) -/* 801D68B8 001D2518 38 07 00 01 */ addi r0, r7, 1 -/* 801D68BC 001D251C 90 E9 00 00 */ stw r7, 0(r9) -/* 801D68C0 001D2520 90 C1 00 14 */ stw r6, 0x14(r1) -/* 801D68C4 001D2524 98 A1 00 1C */ stb r5, 0x1c(r1) -/* 801D68C8 001D2528 90 09 00 00 */ stw r0, 0(r9) -/* 801D68CC 001D252C 90 E1 00 20 */ stw r7, 0x20(r1) -/* 801D68D0 001D2530 48 00 2D 3D */ bl func_801D960C -/* 801D68D4 001D2534 38 61 00 08 */ addi r3, r1, 8 -/* 801D68D8 001D2538 38 80 00 01 */ li r4, 1 -/* 801D68DC 001D253C 4B FF E0 79 */ bl TRKConstructEvent -/* 801D68E0 001D2540 38 61 00 08 */ addi r3, r1, 8 -/* 801D68E4 001D2544 4B FF E0 89 */ bl TRKPostEvent -/* 801D68E8 001D2548 80 01 00 64 */ lwz r0, 0x64(r1) -/* 801D68EC 001D254C 38 60 00 00 */ li r3, 0 -/* 801D68F0 001D2550 7C 08 03 A6 */ mtlr r0 -/* 801D68F4 001D2554 38 21 00 60 */ addi r1, r1, 0x60 -/* 801D68F8 001D2558 4E 80 00 20 */ blr - -.global func_801D68FC -func_801D68FC: -/* 801D68FC 001D255C 94 21 FF B0 */ stwu r1, -0x50(r1) -/* 801D6900 001D2560 7C 08 02 A6 */ mflr r0 -/* 801D6904 001D2564 3C 60 80 49 */ lis r3, lbl_804907EC@ha -/* 801D6908 001D2568 38 A0 00 40 */ li r5, 0x40 -/* 801D690C 001D256C 90 01 00 54 */ stw r0, 0x54(r1) -/* 801D6910 001D2570 38 83 07 EC */ addi r4, r3, lbl_804907EC@l -/* 801D6914 001D2574 38 00 00 01 */ li r0, 1 -/* 801D6918 001D2578 38 61 00 08 */ addi r3, r1, 8 -/* 801D691C 001D257C 90 04 00 00 */ stw r0, 0(r4) -/* 801D6920 001D2580 38 80 00 00 */ li r4, 0 -/* 801D6924 001D2584 4B E2 D8 11 */ bl TRK_memset -/* 801D6928 001D2588 3C 60 80 49 */ lis r3, lbl_804907E8@ha -/* 801D692C 001D258C 38 00 00 80 */ li r0, 0x80 -/* 801D6930 001D2590 39 23 07 E8 */ addi r9, r3, lbl_804907E8@l -/* 801D6934 001D2594 38 C0 00 40 */ li r6, 0x40 -/* 801D6938 001D2598 81 09 00 00 */ lwz r8, 0(r9) -/* 801D693C 001D259C 38 A0 00 00 */ li r5, 0 -/* 801D6940 001D25A0 98 01 00 0C */ stb r0, 0xc(r1) -/* 801D6944 001D25A4 38 61 00 08 */ addi r3, r1, 8 -/* 801D6948 001D25A8 38 E8 00 01 */ addi r7, r8, 1 -/* 801D694C 001D25AC 38 80 00 40 */ li r4, 0x40 -/* 801D6950 001D25B0 91 01 00 14 */ stw r8, 0x14(r1) -/* 801D6954 001D25B4 38 07 00 01 */ addi r0, r7, 1 -/* 801D6958 001D25B8 90 E9 00 00 */ stw r7, 0(r9) -/* 801D695C 001D25BC 90 C1 00 08 */ stw r6, 8(r1) -/* 801D6960 001D25C0 98 A1 00 10 */ stb r5, 0x10(r1) -/* 801D6964 001D25C4 90 09 00 00 */ stw r0, 0(r9) -/* 801D6968 001D25C8 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D696C 001D25CC 48 00 2C A1 */ bl func_801D960C -/* 801D6970 001D25D0 80 01 00 54 */ lwz r0, 0x54(r1) -/* 801D6974 001D25D4 38 60 00 00 */ li r3, 0 -/* 801D6978 001D25D8 7C 08 03 A6 */ mtlr r0 -/* 801D697C 001D25DC 38 21 00 50 */ addi r1, r1, 0x50 -/* 801D6980 001D25E0 4E 80 00 20 */ blr - -.global SetTRKConnected -SetTRKConnected: -/* 801D6984 001D25E4 3C 80 80 49 */ lis r4, lbl_804907EC@ha -/* 801D6988 001D25E8 90 64 07 EC */ stw r3, lbl_804907EC@l(r4) -/* 801D698C 001D25EC 4E 80 00 20 */ blr - -.global func_801D6990 -func_801D6990: -/* 801D6990 001D25F0 3C 60 80 49 */ lis r3, lbl_804907EC@ha -/* 801D6994 001D25F4 38 63 07 EC */ addi r3, r3, lbl_804907EC@l -/* 801D6998 001D25F8 80 63 00 00 */ lwz r3, 0(r3) -/* 801D699C 001D25FC 4E 80 00 20 */ blr - -.global HandlePositionFileSupportRequest -HandlePositionFileSupportRequest: -/* 801D69A0 001D2600 94 21 FF 90 */ stwu r1, -0x70(r1) -/* 801D69A4 001D2604 7C 08 02 A6 */ mflr r0 -/* 801D69A8 001D2608 90 01 00 74 */ stw r0, 0x74(r1) -/* 801D69AC 001D260C 93 E1 00 6C */ stw r31, 0x6c(r1) -/* 801D69B0 001D2610 7C BF 2B 78 */ mr r31, r5 -/* 801D69B4 001D2614 38 A0 00 40 */ li r5, 0x40 -/* 801D69B8 001D2618 93 C1 00 68 */ stw r30, 0x68(r1) -/* 801D69BC 001D261C 7C DE 33 78 */ mr r30, r6 -/* 801D69C0 001D2620 93 A1 00 64 */ stw r29, 0x64(r1) -/* 801D69C4 001D2624 7C 9D 23 78 */ mr r29, r4 -/* 801D69C8 001D2628 38 80 00 00 */ li r4, 0 -/* 801D69CC 001D262C 93 81 00 60 */ stw r28, 0x60(r1) -/* 801D69D0 001D2630 7C 7C 1B 78 */ mr r28, r3 -/* 801D69D4 001D2634 38 61 00 14 */ addi r3, r1, 0x14 -/* 801D69D8 001D2638 4B E2 D7 5D */ bl TRK_memset -/* 801D69DC 001D263C 38 60 00 D4 */ li r3, 0xd4 -/* 801D69E0 001D2640 38 00 00 40 */ li r0, 0x40 -/* 801D69E4 001D2644 98 61 00 18 */ stb r3, 0x18(r1) -/* 801D69E8 001D2648 38 61 00 0C */ addi r3, r1, 0xc -/* 801D69EC 001D264C 38 81 00 08 */ addi r4, r1, 8 -/* 801D69F0 001D2650 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D69F4 001D2654 93 81 00 1C */ stw r28, 0x1c(r1) -/* 801D69F8 001D2658 80 1D 00 00 */ lwz r0, 0(r29) -/* 801D69FC 001D265C 90 01 00 20 */ stw r0, 0x20(r1) -/* 801D6A00 001D2660 9B E1 00 24 */ stb r31, 0x24(r1) -/* 801D6A04 001D2664 4B FF EA 05 */ bl TRKGetFreeBuffer -/* 801D6A08 001D2668 7C 7F 1B 79 */ or. r31, r3, r3 -/* 801D6A0C 001D266C 40 82 00 18 */ bne lbl_801D6A24 -/* 801D6A10 001D2670 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6A14 001D2674 38 81 00 14 */ addi r4, r1, 0x14 -/* 801D6A18 001D2678 38 A0 00 40 */ li r5, 0x40 -/* 801D6A1C 001D267C 4B FF E6 59 */ bl TRKAppendBuffer_ui8 -/* 801D6A20 001D2680 7C 7F 1B 78 */ mr r31, r3 -lbl_801D6A24: -/* 801D6A24 001D2684 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D6A28 001D2688 40 82 00 5C */ bne lbl_801D6A84 -/* 801D6A2C 001D268C 38 60 00 00 */ li r3, 0 -/* 801D6A30 001D2690 38 00 FF FF */ li r0, -1 -/* 801D6A34 001D2694 90 7E 00 00 */ stw r3, 0(r30) -/* 801D6A38 001D2698 38 81 00 10 */ addi r4, r1, 0x10 -/* 801D6A3C 001D269C 38 A0 00 03 */ li r5, 3 -/* 801D6A40 001D26A0 38 C0 00 03 */ li r6, 3 -/* 801D6A44 001D26A4 90 1D 00 00 */ stw r0, 0(r29) -/* 801D6A48 001D26A8 38 E0 00 00 */ li r7, 0 -/* 801D6A4C 001D26AC 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6A50 001D26B0 48 00 02 65 */ bl func_801D6CB4 -/* 801D6A54 001D26B4 7C 7F 1B 79 */ or. r31, r3, r3 -/* 801D6A58 001D26B8 40 82 00 24 */ bne lbl_801D6A7C -/* 801D6A5C 001D26BC 80 61 00 10 */ lwz r3, 0x10(r1) -/* 801D6A60 001D26C0 4B FF E9 7D */ bl TRKGetBuffer -/* 801D6A64 001D26C4 28 03 00 00 */ cmplwi r3, 0 -/* 801D6A68 001D26C8 41 82 00 14 */ beq lbl_801D6A7C -/* 801D6A6C 001D26CC 80 03 00 20 */ lwz r0, 0x20(r3) -/* 801D6A70 001D26D0 90 1E 00 00 */ stw r0, 0(r30) -/* 801D6A74 001D26D4 80 03 00 28 */ lwz r0, 0x28(r3) -/* 801D6A78 001D26D8 90 1D 00 00 */ stw r0, 0(r29) -lbl_801D6A7C: -/* 801D6A7C 001D26DC 80 61 00 10 */ lwz r3, 0x10(r1) -/* 801D6A80 001D26E0 4B FF E8 F9 */ bl TRKReleaseBuffer -lbl_801D6A84: -/* 801D6A84 001D26E4 80 61 00 0C */ lwz r3, 0xc(r1) -/* 801D6A88 001D26E8 4B FF E8 F1 */ bl TRKReleaseBuffer -/* 801D6A8C 001D26EC 80 01 00 74 */ lwz r0, 0x74(r1) -/* 801D6A90 001D26F0 7F E3 FB 78 */ mr r3, r31 -/* 801D6A94 001D26F4 83 E1 00 6C */ lwz r31, 0x6c(r1) -/* 801D6A98 001D26F8 83 C1 00 68 */ lwz r30, 0x68(r1) -/* 801D6A9C 001D26FC 83 A1 00 64 */ lwz r29, 0x64(r1) -/* 801D6AA0 001D2700 83 81 00 60 */ lwz r28, 0x60(r1) -/* 801D6AA4 001D2704 7C 08 03 A6 */ mtlr r0 -/* 801D6AA8 001D2708 38 21 00 70 */ addi r1, r1, 0x70 -/* 801D6AAC 001D270C 4E 80 00 20 */ blr - -.global HandleCloseFileSupportRequest -HandleCloseFileSupportRequest: -/* 801D6AB0 001D2710 94 21 FF 90 */ stwu r1, -0x70(r1) -/* 801D6AB4 001D2714 7C 08 02 A6 */ mflr r0 -/* 801D6AB8 001D2718 38 A0 00 40 */ li r5, 0x40 -/* 801D6ABC 001D271C 90 01 00 74 */ stw r0, 0x74(r1) -/* 801D6AC0 001D2720 93 E1 00 6C */ stw r31, 0x6c(r1) -/* 801D6AC4 001D2724 7C 7F 1B 78 */ mr r31, r3 -/* 801D6AC8 001D2728 38 61 00 14 */ addi r3, r1, 0x14 -/* 801D6ACC 001D272C 93 C1 00 68 */ stw r30, 0x68(r1) -/* 801D6AD0 001D2730 93 A1 00 64 */ stw r29, 0x64(r1) -/* 801D6AD4 001D2734 7C 9D 23 78 */ mr r29, r4 -/* 801D6AD8 001D2738 38 80 00 00 */ li r4, 0 -/* 801D6ADC 001D273C 4B E2 D6 59 */ bl TRK_memset -/* 801D6AE0 001D2740 38 60 00 D3 */ li r3, 0xd3 -/* 801D6AE4 001D2744 38 00 00 40 */ li r0, 0x40 -/* 801D6AE8 001D2748 98 61 00 18 */ stb r3, 0x18(r1) -/* 801D6AEC 001D274C 38 61 00 0C */ addi r3, r1, 0xc -/* 801D6AF0 001D2750 38 81 00 08 */ addi r4, r1, 8 -/* 801D6AF4 001D2754 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D6AF8 001D2758 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D6AFC 001D275C 4B FF E9 0D */ bl TRKGetFreeBuffer -/* 801D6B00 001D2760 7C 7F 1B 79 */ or. r31, r3, r3 -/* 801D6B04 001D2764 40 82 00 18 */ bne lbl_801D6B1C -/* 801D6B08 001D2768 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6B0C 001D276C 38 81 00 14 */ addi r4, r1, 0x14 -/* 801D6B10 001D2770 38 A0 00 40 */ li r5, 0x40 -/* 801D6B14 001D2774 4B FF E5 61 */ bl TRKAppendBuffer_ui8 -/* 801D6B18 001D2778 7C 7F 1B 78 */ mr r31, r3 -lbl_801D6B1C: -/* 801D6B1C 001D277C 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D6B20 001D2780 40 82 00 50 */ bne lbl_801D6B70 -/* 801D6B24 001D2784 38 00 00 00 */ li r0, 0 -/* 801D6B28 001D2788 38 81 00 10 */ addi r4, r1, 0x10 -/* 801D6B2C 001D278C 90 1D 00 00 */ stw r0, 0(r29) -/* 801D6B30 001D2790 38 A0 00 03 */ li r5, 3 -/* 801D6B34 001D2794 38 C0 00 03 */ li r6, 3 -/* 801D6B38 001D2798 38 E0 00 00 */ li r7, 0 -/* 801D6B3C 001D279C 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6B40 001D27A0 48 00 01 75 */ bl func_801D6CB4 -/* 801D6B44 001D27A4 7C 7F 1B 79 */ or. r31, r3, r3 -/* 801D6B48 001D27A8 40 82 00 10 */ bne lbl_801D6B58 -/* 801D6B4C 001D27AC 80 61 00 10 */ lwz r3, 0x10(r1) -/* 801D6B50 001D27B0 4B FF E8 8D */ bl TRKGetBuffer -/* 801D6B54 001D27B4 7C 7E 1B 78 */ mr r30, r3 -lbl_801D6B58: -/* 801D6B58 001D27B8 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D6B5C 001D27BC 40 82 00 0C */ bne lbl_801D6B68 -/* 801D6B60 001D27C0 80 1E 00 20 */ lwz r0, 0x20(r30) -/* 801D6B64 001D27C4 90 1D 00 00 */ stw r0, 0(r29) -lbl_801D6B68: -/* 801D6B68 001D27C8 80 61 00 10 */ lwz r3, 0x10(r1) -/* 801D6B6C 001D27CC 4B FF E8 0D */ bl TRKReleaseBuffer -lbl_801D6B70: -/* 801D6B70 001D27D0 80 61 00 0C */ lwz r3, 0xc(r1) -/* 801D6B74 001D27D4 4B FF E8 05 */ bl TRKReleaseBuffer -/* 801D6B78 001D27D8 80 01 00 74 */ lwz r0, 0x74(r1) -/* 801D6B7C 001D27DC 7F E3 FB 78 */ mr r3, r31 -/* 801D6B80 001D27E0 83 E1 00 6C */ lwz r31, 0x6c(r1) -/* 801D6B84 001D27E4 83 C1 00 68 */ lwz r30, 0x68(r1) -/* 801D6B88 001D27E8 83 A1 00 64 */ lwz r29, 0x64(r1) -/* 801D6B8C 001D27EC 7C 08 03 A6 */ mtlr r0 -/* 801D6B90 001D27F0 38 21 00 70 */ addi r1, r1, 0x70 -/* 801D6B94 001D27F4 4E 80 00 20 */ blr - -.global HandleOpenFileSupportRequest -HandleOpenFileSupportRequest: -/* 801D6B98 001D27F8 94 21 FF 90 */ stwu r1, -0x70(r1) -/* 801D6B9C 001D27FC 7C 08 02 A6 */ mflr r0 -/* 801D6BA0 001D2800 90 01 00 74 */ stw r0, 0x74(r1) -/* 801D6BA4 001D2804 BF 61 00 5C */ stmw r27, 0x5c(r1) -/* 801D6BA8 001D2808 7C 7B 1B 78 */ mr r27, r3 -/* 801D6BAC 001D280C 7C 9F 23 78 */ mr r31, r4 -/* 801D6BB0 001D2810 7C BC 2B 78 */ mr r28, r5 -/* 801D6BB4 001D2814 7C DD 33 78 */ mr r29, r6 -/* 801D6BB8 001D2818 38 61 00 14 */ addi r3, r1, 0x14 -/* 801D6BBC 001D281C 38 80 00 00 */ li r4, 0 -/* 801D6BC0 001D2820 38 A0 00 40 */ li r5, 0x40 -/* 801D6BC4 001D2824 4B E2 D5 71 */ bl TRK_memset -/* 801D6BC8 001D2828 38 60 00 00 */ li r3, 0 -/* 801D6BCC 001D282C 38 00 00 D2 */ li r0, 0xd2 -/* 801D6BD0 001D2830 90 7C 00 00 */ stw r3, 0(r28) -/* 801D6BD4 001D2834 7F 63 DB 78 */ mr r3, r27 -/* 801D6BD8 001D2838 98 01 00 18 */ stb r0, 0x18(r1) -/* 801D6BDC 001D283C 48 00 06 19 */ bl TRK_strlen -/* 801D6BE0 001D2840 38 03 00 41 */ addi r0, r3, 0x41 -/* 801D6BE4 001D2844 9B E1 00 1C */ stb r31, 0x1c(r1) -/* 801D6BE8 001D2848 7F 63 DB 78 */ mr r3, r27 -/* 801D6BEC 001D284C 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D6BF0 001D2850 48 00 06 05 */ bl TRK_strlen -/* 801D6BF4 001D2854 38 03 00 01 */ addi r0, r3, 1 -/* 801D6BF8 001D2858 38 61 00 0C */ addi r3, r1, 0xc -/* 801D6BFC 001D285C B0 01 00 20 */ sth r0, 0x20(r1) -/* 801D6C00 001D2860 38 81 00 08 */ addi r4, r1, 8 -/* 801D6C04 001D2864 4B FF E8 05 */ bl TRKGetFreeBuffer -/* 801D6C08 001D2868 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6C0C 001D286C 38 81 00 14 */ addi r4, r1, 0x14 -/* 801D6C10 001D2870 38 A0 00 40 */ li r5, 0x40 -/* 801D6C14 001D2874 4B FF E4 61 */ bl TRKAppendBuffer_ui8 -/* 801D6C18 001D2878 7C 7F 1B 79 */ or. r31, r3, r3 -/* 801D6C1C 001D287C 40 82 00 24 */ bne lbl_801D6C40 -/* 801D6C20 001D2880 7F 63 DB 78 */ mr r3, r27 -/* 801D6C24 001D2884 48 00 05 D1 */ bl TRK_strlen -/* 801D6C28 001D2888 7C 65 1B 78 */ mr r5, r3 -/* 801D6C2C 001D288C 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6C30 001D2890 7F 64 DB 78 */ mr r4, r27 -/* 801D6C34 001D2894 38 A5 00 01 */ addi r5, r5, 1 -/* 801D6C38 001D2898 4B FF E4 3D */ bl TRKAppendBuffer_ui8 -/* 801D6C3C 001D289C 7C 7F 1B 78 */ mr r31, r3 -lbl_801D6C40: -/* 801D6C40 001D28A0 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D6C44 001D28A4 40 82 00 50 */ bne lbl_801D6C94 -/* 801D6C48 001D28A8 38 00 00 00 */ li r0, 0 -/* 801D6C4C 001D28AC 38 81 00 10 */ addi r4, r1, 0x10 -/* 801D6C50 001D28B0 90 1D 00 00 */ stw r0, 0(r29) -/* 801D6C54 001D28B4 38 A0 00 07 */ li r5, 7 -/* 801D6C58 001D28B8 38 C0 00 03 */ li r6, 3 -/* 801D6C5C 001D28BC 38 E0 00 00 */ li r7, 0 -/* 801D6C60 001D28C0 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6C64 001D28C4 48 00 00 51 */ bl func_801D6CB4 -/* 801D6C68 001D28C8 7C 7F 1B 79 */ or. r31, r3, r3 -/* 801D6C6C 001D28CC 40 82 00 10 */ bne lbl_801D6C7C -/* 801D6C70 001D28D0 80 61 00 10 */ lwz r3, 0x10(r1) -/* 801D6C74 001D28D4 4B FF E7 69 */ bl TRKGetBuffer -/* 801D6C78 001D28D8 7C 7E 1B 78 */ mr r30, r3 -lbl_801D6C7C: -/* 801D6C7C 001D28DC 80 1E 00 20 */ lwz r0, 0x20(r30) -/* 801D6C80 001D28E0 90 1D 00 00 */ stw r0, 0(r29) -/* 801D6C84 001D28E4 80 1E 00 18 */ lwz r0, 0x18(r30) -/* 801D6C88 001D28E8 90 1C 00 00 */ stw r0, 0(r28) -/* 801D6C8C 001D28EC 80 61 00 10 */ lwz r3, 0x10(r1) -/* 801D6C90 001D28F0 4B FF E6 E9 */ bl TRKReleaseBuffer -lbl_801D6C94: -/* 801D6C94 001D28F4 80 61 00 0C */ lwz r3, 0xc(r1) -/* 801D6C98 001D28F8 4B FF E6 E1 */ bl TRKReleaseBuffer -/* 801D6C9C 001D28FC 7F E3 FB 78 */ mr r3, r31 -/* 801D6CA0 001D2900 BB 61 00 5C */ lmw r27, 0x5c(r1) -/* 801D6CA4 001D2904 80 01 00 74 */ lwz r0, 0x74(r1) -/* 801D6CA8 001D2908 7C 08 03 A6 */ mtlr r0 -/* 801D6CAC 001D290C 38 21 00 70 */ addi r1, r1, 0x70 -/* 801D6CB0 001D2910 4E 80 00 20 */ blr - -.global func_801D6CB4 -func_801D6CB4: -/* 801D6CB4 001D2914 94 21 FF D0 */ stwu r1, -0x30(r1) -/* 801D6CB8 001D2918 7C 08 02 A6 */ mflr r0 -/* 801D6CBC 001D291C 90 01 00 34 */ stw r0, 0x34(r1) -/* 801D6CC0 001D2920 38 00 FF FF */ li r0, -1 -/* 801D6CC4 001D2924 BE C1 00 08 */ stmw r22, 8(r1) -/* 801D6CC8 001D2928 7C 97 23 78 */ mr r23, r4 -/* 801D6CCC 001D292C 7C 76 1B 78 */ mr r22, r3 -/* 801D6CD0 001D2930 7C F8 3B 78 */ mr r24, r7 -/* 801D6CD4 001D2934 3B 86 00 01 */ addi r28, r6, 1 -/* 801D6CD8 001D2938 3B E0 00 00 */ li r31, 0 -/* 801D6CDC 001D293C 3B 20 00 01 */ li r25, 1 -/* 801D6CE0 001D2940 90 04 00 00 */ stw r0, 0(r4) -/* 801D6CE4 001D2944 48 00 01 0C */ b lbl_801D6DF0 -lbl_801D6CE8: -/* 801D6CE8 001D2948 7E C3 B3 78 */ mr r3, r22 -/* 801D6CEC 001D294C 4B FF DF F1 */ bl func_801D4CDC -/* 801D6CF0 001D2950 7C 7F 1B 79 */ or. r31, r3, r3 -/* 801D6CF4 001D2954 40 82 00 F8 */ bne lbl_801D6DEC -/* 801D6CF8 001D2958 2C 18 00 00 */ cmpwi r24, 0 -/* 801D6CFC 001D295C 41 82 00 08 */ beq lbl_801D6D04 -/* 801D6D00 001D2960 3B A0 00 00 */ li r29, 0 -lbl_801D6D04: -/* 801D6D04 001D2964 4B FF E9 1D */ bl func_801D5620 -/* 801D6D08 001D2968 90 77 00 00 */ stw r3, 0(r23) -/* 801D6D0C 001D296C 80 77 00 00 */ lwz r3, 0(r23) -/* 801D6D10 001D2970 2C 03 FF FF */ cmpwi r3, -1 -/* 801D6D14 001D2974 40 82 00 20 */ bne lbl_801D6D34 -/* 801D6D18 001D2978 2C 18 00 00 */ cmpwi r24, 0 -/* 801D6D1C 001D297C 41 82 FF E8 */ beq lbl_801D6D04 -/* 801D6D20 001D2980 3C 80 04 C5 */ lis r4, 0x04C4B3EC@ha -/* 801D6D24 001D2984 3B BD 00 01 */ addi r29, r29, 1 -/* 801D6D28 001D2988 38 04 B3 EC */ addi r0, r4, 0x04C4B3EC@l -/* 801D6D2C 001D298C 7C 1D 00 40 */ cmplw r29, r0 -/* 801D6D30 001D2990 41 80 FF D4 */ blt lbl_801D6D04 -lbl_801D6D34: -/* 801D6D34 001D2994 2C 03 FF FF */ cmpwi r3, -1 -/* 801D6D38 001D2998 41 82 00 44 */ beq lbl_801D6D7C -/* 801D6D3C 001D299C 3B 20 00 00 */ li r25, 0 -/* 801D6D40 001D29A0 4B FF E6 9D */ bl TRKGetBuffer -/* 801D6D44 001D29A4 38 80 00 00 */ li r4, 0 -/* 801D6D48 001D29A8 7C 7E 1B 78 */ mr r30, r3 -/* 801D6D4C 001D29AC 4B FF E5 BD */ bl TRKSetBufferPosition -/* 801D6D50 001D29B0 80 9E 00 08 */ lwz r4, 8(r30) -/* 801D6D54 001D29B4 38 7E 00 10 */ addi r3, r30, 0x10 -/* 801D6D58 001D29B8 48 00 2F 0D */ bl func_801D9C64 -/* 801D6D5C 001D29BC 8B 7E 00 14 */ lbz r27, 0x14(r30) -/* 801D6D60 001D29C0 28 1B 00 80 */ cmplwi r27, 0x80 -/* 801D6D64 001D29C4 40 80 00 18 */ bge lbl_801D6D7C -/* 801D6D68 001D29C8 80 77 00 00 */ lwz r3, 0(r23) -/* 801D6D6C 001D29CC 4B FF E8 05 */ bl TRKProcessInput -/* 801D6D70 001D29D0 38 00 FF FF */ li r0, -1 -/* 801D6D74 001D29D4 90 17 00 00 */ stw r0, 0(r23) -/* 801D6D78 001D29D8 4B FF FF 8C */ b lbl_801D6D04 -lbl_801D6D7C: -/* 801D6D7C 001D29DC 80 77 00 00 */ lwz r3, 0(r23) -/* 801D6D80 001D29E0 2C 03 FF FF */ cmpwi r3, -1 -/* 801D6D84 001D29E4 41 82 00 68 */ beq lbl_801D6DEC -/* 801D6D88 001D29E8 80 1E 00 08 */ lwz r0, 8(r30) -/* 801D6D8C 001D29EC 28 00 00 40 */ cmplwi r0, 0x40 -/* 801D6D90 001D29F0 40 80 00 08 */ bge lbl_801D6D98 -/* 801D6D94 001D29F4 3B 20 00 01 */ li r25, 1 -lbl_801D6D98: -/* 801D6D98 001D29F8 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D6D9C 001D29FC 40 82 00 10 */ bne lbl_801D6DAC -/* 801D6DA0 001D2A00 2C 19 00 00 */ cmpwi r25, 0 -/* 801D6DA4 001D2A04 40 82 00 08 */ bne lbl_801D6DAC -/* 801D6DA8 001D2A08 8B 5E 00 18 */ lbz r26, 0x18(r30) -lbl_801D6DAC: -/* 801D6DAC 001D2A0C 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D6DB0 001D2A10 40 82 00 20 */ bne lbl_801D6DD0 -/* 801D6DB4 001D2A14 2C 19 00 00 */ cmpwi r25, 0 -/* 801D6DB8 001D2A18 40 82 00 18 */ bne lbl_801D6DD0 -/* 801D6DBC 001D2A1C 2C 1B 00 80 */ cmpwi r27, 0x80 -/* 801D6DC0 001D2A20 40 82 00 0C */ bne lbl_801D6DCC -/* 801D6DC4 001D2A24 2C 1A 00 00 */ cmpwi r26, 0 -/* 801D6DC8 001D2A28 41 82 00 08 */ beq lbl_801D6DD0 -lbl_801D6DCC: -/* 801D6DCC 001D2A2C 3B 20 00 01 */ li r25, 1 -lbl_801D6DD0: -/* 801D6DD0 001D2A30 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D6DD4 001D2A34 40 82 00 0C */ bne lbl_801D6DE0 -/* 801D6DD8 001D2A38 2C 19 00 00 */ cmpwi r25, 0 -/* 801D6DDC 001D2A3C 41 82 00 10 */ beq lbl_801D6DEC -lbl_801D6DE0: -/* 801D6DE0 001D2A40 4B FF E5 99 */ bl TRKReleaseBuffer -/* 801D6DE4 001D2A44 38 00 FF FF */ li r0, -1 -/* 801D6DE8 001D2A48 90 17 00 00 */ stw r0, 0(r23) -lbl_801D6DEC: -/* 801D6DEC 001D2A4C 3B 9C FF FF */ addi r28, r28, -1 -lbl_801D6DF0: -/* 801D6DF0 001D2A50 2C 1C 00 00 */ cmpwi r28, 0 -/* 801D6DF4 001D2A54 41 82 00 18 */ beq lbl_801D6E0C -/* 801D6DF8 001D2A58 80 17 00 00 */ lwz r0, 0(r23) -/* 801D6DFC 001D2A5C 2C 00 FF FF */ cmpwi r0, -1 -/* 801D6E00 001D2A60 40 82 00 0C */ bne lbl_801D6E0C -/* 801D6E04 001D2A64 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D6E08 001D2A68 41 82 FE E0 */ beq lbl_801D6CE8 -lbl_801D6E0C: -/* 801D6E0C 001D2A6C 80 17 00 00 */ lwz r0, 0(r23) -/* 801D6E10 001D2A70 2C 00 FF FF */ cmpwi r0, -1 -/* 801D6E14 001D2A74 40 82 00 08 */ bne lbl_801D6E1C -/* 801D6E18 001D2A78 3B E0 08 00 */ li r31, 0x800 -lbl_801D6E1C: -/* 801D6E1C 001D2A7C 7F E3 FB 78 */ mr r3, r31 -/* 801D6E20 001D2A80 BA C1 00 08 */ lmw r22, 8(r1) -/* 801D6E24 001D2A84 80 01 00 34 */ lwz r0, 0x34(r1) -/* 801D6E28 001D2A88 7C 08 03 A6 */ mtlr r0 -/* 801D6E2C 001D2A8C 38 21 00 30 */ addi r1, r1, 0x30 -/* 801D6E30 001D2A90 4E 80 00 20 */ blr - -.global TRKSuppAccessFile -TRKSuppAccessFile: -/* 801D6E34 001D2A94 94 21 FF 70 */ stwu r1, -0x90(r1) -/* 801D6E38 001D2A98 7C 08 02 A6 */ mflr r0 -/* 801D6E3C 001D2A9C 90 01 00 94 */ stw r0, 0x94(r1) -/* 801D6E40 001D2AA0 BE 61 00 5C */ stmw r19, 0x5c(r1) -/* 801D6E44 001D2AA4 7C 98 23 79 */ or. r24, r4, r4 -/* 801D6E48 001D2AA8 7C 77 1B 78 */ mr r23, r3 -/* 801D6E4C 001D2AAC 7C B9 2B 78 */ mr r25, r5 -/* 801D6E50 001D2AB0 7C DA 33 78 */ mr r26, r6 -/* 801D6E54 001D2AB4 7C FB 3B 78 */ mr r27, r7 -/* 801D6E58 001D2AB8 7D 1C 43 78 */ mr r28, r8 -/* 801D6E5C 001D2ABC 41 82 00 10 */ beq lbl_801D6E6C -/* 801D6E60 001D2AC0 80 19 00 00 */ lwz r0, 0(r25) -/* 801D6E64 001D2AC4 28 00 00 00 */ cmplwi r0, 0 -/* 801D6E68 001D2AC8 40 82 00 0C */ bne lbl_801D6E74 -lbl_801D6E6C: -/* 801D6E6C 001D2ACC 38 60 00 02 */ li r3, 2 -/* 801D6E70 001D2AD0 48 00 01 D0 */ b lbl_801D7040 -lbl_801D6E74: -/* 801D6E74 001D2AD4 38 00 00 00 */ li r0, 0 -/* 801D6E78 001D2AD8 3B A0 00 00 */ li r29, 0 -/* 801D6E7C 001D2ADC 90 1A 00 00 */ stw r0, 0(r26) -/* 801D6E80 001D2AE0 3B C0 00 00 */ li r30, 0 -/* 801D6E84 001D2AE4 3A A0 00 00 */ li r21, 0 -/* 801D6E88 001D2AE8 48 00 01 88 */ b lbl_801D7010 -lbl_801D6E8C: -/* 801D6E8C 001D2AEC 38 61 00 14 */ addi r3, r1, 0x14 -/* 801D6E90 001D2AF0 38 80 00 00 */ li r4, 0 -/* 801D6E94 001D2AF4 38 A0 00 40 */ li r5, 0x40 -/* 801D6E98 001D2AF8 4B E2 D2 9D */ bl TRK_memset -/* 801D6E9C 001D2AFC 80 19 00 00 */ lwz r0, 0(r25) -/* 801D6EA0 001D2B00 38 60 08 00 */ li r3, 0x800 -/* 801D6EA4 001D2B04 7C 1E 00 50 */ subf r0, r30, r0 -/* 801D6EA8 001D2B08 28 00 08 00 */ cmplwi r0, 0x800 -/* 801D6EAC 001D2B0C 41 81 00 08 */ bgt lbl_801D6EB4 -/* 801D6EB0 001D2B10 7C 03 03 78 */ mr r3, r0 -lbl_801D6EB4: -/* 801D6EB4 001D2B14 2C 1C 00 00 */ cmpwi r28, 0 -/* 801D6EB8 001D2B18 7C 7F 1B 78 */ mr r31, r3 -/* 801D6EBC 001D2B1C 38 00 00 D0 */ li r0, 0xd0 -/* 801D6EC0 001D2B20 41 82 00 08 */ beq lbl_801D6EC8 -/* 801D6EC4 001D2B24 38 00 00 D1 */ li r0, 0xd1 -lbl_801D6EC8: -/* 801D6EC8 001D2B28 2C 1C 00 00 */ cmpwi r28, 0 -/* 801D6ECC 001D2B2C 98 01 00 18 */ stb r0, 0x18(r1) -/* 801D6ED0 001D2B30 38 00 00 40 */ li r0, 0x40 -/* 801D6ED4 001D2B34 40 82 00 08 */ bne lbl_801D6EDC -/* 801D6ED8 001D2B38 38 1F 00 40 */ addi r0, r31, 0x40 -lbl_801D6EDC: -/* 801D6EDC 001D2B3C 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D6EE0 001D2B40 38 61 00 0C */ addi r3, r1, 0xc -/* 801D6EE4 001D2B44 38 81 00 08 */ addi r4, r1, 8 -/* 801D6EE8 001D2B48 92 E1 00 1C */ stw r23, 0x1c(r1) -/* 801D6EEC 001D2B4C B3 E1 00 20 */ sth r31, 0x20(r1) -/* 801D6EF0 001D2B50 4B FF E5 19 */ bl TRKGetFreeBuffer -/* 801D6EF4 001D2B54 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6EF8 001D2B58 38 81 00 14 */ addi r4, r1, 0x14 -/* 801D6EFC 001D2B5C 38 A0 00 40 */ li r5, 0x40 -/* 801D6F00 001D2B60 4B FF E1 75 */ bl TRKAppendBuffer_ui8 -/* 801D6F04 001D2B64 2C 1C 00 00 */ cmpwi r28, 0 -/* 801D6F08 001D2B68 7C 75 1B 78 */ mr r21, r3 -/* 801D6F0C 001D2B6C 40 82 00 20 */ bne lbl_801D6F2C -/* 801D6F10 001D2B70 2C 15 00 00 */ cmpwi r21, 0 -/* 801D6F14 001D2B74 40 82 00 18 */ bne lbl_801D6F2C -/* 801D6F18 001D2B78 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6F1C 001D2B7C 7F E5 FB 78 */ mr r5, r31 -/* 801D6F20 001D2B80 7C 98 F2 14 */ add r4, r24, r30 -/* 801D6F24 001D2B84 4B FF E1 51 */ bl TRKAppendBuffer_ui8 -/* 801D6F28 001D2B88 7C 75 1B 78 */ mr r21, r3 -lbl_801D6F2C: -/* 801D6F2C 001D2B8C 2C 15 00 00 */ cmpwi r21, 0 -/* 801D6F30 001D2B90 40 82 00 D4 */ bne lbl_801D7004 -/* 801D6F34 001D2B94 2C 1B 00 00 */ cmpwi r27, 0 -/* 801D6F38 001D2B98 41 82 00 C0 */ beq lbl_801D6FF8 -/* 801D6F3C 001D2B9C 2C 1C 00 00 */ cmpwi r28, 0 -/* 801D6F40 001D2BA0 38 00 00 00 */ li r0, 0 -/* 801D6F44 001D2BA4 41 82 00 10 */ beq lbl_801D6F54 -/* 801D6F48 001D2BA8 28 17 00 00 */ cmplwi r23, 0 -/* 801D6F4C 001D2BAC 40 82 00 08 */ bne lbl_801D6F54 -/* 801D6F50 001D2BB0 38 00 00 01 */ li r0, 1 -lbl_801D6F54: -/* 801D6F54 001D2BB4 2C 1C 00 00 */ cmpwi r28, 0 -/* 801D6F58 001D2BB8 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6F5C 001D2BBC 38 81 00 10 */ addi r4, r1, 0x10 -/* 801D6F60 001D2BC0 38 A0 00 05 */ li r5, 5 -/* 801D6F64 001D2BC4 7C 00 00 34 */ cntlzw r0, r0 -/* 801D6F68 001D2BC8 38 C0 00 03 */ li r6, 3 -/* 801D6F6C 001D2BCC 54 07 D9 7E */ srwi r7, r0, 5 -/* 801D6F70 001D2BD0 4B FF FD 45 */ bl func_801D6CB4 -/* 801D6F74 001D2BD4 7C 75 1B 79 */ or. r21, r3, r3 -/* 801D6F78 001D2BD8 40 82 00 10 */ bne lbl_801D6F88 -/* 801D6F7C 001D2BDC 80 61 00 10 */ lwz r3, 0x10(r1) -/* 801D6F80 001D2BE0 4B FF E4 5D */ bl TRKGetBuffer -/* 801D6F84 001D2BE4 7C 76 1B 78 */ mr r22, r3 -lbl_801D6F88: -/* 801D6F88 001D2BE8 80 16 00 20 */ lwz r0, 0x20(r22) -/* 801D6F8C 001D2BEC 2C 1C 00 00 */ cmpwi r28, 0 -/* 801D6F90 001D2BF0 A2 76 00 24 */ lhz r19, 0x24(r22) -/* 801D6F94 001D2BF4 54 14 06 3E */ clrlwi r20, r0, 0x18 -/* 801D6F98 001D2BF8 41 82 00 40 */ beq lbl_801D6FD8 -/* 801D6F9C 001D2BFC 2C 15 00 00 */ cmpwi r21, 0 -/* 801D6FA0 001D2C00 40 82 00 38 */ bne lbl_801D6FD8 -/* 801D6FA4 001D2C04 7C 13 F8 40 */ cmplw r19, r31 -/* 801D6FA8 001D2C08 41 81 00 30 */ bgt lbl_801D6FD8 -/* 801D6FAC 001D2C0C 7E C3 B3 78 */ mr r3, r22 -/* 801D6FB0 001D2C10 38 80 00 40 */ li r4, 0x40 -/* 801D6FB4 001D2C14 4B FF E3 55 */ bl TRKSetBufferPosition -/* 801D6FB8 001D2C18 7E C3 B3 78 */ mr r3, r22 -/* 801D6FBC 001D2C1C 7E 65 9B 78 */ mr r5, r19 -/* 801D6FC0 001D2C20 7C 98 F2 14 */ add r4, r24, r30 -/* 801D6FC4 001D2C24 4B FF DE 35 */ bl TRKReadBuffer_ui8 -/* 801D6FC8 001D2C28 7C 75 1B 78 */ mr r21, r3 -/* 801D6FCC 001D2C2C 2C 15 03 02 */ cmpwi r21, 0x302 -/* 801D6FD0 001D2C30 40 82 00 08 */ bne lbl_801D6FD8 -/* 801D6FD4 001D2C34 3A A0 00 00 */ li r21, 0 -lbl_801D6FD8: -/* 801D6FD8 001D2C38 7C 13 F8 40 */ cmplw r19, r31 -/* 801D6FDC 001D2C3C 41 82 00 0C */ beq lbl_801D6FE8 -/* 801D6FE0 001D2C40 7E 7F 9B 78 */ mr r31, r19 -/* 801D6FE4 001D2C44 3B A0 00 01 */ li r29, 1 -lbl_801D6FE8: -/* 801D6FE8 001D2C48 92 9A 00 00 */ stw r20, 0(r26) -/* 801D6FEC 001D2C4C 80 61 00 10 */ lwz r3, 0x10(r1) -/* 801D6FF0 001D2C50 4B FF E3 89 */ bl TRKReleaseBuffer -/* 801D6FF4 001D2C54 48 00 00 10 */ b lbl_801D7004 -lbl_801D6FF8: -/* 801D6FF8 001D2C58 80 61 00 08 */ lwz r3, 8(r1) -/* 801D6FFC 001D2C5C 4B FF DC E1 */ bl func_801D4CDC -/* 801D7000 001D2C60 7C 75 1B 78 */ mr r21, r3 -lbl_801D7004: -/* 801D7004 001D2C64 80 61 00 0C */ lwz r3, 0xc(r1) -/* 801D7008 001D2C68 4B FF E3 71 */ bl TRKReleaseBuffer -/* 801D700C 001D2C6C 7F DE FA 14 */ add r30, r30, r31 -lbl_801D7010: -/* 801D7010 001D2C70 2C 1D 00 00 */ cmpwi r29, 0 -/* 801D7014 001D2C74 40 82 00 24 */ bne lbl_801D7038 -/* 801D7018 001D2C78 80 19 00 00 */ lwz r0, 0(r25) -/* 801D701C 001D2C7C 7C 1E 00 40 */ cmplw r30, r0 -/* 801D7020 001D2C80 40 80 00 18 */ bge lbl_801D7038 -/* 801D7024 001D2C84 2C 15 00 00 */ cmpwi r21, 0 -/* 801D7028 001D2C88 40 82 00 10 */ bne lbl_801D7038 -/* 801D702C 001D2C8C 80 1A 00 00 */ lwz r0, 0(r26) -/* 801D7030 001D2C90 2C 00 00 00 */ cmpwi r0, 0 -/* 801D7034 001D2C94 41 82 FE 58 */ beq lbl_801D6E8C -lbl_801D7038: -/* 801D7038 001D2C98 93 D9 00 00 */ stw r30, 0(r25) -/* 801D703C 001D2C9C 7E A3 AB 78 */ mr r3, r21 -lbl_801D7040: -/* 801D7040 001D2CA0 BA 61 00 5C */ lmw r19, 0x5c(r1) -/* 801D7044 001D2CA4 80 01 00 94 */ lwz r0, 0x94(r1) -/* 801D7048 001D2CA8 7C 08 03 A6 */ mtlr r0 -/* 801D704C 001D2CAC 38 21 00 90 */ addi r1, r1, 0x90 -/* 801D7050 001D2CB0 4E 80 00 20 */ blr - -.global func_801D7054 -func_801D7054: -/* 801D7054 001D2CB4 38 60 00 00 */ li r3, 0 -/* 801D7058 001D2CB8 4E 80 00 20 */ blr - -.global func_801D705C -func_801D705C: -/* 801D705C 001D2CBC 38 60 00 00 */ li r3, 0 -/* 801D7060 001D2CC0 4E 80 00 20 */ blr - -.global func_801D7064 -func_801D7064: -/* 801D7064 001D2CC4 38 60 00 00 */ li r3, 0 -/* 801D7068 001D2CC8 4E 80 00 20 */ blr - -.global TRKDoNotifyStopped -TRKDoNotifyStopped: -/* 801D706C 001D2CCC 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D7070 001D2CD0 7C 08 02 A6 */ mflr r0 -/* 801D7074 001D2CD4 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D7078 001D2CD8 38 81 00 08 */ addi r4, r1, 8 -/* 801D707C 001D2CDC 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D7080 001D2CE0 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D7084 001D2CE4 7C 7E 1B 78 */ mr r30, r3 -/* 801D7088 001D2CE8 38 61 00 0C */ addi r3, r1, 0xc -/* 801D708C 001D2CEC 4B FF E3 7D */ bl TRKGetFreeBuffer -/* 801D7090 001D2CF0 7C 7F 1B 79 */ or. r31, r3, r3 -/* 801D7094 001D2CF4 40 82 00 54 */ bne lbl_801D70E8 -/* 801D7098 001D2CF8 40 82 00 20 */ bne lbl_801D70B8 -/* 801D709C 001D2CFC 2C 1E 00 90 */ cmpwi r30, 0x90 -/* 801D70A0 001D2D00 40 82 00 10 */ bne lbl_801D70B0 -/* 801D70A4 001D2D04 80 61 00 08 */ lwz r3, 8(r1) -/* 801D70A8 001D2D08 48 00 09 09 */ bl TRKTargetAddStopInfo -/* 801D70AC 001D2D0C 48 00 00 0C */ b lbl_801D70B8 -lbl_801D70B0: -/* 801D70B0 001D2D10 80 61 00 08 */ lwz r3, 8(r1) -/* 801D70B4 001D2D14 48 00 08 79 */ bl TRKTargetAddExceptionInfo -lbl_801D70B8: -/* 801D70B8 001D2D18 80 61 00 08 */ lwz r3, 8(r1) -/* 801D70BC 001D2D1C 38 81 00 10 */ addi r4, r1, 0x10 -/* 801D70C0 001D2D20 38 A0 00 02 */ li r5, 2 -/* 801D70C4 001D2D24 38 C0 00 03 */ li r6, 3 -/* 801D70C8 001D2D28 38 E0 00 01 */ li r7, 1 -/* 801D70CC 001D2D2C 4B FF FB E9 */ bl func_801D6CB4 -/* 801D70D0 001D2D30 7C 7F 1B 79 */ or. r31, r3, r3 -/* 801D70D4 001D2D34 40 82 00 0C */ bne lbl_801D70E0 -/* 801D70D8 001D2D38 80 61 00 10 */ lwz r3, 0x10(r1) -/* 801D70DC 001D2D3C 4B FF E2 9D */ bl TRKReleaseBuffer -lbl_801D70E0: -/* 801D70E0 001D2D40 80 61 00 0C */ lwz r3, 0xc(r1) -/* 801D70E4 001D2D44 4B FF E2 95 */ bl TRKReleaseBuffer -lbl_801D70E8: -/* 801D70E8 001D2D48 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D70EC 001D2D4C 7F E3 FB 78 */ mr r3, r31 -/* 801D70F0 001D2D50 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D70F4 001D2D54 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D70F8 001D2D58 7C 08 03 A6 */ mtlr r0 -/* 801D70FC 001D2D5C 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D7100 001D2D60 4E 80 00 20 */ blr - -.global TRK_flush_cache -TRK_flush_cache: -/* 801D7104 001D2D64 3C A0 FF FF */ lis r5, 0xFFFFFFF1@h -/* 801D7108 001D2D68 60 A5 FF F1 */ ori r5, r5, 0xFFFFFFF1@l -/* 801D710C 001D2D6C 7C A5 18 38 */ and r5, r5, r3 -/* 801D7110 001D2D70 7C 65 18 50 */ subf r3, r5, r3 -/* 801D7114 001D2D74 7C 84 1A 14 */ add r4, r4, r3 -lbl_801D7118: -/* 801D7118 001D2D78 7C 00 28 6C */ dcbst 0, r5 -/* 801D711C 001D2D7C 7C 00 28 AC */ dcbf 0, r5 -/* 801D7120 001D2D80 7C 00 04 AC */ sync 0 -/* 801D7124 001D2D84 7C 00 2F AC */ icbi 0, r5 -/* 801D7128 001D2D88 30 A5 00 08 */ addic r5, r5, 8 -/* 801D712C 001D2D8C 34 84 FF F8 */ addic. r4, r4, -8 -/* 801D7130 001D2D90 40 80 FF E8 */ bge lbl_801D7118 -/* 801D7134 001D2D94 4C 00 01 2C */ isync -/* 801D7138 001D2D98 4E 80 00 20 */ blr diff --git a/asm/text_6_2.s b/asm/text_6_2.s index 8b8b485..8c3c9dc 100644 --- a/asm/text_6_2.s +++ b/asm/text_6_2.s @@ -2,1879 +2,6 @@ .section .text, "ax" # 0x80006980 - 0x803E1E60 -.global TRK_strlen -TRK_strlen: -/* 801D71F4 001D2E54 38 83 FF FF */ addi r4, r3, -1 -/* 801D71F8 001D2E58 38 60 FF FF */ li r3, -1 -lbl_801D71FC: -/* 801D71FC 001D2E5C 8C 04 00 01 */ lbzu r0, 1(r4) -/* 801D7200 001D2E60 38 63 00 01 */ addi r3, r3, 1 -/* 801D7204 001D2E64 28 00 00 00 */ cmplwi r0, 0 -/* 801D7208 001D2E68 40 82 FF F4 */ bne lbl_801D71FC -/* 801D720C 001D2E6C 4E 80 00 20 */ blr - -.global func_801D7210 -func_801D7210: -/* 801D7210 001D2E70 7C 60 00 A6 */ mfmsr r3 -/* 801D7214 001D2E74 4E 80 00 20 */ blr - -.global func_801D7218 -func_801D7218: -/* 801D7218 001D2E78 7C 60 01 24 */ mtmsr r3 -/* 801D721C 001D2E7C 4E 80 00 20 */ blr - -.global TRK_ppc_memcpy -TRK_ppc_memcpy: -/* 801D7220 001D2E80 7D 00 00 A6 */ mfmsr r8 -/* 801D7224 001D2E84 39 40 00 00 */ li r10, 0 -lbl_801D7228: -/* 801D7228 001D2E88 7C 0A 28 00 */ cmpw r10, r5 -/* 801D722C 001D2E8C 41 82 00 24 */ beq lbl_801D7250 -/* 801D7230 001D2E90 7C E0 01 24 */ mtmsr r7 -/* 801D7234 001D2E94 7C 00 04 AC */ sync 0 -/* 801D7238 001D2E98 7D 2A 20 AE */ lbzx r9, r10, r4 -/* 801D723C 001D2E9C 7C C0 01 24 */ mtmsr r6 -/* 801D7240 001D2EA0 7C 00 04 AC */ sync 0 -/* 801D7244 001D2EA4 7D 2A 19 AE */ stbx r9, r10, r3 -/* 801D7248 001D2EA8 39 4A 00 01 */ addi r10, r10, 1 -/* 801D724C 001D2EAC 4B FF FF DC */ b lbl_801D7228 -lbl_801D7250: -/* 801D7250 001D2EB0 7D 00 01 24 */ mtmsr r8 -/* 801D7254 001D2EB4 7C 00 04 AC */ sync 0 -/* 801D7258 001D2EB8 4E 80 00 20 */ blr - -.global TRKInterruptHandler -TRKInterruptHandler: -/* 801D725C 001D2EBC 7C 5A 03 A6 */ mtspr 0x1a, r2 -/* 801D7260 001D2EC0 7C 9B 03 A6 */ mtspr 0x1b, r4 -/* 801D7264 001D2EC4 7C 93 42 A6 */ mfspr r4, 0x113 -/* 801D7268 001D2EC8 7C 40 00 26 */ mfcr r2 -/* 801D726C 001D2ECC 7C 53 43 A6 */ mtspr 0x113, r2 -/* 801D7270 001D2ED0 3C 40 80 49 */ lis r2, lbl_804907F4@h -/* 801D7274 001D2ED4 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l -/* 801D7278 001D2ED8 80 42 00 8C */ lwz r2, 0x8c(r2) -/* 801D727C 001D2EDC 60 42 80 02 */ ori r2, r2, 0x8002 -/* 801D7280 001D2EE0 68 42 80 02 */ xori r2, r2, 0x8002 -/* 801D7284 001D2EE4 7C 00 04 AC */ sync 0 -/* 801D7288 001D2EE8 7C 40 01 24 */ mtmsr r2 -/* 801D728C 001D2EEC 7C 00 04 AC */ sync 0 -/* 801D7290 001D2EF0 3C 40 80 49 */ lis r2, lbl_804907F0@h -/* 801D7294 001D2EF4 60 42 07 F0 */ ori r2, r2, lbl_804907F0@l -/* 801D7298 001D2EF8 B0 62 00 00 */ sth r3, 0(r2) -/* 801D729C 001D2EFC 2C 03 05 00 */ cmpwi r3, 0x500 -/* 801D72A0 001D2F00 40 82 00 84 */ bne lbl_801D7324 -/* 801D72A4 001D2F04 3C 40 80 49 */ lis r2, lbl_80490898@h -/* 801D72A8 001D2F08 60 42 08 98 */ ori r2, r2, lbl_80490898@l -/* 801D72AC 001D2F0C 7C 68 02 A6 */ mflr r3 -/* 801D72B0 001D2F10 90 62 04 2C */ stw r3, 0x42c(r2) -/* 801D72B4 001D2F14 48 00 22 6D */ bl func_801D9520 -/* 801D72B8 001D2F18 3C 40 80 49 */ lis r2, lbl_80490898@h -/* 801D72BC 001D2F1C 60 42 08 98 */ ori r2, r2, lbl_80490898@l -/* 801D72C0 001D2F20 80 62 04 2C */ lwz r3, 0x42c(r2) -/* 801D72C4 001D2F24 7C 68 03 A6 */ mtlr r3 -/* 801D72C8 001D2F28 3C 40 80 49 */ lis r2, lbl_804907F4@h -/* 801D72CC 001D2F2C 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l -/* 801D72D0 001D2F30 80 42 00 A0 */ lwz r2, 0xa0(r2) -/* 801D72D4 001D2F34 88 42 00 00 */ lbz r2, 0(r2) -/* 801D72D8 001D2F38 2C 02 00 00 */ cmpwi r2, 0 -/* 801D72DC 001D2F3C 41 82 00 2C */ beq lbl_801D7308 -/* 801D72E0 001D2F40 3C 40 80 42 */ lis r2, lbl_8042323C@h -/* 801D72E4 001D2F44 60 42 32 3C */ ori r2, r2, lbl_8042323C@l -/* 801D72E8 001D2F48 88 42 00 0C */ lbz r2, 0xc(r2) -/* 801D72EC 001D2F4C 2C 02 00 01 */ cmpwi r2, 1 -/* 801D72F0 001D2F50 41 82 00 18 */ beq lbl_801D7308 -/* 801D72F4 001D2F54 3C 40 80 49 */ lis r2, lbl_804907F4@h -/* 801D72F8 001D2F58 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l -/* 801D72FC 001D2F5C 38 60 00 01 */ li r3, 1 -/* 801D7300 001D2F60 98 62 00 9C */ stb r3, 0x9c(r2) -/* 801D7304 001D2F64 48 00 00 20 */ b lbl_801D7324 -lbl_801D7308: -/* 801D7308 001D2F68 3C 40 80 49 */ lis r2, lbl_80490CC8@h -/* 801D730C 001D2F6C 60 42 0C C8 */ ori r2, r2, lbl_80490CC8@l -/* 801D7310 001D2F70 80 62 00 88 */ lwz r3, 0x88(r2) -/* 801D7314 001D2F74 7C 6F F1 20 */ mtcrf 0xff, r3 -/* 801D7318 001D2F78 80 62 00 0C */ lwz r3, 0xc(r2) -/* 801D731C 001D2F7C 80 42 00 08 */ lwz r2, 8(r2) -/* 801D7320 001D2F80 4C 00 00 64 */ rfi -lbl_801D7324: -/* 801D7324 001D2F84 3C 40 80 49 */ lis r2, lbl_804907F0@h -/* 801D7328 001D2F88 60 42 07 F0 */ ori r2, r2, lbl_804907F0@l -/* 801D732C 001D2F8C A0 62 00 00 */ lhz r3, 0(r2) -/* 801D7330 001D2F90 3C 40 80 42 */ lis r2, lbl_8042323C@h -/* 801D7334 001D2F94 60 42 32 3C */ ori r2, r2, lbl_8042323C@l -/* 801D7338 001D2F98 88 42 00 0C */ lbz r2, 0xc(r2) -/* 801D733C 001D2F9C 2C 02 00 00 */ cmpwi r2, 0 -/* 801D7340 001D2FA0 40 82 00 B0 */ bne lbl_801D73F0 -/* 801D7344 001D2FA4 3C 40 80 49 */ lis r2, lbl_80490898@h -/* 801D7348 001D2FA8 60 42 08 98 */ ori r2, r2, lbl_80490898@l -/* 801D734C 001D2FAC 90 02 00 00 */ stw r0, 0(r2) -/* 801D7350 001D2FB0 90 22 00 04 */ stw r1, 4(r2) -/* 801D7354 001D2FB4 7C 11 42 A6 */ mfspr r0, 0x111 -/* 801D7358 001D2FB8 90 02 00 08 */ stw r0, 8(r2) -/* 801D735C 001D2FBC B0 62 02 F8 */ sth r3, 0x2f8(r2) -/* 801D7360 001D2FC0 B0 62 02 FA */ sth r3, 0x2fa(r2) -/* 801D7364 001D2FC4 7C 12 42 A6 */ mfspr r0, 0x112 -/* 801D7368 001D2FC8 90 02 00 0C */ stw r0, 0xc(r2) -/* 801D736C 001D2FCC BC 82 00 10 */ stmw r4, 0x10(r2) -/* 801D7370 001D2FD0 7F 7A 02 A6 */ mfspr r27, 0x1a -/* 801D7374 001D2FD4 7F 88 02 A6 */ mflr r28 -/* 801D7378 001D2FD8 7F B3 42 A6 */ mfspr r29, 0x113 -/* 801D737C 001D2FDC 7F C9 02 A6 */ mfctr r30 -/* 801D7380 001D2FE0 7F E1 02 A6 */ mfxer r31 -/* 801D7384 001D2FE4 BF 62 00 80 */ stmw r27, 0x80(r2) -/* 801D7388 001D2FE8 48 00 18 C9 */ bl TRKSaveExtended1Block -/* 801D738C 001D2FEC 3C 40 80 42 */ lis r2, lbl_8042323C@h -/* 801D7390 001D2FF0 60 42 32 3C */ ori r2, r2, lbl_8042323C@l -/* 801D7394 001D2FF4 38 60 00 01 */ li r3, 1 -/* 801D7398 001D2FF8 98 62 00 0C */ stb r3, 0xc(r2) -/* 801D739C 001D2FFC 3C 40 80 49 */ lis r2, lbl_804907F4@h -/* 801D73A0 001D3000 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l -/* 801D73A4 001D3004 80 02 00 8C */ lwz r0, 0x8c(r2) -/* 801D73A8 001D3008 7C 00 04 AC */ sync 0 -/* 801D73AC 001D300C 7C 00 01 24 */ mtmsr r0 -/* 801D73B0 001D3010 7C 00 04 AC */ sync 0 -/* 801D73B4 001D3014 80 02 00 80 */ lwz r0, 0x80(r2) -/* 801D73B8 001D3018 7C 08 03 A6 */ mtlr r0 -/* 801D73BC 001D301C 80 02 00 84 */ lwz r0, 0x84(r2) -/* 801D73C0 001D3020 7C 09 03 A6 */ mtctr r0 -/* 801D73C4 001D3024 80 02 00 88 */ lwz r0, 0x88(r2) -/* 801D73C8 001D3028 7C 01 03 A6 */ mtxer r0 -/* 801D73CC 001D302C 80 02 00 94 */ lwz r0, 0x94(r2) -/* 801D73D0 001D3030 7C 12 03 A6 */ mtdsisr r0 -/* 801D73D4 001D3034 80 02 00 90 */ lwz r0, 0x90(r2) -/* 801D73D8 001D3038 7C 13 03 A6 */ mtdar r0 -/* 801D73DC 001D303C B8 62 00 0C */ lmw r3, 0xc(r2) -/* 801D73E0 001D3040 80 02 00 00 */ lwz r0, 0(r2) -/* 801D73E4 001D3044 80 22 00 04 */ lwz r1, 4(r2) -/* 801D73E8 001D3048 80 42 00 08 */ lwz r2, 8(r2) -/* 801D73EC 001D304C 48 00 07 AC */ b TRKPostInterruptEvent -lbl_801D73F0: -/* 801D73F0 001D3050 3C 40 80 42 */ lis r2, lbl_8042323C@h -/* 801D73F4 001D3054 60 42 32 3C */ ori r2, r2, lbl_8042323C@l -/* 801D73F8 001D3058 B0 62 00 08 */ sth r3, 8(r2) -/* 801D73FC 001D305C 7C 7A 02 A6 */ mfspr r3, 0x1a -/* 801D7400 001D3060 90 62 00 00 */ stw r3, 0(r2) -/* 801D7404 001D3064 A0 62 00 08 */ lhz r3, 8(r2) -/* 801D7408 001D3068 2C 03 02 00 */ cmpwi r3, 0x200 -/* 801D740C 001D306C 41 82 00 50 */ beq lbl_801D745C -/* 801D7410 001D3070 2C 03 03 00 */ cmpwi r3, 0x300 -/* 801D7414 001D3074 41 82 00 48 */ beq lbl_801D745C -/* 801D7418 001D3078 2C 03 04 00 */ cmpwi r3, 0x400 -/* 801D741C 001D307C 41 82 00 40 */ beq lbl_801D745C -/* 801D7420 001D3080 2C 03 06 00 */ cmpwi r3, 0x600 -/* 801D7424 001D3084 41 82 00 38 */ beq lbl_801D745C -/* 801D7428 001D3088 2C 03 07 00 */ cmpwi r3, 0x700 -/* 801D742C 001D308C 41 82 00 30 */ beq lbl_801D745C -/* 801D7430 001D3090 2C 03 08 00 */ cmpwi r3, 0x800 -/* 801D7434 001D3094 41 82 00 28 */ beq lbl_801D745C -/* 801D7438 001D3098 2C 03 10 00 */ cmpwi r3, 0x1000 -/* 801D743C 001D309C 41 82 00 20 */ beq lbl_801D745C -/* 801D7440 001D30A0 2C 03 11 00 */ cmpwi r3, 0x1100 -/* 801D7444 001D30A4 41 82 00 18 */ beq lbl_801D745C -/* 801D7448 001D30A8 2C 03 12 00 */ cmpwi r3, 0x1200 -/* 801D744C 001D30AC 41 82 00 10 */ beq lbl_801D745C -/* 801D7450 001D30B0 2C 03 13 00 */ cmpwi r3, 0x1300 -/* 801D7454 001D30B4 41 82 00 08 */ beq lbl_801D745C -/* 801D7458 001D30B8 48 00 00 10 */ b lbl_801D7468 -lbl_801D745C: -/* 801D745C 001D30BC 7C 7A 02 A6 */ mfspr r3, 0x1a -/* 801D7460 001D30C0 38 63 00 04 */ addi r3, r3, 4 -/* 801D7464 001D30C4 7C 7A 03 A6 */ mtspr 0x1a, r3 -lbl_801D7468: -/* 801D7468 001D30C8 3C 40 80 42 */ lis r2, lbl_8042323C@h -/* 801D746C 001D30CC 60 42 32 3C */ ori r2, r2, lbl_8042323C@l -/* 801D7470 001D30D0 38 60 00 01 */ li r3, 1 -/* 801D7474 001D30D4 98 62 00 0D */ stb r3, 0xd(r2) -/* 801D7478 001D30D8 7C 73 42 A6 */ mfspr r3, 0x113 -/* 801D747C 001D30DC 7C 6F F1 20 */ mtcrf 0xff, r3 -/* 801D7480 001D30E0 7C 51 42 A6 */ mfspr r2, 0x111 -/* 801D7484 001D30E4 7C 72 42 A6 */ mfspr r3, 0x112 -/* 801D7488 001D30E8 4C 00 00 64 */ rfi - -.global TRKSwapAndGo -TRKSwapAndGo: -/* 801D748C 001D30EC 3C 60 80 49 */ lis r3, lbl_804907F4@h -/* 801D7490 001D30F0 60 63 07 F4 */ ori r3, r3, lbl_804907F4@l -/* 801D7494 001D30F4 BC 03 00 00 */ stmw r0, 0(r3) -/* 801D7498 001D30F8 7C 00 00 A6 */ mfmsr r0 -/* 801D749C 001D30FC 90 03 00 8C */ stw r0, 0x8c(r3) -/* 801D74A0 001D3100 7C 08 02 A6 */ mflr r0 -/* 801D74A4 001D3104 90 03 00 80 */ stw r0, 0x80(r3) -/* 801D74A8 001D3108 7C 09 02 A6 */ mfctr r0 -/* 801D74AC 001D310C 90 03 00 84 */ stw r0, 0x84(r3) -/* 801D74B0 001D3110 7C 01 02 A6 */ mfxer r0 -/* 801D74B4 001D3114 90 03 00 88 */ stw r0, 0x88(r3) -/* 801D74B8 001D3118 7C 12 02 A6 */ mfdsisr r0 -/* 801D74BC 001D311C 90 03 00 94 */ stw r0, 0x94(r3) -/* 801D74C0 001D3120 7C 13 02 A6 */ mfdar r0 -/* 801D74C4 001D3124 90 03 00 90 */ stw r0, 0x90(r3) -/* 801D74C8 001D3128 38 20 80 02 */ li r1, -32766 -/* 801D74CC 001D312C 7C 21 08 F8 */ nor r1, r1, r1 -/* 801D74D0 001D3130 7C 60 00 A6 */ mfmsr r3 -/* 801D74D4 001D3134 7C 63 08 38 */ and r3, r3, r1 -/* 801D74D8 001D3138 7C 60 01 24 */ mtmsr r3 -/* 801D74DC 001D313C 3C 40 80 49 */ lis r2, lbl_804907F4@h -/* 801D74E0 001D3140 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l -/* 801D74E4 001D3144 80 42 00 A0 */ lwz r2, 0xa0(r2) -/* 801D74E8 001D3148 88 42 00 00 */ lbz r2, 0(r2) -/* 801D74EC 001D314C 2C 02 00 00 */ cmpwi r2, 0 -/* 801D74F0 001D3150 41 82 00 18 */ beq lbl_801D7508 -/* 801D74F4 001D3154 3C 40 80 49 */ lis r2, lbl_804907F4@h -/* 801D74F8 001D3158 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l -/* 801D74FC 001D315C 38 60 00 01 */ li r3, 1 -/* 801D7500 001D3160 98 62 00 9C */ stb r3, 0x9c(r2) -/* 801D7504 001D3164 48 00 00 4C */ b lbl_801D7550 -lbl_801D7508: -/* 801D7508 001D3168 3C 40 80 42 */ lis r2, lbl_8042323C@h -/* 801D750C 001D316C 60 42 32 3C */ ori r2, r2, lbl_8042323C@l -/* 801D7510 001D3170 38 60 00 00 */ li r3, 0 -/* 801D7514 001D3174 98 62 00 0C */ stb r3, 0xc(r2) -/* 801D7518 001D3178 48 00 18 F1 */ bl TRKRestoreExtended1Block -/* 801D751C 001D317C 3C 40 80 49 */ lis r2, lbl_80490898@h -/* 801D7520 001D3180 60 42 08 98 */ ori r2, r2, lbl_80490898@l -/* 801D7524 001D3184 BB 62 00 80 */ lmw r27, 0x80(r2) -/* 801D7528 001D3188 7F 7A 03 A6 */ mtspr 0x1a, r27 -/* 801D752C 001D318C 7F 88 03 A6 */ mtlr r28 -/* 801D7530 001D3190 7F AF F1 20 */ mtcrf 0xff, r29 -/* 801D7534 001D3194 7F C9 03 A6 */ mtctr r30 -/* 801D7538 001D3198 7F E1 03 A6 */ mtxer r31 -/* 801D753C 001D319C B8 62 00 0C */ lmw r3, 0xc(r2) -/* 801D7540 001D31A0 80 02 00 00 */ lwz r0, 0(r2) -/* 801D7544 001D31A4 80 22 00 04 */ lwz r1, 4(r2) -/* 801D7548 001D31A8 80 42 00 08 */ lwz r2, 8(r2) -/* 801D754C 001D31AC 4C 00 00 64 */ rfi -lbl_801D7550: -/* 801D7550 001D31B0 3C 40 80 49 */ lis r2, lbl_804907F4@h -/* 801D7554 001D31B4 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l -/* 801D7558 001D31B8 80 02 00 8C */ lwz r0, 0x8c(r2) -/* 801D755C 001D31BC 7C 00 04 AC */ sync 0 -/* 801D7560 001D31C0 7C 00 01 24 */ mtmsr r0 -/* 801D7564 001D31C4 7C 00 04 AC */ sync 0 -/* 801D7568 001D31C8 80 02 00 80 */ lwz r0, 0x80(r2) -/* 801D756C 001D31CC 7C 08 03 A6 */ mtlr r0 -/* 801D7570 001D31D0 80 02 00 84 */ lwz r0, 0x84(r2) -/* 801D7574 001D31D4 7C 09 03 A6 */ mtctr r0 -/* 801D7578 001D31D8 80 02 00 88 */ lwz r0, 0x88(r2) -/* 801D757C 001D31DC 7C 01 03 A6 */ mtxer r0 -/* 801D7580 001D31E0 80 02 00 94 */ lwz r0, 0x94(r2) -/* 801D7584 001D31E4 7C 12 03 A6 */ mtdsisr r0 -/* 801D7588 001D31E8 80 02 00 90 */ lwz r0, 0x90(r2) -/* 801D758C 001D31EC 7C 13 03 A6 */ mtdar r0 -/* 801D7590 001D31F0 B8 62 00 0C */ lmw r3, 0xc(r2) -/* 801D7594 001D31F4 80 02 00 00 */ lwz r0, 0(r2) -/* 801D7598 001D31F8 80 22 00 04 */ lwz r1, 4(r2) -/* 801D759C 001D31FC 80 42 00 08 */ lwz r2, 8(r2) -/* 801D75A0 001D3200 48 00 05 F8 */ b TRKPostInterruptEvent - -.global ReadFPSCR -ReadFPSCR: -/* 801D75A4 001D3204 94 21 FF C0 */ stwu r1, -0x40(r1) -/* 801D75A8 001D3208 DB E1 00 10 */ stfd f31, 0x10(r1) -/* 801D75AC 001D320C F3 E1 00 20 */ psq_st f31, 32(r1), 0, qr0 -/* 801D75B0 001D3210 FF E0 04 8E */ mffs f31 -/* 801D75B4 001D3214 DB E3 00 00 */ stfd f31, 0(r3) -/* 801D75B8 001D3218 E3 E1 00 20 */ psq_l f31, 32(r1), 0, qr0 -/* 801D75BC 001D321C CB E1 00 10 */ lfd f31, 0x10(r1) -/* 801D75C0 001D3220 38 21 00 40 */ addi r1, r1, 0x40 -/* 801D75C4 001D3224 4E 80 00 20 */ blr - -.global WriteFPSCR -WriteFPSCR: -/* 801D75C8 001D3228 94 21 FF C0 */ stwu r1, -0x40(r1) -/* 801D75CC 001D322C DB E1 00 10 */ stfd f31, 0x10(r1) -/* 801D75D0 001D3230 F3 E1 00 20 */ psq_st f31, 32(r1), 0, qr0 -/* 801D75D4 001D3234 CB E3 00 00 */ lfd f31, 0(r3) -/* 801D75D8 001D3238 FD FE FD 8E */ mtfsf 0xff, f31 -/* 801D75DC 001D323C E3 E1 00 20 */ psq_l f31, 32(r1), 0, qr0 -/* 801D75E0 001D3240 CB E1 00 10 */ lfd f31, 0x10(r1) -/* 801D75E4 001D3244 38 21 00 40 */ addi r1, r1, 0x40 -/* 801D75E8 001D3248 4E 80 00 20 */ blr - -.global func_801D75EC -func_801D75EC: -/* 801D75EC 001D324C 3C 80 80 49 */ lis r4, lbl_804907F4@ha -/* 801D75F0 001D3250 38 84 07 F4 */ addi r4, r4, lbl_804907F4@l -/* 801D75F4 001D3254 90 64 00 A0 */ stw r3, 0xa0(r4) -/* 801D75F8 001D3258 4E 80 00 20 */ blr - -.global TRKTargetStop -TRKTargetStop: -/* 801D75FC 001D325C 3C 60 80 49 */ lis r3, lbl_804907F4@ha -/* 801D7600 001D3260 38 00 00 01 */ li r0, 1 -/* 801D7604 001D3264 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l -/* 801D7608 001D3268 38 60 00 00 */ li r3, 0 -/* 801D760C 001D326C 90 04 00 98 */ stw r0, 0x98(r4) -/* 801D7610 001D3270 4E 80 00 20 */ blr - -.global func_801D7614 -func_801D7614: -/* 801D7614 001D3274 3C 80 80 49 */ lis r4, lbl_804907F4@ha -/* 801D7618 001D3278 38 84 07 F4 */ addi r4, r4, lbl_804907F4@l -/* 801D761C 001D327C 90 64 00 98 */ stw r3, 0x98(r4) -/* 801D7620 001D3280 4E 80 00 20 */ blr - -.global func_801D7624 -func_801D7624: -/* 801D7624 001D3284 3C 60 80 49 */ lis r3, lbl_804907F4@ha -/* 801D7628 001D3288 38 63 07 F4 */ addi r3, r3, lbl_804907F4@l -/* 801D762C 001D328C 80 63 00 98 */ lwz r3, 0x98(r3) -/* 801D7630 001D3290 4E 80 00 20 */ blr - -.global TRKTargetSupportRequest -TRKTargetSupportRequest: -/* 801D7634 001D3294 94 21 FF C0 */ stwu r1, -0x40(r1) -/* 801D7638 001D3298 7C 08 02 A6 */ mflr r0 -/* 801D763C 001D329C 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D7640 001D32A0 90 01 00 44 */ stw r0, 0x44(r1) -/* 801D7644 001D32A4 BF 61 00 2C */ stmw r27, 0x2c(r1) -/* 801D7648 001D32A8 3B E3 08 98 */ addi r31, r3, lbl_80490898@l -/* 801D764C 001D32AC 83 7F 00 0C */ lwz r27, 0xc(r31) -/* 801D7650 001D32B0 2C 1B 00 D1 */ cmpwi r27, 0xd1 -/* 801D7654 001D32B4 41 82 00 40 */ beq lbl_801D7694 -/* 801D7658 001D32B8 2C 1B 00 D0 */ cmpwi r27, 0xd0 -/* 801D765C 001D32BC 41 82 00 38 */ beq lbl_801D7694 -/* 801D7660 001D32C0 2C 1B 00 D2 */ cmpwi r27, 0xd2 -/* 801D7664 001D32C4 41 82 00 30 */ beq lbl_801D7694 -/* 801D7668 001D32C8 2C 1B 00 D3 */ cmpwi r27, 0xd3 -/* 801D766C 001D32CC 41 82 00 28 */ beq lbl_801D7694 -/* 801D7670 001D32D0 2C 1B 00 D4 */ cmpwi r27, 0xd4 -/* 801D7674 001D32D4 41 82 00 20 */ beq lbl_801D7694 -/* 801D7678 001D32D8 38 61 00 10 */ addi r3, r1, 0x10 -/* 801D767C 001D32DC 38 80 00 04 */ li r4, 4 -/* 801D7680 001D32E0 4B FF D2 D5 */ bl TRKConstructEvent -/* 801D7684 001D32E4 38 61 00 10 */ addi r3, r1, 0x10 -/* 801D7688 001D32E8 4B FF D2 E5 */ bl TRKPostEvent -/* 801D768C 001D32EC 38 60 00 00 */ li r3, 0 -/* 801D7690 001D32F0 48 00 01 90 */ b lbl_801D7820 -lbl_801D7694: -/* 801D7694 001D32F4 2C 1B 00 D2 */ cmpwi r27, 0xd2 -/* 801D7698 001D32F8 40 82 00 50 */ bne lbl_801D76E8 -/* 801D769C 001D32FC 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D76A0 001D3300 38 C1 00 0C */ addi r6, r1, 0xc -/* 801D76A4 001D3304 38 83 08 98 */ addi r4, r3, lbl_80490898@l -/* 801D76A8 001D3308 80 04 00 14 */ lwz r0, 0x14(r4) -/* 801D76AC 001D330C 80 64 00 10 */ lwz r3, 0x10(r4) -/* 801D76B0 001D3310 80 A4 00 18 */ lwz r5, 0x18(r4) -/* 801D76B4 001D3314 54 04 06 3E */ clrlwi r4, r0, 0x18 -/* 801D76B8 001D3318 4B FF F4 E1 */ bl HandleOpenFileSupportRequest -/* 801D76BC 001D331C 80 01 00 0C */ lwz r0, 0xc(r1) -/* 801D76C0 001D3320 7C 7E 1B 78 */ mr r30, r3 -/* 801D76C4 001D3324 2C 00 00 00 */ cmpwi r0, 0 -/* 801D76C8 001D3328 40 82 00 14 */ bne lbl_801D76DC -/* 801D76CC 001D332C 2C 1E 00 00 */ cmpwi r30, 0 -/* 801D76D0 001D3330 41 82 00 0C */ beq lbl_801D76DC -/* 801D76D4 001D3334 38 00 00 01 */ li r0, 1 -/* 801D76D8 001D3338 90 01 00 0C */ stw r0, 0xc(r1) -lbl_801D76DC: -/* 801D76DC 001D333C 80 01 00 0C */ lwz r0, 0xc(r1) -/* 801D76E0 001D3340 90 1F 00 0C */ stw r0, 0xc(r31) -/* 801D76E4 001D3344 48 00 01 24 */ b lbl_801D7808 -lbl_801D76E8: -/* 801D76E8 001D3348 2C 1B 00 D3 */ cmpwi r27, 0xd3 -/* 801D76EC 001D334C 40 82 00 44 */ bne lbl_801D7730 -/* 801D76F0 001D3350 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D76F4 001D3354 38 81 00 0C */ addi r4, r1, 0xc -/* 801D76F8 001D3358 38 63 08 98 */ addi r3, r3, lbl_80490898@l -/* 801D76FC 001D335C 80 63 00 10 */ lwz r3, 0x10(r3) -/* 801D7700 001D3360 4B FF F3 B1 */ bl HandleCloseFileSupportRequest -/* 801D7704 001D3364 80 01 00 0C */ lwz r0, 0xc(r1) -/* 801D7708 001D3368 7C 7E 1B 78 */ mr r30, r3 -/* 801D770C 001D336C 2C 00 00 00 */ cmpwi r0, 0 -/* 801D7710 001D3370 40 82 00 14 */ bne lbl_801D7724 -/* 801D7714 001D3374 2C 1E 00 00 */ cmpwi r30, 0 -/* 801D7718 001D3378 41 82 00 0C */ beq lbl_801D7724 -/* 801D771C 001D337C 38 00 00 01 */ li r0, 1 -/* 801D7720 001D3380 90 01 00 0C */ stw r0, 0xc(r1) -lbl_801D7724: -/* 801D7724 001D3384 80 01 00 0C */ lwz r0, 0xc(r1) -/* 801D7728 001D3388 90 1F 00 0C */ stw r0, 0xc(r31) -/* 801D772C 001D338C 48 00 00 DC */ b lbl_801D7808 -lbl_801D7730: -/* 801D7730 001D3390 2C 1B 00 D4 */ cmpwi r27, 0xd4 -/* 801D7734 001D3394 40 82 00 68 */ bne lbl_801D779C -/* 801D7738 001D3398 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D773C 001D339C 38 81 00 08 */ addi r4, r1, 8 -/* 801D7740 001D33A0 3B A3 08 98 */ addi r29, r3, lbl_80490898@l -/* 801D7744 001D33A4 38 C1 00 0C */ addi r6, r1, 0xc -/* 801D7748 001D33A8 80 7D 00 14 */ lwz r3, 0x14(r29) -/* 801D774C 001D33AC 80 1D 00 18 */ lwz r0, 0x18(r29) -/* 801D7750 001D33B0 80 E3 00 00 */ lwz r7, 0(r3) -/* 801D7754 001D33B4 80 7D 00 10 */ lwz r3, 0x10(r29) -/* 801D7758 001D33B8 54 05 06 3E */ clrlwi r5, r0, 0x18 -/* 801D775C 001D33BC 90 E1 00 08 */ stw r7, 8(r1) -/* 801D7760 001D33C0 4B FF F2 41 */ bl HandlePositionFileSupportRequest -/* 801D7764 001D33C4 80 01 00 0C */ lwz r0, 0xc(r1) -/* 801D7768 001D33C8 7C 7E 1B 78 */ mr r30, r3 -/* 801D776C 001D33CC 2C 00 00 00 */ cmpwi r0, 0 -/* 801D7770 001D33D0 40 82 00 14 */ bne lbl_801D7784 -/* 801D7774 001D33D4 2C 1E 00 00 */ cmpwi r30, 0 -/* 801D7778 001D33D8 41 82 00 0C */ beq lbl_801D7784 -/* 801D777C 001D33DC 38 00 00 01 */ li r0, 1 -/* 801D7780 001D33E0 90 01 00 0C */ stw r0, 0xc(r1) -lbl_801D7784: -/* 801D7784 001D33E4 80 61 00 0C */ lwz r3, 0xc(r1) -/* 801D7788 001D33E8 80 01 00 08 */ lwz r0, 8(r1) -/* 801D778C 001D33EC 90 7F 00 0C */ stw r3, 0xc(r31) -/* 801D7790 001D33F0 80 7D 00 14 */ lwz r3, 0x14(r29) -/* 801D7794 001D33F4 90 03 00 00 */ stw r0, 0(r3) -/* 801D7798 001D33F8 48 00 00 70 */ b lbl_801D7808 -lbl_801D779C: -/* 801D779C 001D33FC 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D77A0 001D3400 20 1B 00 D1 */ subfic r0, r27, 0xd1 -/* 801D77A4 001D3404 3B A3 08 98 */ addi r29, r3, lbl_80490898@l -/* 801D77A8 001D3408 38 C1 00 0C */ addi r6, r1, 0xc -/* 801D77AC 001D340C 83 9D 00 14 */ lwz r28, 0x14(r29) -/* 801D77B0 001D3410 7C 00 00 34 */ cntlzw r0, r0 -/* 801D77B4 001D3414 80 7D 00 10 */ lwz r3, 0x10(r29) -/* 801D77B8 001D3418 54 08 D9 7E */ srwi r8, r0, 5 -/* 801D77BC 001D341C 80 9D 00 18 */ lwz r4, 0x18(r29) -/* 801D77C0 001D3420 7F 85 E3 78 */ mr r5, r28 -/* 801D77C4 001D3424 38 E0 00 01 */ li r7, 1 -/* 801D77C8 001D3428 4B FF F6 6D */ bl TRKSuppAccessFile -/* 801D77CC 001D342C 80 01 00 0C */ lwz r0, 0xc(r1) -/* 801D77D0 001D3430 7C 7E 1B 78 */ mr r30, r3 -/* 801D77D4 001D3434 2C 00 00 00 */ cmpwi r0, 0 -/* 801D77D8 001D3438 40 82 00 14 */ bne lbl_801D77EC -/* 801D77DC 001D343C 2C 1E 00 00 */ cmpwi r30, 0 -/* 801D77E0 001D3440 41 82 00 0C */ beq lbl_801D77EC -/* 801D77E4 001D3444 38 00 00 01 */ li r0, 1 -/* 801D77E8 001D3448 90 01 00 0C */ stw r0, 0xc(r1) -lbl_801D77EC: -/* 801D77EC 001D344C 80 01 00 0C */ lwz r0, 0xc(r1) -/* 801D77F0 001D3450 2C 1B 00 D1 */ cmpwi r27, 0xd1 -/* 801D77F4 001D3454 90 1F 00 0C */ stw r0, 0xc(r31) -/* 801D77F8 001D3458 40 82 00 10 */ bne lbl_801D7808 -/* 801D77FC 001D345C 80 7D 00 18 */ lwz r3, 0x18(r29) -/* 801D7800 001D3460 80 9C 00 00 */ lwz r4, 0(r28) -/* 801D7804 001D3464 4B FF F9 01 */ bl TRK_flush_cache -lbl_801D7808: -/* 801D7808 001D3468 3C 80 80 49 */ lis r4, lbl_80490898@ha -/* 801D780C 001D346C 7F C3 F3 78 */ mr r3, r30 -/* 801D7810 001D3470 38 A4 08 98 */ addi r5, r4, lbl_80490898@l -/* 801D7814 001D3474 80 85 00 80 */ lwz r4, 0x80(r5) -/* 801D7818 001D3478 38 04 00 04 */ addi r0, r4, 4 -/* 801D781C 001D347C 90 05 00 80 */ stw r0, 0x80(r5) -lbl_801D7820: -/* 801D7820 001D3480 BB 61 00 2C */ lmw r27, 0x2c(r1) -/* 801D7824 001D3484 80 01 00 44 */ lwz r0, 0x44(r1) -/* 801D7828 001D3488 7C 08 03 A6 */ mtlr r0 -/* 801D782C 001D348C 38 21 00 40 */ addi r1, r1, 0x40 -/* 801D7830 001D3490 4E 80 00 20 */ blr - -.global func_801D7834 -func_801D7834: -/* 801D7834 001D3494 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D7838 001D3498 38 63 08 98 */ addi r3, r3, lbl_80490898@l -/* 801D783C 001D349C 80 63 00 80 */ lwz r3, 0x80(r3) -/* 801D7840 001D34A0 4E 80 00 20 */ blr - -.global func_801D7844 -func_801D7844: -/* 801D7844 001D34A4 2C 05 00 00 */ cmpwi r5, 0 -/* 801D7848 001D34A8 41 82 00 0C */ beq lbl_801D7854 -/* 801D784C 001D34AC 38 60 07 03 */ li r3, 0x703 -/* 801D7850 001D34B0 4E 80 00 20 */ blr -lbl_801D7854: -/* 801D7854 001D34B4 3C A0 80 49 */ lis r5, lbl_80490898@ha -/* 801D7858 001D34B8 38 E0 00 01 */ li r7, 1 -/* 801D785C 001D34BC 38 A5 08 98 */ addi r5, r5, lbl_80490898@l -/* 801D7860 001D34C0 3C C0 80 42 */ lis r6, lbl_8042324C@ha -/* 801D7864 001D34C4 80 05 01 F8 */ lwz r0, 0x1f8(r5) -/* 801D7868 001D34C8 38 C6 32 4C */ addi r6, r6, lbl_8042324C@l -/* 801D786C 001D34CC 2C 07 00 00 */ cmpwi r7, 0 -/* 801D7870 001D34D0 90 E6 00 04 */ stw r7, 4(r6) -/* 801D7874 001D34D4 60 00 04 00 */ ori r0, r0, 0x400 -/* 801D7878 001D34D8 90 66 00 0C */ stw r3, 0xc(r6) -/* 801D787C 001D34DC 90 86 00 10 */ stw r4, 0x10(r6) -/* 801D7880 001D34E0 90 E6 00 00 */ stw r7, 0(r6) -/* 801D7884 001D34E4 90 05 01 F8 */ stw r0, 0x1f8(r5) -/* 801D7888 001D34E8 41 82 00 0C */ beq lbl_801D7894 -/* 801D788C 001D34EC 2C 07 00 10 */ cmpwi r7, 0x10 -/* 801D7890 001D34F0 40 82 00 18 */ bne lbl_801D78A8 -lbl_801D7894: -/* 801D7894 001D34F4 3C 60 80 42 */ lis r3, lbl_8042324C@ha -/* 801D7898 001D34F8 38 83 32 4C */ addi r4, r3, lbl_8042324C@l -/* 801D789C 001D34FC 80 64 00 08 */ lwz r3, 8(r4) -/* 801D78A0 001D3500 38 03 FF FF */ addi r0, r3, -1 -/* 801D78A4 001D3504 90 04 00 08 */ stw r0, 8(r4) -lbl_801D78A8: -/* 801D78A8 001D3508 3C 60 80 49 */ lis r3, lbl_804907F4@ha -/* 801D78AC 001D350C 38 00 00 00 */ li r0, 0 -/* 801D78B0 001D3510 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l -/* 801D78B4 001D3514 38 60 00 00 */ li r3, 0 -/* 801D78B8 001D3518 90 04 00 98 */ stw r0, 0x98(r4) -/* 801D78BC 001D351C 4E 80 00 20 */ blr - -.global func_801D78C0 -func_801D78C0: -/* 801D78C0 001D3520 2C 04 00 00 */ cmpwi r4, 0 -/* 801D78C4 001D3524 41 82 00 0C */ beq lbl_801D78D0 -/* 801D78C8 001D3528 38 60 07 03 */ li r3, 0x703 -/* 801D78CC 001D352C 4E 80 00 20 */ blr -lbl_801D78D0: -/* 801D78D0 001D3530 3C 80 80 49 */ lis r4, lbl_80490898@ha -/* 801D78D4 001D3534 3C A0 80 42 */ lis r5, lbl_8042324C@ha -/* 801D78D8 001D3538 38 84 08 98 */ addi r4, r4, lbl_80490898@l -/* 801D78DC 001D353C 38 E0 00 00 */ li r7, 0 -/* 801D78E0 001D3540 80 04 01 F8 */ lwz r0, 0x1f8(r4) -/* 801D78E4 001D3544 38 C5 32 4C */ addi r6, r5, lbl_8042324C@l -/* 801D78E8 001D3548 38 A0 00 01 */ li r5, 1 -/* 801D78EC 001D354C 90 E6 00 04 */ stw r7, 4(r6) -/* 801D78F0 001D3550 60 00 04 00 */ ori r0, r0, 0x400 -/* 801D78F4 001D3554 90 66 00 08 */ stw r3, 8(r6) -/* 801D78F8 001D3558 90 A6 00 00 */ stw r5, 0(r6) -/* 801D78FC 001D355C 90 04 01 F8 */ stw r0, 0x1f8(r4) -/* 801D7900 001D3560 48 00 00 08 */ b lbl_801D7908 -/* 801D7904 001D3564 40 82 00 10 */ bne lbl_801D7914 -lbl_801D7908: -/* 801D7908 001D3568 80 66 00 08 */ lwz r3, 8(r6) -/* 801D790C 001D356C 38 03 FF FF */ addi r0, r3, -1 -/* 801D7910 001D3570 90 06 00 08 */ stw r0, 8(r6) -lbl_801D7914: -/* 801D7914 001D3574 3C 60 80 49 */ lis r3, lbl_804907F4@ha -/* 801D7918 001D3578 38 00 00 00 */ li r0, 0 -/* 801D791C 001D357C 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l -/* 801D7920 001D3580 38 60 00 00 */ li r3, 0 -/* 801D7924 001D3584 90 04 00 98 */ stw r0, 0x98(r4) -/* 801D7928 001D3588 4E 80 00 20 */ blr - -.global TRKTargetAddExceptionInfo -TRKTargetAddExceptionInfo: -/* 801D792C 001D358C 94 21 FF A0 */ stwu r1, -0x60(r1) -/* 801D7930 001D3590 7C 08 02 A6 */ mflr r0 -/* 801D7934 001D3594 38 80 00 00 */ li r4, 0 -/* 801D7938 001D3598 38 A0 00 40 */ li r5, 0x40 -/* 801D793C 001D359C 90 01 00 64 */ stw r0, 0x64(r1) -/* 801D7940 001D35A0 93 E1 00 5C */ stw r31, 0x5c(r1) -/* 801D7944 001D35A4 7C 7F 1B 78 */ mr r31, r3 -/* 801D7948 001D35A8 38 61 00 0C */ addi r3, r1, 0xc -/* 801D794C 001D35AC 4B E2 C7 E9 */ bl TRK_memset -/* 801D7950 001D35B0 3C 60 80 42 */ lis r3, lbl_8042323C@ha -/* 801D7954 001D35B4 38 A0 00 40 */ li r5, 0x40 -/* 801D7958 001D35B8 80 83 32 3C */ lwz r4, lbl_8042323C@l(r3) -/* 801D795C 001D35BC 38 00 00 91 */ li r0, 0x91 -/* 801D7960 001D35C0 90 A1 00 0C */ stw r5, 0xc(r1) -/* 801D7964 001D35C4 38 61 00 08 */ addi r3, r1, 8 -/* 801D7968 001D35C8 98 01 00 10 */ stb r0, 0x10(r1) -/* 801D796C 001D35CC 90 81 00 14 */ stw r4, 0x14(r1) -/* 801D7970 001D35D0 48 00 0E 7D */ bl TRKTargetReadInstruction -/* 801D7974 001D35D4 3C 60 80 42 */ lis r3, lbl_8042323C@ha -/* 801D7978 001D35D8 80 A1 00 08 */ lwz r5, 8(r1) -/* 801D797C 001D35DC 38 83 32 3C */ addi r4, r3, lbl_8042323C@l -/* 801D7980 001D35E0 7F E3 FB 78 */ mr r3, r31 -/* 801D7984 001D35E4 A0 04 00 08 */ lhz r0, 8(r4) -/* 801D7988 001D35E8 38 81 00 0C */ addi r4, r1, 0xc -/* 801D798C 001D35EC 90 A1 00 18 */ stw r5, 0x18(r1) -/* 801D7990 001D35F0 38 A0 00 40 */ li r5, 0x40 -/* 801D7994 001D35F4 90 01 00 1C */ stw r0, 0x1c(r1) -/* 801D7998 001D35F8 4B FF D6 DD */ bl TRKAppendBuffer_ui8 -/* 801D799C 001D35FC 80 01 00 64 */ lwz r0, 0x64(r1) -/* 801D79A0 001D3600 83 E1 00 5C */ lwz r31, 0x5c(r1) -/* 801D79A4 001D3604 7C 08 03 A6 */ mtlr r0 -/* 801D79A8 001D3608 38 21 00 60 */ addi r1, r1, 0x60 -/* 801D79AC 001D360C 4E 80 00 20 */ blr - -.global TRKTargetAddStopInfo -TRKTargetAddStopInfo: -/* 801D79B0 001D3610 94 21 FF A0 */ stwu r1, -0x60(r1) -/* 801D79B4 001D3614 7C 08 02 A6 */ mflr r0 -/* 801D79B8 001D3618 38 80 00 00 */ li r4, 0 -/* 801D79BC 001D361C 38 A0 00 40 */ li r5, 0x40 -/* 801D79C0 001D3620 90 01 00 64 */ stw r0, 0x64(r1) -/* 801D79C4 001D3624 93 E1 00 5C */ stw r31, 0x5c(r1) -/* 801D79C8 001D3628 7C 7F 1B 78 */ mr r31, r3 -/* 801D79CC 001D362C 38 61 00 0C */ addi r3, r1, 0xc -/* 801D79D0 001D3630 4B E2 C7 65 */ bl TRK_memset -/* 801D79D4 001D3634 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D79D8 001D3638 38 A0 00 40 */ li r5, 0x40 -/* 801D79DC 001D363C 38 63 08 98 */ addi r3, r3, lbl_80490898@l -/* 801D79E0 001D3640 38 00 00 90 */ li r0, 0x90 -/* 801D79E4 001D3644 80 83 00 80 */ lwz r4, 0x80(r3) -/* 801D79E8 001D3648 38 61 00 08 */ addi r3, r1, 8 -/* 801D79EC 001D364C 90 A1 00 0C */ stw r5, 0xc(r1) -/* 801D79F0 001D3650 98 01 00 10 */ stb r0, 0x10(r1) -/* 801D79F4 001D3654 90 81 00 14 */ stw r4, 0x14(r1) -/* 801D79F8 001D3658 48 00 0D F5 */ bl TRKTargetReadInstruction -/* 801D79FC 001D365C 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D7A00 001D3660 80 A1 00 08 */ lwz r5, 8(r1) -/* 801D7A04 001D3664 38 83 08 98 */ addi r4, r3, lbl_80490898@l -/* 801D7A08 001D3668 7F E3 FB 78 */ mr r3, r31 -/* 801D7A0C 001D366C 80 04 02 F8 */ lwz r0, 0x2f8(r4) -/* 801D7A10 001D3670 38 81 00 0C */ addi r4, r1, 0xc -/* 801D7A14 001D3674 90 A1 00 18 */ stw r5, 0x18(r1) -/* 801D7A18 001D3678 38 A0 00 40 */ li r5, 0x40 -/* 801D7A1C 001D367C 54 00 04 3E */ clrlwi r0, r0, 0x10 -/* 801D7A20 001D3680 90 01 00 1C */ stw r0, 0x1c(r1) -/* 801D7A24 001D3684 4B FF D6 51 */ bl TRKAppendBuffer_ui8 -/* 801D7A28 001D3688 80 01 00 64 */ lwz r0, 0x64(r1) -/* 801D7A2C 001D368C 83 E1 00 5C */ lwz r31, 0x5c(r1) -/* 801D7A30 001D3690 7C 08 03 A6 */ mtlr r0 -/* 801D7A34 001D3694 38 21 00 60 */ addi r1, r1, 0x60 -/* 801D7A38 001D3698 4E 80 00 20 */ blr - -.global func_801D7A3C -func_801D7A3C: -/* 801D7A3C 001D369C 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D7A40 001D36A0 7C 08 02 A6 */ mflr r0 -/* 801D7A44 001D36A4 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D7A48 001D36A8 80 03 00 00 */ lwz r0, 0(r3) -/* 801D7A4C 001D36AC 38 60 00 00 */ li r3, 0 -/* 801D7A50 001D36B0 2C 00 00 05 */ cmpwi r0, 5 -/* 801D7A54 001D36B4 40 80 01 34 */ bge lbl_801D7B88 -/* 801D7A58 001D36B8 2C 00 00 03 */ cmpwi r0, 3 -/* 801D7A5C 001D36BC 40 80 00 08 */ bge lbl_801D7A64 -/* 801D7A60 001D36C0 48 00 01 28 */ b lbl_801D7B88 -lbl_801D7A64: -/* 801D7A64 001D36C4 3C 80 80 42 */ lis r4, lbl_8042324C@ha -/* 801D7A68 001D36C8 38 A4 32 4C */ addi r5, r4, lbl_8042324C@l -/* 801D7A6C 001D36CC 80 05 00 00 */ lwz r0, 0(r5) -/* 801D7A70 001D36D0 2C 00 00 00 */ cmpwi r0, 0 -/* 801D7A74 001D36D4 41 82 00 EC */ beq lbl_801D7B60 -/* 801D7A78 001D36D8 3C 80 80 49 */ lis r4, lbl_80490898@ha -/* 801D7A7C 001D36DC 38 E0 00 01 */ li r7, 1 -/* 801D7A80 001D36E0 38 C4 08 98 */ addi r6, r4, lbl_80490898@l -/* 801D7A84 001D36E4 80 06 01 F8 */ lwz r0, 0x1f8(r6) -/* 801D7A88 001D36E8 54 00 05 A8 */ rlwinm r0, r0, 0, 0x16, 0x14 -/* 801D7A8C 001D36EC 90 06 01 F8 */ stw r0, 0x1f8(r6) -/* 801D7A90 001D36F0 41 82 00 64 */ beq lbl_801D7AF4 -/* 801D7A94 001D36F4 80 06 02 F8 */ lwz r0, 0x2f8(r6) -/* 801D7A98 001D36F8 54 00 04 3E */ clrlwi r0, r0, 0x10 -/* 801D7A9C 001D36FC 28 00 0D 00 */ cmplwi r0, 0xd00 -/* 801D7AA0 001D3700 40 82 00 54 */ bne lbl_801D7AF4 -/* 801D7AA4 001D3704 80 05 00 04 */ lwz r0, 4(r5) -/* 801D7AA8 001D3708 2C 00 00 01 */ cmpwi r0, 1 -/* 801D7AAC 001D370C 41 82 00 28 */ beq lbl_801D7AD4 -/* 801D7AB0 001D3710 40 80 00 44 */ bge lbl_801D7AF4 -/* 801D7AB4 001D3714 2C 00 00 00 */ cmpwi r0, 0 -/* 801D7AB8 001D3718 40 80 00 08 */ bge lbl_801D7AC0 -/* 801D7ABC 001D371C 48 00 00 38 */ b lbl_801D7AF4 -lbl_801D7AC0: -/* 801D7AC0 001D3720 80 05 00 08 */ lwz r0, 8(r5) -/* 801D7AC4 001D3724 28 00 00 00 */ cmplwi r0, 0 -/* 801D7AC8 001D3728 41 82 00 2C */ beq lbl_801D7AF4 -/* 801D7ACC 001D372C 38 E0 00 00 */ li r7, 0 -/* 801D7AD0 001D3730 48 00 00 24 */ b lbl_801D7AF4 -lbl_801D7AD4: -/* 801D7AD4 001D3734 80 86 00 80 */ lwz r4, 0x80(r6) -/* 801D7AD8 001D3738 80 05 00 0C */ lwz r0, 0xc(r5) -/* 801D7ADC 001D373C 7C 04 00 40 */ cmplw r4, r0 -/* 801D7AE0 001D3740 41 80 00 14 */ blt lbl_801D7AF4 -/* 801D7AE4 001D3744 80 05 00 10 */ lwz r0, 0x10(r5) -/* 801D7AE8 001D3748 7C 04 00 40 */ cmplw r4, r0 -/* 801D7AEC 001D374C 41 81 00 08 */ bgt lbl_801D7AF4 -/* 801D7AF0 001D3750 38 E0 00 00 */ li r7, 0 -lbl_801D7AF4: -/* 801D7AF4 001D3754 2C 07 00 00 */ cmpwi r7, 0 -/* 801D7AF8 001D3758 41 82 00 14 */ beq lbl_801D7B0C -/* 801D7AFC 001D375C 3C 80 80 42 */ lis r4, lbl_8042324C@ha -/* 801D7B00 001D3760 38 00 00 00 */ li r0, 0 -/* 801D7B04 001D3764 90 04 32 4C */ stw r0, lbl_8042324C@l(r4) -/* 801D7B08 001D3768 48 00 00 58 */ b lbl_801D7B60 -lbl_801D7B0C: -/* 801D7B0C 001D376C 3C 80 80 42 */ lis r4, lbl_8042324C@ha -/* 801D7B10 001D3770 80 06 01 F8 */ lwz r0, 0x1f8(r6) -/* 801D7B14 001D3774 38 84 32 4C */ addi r4, r4, lbl_8042324C@l -/* 801D7B18 001D3778 38 A0 00 01 */ li r5, 1 -/* 801D7B1C 001D377C 80 E4 00 04 */ lwz r7, 4(r4) -/* 801D7B20 001D3780 60 00 04 00 */ ori r0, r0, 0x400 -/* 801D7B24 001D3784 90 A4 00 00 */ stw r5, 0(r4) -/* 801D7B28 001D3788 2C 07 00 00 */ cmpwi r7, 0 -/* 801D7B2C 001D378C 90 06 01 F8 */ stw r0, 0x1f8(r6) -/* 801D7B30 001D3790 41 82 00 0C */ beq lbl_801D7B3C -/* 801D7B34 001D3794 2C 07 00 10 */ cmpwi r7, 0x10 -/* 801D7B38 001D3798 40 82 00 18 */ bne lbl_801D7B50 -lbl_801D7B3C: -/* 801D7B3C 001D379C 3C 80 80 42 */ lis r4, lbl_8042324C@ha -/* 801D7B40 001D37A0 38 A4 32 4C */ addi r5, r4, lbl_8042324C@l -/* 801D7B44 001D37A4 80 85 00 08 */ lwz r4, 8(r5) -/* 801D7B48 001D37A8 38 04 FF FF */ addi r0, r4, -1 -/* 801D7B4C 001D37AC 90 05 00 08 */ stw r0, 8(r5) -lbl_801D7B50: -/* 801D7B50 001D37B0 3C 80 80 49 */ lis r4, lbl_804907F4@ha -/* 801D7B54 001D37B4 38 00 00 00 */ li r0, 0 -/* 801D7B58 001D37B8 38 84 07 F4 */ addi r4, r4, lbl_804907F4@l -/* 801D7B5C 001D37BC 90 04 00 98 */ stw r0, 0x98(r4) -lbl_801D7B60: -/* 801D7B60 001D37C0 3C 80 80 42 */ lis r4, lbl_8042324C@ha -/* 801D7B64 001D37C4 80 04 32 4C */ lwz r0, lbl_8042324C@l(r4) -/* 801D7B68 001D37C8 2C 00 00 00 */ cmpwi r0, 0 -/* 801D7B6C 001D37CC 40 82 00 1C */ bne lbl_801D7B88 -/* 801D7B70 001D37D0 3C 60 80 49 */ lis r3, lbl_804907F4@ha -/* 801D7B74 001D37D4 38 00 00 01 */ li r0, 1 -/* 801D7B78 001D37D8 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l -/* 801D7B7C 001D37DC 38 60 00 90 */ li r3, 0x90 -/* 801D7B80 001D37E0 90 04 00 98 */ stw r0, 0x98(r4) -/* 801D7B84 001D37E4 4B FF F4 E9 */ bl TRKDoNotifyStopped -lbl_801D7B88: -/* 801D7B88 001D37E8 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D7B8C 001D37EC 7C 08 03 A6 */ mtlr r0 -/* 801D7B90 001D37F0 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D7B94 001D37F4 4E 80 00 20 */ blr - -.global TRKPostInterruptEvent -TRKPostInterruptEvent: -/* 801D7B98 001D37F8 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D7B9C 001D37FC 7C 08 02 A6 */ mflr r0 -/* 801D7BA0 001D3800 3C 60 80 49 */ lis r3, lbl_804907F4@ha -/* 801D7BA4 001D3804 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D7BA8 001D3808 38 63 07 F4 */ addi r3, r3, lbl_804907F4@l -/* 801D7BAC 001D380C 80 03 00 9C */ lwz r0, 0x9c(r3) -/* 801D7BB0 001D3810 2C 00 00 00 */ cmpwi r0, 0 -/* 801D7BB4 001D3814 41 82 00 10 */ beq lbl_801D7BC4 -/* 801D7BB8 001D3818 38 00 00 00 */ li r0, 0 -/* 801D7BBC 001D381C 90 03 00 9C */ stw r0, 0x9c(r3) -/* 801D7BC0 001D3820 48 00 00 74 */ b lbl_801D7C34 -lbl_801D7BC4: -/* 801D7BC4 001D3824 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D7BC8 001D3828 38 63 08 98 */ addi r3, r3, lbl_80490898@l -/* 801D7BCC 001D382C 80 03 02 F8 */ lwz r0, 0x2f8(r3) -/* 801D7BD0 001D3830 54 00 04 3E */ clrlwi r0, r0, 0x10 -/* 801D7BD4 001D3834 2C 00 0D 00 */ cmpwi r0, 0xd00 -/* 801D7BD8 001D3838 41 82 00 14 */ beq lbl_801D7BEC -/* 801D7BDC 001D383C 40 80 00 44 */ bge lbl_801D7C20 -/* 801D7BE0 001D3840 2C 00 07 00 */ cmpwi r0, 0x700 -/* 801D7BE4 001D3844 41 82 00 08 */ beq lbl_801D7BEC -/* 801D7BE8 001D3848 48 00 00 38 */ b lbl_801D7C20 -lbl_801D7BEC: -/* 801D7BEC 001D384C 3C 80 80 49 */ lis r4, lbl_80490898@ha -/* 801D7BF0 001D3850 38 61 00 08 */ addi r3, r1, 8 -/* 801D7BF4 001D3854 38 84 08 98 */ addi r4, r4, lbl_80490898@l -/* 801D7BF8 001D3858 80 84 00 80 */ lwz r4, 0x80(r4) -/* 801D7BFC 001D385C 48 00 0B F1 */ bl TRKTargetReadInstruction -/* 801D7C00 001D3860 80 61 00 08 */ lwz r3, 8(r1) -/* 801D7C04 001D3864 3C 03 F0 20 */ addis r0, r3, 0xf020 -/* 801D7C08 001D3868 28 00 00 00 */ cmplwi r0, 0 -/* 801D7C0C 001D386C 40 82 00 0C */ bne lbl_801D7C18 -/* 801D7C10 001D3870 38 80 00 05 */ li r4, 5 -/* 801D7C14 001D3874 48 00 00 10 */ b lbl_801D7C24 -lbl_801D7C18: -/* 801D7C18 001D3878 38 80 00 03 */ li r4, 3 -/* 801D7C1C 001D387C 48 00 00 08 */ b lbl_801D7C24 -lbl_801D7C20: -/* 801D7C20 001D3880 38 80 00 04 */ li r4, 4 -lbl_801D7C24: -/* 801D7C24 001D3884 38 61 00 0C */ addi r3, r1, 0xc -/* 801D7C28 001D3888 4B FF CD 2D */ bl TRKConstructEvent -/* 801D7C2C 001D388C 38 61 00 0C */ addi r3, r1, 0xc -/* 801D7C30 001D3890 4B FF CD 3D */ bl TRKPostEvent -lbl_801D7C34: -/* 801D7C34 001D3894 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D7C38 001D3898 7C 08 03 A6 */ mtlr r0 -/* 801D7C3C 001D389C 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D7C40 001D38A0 4E 80 00 20 */ blr - -.global TRKTargetAccessExtended2 -TRKTargetAccessExtended2: -/* 801D7C44 001D38A4 94 21 FE D0 */ stwu r1, -0x130(r1) -/* 801D7C48 001D38A8 7C 08 02 A6 */ mflr r0 -/* 801D7C4C 001D38AC 90 01 01 34 */ stw r0, 0x134(r1) -/* 801D7C50 001D38B0 BE 61 00 FC */ stmw r19, 0xfc(r1) -/* 801D7C54 001D38B4 7C 97 23 78 */ mr r23, r4 -/* 801D7C58 001D38B8 28 17 00 1F */ cmplwi r23, 0x1f -/* 801D7C5C 001D38BC 7C 7B 1B 78 */ mr r27, r3 -/* 801D7C60 001D38C0 7C B8 2B 78 */ mr r24, r5 -/* 801D7C64 001D38C4 7C D9 33 78 */ mr r25, r6 -/* 801D7C68 001D38C8 7C FA 3B 78 */ mr r26, r7 -/* 801D7C6C 001D38CC 40 81 00 0C */ ble lbl_801D7C78 -/* 801D7C70 001D38D0 38 60 07 01 */ li r3, 0x701 -/* 801D7C74 001D38D4 48 00 03 F4 */ b lbl_801D8068 -lbl_801D7C78: -/* 801D7C78 001D38D8 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha -/* 801D7C7C 001D38DC 3C A0 80 42 */ lis r5, lbl_8042323C@ha -/* 801D7C80 001D38E0 3B A3 D6 C8 */ addi r29, r3, lbl_803FD6C8@l -/* 801D7C84 001D38E4 3C 80 7C 99 */ lis r4, 0x7C98E2A6@ha -/* 801D7C88 001D38E8 80 1D 00 00 */ lwz r0, 0(r29) -/* 801D7C8C 001D38EC 3B E5 32 3C */ addi r31, r5, lbl_8042323C@l -/* 801D7C90 001D38F0 81 1D 00 04 */ lwz r8, 4(r29) -/* 801D7C94 001D38F4 3C 60 4E 80 */ lis r3, 0x4E800020@ha -/* 801D7C98 001D38F8 80 FD 00 24 */ lwz r7, 0x24(r29) -/* 801D7C9C 001D38FC 38 C4 E2 A6 */ addi r6, r4, 0x7C98E2A6@l -/* 801D7CA0 001D3900 90 01 00 C4 */ stw r0, 0xc4(r1) -/* 801D7CA4 001D3904 38 03 00 20 */ addi r0, r3, 0x4E800020@l -/* 801D7CA8 001D3908 82 7F 00 00 */ lwz r19, 0(r31) -/* 801D7CAC 001D390C 3B C0 00 00 */ li r30, 0 -/* 801D7CB0 001D3910 82 DF 00 0C */ lwz r22, 0xc(r31) -/* 801D7CB4 001D3914 3C A0 90 83 */ lis r5, 0x9083 -/* 801D7CB8 001D3918 91 01 00 C8 */ stw r8, 0xc8(r1) -/* 801D7CBC 001D391C 38 61 00 C4 */ addi r3, r1, 0xc4 -/* 801D7CC0 001D3920 82 9F 00 04 */ lwz r20, 4(r31) -/* 801D7CC4 001D3924 38 80 00 28 */ li r4, 0x28 -/* 801D7CC8 001D3928 90 E1 00 E8 */ stw r7, 0xe8(r1) -/* 801D7CCC 001D392C 82 BF 00 08 */ lwz r21, 8(r31) -/* 801D7CD0 001D3930 83 9D 00 08 */ lwz r28, 8(r29) -/* 801D7CD4 001D3934 81 9D 00 0C */ lwz r12, 0xc(r29) -/* 801D7CD8 001D3938 81 7D 00 10 */ lwz r11, 0x10(r29) -/* 801D7CDC 001D393C 81 5D 00 14 */ lwz r10, 0x14(r29) -/* 801D7CE0 001D3940 81 3D 00 18 */ lwz r9, 0x18(r29) -/* 801D7CE4 001D3944 81 1D 00 1C */ lwz r8, 0x1c(r29) -/* 801D7CE8 001D3948 80 FD 00 20 */ lwz r7, 0x20(r29) -/* 801D7CEC 001D394C 92 61 00 14 */ stw r19, 0x14(r1) -/* 801D7CF0 001D3950 92 81 00 18 */ stw r20, 0x18(r1) -/* 801D7CF4 001D3954 92 A1 00 1C */ stw r21, 0x1c(r1) -/* 801D7CF8 001D3958 92 C1 00 20 */ stw r22, 0x20(r1) -/* 801D7CFC 001D395C 9B DF 00 0D */ stb r30, 0xd(r31) -/* 801D7D00 001D3960 93 81 00 CC */ stw r28, 0xcc(r1) -/* 801D7D04 001D3964 91 81 00 D0 */ stw r12, 0xd0(r1) -/* 801D7D08 001D3968 91 61 00 D4 */ stw r11, 0xd4(r1) -/* 801D7D0C 001D396C 91 41 00 D8 */ stw r10, 0xd8(r1) -/* 801D7D10 001D3970 91 21 00 DC */ stw r9, 0xdc(r1) -/* 801D7D14 001D3974 91 01 00 E0 */ stw r8, 0xe0(r1) -/* 801D7D18 001D3978 90 E1 00 E4 */ stw r7, 0xe4(r1) -/* 801D7D1C 001D397C 90 C1 00 C4 */ stw r6, 0xc4(r1) -/* 801D7D20 001D3980 90 A1 00 C8 */ stw r5, 0xc8(r1) -/* 801D7D24 001D3984 90 01 00 E8 */ stw r0, 0xe8(r1) -/* 801D7D28 001D3988 4B FF F3 DD */ bl TRK_flush_cache -/* 801D7D2C 001D398C 3C 60 80 49 */ lis r3, lbl_80490D5C@ha -/* 801D7D30 001D3990 39 81 00 C4 */ addi r12, r1, 0xc4 -/* 801D7D34 001D3994 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l -/* 801D7D38 001D3998 38 61 00 08 */ addi r3, r1, 8 -/* 801D7D3C 001D399C 7D 89 03 A6 */ mtctr r12 -/* 801D7D40 001D39A0 4E 80 04 21 */ bctrl -/* 801D7D44 001D39A4 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha -/* 801D7D48 001D39A8 80 A1 00 08 */ lwz r5, 8(r1) -/* 801D7D4C 001D39AC 3B A3 D6 C8 */ addi r29, r3, lbl_803FD6C8@l -/* 801D7D50 001D39B0 3C 80 7C 99 */ lis r4, 0x7C98E3A6@ha -/* 801D7D54 001D39B4 81 1D 00 00 */ lwz r8, 0(r29) -/* 801D7D58 001D39B8 3C 60 4E 80 */ lis r3, 0x4E800020@ha -/* 801D7D5C 001D39BC 80 1D 00 04 */ lwz r0, 4(r29) -/* 801D7D60 001D39C0 64 BE A0 00 */ oris r30, r5, 0xa000 -/* 801D7D64 001D39C4 80 FD 00 24 */ lwz r7, 0x24(r29) -/* 801D7D68 001D39C8 38 A4 E3 A6 */ addi r5, r4, 0x7C98E3A6@l -/* 801D7D6C 001D39CC 90 01 00 A0 */ stw r0, 0xa0(r1) -/* 801D7D70 001D39D0 38 03 00 20 */ addi r0, r3, 0x4E800020@l -/* 801D7D74 001D39D4 83 9D 00 08 */ lwz r28, 8(r29) -/* 801D7D78 001D39D8 3C C0 80 83 */ lis r6, 0x8083 -/* 801D7D7C 001D39DC 91 01 00 9C */ stw r8, 0x9c(r1) -/* 801D7D80 001D39E0 38 61 00 9C */ addi r3, r1, 0x9c -/* 801D7D84 001D39E4 81 9D 00 0C */ lwz r12, 0xc(r29) -/* 801D7D88 001D39E8 38 80 00 28 */ li r4, 0x28 -/* 801D7D8C 001D39EC 90 E1 00 C0 */ stw r7, 0xc0(r1) -/* 801D7D90 001D39F0 81 7D 00 10 */ lwz r11, 0x10(r29) -/* 801D7D94 001D39F4 81 5D 00 14 */ lwz r10, 0x14(r29) -/* 801D7D98 001D39F8 81 3D 00 18 */ lwz r9, 0x18(r29) -/* 801D7D9C 001D39FC 81 1D 00 1C */ lwz r8, 0x1c(r29) -/* 801D7DA0 001D3A00 80 FD 00 20 */ lwz r7, 0x20(r29) -/* 801D7DA4 001D3A04 93 C1 00 08 */ stw r30, 8(r1) -/* 801D7DA8 001D3A08 93 81 00 A4 */ stw r28, 0xa4(r1) -/* 801D7DAC 001D3A0C 91 81 00 A8 */ stw r12, 0xa8(r1) -/* 801D7DB0 001D3A10 91 61 00 AC */ stw r11, 0xac(r1) -/* 801D7DB4 001D3A14 91 41 00 B0 */ stw r10, 0xb0(r1) -/* 801D7DB8 001D3A18 91 21 00 B4 */ stw r9, 0xb4(r1) -/* 801D7DBC 001D3A1C 91 01 00 B8 */ stw r8, 0xb8(r1) -/* 801D7DC0 001D3A20 90 E1 00 BC */ stw r7, 0xbc(r1) -/* 801D7DC4 001D3A24 90 C1 00 9C */ stw r6, 0x9c(r1) -/* 801D7DC8 001D3A28 90 A1 00 A0 */ stw r5, 0xa0(r1) -/* 801D7DCC 001D3A2C 90 01 00 C0 */ stw r0, 0xc0(r1) -/* 801D7DD0 001D3A30 4B FF F3 35 */ bl TRK_flush_cache -/* 801D7DD4 001D3A34 3C 60 80 49 */ lis r3, lbl_80490D5C@ha -/* 801D7DD8 001D3A38 39 81 00 9C */ addi r12, r1, 0x9c -/* 801D7DDC 001D3A3C 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l -/* 801D7DE0 001D3A40 38 61 00 08 */ addi r3, r1, 8 -/* 801D7DE4 001D3A44 7D 89 03 A6 */ mtctr r12 -/* 801D7DE8 001D3A48 4E 80 04 21 */ bctrl -/* 801D7DEC 001D3A4C 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha -/* 801D7DF0 001D3A50 3C 80 7C 91 */ lis r4, 0x7C90E3A6@ha -/* 801D7DF4 001D3A54 3B A3 D6 C8 */ addi r29, r3, lbl_803FD6C8@l -/* 801D7DF8 001D3A58 3C 60 4E 80 */ lis r3, 0x4E800020@ha -/* 801D7DFC 001D3A5C 81 1D 00 00 */ lwz r8, 0(r29) -/* 801D7E00 001D3A60 3B C0 00 00 */ li r30, 0 -/* 801D7E04 001D3A64 80 DD 00 04 */ lwz r6, 4(r29) -/* 801D7E08 001D3A68 38 A4 E3 A6 */ addi r5, r4, 0x7C90E3A6@l -/* 801D7E0C 001D3A6C 80 FD 00 24 */ lwz r7, 0x24(r29) -/* 801D7E10 001D3A70 38 03 00 20 */ addi r0, r3, 0x4E800020@l -/* 801D7E14 001D3A74 90 C1 00 78 */ stw r6, 0x78(r1) -/* 801D7E18 001D3A78 3C C0 80 83 */ lis r6, 0x8083 -/* 801D7E1C 001D3A7C 83 9D 00 08 */ lwz r28, 8(r29) -/* 801D7E20 001D3A80 38 61 00 74 */ addi r3, r1, 0x74 -/* 801D7E24 001D3A84 91 01 00 74 */ stw r8, 0x74(r1) -/* 801D7E28 001D3A88 38 80 00 28 */ li r4, 0x28 -/* 801D7E2C 001D3A8C 81 9D 00 0C */ lwz r12, 0xc(r29) -/* 801D7E30 001D3A90 90 E1 00 98 */ stw r7, 0x98(r1) -/* 801D7E34 001D3A94 81 7D 00 10 */ lwz r11, 0x10(r29) -/* 801D7E38 001D3A98 81 5D 00 14 */ lwz r10, 0x14(r29) -/* 801D7E3C 001D3A9C 81 3D 00 18 */ lwz r9, 0x18(r29) -/* 801D7E40 001D3AA0 81 1D 00 1C */ lwz r8, 0x1c(r29) -/* 801D7E44 001D3AA4 80 FD 00 20 */ lwz r7, 0x20(r29) -/* 801D7E48 001D3AA8 93 C1 00 08 */ stw r30, 8(r1) -/* 801D7E4C 001D3AAC 93 81 00 7C */ stw r28, 0x7c(r1) -/* 801D7E50 001D3AB0 91 81 00 80 */ stw r12, 0x80(r1) -/* 801D7E54 001D3AB4 91 61 00 84 */ stw r11, 0x84(r1) -/* 801D7E58 001D3AB8 91 41 00 88 */ stw r10, 0x88(r1) -/* 801D7E5C 001D3ABC 91 21 00 8C */ stw r9, 0x8c(r1) -/* 801D7E60 001D3AC0 91 01 00 90 */ stw r8, 0x90(r1) -/* 801D7E64 001D3AC4 90 E1 00 94 */ stw r7, 0x94(r1) -/* 801D7E68 001D3AC8 90 C1 00 74 */ stw r6, 0x74(r1) -/* 801D7E6C 001D3ACC 90 A1 00 78 */ stw r5, 0x78(r1) -/* 801D7E70 001D3AD0 90 01 00 98 */ stw r0, 0x98(r1) -/* 801D7E74 001D3AD4 4B FF F2 91 */ bl TRK_flush_cache -/* 801D7E78 001D3AD8 3C 60 80 49 */ lis r3, lbl_80490D5C@ha -/* 801D7E7C 001D3ADC 39 81 00 74 */ addi r12, r1, 0x74 -/* 801D7E80 001D3AE0 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l -/* 801D7E84 001D3AE4 38 61 00 08 */ addi r3, r1, 8 -/* 801D7E88 001D3AE8 7D 89 03 A6 */ mtctr r12 -/* 801D7E8C 001D3AEC 4E 80 04 21 */ bctrl -/* 801D7E90 001D3AF0 38 00 00 00 */ li r0, 0 -/* 801D7E94 001D3AF4 57 7E A8 14 */ slwi r30, r27, 0x15 -/* 801D7E98 001D3AF8 90 19 00 00 */ stw r0, 0(r25) -/* 801D7E9C 001D3AFC 3B A1 00 4C */ addi r29, r1, 0x4c -/* 801D7EA0 001D3B00 3B 81 00 24 */ addi r28, r1, 0x24 -/* 801D7EA4 001D3B04 38 60 00 00 */ li r3, 0 -/* 801D7EA8 001D3B08 48 00 01 70 */ b lbl_801D8018 -lbl_801D7EAC: -/* 801D7EAC 001D3B0C 2C 1A 00 00 */ cmpwi r26, 0 -/* 801D7EB0 001D3B10 41 82 00 AC */ beq lbl_801D7F5C -/* 801D7EB4 001D3B14 3C 60 80 40 */ lis r3, lbl_80400004@ha -/* 801D7EB8 001D3B18 85 83 D6 F0 */ lwzu r12, -0x2910(r3) -/* 801D7EBC 001D3B1C 67 C0 E0 03 */ oris r0, r30, 0xe003 -/* 801D7EC0 001D3B20 81 63 00 04 */ lwz r11, lbl_80400004@l(r3) -/* 801D7EC4 001D3B24 81 43 00 08 */ lwz r10, 8(r3) -/* 801D7EC8 001D3B28 81 23 00 0C */ lwz r9, 0xc(r3) -/* 801D7ECC 001D3B2C 81 03 00 10 */ lwz r8, 0x10(r3) -/* 801D7ED0 001D3B30 80 E3 00 14 */ lwz r7, 0x14(r3) -/* 801D7ED4 001D3B34 80 C3 00 18 */ lwz r6, 0x18(r3) -/* 801D7ED8 001D3B38 80 A3 00 1C */ lwz r5, 0x1c(r3) -/* 801D7EDC 001D3B3C 80 83 00 20 */ lwz r4, 0x20(r3) -/* 801D7EE0 001D3B40 80 63 00 24 */ lwz r3, 0x24(r3) -/* 801D7EE4 001D3B44 91 81 00 4C */ stw r12, 0x4c(r1) -/* 801D7EE8 001D3B48 91 61 00 50 */ stw r11, 0x50(r1) -/* 801D7EEC 001D3B4C 91 41 00 54 */ stw r10, 0x54(r1) -/* 801D7EF0 001D3B50 91 21 00 58 */ stw r9, 0x58(r1) -/* 801D7EF4 001D3B54 91 01 00 5C */ stw r8, 0x5c(r1) -/* 801D7EF8 001D3B58 90 E1 00 60 */ stw r7, 0x60(r1) -/* 801D7EFC 001D3B5C 90 C1 00 64 */ stw r6, 0x64(r1) -/* 801D7F00 001D3B60 90 A1 00 68 */ stw r5, 0x68(r1) -/* 801D7F04 001D3B64 90 81 00 6C */ stw r4, 0x6c(r1) -/* 801D7F08 001D3B68 90 61 00 70 */ stw r3, 0x70(r1) -/* 801D7F0C 001D3B6C 41 82 00 08 */ beq lbl_801D7F14 -/* 801D7F10 001D3B70 67 C0 F0 03 */ oris r0, r30, 0xf003 -lbl_801D7F14: -/* 801D7F14 001D3B74 3C 60 4E 80 */ lis r3, 0x4E800020@ha -/* 801D7F18 001D3B78 90 01 00 4C */ stw r0, 0x4c(r1) -/* 801D7F1C 001D3B7C 38 03 00 20 */ addi r0, r3, 0x4E800020@l -/* 801D7F20 001D3B80 7F A3 EB 78 */ mr r3, r29 -/* 801D7F24 001D3B84 90 01 00 70 */ stw r0, 0x70(r1) -/* 801D7F28 001D3B88 38 80 00 28 */ li r4, 0x28 -/* 801D7F2C 001D3B8C 4B FF F1 D9 */ bl TRK_flush_cache -/* 801D7F30 001D3B90 3C 60 80 49 */ lis r3, lbl_80490D5C@ha -/* 801D7F34 001D3B94 39 81 00 4C */ addi r12, r1, 0x4c -/* 801D7F38 001D3B98 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l -/* 801D7F3C 001D3B9C 38 61 00 0C */ addi r3, r1, 0xc -/* 801D7F40 001D3BA0 7D 89 03 A6 */ mtctr r12 -/* 801D7F44 001D3BA4 4E 80 04 21 */ bctrl -/* 801D7F48 001D3BA8 80 A1 00 0C */ lwz r5, 0xc(r1) -/* 801D7F4C 001D3BAC 7F 03 C3 78 */ mr r3, r24 -/* 801D7F50 001D3BB0 80 C1 00 10 */ lwz r6, 0x10(r1) -/* 801D7F54 001D3BB4 4B FF D1 89 */ bl TRKAppendBuffer1_ui64 -/* 801D7F58 001D3BB8 48 00 00 AC */ b lbl_801D8004 -lbl_801D7F5C: -/* 801D7F5C 001D3BBC 7F 03 C3 78 */ mr r3, r24 -/* 801D7F60 001D3BC0 38 81 00 0C */ addi r4, r1, 0xc -/* 801D7F64 001D3BC4 4B FF CF 2D */ bl TRKReadBuffer1_ui64 -/* 801D7F68 001D3BC8 3C 60 80 40 */ lis r3, lbl_80400004@ha -/* 801D7F6C 001D3BCC 85 83 D6 F0 */ lwzu r12, -0x2910(r3) -/* 801D7F70 001D3BD0 2C 1A 00 00 */ cmpwi r26, 0 -/* 801D7F74 001D3BD4 67 C0 E0 03 */ oris r0, r30, 0xe003 -/* 801D7F78 001D3BD8 81 63 00 04 */ lwz r11, lbl_80400004@l(r3) -/* 801D7F7C 001D3BDC 81 43 00 08 */ lwz r10, 8(r3) -/* 801D7F80 001D3BE0 81 23 00 0C */ lwz r9, 0xc(r3) -/* 801D7F84 001D3BE4 81 03 00 10 */ lwz r8, 0x10(r3) -/* 801D7F88 001D3BE8 80 E3 00 14 */ lwz r7, 0x14(r3) -/* 801D7F8C 001D3BEC 80 C3 00 18 */ lwz r6, 0x18(r3) -/* 801D7F90 001D3BF0 80 A3 00 1C */ lwz r5, 0x1c(r3) -/* 801D7F94 001D3BF4 80 83 00 20 */ lwz r4, 0x20(r3) -/* 801D7F98 001D3BF8 80 63 00 24 */ lwz r3, 0x24(r3) -/* 801D7F9C 001D3BFC 91 81 00 24 */ stw r12, 0x24(r1) -/* 801D7FA0 001D3C00 91 61 00 28 */ stw r11, 0x28(r1) -/* 801D7FA4 001D3C04 91 41 00 2C */ stw r10, 0x2c(r1) -/* 801D7FA8 001D3C08 91 21 00 30 */ stw r9, 0x30(r1) -/* 801D7FAC 001D3C0C 91 01 00 34 */ stw r8, 0x34(r1) -/* 801D7FB0 001D3C10 90 E1 00 38 */ stw r7, 0x38(r1) -/* 801D7FB4 001D3C14 90 C1 00 3C */ stw r6, 0x3c(r1) -/* 801D7FB8 001D3C18 90 A1 00 40 */ stw r5, 0x40(r1) -/* 801D7FBC 001D3C1C 90 81 00 44 */ stw r4, 0x44(r1) -/* 801D7FC0 001D3C20 90 61 00 48 */ stw r3, 0x48(r1) -/* 801D7FC4 001D3C24 41 82 00 08 */ beq lbl_801D7FCC -/* 801D7FC8 001D3C28 67 C0 F0 03 */ oris r0, r30, 0xf003 -lbl_801D7FCC: -/* 801D7FCC 001D3C2C 3C 60 4E 80 */ lis r3, 0x4E800020@ha -/* 801D7FD0 001D3C30 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D7FD4 001D3C34 38 03 00 20 */ addi r0, r3, 0x4E800020@l -/* 801D7FD8 001D3C38 7F 83 E3 78 */ mr r3, r28 -/* 801D7FDC 001D3C3C 90 01 00 48 */ stw r0, 0x48(r1) -/* 801D7FE0 001D3C40 38 80 00 28 */ li r4, 0x28 -/* 801D7FE4 001D3C44 4B FF F1 21 */ bl TRK_flush_cache -/* 801D7FE8 001D3C48 3C 60 80 49 */ lis r3, lbl_80490D5C@ha -/* 801D7FEC 001D3C4C 39 81 00 24 */ addi r12, r1, 0x24 -/* 801D7FF0 001D3C50 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l -/* 801D7FF4 001D3C54 38 61 00 0C */ addi r3, r1, 0xc -/* 801D7FF8 001D3C58 7D 89 03 A6 */ mtctr r12 -/* 801D7FFC 001D3C5C 4E 80 04 21 */ bctrl -/* 801D8000 001D3C60 38 60 00 00 */ li r3, 0 -lbl_801D8004: -/* 801D8004 001D3C64 80 99 00 00 */ lwz r4, 0(r25) -/* 801D8008 001D3C68 3F DE 00 20 */ addis r30, r30, 0x20 -/* 801D800C 001D3C6C 3B 7B 00 01 */ addi r27, r27, 1 -/* 801D8010 001D3C70 38 04 00 08 */ addi r0, r4, 8 -/* 801D8014 001D3C74 90 19 00 00 */ stw r0, 0(r25) -lbl_801D8018: -/* 801D8018 001D3C78 7C 1B B8 40 */ cmplw r27, r23 -/* 801D801C 001D3C7C 41 81 00 0C */ bgt lbl_801D8028 -/* 801D8020 001D3C80 2C 03 00 00 */ cmpwi r3, 0 -/* 801D8024 001D3C84 41 82 FE 88 */ beq lbl_801D7EAC -lbl_801D8028: -/* 801D8028 001D3C88 88 1F 00 0D */ lbz r0, 0xd(r31) -/* 801D802C 001D3C8C 28 00 00 00 */ cmplwi r0, 0 -/* 801D8030 001D3C90 41 82 00 10 */ beq lbl_801D8040 -/* 801D8034 001D3C94 38 00 00 00 */ li r0, 0 -/* 801D8038 001D3C98 38 60 07 02 */ li r3, 0x702 -/* 801D803C 001D3C9C 90 19 00 00 */ stw r0, 0(r25) -lbl_801D8040: -/* 801D8040 001D3CA0 3C 80 80 42 */ lis r4, lbl_8042323C@ha -/* 801D8044 001D3CA4 80 C1 00 14 */ lwz r6, 0x14(r1) -/* 801D8048 001D3CA8 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l -/* 801D804C 001D3CAC 80 A1 00 18 */ lwz r5, 0x18(r1) -/* 801D8050 001D3CB0 80 81 00 1C */ lwz r4, 0x1c(r1) -/* 801D8054 001D3CB4 80 01 00 20 */ lwz r0, 0x20(r1) -/* 801D8058 001D3CB8 90 C7 00 00 */ stw r6, 0(r7) -/* 801D805C 001D3CBC 90 A7 00 04 */ stw r5, 4(r7) -/* 801D8060 001D3CC0 90 87 00 08 */ stw r4, 8(r7) -/* 801D8064 001D3CC4 90 07 00 0C */ stw r0, 0xc(r7) -lbl_801D8068: -/* 801D8068 001D3CC8 BA 61 00 FC */ lmw r19, 0xfc(r1) -/* 801D806C 001D3CCC 80 01 01 34 */ lwz r0, 0x134(r1) -/* 801D8070 001D3CD0 7C 08 03 A6 */ mtlr r0 -/* 801D8074 001D3CD4 38 21 01 30 */ addi r1, r1, 0x130 -/* 801D8078 001D3CD8 4E 80 00 20 */ blr - -.global TRKTargetAccessExtended1 -TRKTargetAccessExtended1: -/* 801D807C 001D3CDC 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D8080 001D3CE0 7C 08 02 A6 */ mflr r0 -/* 801D8084 001D3CE4 28 04 00 60 */ cmplwi r4, 0x60 -/* 801D8088 001D3CE8 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D808C 001D3CEC 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D8090 001D3CF0 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D8094 001D3CF4 7C DE 33 78 */ mr r30, r6 -/* 801D8098 001D3CF8 40 81 00 0C */ ble lbl_801D80A4 -/* 801D809C 001D3CFC 38 60 07 01 */ li r3, 0x701 -/* 801D80A0 001D3D00 48 00 01 34 */ b lbl_801D81D4 -lbl_801D80A4: -/* 801D80A4 001D3D04 3C C0 80 42 */ lis r6, lbl_8042323C@ha -/* 801D80A8 001D3D08 38 00 00 00 */ li r0, 0 -/* 801D80AC 001D3D0C 3B E6 32 3C */ addi r31, r6, lbl_8042323C@l -/* 801D80B0 001D3D10 7C 03 20 40 */ cmplw r3, r4 -/* 801D80B4 001D3D14 80 DF 00 0C */ lwz r6, 0xc(r31) -/* 801D80B8 001D3D18 81 5F 00 00 */ lwz r10, 0(r31) -/* 801D80BC 001D3D1C 81 3F 00 04 */ lwz r9, 4(r31) -/* 801D80C0 001D3D20 81 1F 00 08 */ lwz r8, 8(r31) -/* 801D80C4 001D3D24 98 1F 00 0D */ stb r0, 0xd(r31) -/* 801D80C8 001D3D28 91 41 00 08 */ stw r10, 8(r1) -/* 801D80CC 001D3D2C 91 21 00 0C */ stw r9, 0xc(r1) -/* 801D80D0 001D3D30 91 01 00 10 */ stw r8, 0x10(r1) -/* 801D80D4 001D3D34 90 C1 00 14 */ stw r6, 0x14(r1) -/* 801D80D8 001D3D38 90 1E 00 00 */ stw r0, 0(r30) -/* 801D80DC 001D3D3C 41 81 00 B8 */ bgt lbl_801D8194 -/* 801D80E0 001D3D40 7C 83 20 50 */ subf r4, r3, r4 -/* 801D80E4 001D3D44 3D 00 80 49 */ lis r8, lbl_80490898@ha -/* 801D80E8 001D3D48 38 04 00 01 */ addi r0, r4, 1 -/* 801D80EC 001D3D4C 80 9E 00 00 */ lwz r4, 0(r30) -/* 801D80F0 001D3D50 54 06 10 3A */ slwi r6, r0, 2 -/* 801D80F4 001D3D54 2C 07 00 00 */ cmpwi r7, 0 -/* 801D80F8 001D3D58 7C 84 32 14 */ add r4, r4, r6 -/* 801D80FC 001D3D5C 38 E8 08 98 */ addi r7, r8, lbl_80490898@l -/* 801D8100 001D3D60 54 63 10 3A */ slwi r3, r3, 2 -/* 801D8104 001D3D64 90 9E 00 00 */ stw r4, 0(r30) -/* 801D8108 001D3D68 7C 87 1A 14 */ add r4, r7, r3 -/* 801D810C 001D3D6C 38 84 01 A8 */ addi r4, r4, 0x1a8 -/* 801D8110 001D3D70 41 82 00 14 */ beq lbl_801D8124 -/* 801D8114 001D3D74 7C A3 2B 78 */ mr r3, r5 -/* 801D8118 001D3D78 7C 05 03 78 */ mr r5, r0 -/* 801D811C 001D3D7C 4B FF CE 5D */ bl TRKAppendBuffer_ui32 -/* 801D8120 001D3D80 48 00 00 74 */ b lbl_801D8194 -lbl_801D8124: -/* 801D8124 001D3D84 38 67 01 EC */ addi r3, r7, 0x1ec -/* 801D8128 001D3D88 7C 04 18 40 */ cmplw r4, r3 -/* 801D812C 001D3D8C 41 81 00 24 */ bgt lbl_801D8150 -/* 801D8130 001D3D90 38 C6 FF FC */ addi r6, r6, -4 -/* 801D8134 001D3D94 38 67 01 E8 */ addi r3, r7, 0x1e8 -/* 801D8138 001D3D98 7C C4 32 14 */ add r6, r4, r6 -/* 801D813C 001D3D9C 7C 06 18 40 */ cmplw r6, r3 -/* 801D8140 001D3DA0 41 80 00 10 */ blt lbl_801D8150 -/* 801D8144 001D3DA4 3C 60 80 42 */ lis r3, lbl_80423230@ha -/* 801D8148 001D3DA8 38 C0 00 01 */ li r6, 1 -/* 801D814C 001D3DAC 98 C3 32 30 */ stb r6, lbl_80423230@l(r3) -lbl_801D8150: -/* 801D8150 001D3DB0 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D8154 001D3DB4 38 63 08 98 */ addi r3, r3, lbl_80490898@l -/* 801D8158 001D3DB8 38 C3 02 78 */ addi r6, r3, 0x278 -/* 801D815C 001D3DBC 7C 04 30 40 */ cmplw r4, r6 -/* 801D8160 001D3DC0 41 81 00 28 */ bgt lbl_801D8188 -/* 801D8164 001D3DC4 54 03 10 3A */ slwi r3, r0, 2 -/* 801D8168 001D3DC8 38 63 FF FC */ addi r3, r3, -4 -/* 801D816C 001D3DCC 7C 64 1A 14 */ add r3, r4, r3 -/* 801D8170 001D3DD0 7C 03 30 40 */ cmplw r3, r6 -/* 801D8174 001D3DD4 41 80 00 14 */ blt lbl_801D8188 -/* 801D8178 001D3DD8 3C 60 80 42 */ lis r3, lbl_80423230@ha -/* 801D817C 001D3DDC 38 C0 00 01 */ li r6, 1 -/* 801D8180 001D3DE0 38 63 32 30 */ addi r3, r3, lbl_80423230@l -/* 801D8184 001D3DE4 98 C3 00 01 */ stb r6, 1(r3) -lbl_801D8188: -/* 801D8188 001D3DE8 7C A3 2B 78 */ mr r3, r5 -/* 801D818C 001D3DEC 7C 05 03 78 */ mr r5, r0 -/* 801D8190 001D3DF0 4B FF CB 79 */ bl TRKReadBuffer_ui32 -lbl_801D8194: -/* 801D8194 001D3DF4 88 1F 00 0D */ lbz r0, 0xd(r31) -/* 801D8198 001D3DF8 28 00 00 00 */ cmplwi r0, 0 -/* 801D819C 001D3DFC 41 82 00 10 */ beq lbl_801D81AC -/* 801D81A0 001D3E00 38 00 00 00 */ li r0, 0 -/* 801D81A4 001D3E04 38 60 07 02 */ li r3, 0x702 -/* 801D81A8 001D3E08 90 1E 00 00 */ stw r0, 0(r30) -lbl_801D81AC: -/* 801D81AC 001D3E0C 3C 80 80 42 */ lis r4, lbl_8042323C@ha -/* 801D81B0 001D3E10 80 C1 00 08 */ lwz r6, 8(r1) -/* 801D81B4 001D3E14 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l -/* 801D81B8 001D3E18 80 A1 00 0C */ lwz r5, 0xc(r1) -/* 801D81BC 001D3E1C 80 81 00 10 */ lwz r4, 0x10(r1) -/* 801D81C0 001D3E20 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D81C4 001D3E24 90 C7 00 00 */ stw r6, 0(r7) -/* 801D81C8 001D3E28 90 A7 00 04 */ stw r5, 4(r7) -/* 801D81CC 001D3E2C 90 87 00 08 */ stw r4, 8(r7) -/* 801D81D0 001D3E30 90 07 00 0C */ stw r0, 0xc(r7) -lbl_801D81D4: -/* 801D81D4 001D3E34 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D81D8 001D3E38 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D81DC 001D3E3C 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D81E0 001D3E40 7C 08 03 A6 */ mtlr r0 -/* 801D81E4 001D3E44 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D81E8 001D3E48 4E 80 00 20 */ blr - -.global TRKTargetAccessFP -TRKTargetAccessFP: -/* 801D81EC 001D3E4C 94 21 FF 10 */ stwu r1, -0xf0(r1) -/* 801D81F0 001D3E50 7C 08 02 A6 */ mflr r0 -/* 801D81F4 001D3E54 90 01 00 F4 */ stw r0, 0xf4(r1) -/* 801D81F8 001D3E58 BE 81 00 C0 */ stmw r20, 0xc0(r1) -/* 801D81FC 001D3E5C 7C 9C 23 78 */ mr r28, r4 -/* 801D8200 001D3E60 28 1C 00 21 */ cmplwi r28, 0x21 -/* 801D8204 001D3E64 7C 74 1B 78 */ mr r20, r3 -/* 801D8208 001D3E68 7C BD 2B 78 */ mr r29, r5 -/* 801D820C 001D3E6C 7C DE 33 78 */ mr r30, r6 -/* 801D8210 001D3E70 7C FF 3B 78 */ mr r31, r7 -/* 801D8214 001D3E74 40 81 00 0C */ ble lbl_801D8220 -/* 801D8218 001D3E78 38 60 07 01 */ li r3, 0x701 -/* 801D821C 001D3E7C 48 00 04 C8 */ b lbl_801D86E4 -lbl_801D8220: -/* 801D8220 001D3E80 3C 60 80 42 */ lis r3, lbl_8042323C@ha -/* 801D8224 001D3E84 38 00 00 00 */ li r0, 0 -/* 801D8228 001D3E88 3B 63 32 3C */ addi r27, r3, lbl_8042323C@l -/* 801D822C 001D3E8C 80 7B 00 0C */ lwz r3, 0xc(r27) -/* 801D8230 001D3E90 80 DB 00 00 */ lwz r6, 0(r27) -/* 801D8234 001D3E94 80 BB 00 04 */ lwz r5, 4(r27) -/* 801D8238 001D3E98 80 9B 00 08 */ lwz r4, 8(r27) -/* 801D823C 001D3E9C 90 C1 00 10 */ stw r6, 0x10(r1) -/* 801D8240 001D3EA0 90 A1 00 14 */ stw r5, 0x14(r1) -/* 801D8244 001D3EA4 90 81 00 18 */ stw r4, 0x18(r1) -/* 801D8248 001D3EA8 90 61 00 1C */ stw r3, 0x1c(r1) -/* 801D824C 001D3EAC 98 1B 00 0D */ stb r0, 0xd(r27) -/* 801D8250 001D3EB0 4B FF EF C1 */ bl func_801D7210 -/* 801D8254 001D3EB4 60 63 20 00 */ ori r3, r3, 0x2000 -/* 801D8258 001D3EB8 4B FF EF C1 */ bl func_801D7218 -/* 801D825C 001D3EBC 38 00 00 00 */ li r0, 0 -/* 801D8260 001D3EC0 7E 95 A3 78 */ mr r21, r20 -/* 801D8264 001D3EC4 90 1E 00 00 */ stw r0, 0(r30) -/* 801D8268 001D3EC8 56 9A A8 14 */ slwi r26, r20, 0x15 -/* 801D826C 001D3ECC 3B 21 00 98 */ addi r25, r1, 0x98 -/* 801D8270 001D3ED0 3B 01 00 48 */ addi r24, r1, 0x48 -/* 801D8274 001D3ED4 3A E1 00 70 */ addi r23, r1, 0x70 -/* 801D8278 001D3ED8 3A C1 00 20 */ addi r22, r1, 0x20 -/* 801D827C 001D3EDC 38 60 00 00 */ li r3, 0 -/* 801D8280 001D3EE0 48 00 04 14 */ b lbl_801D8694 -lbl_801D8284: -/* 801D8284 001D3EE4 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D8288 001D3EE8 41 82 01 FC */ beq lbl_801D8484 -/* 801D828C 001D3EEC 3C 60 80 40 */ lis r3, lbl_803FD718@ha -/* 801D8290 001D3EF0 28 15 00 20 */ cmplwi r21, 0x20 -/* 801D8294 001D3EF4 39 83 D7 18 */ addi r12, r3, lbl_803FD718@l -/* 801D8298 001D3EF8 81 6C 00 00 */ lwz r11, 0(r12) -/* 801D829C 001D3EFC 81 4C 00 04 */ lwz r10, 4(r12) -/* 801D82A0 001D3F00 81 2C 00 08 */ lwz r9, 8(r12) -/* 801D82A4 001D3F04 81 0C 00 0C */ lwz r8, 0xc(r12) -/* 801D82A8 001D3F08 80 EC 00 10 */ lwz r7, 0x10(r12) -/* 801D82AC 001D3F0C 80 CC 00 14 */ lwz r6, 0x14(r12) -/* 801D82B0 001D3F10 80 AC 00 18 */ lwz r5, 0x18(r12) -/* 801D82B4 001D3F14 80 8C 00 1C */ lwz r4, 0x1c(r12) -/* 801D82B8 001D3F18 80 6C 00 20 */ lwz r3, 0x20(r12) -/* 801D82BC 001D3F1C 80 0C 00 24 */ lwz r0, 0x24(r12) -/* 801D82C0 001D3F20 91 61 00 98 */ stw r11, 0x98(r1) -/* 801D82C4 001D3F24 91 41 00 9C */ stw r10, 0x9c(r1) -/* 801D82C8 001D3F28 91 21 00 A0 */ stw r9, 0xa0(r1) -/* 801D82CC 001D3F2C 91 01 00 A4 */ stw r8, 0xa4(r1) -/* 801D82D0 001D3F30 90 E1 00 A8 */ stw r7, 0xa8(r1) -/* 801D82D4 001D3F34 90 C1 00 AC */ stw r6, 0xac(r1) -/* 801D82D8 001D3F38 90 A1 00 B0 */ stw r5, 0xb0(r1) -/* 801D82DC 001D3F3C 90 81 00 B4 */ stw r4, 0xb4(r1) -/* 801D82E0 001D3F40 90 61 00 B8 */ stw r3, 0xb8(r1) -/* 801D82E4 001D3F44 90 01 00 BC */ stw r0, 0xbc(r1) -/* 801D82E8 001D3F48 40 80 00 4C */ bge lbl_801D8334 -/* 801D82EC 001D3F4C 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D82F0 001D3F50 67 40 C8 03 */ oris r0, r26, 0xc803 -/* 801D82F4 001D3F54 41 82 00 08 */ beq lbl_801D82FC -/* 801D82F8 001D3F58 67 40 D8 03 */ oris r0, r26, 0xd803 -lbl_801D82FC: -/* 801D82FC 001D3F5C 3C 60 4E 80 */ lis r3, 0x4E800020@ha -/* 801D8300 001D3F60 90 01 00 98 */ stw r0, 0x98(r1) -/* 801D8304 001D3F64 38 03 00 20 */ addi r0, r3, 0x4E800020@l -/* 801D8308 001D3F68 7F 23 CB 78 */ mr r3, r25 -/* 801D830C 001D3F6C 90 01 00 BC */ stw r0, 0xbc(r1) -/* 801D8310 001D3F70 38 80 00 28 */ li r4, 0x28 -/* 801D8314 001D3F74 4B FF ED F1 */ bl TRK_flush_cache -/* 801D8318 001D3F78 3C 60 80 49 */ lis r3, lbl_80490D5C@ha -/* 801D831C 001D3F7C 39 81 00 98 */ addi r12, r1, 0x98 -/* 801D8320 001D3F80 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l -/* 801D8324 001D3F84 38 61 00 08 */ addi r3, r1, 8 -/* 801D8328 001D3F88 7D 89 03 A6 */ mtctr r12 -/* 801D832C 001D3F8C 4E 80 04 21 */ bctrl -/* 801D8330 001D3F90 48 00 01 40 */ b lbl_801D8470 -lbl_801D8334: -/* 801D8334 001D3F94 40 82 00 44 */ bne lbl_801D8378 -/* 801D8338 001D3F98 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D833C 001D3F9C 41 82 00 10 */ beq lbl_801D834C -/* 801D8340 001D3FA0 38 61 00 08 */ addi r3, r1, 8 -/* 801D8344 001D3FA4 4B FF F2 61 */ bl ReadFPSCR -/* 801D8348 001D3FA8 48 00 00 0C */ b lbl_801D8354 -lbl_801D834C: -/* 801D834C 001D3FAC 38 61 00 08 */ addi r3, r1, 8 -/* 801D8350 001D3FB0 4B FF F2 79 */ bl WriteFPSCR -lbl_801D8354: -/* 801D8354 001D3FB4 80 81 00 08 */ lwz r4, 8(r1) -/* 801D8358 001D3FB8 38 00 00 00 */ li r0, 0 -/* 801D835C 001D3FBC 80 A1 00 0C */ lwz r5, 0xc(r1) -/* 801D8360 001D3FC0 38 60 FF FF */ li r3, -1 -/* 801D8364 001D3FC4 7C 80 00 38 */ and r0, r4, r0 -/* 801D8368 001D3FC8 7C A3 18 38 */ and r3, r5, r3 -/* 801D836C 001D3FCC 90 01 00 08 */ stw r0, 8(r1) -/* 801D8370 001D3FD0 90 61 00 0C */ stw r3, 0xc(r1) -/* 801D8374 001D3FD4 48 00 00 FC */ b lbl_801D8470 -lbl_801D8378: -/* 801D8378 001D3FD8 28 15 00 21 */ cmplwi r21, 0x21 -/* 801D837C 001D3FDC 40 82 00 F4 */ bne lbl_801D8470 -/* 801D8380 001D3FE0 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D8384 001D3FE4 40 82 00 0C */ bne lbl_801D8390 -/* 801D8388 001D3FE8 80 01 00 0C */ lwz r0, 0xc(r1) -/* 801D838C 001D3FEC 90 01 00 08 */ stw r0, 8(r1) -lbl_801D8390: -/* 801D8390 001D3FF0 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha -/* 801D8394 001D3FF4 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D8398 001D3FF8 39 83 D6 C8 */ addi r12, r3, lbl_803FD6C8@l -/* 801D839C 001D3FFC 81 6C 00 00 */ lwz r11, 0(r12) -/* 801D83A0 001D4000 81 4C 00 04 */ lwz r10, 4(r12) -/* 801D83A4 001D4004 81 2C 00 08 */ lwz r9, 8(r12) -/* 801D83A8 001D4008 81 0C 00 0C */ lwz r8, 0xc(r12) -/* 801D83AC 001D400C 80 EC 00 10 */ lwz r7, 0x10(r12) -/* 801D83B0 001D4010 80 CC 00 14 */ lwz r6, 0x14(r12) -/* 801D83B4 001D4014 80 AC 00 18 */ lwz r5, 0x18(r12) -/* 801D83B8 001D4018 80 8C 00 1C */ lwz r4, 0x1c(r12) -/* 801D83BC 001D401C 80 6C 00 20 */ lwz r3, 0x20(r12) -/* 801D83C0 001D4020 80 0C 00 24 */ lwz r0, 0x24(r12) -/* 801D83C4 001D4024 91 61 00 48 */ stw r11, 0x48(r1) -/* 801D83C8 001D4028 91 41 00 4C */ stw r10, 0x4c(r1) -/* 801D83CC 001D402C 91 21 00 50 */ stw r9, 0x50(r1) -/* 801D83D0 001D4030 91 01 00 54 */ stw r8, 0x54(r1) -/* 801D83D4 001D4034 90 E1 00 58 */ stw r7, 0x58(r1) -/* 801D83D8 001D4038 90 C1 00 5C */ stw r6, 0x5c(r1) -/* 801D83DC 001D403C 90 A1 00 60 */ stw r5, 0x60(r1) -/* 801D83E0 001D4040 90 81 00 64 */ stw r4, 0x64(r1) -/* 801D83E4 001D4044 90 61 00 68 */ stw r3, 0x68(r1) -/* 801D83E8 001D4048 90 01 00 6C */ stw r0, 0x6c(r1) -/* 801D83EC 001D404C 41 82 00 1C */ beq lbl_801D8408 -/* 801D83F0 001D4050 3C 60 7C 9F */ lis r3, 0x7C9EFAA6@ha -/* 801D83F4 001D4054 3C 00 90 83 */ lis r0, 0x9083 -/* 801D83F8 001D4058 38 63 FA A6 */ addi r3, r3, 0x7C9EFAA6@l -/* 801D83FC 001D405C 90 01 00 4C */ stw r0, 0x4c(r1) -/* 801D8400 001D4060 90 61 00 48 */ stw r3, 0x48(r1) -/* 801D8404 001D4064 48 00 00 18 */ b lbl_801D841C -lbl_801D8408: -/* 801D8408 001D4068 3C 60 7C 9F */ lis r3, 0x7C9EFBA6@ha -/* 801D840C 001D406C 3C 80 80 83 */ lis r4, 0x8083 -/* 801D8410 001D4070 38 03 FB A6 */ addi r0, r3, 0x7C9EFBA6@l -/* 801D8414 001D4074 90 81 00 48 */ stw r4, 0x48(r1) -/* 801D8418 001D4078 90 01 00 4C */ stw r0, 0x4c(r1) -lbl_801D841C: -/* 801D841C 001D407C 3C 80 4E 80 */ lis r4, 0x4E800020@ha -/* 801D8420 001D4080 7F 03 C3 78 */ mr r3, r24 -/* 801D8424 001D4084 38 04 00 20 */ addi r0, r4, 0x4E800020@l -/* 801D8428 001D4088 38 80 00 28 */ li r4, 0x28 -/* 801D842C 001D408C 90 01 00 6C */ stw r0, 0x6c(r1) -/* 801D8430 001D4090 4B FF EC D5 */ bl TRK_flush_cache -/* 801D8434 001D4094 3C 60 80 49 */ lis r3, lbl_80490D5C@ha -/* 801D8438 001D4098 39 81 00 48 */ addi r12, r1, 0x48 -/* 801D843C 001D409C 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l -/* 801D8440 001D40A0 38 61 00 08 */ addi r3, r1, 8 -/* 801D8444 001D40A4 7D 89 03 A6 */ mtctr r12 -/* 801D8448 001D40A8 4E 80 04 21 */ bctrl -/* 801D844C 001D40AC 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D8450 001D40B0 41 82 00 20 */ beq lbl_801D8470 -/* 801D8454 001D40B4 80 61 00 08 */ lwz r3, 8(r1) -/* 801D8458 001D40B8 38 80 00 00 */ li r4, 0 -/* 801D845C 001D40BC 38 00 FF FF */ li r0, -1 -/* 801D8460 001D40C0 7C 63 00 38 */ and r3, r3, r0 -/* 801D8464 001D40C4 7C 80 20 38 */ and r0, r4, r4 -/* 801D8468 001D40C8 90 61 00 0C */ stw r3, 0xc(r1) -/* 801D846C 001D40CC 90 01 00 08 */ stw r0, 8(r1) -lbl_801D8470: -/* 801D8470 001D40D0 80 A1 00 08 */ lwz r5, 8(r1) -/* 801D8474 001D40D4 7F A3 EB 78 */ mr r3, r29 -/* 801D8478 001D40D8 80 C1 00 0C */ lwz r6, 0xc(r1) -/* 801D847C 001D40DC 4B FF CC 61 */ bl TRKAppendBuffer1_ui64 -/* 801D8480 001D40E0 48 00 02 00 */ b lbl_801D8680 -lbl_801D8484: -/* 801D8484 001D40E4 7F A3 EB 78 */ mr r3, r29 -/* 801D8488 001D40E8 38 81 00 08 */ addi r4, r1, 8 -/* 801D848C 001D40EC 4B FF CA 05 */ bl TRKReadBuffer1_ui64 -/* 801D8490 001D40F0 3C 60 80 40 */ lis r3, lbl_803FD718@ha -/* 801D8494 001D40F4 28 15 00 20 */ cmplwi r21, 0x20 -/* 801D8498 001D40F8 39 83 D7 18 */ addi r12, r3, lbl_803FD718@l -/* 801D849C 001D40FC 3A 80 00 00 */ li r20, 0 -/* 801D84A0 001D4100 81 6C 00 00 */ lwz r11, 0(r12) -/* 801D84A4 001D4104 81 4C 00 04 */ lwz r10, 4(r12) -/* 801D84A8 001D4108 81 2C 00 08 */ lwz r9, 8(r12) -/* 801D84AC 001D410C 81 0C 00 0C */ lwz r8, 0xc(r12) -/* 801D84B0 001D4110 80 EC 00 10 */ lwz r7, 0x10(r12) -/* 801D84B4 001D4114 80 CC 00 14 */ lwz r6, 0x14(r12) -/* 801D84B8 001D4118 80 AC 00 18 */ lwz r5, 0x18(r12) -/* 801D84BC 001D411C 80 8C 00 1C */ lwz r4, 0x1c(r12) -/* 801D84C0 001D4120 80 6C 00 20 */ lwz r3, 0x20(r12) -/* 801D84C4 001D4124 80 0C 00 24 */ lwz r0, 0x24(r12) -/* 801D84C8 001D4128 91 61 00 70 */ stw r11, 0x70(r1) -/* 801D84CC 001D412C 91 41 00 74 */ stw r10, 0x74(r1) -/* 801D84D0 001D4130 91 21 00 78 */ stw r9, 0x78(r1) -/* 801D84D4 001D4134 91 01 00 7C */ stw r8, 0x7c(r1) -/* 801D84D8 001D4138 90 E1 00 80 */ stw r7, 0x80(r1) -/* 801D84DC 001D413C 90 C1 00 84 */ stw r6, 0x84(r1) -/* 801D84E0 001D4140 90 A1 00 88 */ stw r5, 0x88(r1) -/* 801D84E4 001D4144 90 81 00 8C */ stw r4, 0x8c(r1) -/* 801D84E8 001D4148 90 61 00 90 */ stw r3, 0x90(r1) -/* 801D84EC 001D414C 90 01 00 94 */ stw r0, 0x94(r1) -/* 801D84F0 001D4150 40 80 00 50 */ bge lbl_801D8540 -/* 801D84F4 001D4154 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D84F8 001D4158 67 40 C8 03 */ oris r0, r26, 0xc803 -/* 801D84FC 001D415C 41 82 00 08 */ beq lbl_801D8504 -/* 801D8500 001D4160 67 40 D8 03 */ oris r0, r26, 0xd803 -lbl_801D8504: -/* 801D8504 001D4164 3C 60 4E 80 */ lis r3, 0x4E800020@ha -/* 801D8508 001D4168 90 01 00 70 */ stw r0, 0x70(r1) -/* 801D850C 001D416C 38 03 00 20 */ addi r0, r3, 0x4E800020@l -/* 801D8510 001D4170 7E E3 BB 78 */ mr r3, r23 -/* 801D8514 001D4174 90 01 00 94 */ stw r0, 0x94(r1) -/* 801D8518 001D4178 38 80 00 28 */ li r4, 0x28 -/* 801D851C 001D417C 4B FF EB E9 */ bl TRK_flush_cache -/* 801D8520 001D4180 3C 60 80 49 */ lis r3, lbl_80490D5C@ha -/* 801D8524 001D4184 39 81 00 70 */ addi r12, r1, 0x70 -/* 801D8528 001D4188 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l -/* 801D852C 001D418C 38 61 00 08 */ addi r3, r1, 8 -/* 801D8530 001D4190 7D 89 03 A6 */ mtctr r12 -/* 801D8534 001D4194 4E 80 04 21 */ bctrl -/* 801D8538 001D4198 3A 80 00 00 */ li r20, 0 -/* 801D853C 001D419C 48 00 01 40 */ b lbl_801D867C -lbl_801D8540: -/* 801D8540 001D41A0 40 82 00 44 */ bne lbl_801D8584 -/* 801D8544 001D41A4 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D8548 001D41A8 41 82 00 10 */ beq lbl_801D8558 -/* 801D854C 001D41AC 38 61 00 08 */ addi r3, r1, 8 -/* 801D8550 001D41B0 4B FF F0 55 */ bl ReadFPSCR -/* 801D8554 001D41B4 48 00 00 0C */ b lbl_801D8560 -lbl_801D8558: -/* 801D8558 001D41B8 38 61 00 08 */ addi r3, r1, 8 -/* 801D855C 001D41BC 4B FF F0 6D */ bl WriteFPSCR -lbl_801D8560: -/* 801D8560 001D41C0 80 81 00 08 */ lwz r4, 8(r1) -/* 801D8564 001D41C4 38 00 00 00 */ li r0, 0 -/* 801D8568 001D41C8 80 A1 00 0C */ lwz r5, 0xc(r1) -/* 801D856C 001D41CC 38 60 FF FF */ li r3, -1 -/* 801D8570 001D41D0 7C 80 00 38 */ and r0, r4, r0 -/* 801D8574 001D41D4 7C A3 18 38 */ and r3, r5, r3 -/* 801D8578 001D41D8 90 01 00 08 */ stw r0, 8(r1) -/* 801D857C 001D41DC 90 61 00 0C */ stw r3, 0xc(r1) -/* 801D8580 001D41E0 48 00 00 FC */ b lbl_801D867C -lbl_801D8584: -/* 801D8584 001D41E4 28 15 00 21 */ cmplwi r21, 0x21 -/* 801D8588 001D41E8 40 82 00 F4 */ bne lbl_801D867C -/* 801D858C 001D41EC 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D8590 001D41F0 40 82 00 0C */ bne lbl_801D859C -/* 801D8594 001D41F4 80 01 00 0C */ lwz r0, 0xc(r1) -/* 801D8598 001D41F8 90 01 00 08 */ stw r0, 8(r1) -lbl_801D859C: -/* 801D859C 001D41FC 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha -/* 801D85A0 001D4200 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D85A4 001D4204 39 83 D6 C8 */ addi r12, r3, lbl_803FD6C8@l -/* 801D85A8 001D4208 81 6C 00 00 */ lwz r11, 0(r12) -/* 801D85AC 001D420C 81 4C 00 04 */ lwz r10, 4(r12) -/* 801D85B0 001D4210 81 2C 00 08 */ lwz r9, 8(r12) -/* 801D85B4 001D4214 81 0C 00 0C */ lwz r8, 0xc(r12) -/* 801D85B8 001D4218 80 EC 00 10 */ lwz r7, 0x10(r12) -/* 801D85BC 001D421C 80 CC 00 14 */ lwz r6, 0x14(r12) -/* 801D85C0 001D4220 80 AC 00 18 */ lwz r5, 0x18(r12) -/* 801D85C4 001D4224 80 8C 00 1C */ lwz r4, 0x1c(r12) -/* 801D85C8 001D4228 80 6C 00 20 */ lwz r3, 0x20(r12) -/* 801D85CC 001D422C 80 0C 00 24 */ lwz r0, 0x24(r12) -/* 801D85D0 001D4230 91 61 00 20 */ stw r11, 0x20(r1) -/* 801D85D4 001D4234 91 41 00 24 */ stw r10, 0x24(r1) -/* 801D85D8 001D4238 91 21 00 28 */ stw r9, 0x28(r1) -/* 801D85DC 001D423C 91 01 00 2C */ stw r8, 0x2c(r1) -/* 801D85E0 001D4240 90 E1 00 30 */ stw r7, 0x30(r1) -/* 801D85E4 001D4244 90 C1 00 34 */ stw r6, 0x34(r1) -/* 801D85E8 001D4248 90 A1 00 38 */ stw r5, 0x38(r1) -/* 801D85EC 001D424C 90 81 00 3C */ stw r4, 0x3c(r1) -/* 801D85F0 001D4250 90 61 00 40 */ stw r3, 0x40(r1) -/* 801D85F4 001D4254 90 01 00 44 */ stw r0, 0x44(r1) -/* 801D85F8 001D4258 41 82 00 1C */ beq lbl_801D8614 -/* 801D85FC 001D425C 3C 60 7C 9F */ lis r3, 0x7C9EFAA6@ha -/* 801D8600 001D4260 3C 00 90 83 */ lis r0, 0x9083 -/* 801D8604 001D4264 38 63 FA A6 */ addi r3, r3, 0x7C9EFAA6@l -/* 801D8608 001D4268 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D860C 001D426C 90 61 00 20 */ stw r3, 0x20(r1) -/* 801D8610 001D4270 48 00 00 18 */ b lbl_801D8628 -lbl_801D8614: -/* 801D8614 001D4274 3C 60 7C 9F */ lis r3, 0x7C9EFBA6@ha -/* 801D8618 001D4278 3C 80 80 83 */ lis r4, 0x8083 -/* 801D861C 001D427C 38 03 FB A6 */ addi r0, r3, 0x7C9EFBA6@l -/* 801D8620 001D4280 90 81 00 20 */ stw r4, 0x20(r1) -/* 801D8624 001D4284 90 01 00 24 */ stw r0, 0x24(r1) -lbl_801D8628: -/* 801D8628 001D4288 3C 80 4E 80 */ lis r4, 0x4E800020@ha -/* 801D862C 001D428C 7E C3 B3 78 */ mr r3, r22 -/* 801D8630 001D4290 38 04 00 20 */ addi r0, r4, 0x4E800020@l -/* 801D8634 001D4294 38 80 00 28 */ li r4, 0x28 -/* 801D8638 001D4298 90 01 00 44 */ stw r0, 0x44(r1) -/* 801D863C 001D429C 4B FF EA C9 */ bl TRK_flush_cache -/* 801D8640 001D42A0 3C 60 80 49 */ lis r3, lbl_80490D5C@ha -/* 801D8644 001D42A4 39 81 00 20 */ addi r12, r1, 0x20 -/* 801D8648 001D42A8 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l -/* 801D864C 001D42AC 38 61 00 08 */ addi r3, r1, 8 -/* 801D8650 001D42B0 7D 89 03 A6 */ mtctr r12 -/* 801D8654 001D42B4 4E 80 04 21 */ bctrl -/* 801D8658 001D42B8 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D865C 001D42BC 3A 80 00 00 */ li r20, 0 -/* 801D8660 001D42C0 41 82 00 1C */ beq lbl_801D867C -/* 801D8664 001D42C4 80 81 00 08 */ lwz r4, 8(r1) -/* 801D8668 001D42C8 38 60 FF FF */ li r3, -1 -/* 801D866C 001D42CC 7E 80 A0 38 */ and r0, r20, r20 -/* 801D8670 001D42D0 7C 83 18 38 */ and r3, r4, r3 -/* 801D8674 001D42D4 90 01 00 08 */ stw r0, 8(r1) -/* 801D8678 001D42D8 90 61 00 0C */ stw r3, 0xc(r1) -lbl_801D867C: -/* 801D867C 001D42DC 7E 83 A3 78 */ mr r3, r20 -lbl_801D8680: -/* 801D8680 001D42E0 80 9E 00 00 */ lwz r4, 0(r30) -/* 801D8684 001D42E4 3F 5A 00 20 */ addis r26, r26, 0x20 -/* 801D8688 001D42E8 3A B5 00 01 */ addi r21, r21, 1 -/* 801D868C 001D42EC 38 04 00 08 */ addi r0, r4, 8 -/* 801D8690 001D42F0 90 1E 00 00 */ stw r0, 0(r30) -lbl_801D8694: -/* 801D8694 001D42F4 7C 15 E0 40 */ cmplw r21, r28 -/* 801D8698 001D42F8 41 81 00 0C */ bgt lbl_801D86A4 -/* 801D869C 001D42FC 2C 03 00 00 */ cmpwi r3, 0 -/* 801D86A0 001D4300 41 82 FB E4 */ beq lbl_801D8284 -lbl_801D86A4: -/* 801D86A4 001D4304 88 1B 00 0D */ lbz r0, 0xd(r27) -/* 801D86A8 001D4308 28 00 00 00 */ cmplwi r0, 0 -/* 801D86AC 001D430C 41 82 00 10 */ beq lbl_801D86BC -/* 801D86B0 001D4310 38 00 00 00 */ li r0, 0 -/* 801D86B4 001D4314 38 60 07 02 */ li r3, 0x702 -/* 801D86B8 001D4318 90 1E 00 00 */ stw r0, 0(r30) -lbl_801D86BC: -/* 801D86BC 001D431C 3C 80 80 42 */ lis r4, lbl_8042323C@ha -/* 801D86C0 001D4320 80 C1 00 10 */ lwz r6, 0x10(r1) -/* 801D86C4 001D4324 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l -/* 801D86C8 001D4328 80 A1 00 14 */ lwz r5, 0x14(r1) -/* 801D86CC 001D432C 80 81 00 18 */ lwz r4, 0x18(r1) -/* 801D86D0 001D4330 80 01 00 1C */ lwz r0, 0x1c(r1) -/* 801D86D4 001D4334 90 C7 00 00 */ stw r6, 0(r7) -/* 801D86D8 001D4338 90 A7 00 04 */ stw r5, 4(r7) -/* 801D86DC 001D433C 90 87 00 08 */ stw r4, 8(r7) -/* 801D86E0 001D4340 90 07 00 0C */ stw r0, 0xc(r7) -lbl_801D86E4: -/* 801D86E4 001D4344 BA 81 00 C0 */ lmw r20, 0xc0(r1) -/* 801D86E8 001D4348 80 01 00 F4 */ lwz r0, 0xf4(r1) -/* 801D86EC 001D434C 7C 08 03 A6 */ mtlr r0 -/* 801D86F0 001D4350 38 21 00 F0 */ addi r1, r1, 0xf0 -/* 801D86F4 001D4354 4E 80 00 20 */ blr - -.global TRKTargetAccessDefault -TRKTargetAccessDefault: -/* 801D86F8 001D4358 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D86FC 001D435C 7C 08 02 A6 */ mflr r0 -/* 801D8700 001D4360 28 04 00 24 */ cmplwi r4, 0x24 -/* 801D8704 001D4364 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D8708 001D4368 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D870C 001D436C 7C DF 33 78 */ mr r31, r6 -/* 801D8710 001D4370 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D8714 001D4374 40 81 00 0C */ ble lbl_801D8720 -/* 801D8718 001D4378 38 60 07 01 */ li r3, 0x701 -/* 801D871C 001D437C 48 00 00 B8 */ b lbl_801D87D4 -lbl_801D8720: -/* 801D8720 001D4380 3C C0 80 42 */ lis r6, lbl_8042323C@ha -/* 801D8724 001D4384 7C 83 20 50 */ subf r4, r3, r4 -/* 801D8728 001D4388 3B C6 32 3C */ addi r30, r6, lbl_8042323C@l -/* 801D872C 001D438C 3C C0 80 49 */ lis r6, lbl_80490898@ha -/* 801D8730 001D4390 81 3E 00 0C */ lwz r9, 0xc(r30) -/* 801D8734 001D4394 39 00 00 00 */ li r8, 0 -/* 801D8738 001D4398 39 84 00 01 */ addi r12, r4, 1 -/* 801D873C 001D439C 81 7E 00 00 */ lwz r11, 0(r30) -/* 801D8740 001D43A0 81 5E 00 04 */ lwz r10, 4(r30) -/* 801D8744 001D43A4 2C 07 00 00 */ cmpwi r7, 0 -/* 801D8748 001D43A8 80 FE 00 08 */ lwz r7, 8(r30) -/* 801D874C 001D43AC 55 80 10 3A */ slwi r0, r12, 2 -/* 801D8750 001D43B0 99 1E 00 0D */ stb r8, 0xd(r30) -/* 801D8754 001D43B4 54 64 10 3A */ slwi r4, r3, 2 -/* 801D8758 001D43B8 38 66 08 98 */ addi r3, r6, lbl_80490898@l -/* 801D875C 001D43BC 91 61 00 08 */ stw r11, 8(r1) -/* 801D8760 001D43C0 7C 83 22 14 */ add r4, r3, r4 -/* 801D8764 001D43C4 91 41 00 0C */ stw r10, 0xc(r1) -/* 801D8768 001D43C8 90 E1 00 10 */ stw r7, 0x10(r1) -/* 801D876C 001D43CC 91 21 00 14 */ stw r9, 0x14(r1) -/* 801D8770 001D43D0 90 1F 00 00 */ stw r0, 0(r31) -/* 801D8774 001D43D4 41 82 00 14 */ beq lbl_801D8788 -/* 801D8778 001D43D8 7C A3 2B 78 */ mr r3, r5 -/* 801D877C 001D43DC 7D 85 63 78 */ mr r5, r12 -/* 801D8780 001D43E0 4B FF C7 F9 */ bl TRKAppendBuffer_ui32 -/* 801D8784 001D43E4 48 00 00 10 */ b lbl_801D8794 -lbl_801D8788: -/* 801D8788 001D43E8 7C A3 2B 78 */ mr r3, r5 -/* 801D878C 001D43EC 7D 85 63 78 */ mr r5, r12 -/* 801D8790 001D43F0 4B FF C5 79 */ bl TRKReadBuffer_ui32 -lbl_801D8794: -/* 801D8794 001D43F4 88 1E 00 0D */ lbz r0, 0xd(r30) -/* 801D8798 001D43F8 28 00 00 00 */ cmplwi r0, 0 -/* 801D879C 001D43FC 41 82 00 10 */ beq lbl_801D87AC -/* 801D87A0 001D4400 38 00 00 00 */ li r0, 0 -/* 801D87A4 001D4404 38 60 07 02 */ li r3, 0x702 -/* 801D87A8 001D4408 90 1F 00 00 */ stw r0, 0(r31) -lbl_801D87AC: -/* 801D87AC 001D440C 3C 80 80 42 */ lis r4, lbl_8042323C@ha -/* 801D87B0 001D4410 80 C1 00 08 */ lwz r6, 8(r1) -/* 801D87B4 001D4414 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l -/* 801D87B8 001D4418 80 A1 00 0C */ lwz r5, 0xc(r1) -/* 801D87BC 001D441C 80 81 00 10 */ lwz r4, 0x10(r1) -/* 801D87C0 001D4420 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D87C4 001D4424 90 C7 00 00 */ stw r6, 0(r7) -/* 801D87C8 001D4428 90 A7 00 04 */ stw r5, 4(r7) -/* 801D87CC 001D442C 90 87 00 08 */ stw r4, 8(r7) -/* 801D87D0 001D4430 90 07 00 0C */ stw r0, 0xc(r7) -lbl_801D87D4: -/* 801D87D4 001D4434 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D87D8 001D4438 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D87DC 001D443C 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D87E0 001D4440 7C 08 03 A6 */ mtlr r0 -/* 801D87E4 001D4444 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D87E8 001D4448 4E 80 00 20 */ blr - -.global TRKTargetReadInstruction -TRKTargetReadInstruction: -/* 801D87EC 001D444C 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D87F0 001D4450 7C 08 02 A6 */ mflr r0 -/* 801D87F4 001D4454 38 C0 00 00 */ li r6, 0 -/* 801D87F8 001D4458 38 E0 00 01 */ li r7, 1 -/* 801D87FC 001D445C 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D8800 001D4460 38 00 00 04 */ li r0, 4 -/* 801D8804 001D4464 38 A1 00 08 */ addi r5, r1, 8 -/* 801D8808 001D4468 90 01 00 08 */ stw r0, 8(r1) -/* 801D880C 001D446C 48 00 00 2D */ bl TRKTargetAccessMemory -/* 801D8810 001D4470 2C 03 00 00 */ cmpwi r3, 0 -/* 801D8814 001D4474 40 82 00 14 */ bne lbl_801D8828 -/* 801D8818 001D4478 80 01 00 08 */ lwz r0, 8(r1) -/* 801D881C 001D447C 28 00 00 04 */ cmplwi r0, 4 -/* 801D8820 001D4480 41 82 00 08 */ beq lbl_801D8828 -/* 801D8824 001D4484 38 60 07 00 */ li r3, 0x700 -lbl_801D8828: -/* 801D8828 001D4488 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D882C 001D448C 7C 08 03 A6 */ mtlr r0 -/* 801D8830 001D4490 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D8834 001D4494 4E 80 00 20 */ blr - -.global TRKTargetAccessMemory -TRKTargetAccessMemory: -/* 801D8838 001D4498 94 21 FF C0 */ stwu r1, -0x40(r1) -/* 801D883C 001D449C 7C 08 02 A6 */ mflr r0 -/* 801D8840 001D44A0 3C C0 80 42 */ lis r6, lbl_8042323C@ha -/* 801D8844 001D44A4 90 01 00 44 */ stw r0, 0x44(r1) -/* 801D8848 001D44A8 38 00 00 00 */ li r0, 0 -/* 801D884C 001D44AC BF 21 00 24 */ stmw r25, 0x24(r1) -/* 801D8850 001D44B0 3B E6 32 3C */ addi r31, r6, lbl_8042323C@l -/* 801D8854 001D44B4 7C 9B 23 78 */ mr r27, r4 -/* 801D8858 001D44B8 7C BC 2B 78 */ mr r28, r5 -/* 801D885C 001D44BC 7C 7A 1B 78 */ mr r26, r3 -/* 801D8860 001D44C0 7C FD 3B 78 */ mr r29, r7 -/* 801D8864 001D44C4 7F 63 DB 78 */ mr r3, r27 -/* 801D8868 001D44C8 80 9F 00 0C */ lwz r4, 0xc(r31) -/* 801D886C 001D44CC 81 1F 00 00 */ lwz r8, 0(r31) -/* 801D8870 001D44D0 80 DF 00 04 */ lwz r6, 4(r31) -/* 801D8874 001D44D4 80 BF 00 08 */ lwz r5, 8(r31) -/* 801D8878 001D44D8 91 01 00 08 */ stw r8, 8(r1) -/* 801D887C 001D44DC 90 C1 00 0C */ stw r6, 0xc(r1) -/* 801D8880 001D44E0 90 A1 00 10 */ stw r5, 0x10(r1) -/* 801D8884 001D44E4 90 81 00 14 */ stw r4, 0x14(r1) -/* 801D8888 001D44E8 98 1F 00 0D */ stb r0, 0xd(r31) -/* 801D888C 001D44EC 48 00 0B 51 */ bl TRKTargetTranslate -/* 801D8890 001D44F0 7F A0 00 34 */ cntlzw r0, r29 -/* 801D8894 001D44F4 80 9C 00 00 */ lwz r4, 0(r28) -/* 801D8898 001D44F8 7C 79 1B 78 */ mr r25, r3 -/* 801D889C 001D44FC 54 05 D9 7E */ srwi r5, r0, 5 -/* 801D88A0 001D4500 48 00 00 E5 */ bl TRKValidMemory32 -/* 801D88A4 001D4504 7C 7E 1B 79 */ or. r30, r3, r3 -/* 801D88A8 001D4508 41 82 00 10 */ beq lbl_801D88B8 -/* 801D88AC 001D450C 38 00 00 00 */ li r0, 0 -/* 801D88B0 001D4510 90 1C 00 00 */ stw r0, 0(r28) -/* 801D88B4 001D4514 48 00 00 78 */ b lbl_801D892C -lbl_801D88B8: -/* 801D88B8 001D4518 4B FF E9 59 */ bl func_801D7210 -/* 801D88BC 001D451C 3C 80 80 49 */ lis r4, lbl_80490898@ha -/* 801D88C0 001D4520 2C 1D 00 00 */ cmpwi r29, 0 -/* 801D88C4 001D4524 38 84 08 98 */ addi r4, r4, lbl_80490898@l -/* 801D88C8 001D4528 7C 68 1B 78 */ mr r8, r3 -/* 801D88CC 001D452C 80 04 01 F8 */ lwz r0, 0x1f8(r4) -/* 801D88D0 001D4530 54 00 06 F6 */ rlwinm r0, r0, 0, 0x1b, 0x1b -/* 801D88D4 001D4534 7D 07 03 78 */ or r7, r8, r0 -/* 801D88D8 001D4538 41 82 00 1C */ beq lbl_801D88F4 -/* 801D88DC 001D453C 80 BC 00 00 */ lwz r5, 0(r28) -/* 801D88E0 001D4540 7F 43 D3 78 */ mr r3, r26 -/* 801D88E4 001D4544 7F 24 CB 78 */ mr r4, r25 -/* 801D88E8 001D4548 7D 06 43 78 */ mr r6, r8 -/* 801D88EC 001D454C 4B FF E9 35 */ bl TRK_ppc_memcpy -/* 801D88F0 001D4550 48 00 00 3C */ b lbl_801D892C -lbl_801D88F4: -/* 801D88F4 001D4554 80 BC 00 00 */ lwz r5, 0(r28) -/* 801D88F8 001D4558 7F 23 CB 78 */ mr r3, r25 -/* 801D88FC 001D455C 7F 44 D3 78 */ mr r4, r26 -/* 801D8900 001D4560 7C E6 3B 78 */ mr r6, r7 -/* 801D8904 001D4564 7D 07 43 78 */ mr r7, r8 -/* 801D8908 001D4568 4B FF E9 19 */ bl TRK_ppc_memcpy -/* 801D890C 001D456C 80 9C 00 00 */ lwz r4, 0(r28) -/* 801D8910 001D4570 7F 23 CB 78 */ mr r3, r25 -/* 801D8914 001D4574 4B FF E7 F1 */ bl TRK_flush_cache -/* 801D8918 001D4578 7C 1B C8 40 */ cmplw r27, r25 -/* 801D891C 001D457C 41 82 00 10 */ beq lbl_801D892C -/* 801D8920 001D4580 80 9C 00 00 */ lwz r4, 0(r28) -/* 801D8924 001D4584 7F 63 DB 78 */ mr r3, r27 -/* 801D8928 001D4588 4B FF E7 DD */ bl TRK_flush_cache -lbl_801D892C: -/* 801D892C 001D458C 88 1F 00 0D */ lbz r0, 0xd(r31) -/* 801D8930 001D4590 28 00 00 00 */ cmplwi r0, 0 -/* 801D8934 001D4594 41 82 00 10 */ beq lbl_801D8944 -/* 801D8938 001D4598 38 00 00 00 */ li r0, 0 -/* 801D893C 001D459C 3B C0 07 02 */ li r30, 0x702 -/* 801D8940 001D45A0 90 1C 00 00 */ stw r0, 0(r28) -lbl_801D8944: -/* 801D8944 001D45A4 3C 60 80 42 */ lis r3, lbl_8042323C@ha -/* 801D8948 001D45A8 80 C1 00 08 */ lwz r6, 8(r1) -/* 801D894C 001D45AC 38 E3 32 3C */ addi r7, r3, lbl_8042323C@l -/* 801D8950 001D45B0 80 A1 00 0C */ lwz r5, 0xc(r1) -/* 801D8954 001D45B4 80 81 00 10 */ lwz r4, 0x10(r1) -/* 801D8958 001D45B8 7F C3 F3 78 */ mr r3, r30 -/* 801D895C 001D45BC 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D8960 001D45C0 90 C7 00 00 */ stw r6, 0(r7) -/* 801D8964 001D45C4 90 A7 00 04 */ stw r5, 4(r7) -/* 801D8968 001D45C8 90 87 00 08 */ stw r4, 8(r7) -/* 801D896C 001D45CC 90 07 00 0C */ stw r0, 0xc(r7) -/* 801D8970 001D45D0 BB 21 00 24 */ lmw r25, 0x24(r1) -/* 801D8974 001D45D4 80 01 00 44 */ lwz r0, 0x44(r1) -/* 801D8978 001D45D8 7C 08 03 A6 */ mtlr r0 -/* 801D897C 001D45DC 38 21 00 40 */ addi r1, r1, 0x40 -/* 801D8980 001D45E0 4E 80 00 20 */ blr - -.global TRKValidMemory32 -TRKValidMemory32: -/* 801D8984 001D45E4 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D8988 001D45E8 7C 08 02 A6 */ mflr r0 -/* 801D898C 001D45EC 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D8990 001D45F0 BF 41 00 08 */ stmw r26, 8(r1) -/* 801D8994 001D45F4 7F 64 1A 14 */ add r27, r4, r3 -/* 801D8998 001D45F8 3B 7B FF FF */ addi r27, r27, -1 -/* 801D899C 001D45FC 7C BA 2B 78 */ mr r26, r5 -/* 801D89A0 001D4600 7C 1B 18 40 */ cmplw r27, r3 -/* 801D89A4 001D4604 38 A0 07 00 */ li r5, 0x700 -/* 801D89A8 001D4608 40 80 00 0C */ bge lbl_801D89B4 -/* 801D89AC 001D460C 38 60 07 00 */ li r3, 0x700 -/* 801D89B0 001D4610 48 00 02 64 */ b lbl_801D8C14 -lbl_801D89B4: -/* 801D89B4 001D4614 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha -/* 801D89B8 001D4618 38 C0 00 00 */ li r6, 0 -/* 801D89BC 001D461C 3B E4 D6 B8 */ addi r31, r4, lbl_803FD6B8@l -/* 801D89C0 001D4620 80 1F 00 04 */ lwz r0, 4(r31) -/* 801D89C4 001D4624 7C 03 00 40 */ cmplw r3, r0 -/* 801D89C8 001D4628 41 81 02 48 */ bgt lbl_801D8C10 -/* 801D89CC 001D462C 80 1F 00 00 */ lwz r0, 0(r31) -/* 801D89D0 001D4630 7C 1B 00 40 */ cmplw r27, r0 -/* 801D89D4 001D4634 41 80 02 3C */ blt lbl_801D8C10 -/* 801D89D8 001D4638 2C 1A 00 00 */ cmpwi r26, 0 -/* 801D89DC 001D463C 40 82 00 18 */ bne lbl_801D89F4 -/* 801D89E0 001D4640 54 C0 20 36 */ slwi r0, r6, 4 -/* 801D89E4 001D4644 7C 9F 02 14 */ add r4, r31, r0 -/* 801D89E8 001D4648 80 04 00 08 */ lwz r0, 8(r4) -/* 801D89EC 001D464C 2C 00 00 00 */ cmpwi r0, 0 -/* 801D89F0 001D4650 41 82 00 28 */ beq lbl_801D8A18 -lbl_801D89F4: -/* 801D89F4 001D4654 2C 1A 00 01 */ cmpwi r26, 1 -/* 801D89F8 001D4658 40 82 00 28 */ bne lbl_801D8A20 -/* 801D89FC 001D465C 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha -/* 801D8A00 001D4660 54 C0 20 36 */ slwi r0, r6, 4 -/* 801D8A04 001D4664 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l -/* 801D8A08 001D4668 7C 84 02 14 */ add r4, r4, r0 -/* 801D8A0C 001D466C 80 04 00 0C */ lwz r0, 0xc(r4) -/* 801D8A10 001D4670 2C 00 00 00 */ cmpwi r0, 0 -/* 801D8A14 001D4674 40 82 00 0C */ bne lbl_801D8A20 -lbl_801D8A18: -/* 801D8A18 001D4678 38 A0 07 00 */ li r5, 0x700 -/* 801D8A1C 001D467C 48 00 01 F4 */ b lbl_801D8C10 -lbl_801D8A20: -/* 801D8A20 001D4680 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha -/* 801D8A24 001D4684 54 DD 20 36 */ slwi r29, r6, 4 -/* 801D8A28 001D4688 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l -/* 801D8A2C 001D468C 38 A0 00 00 */ li r5, 0 -/* 801D8A30 001D4690 7C 04 E8 2E */ lwzx r0, r4, r29 -/* 801D8A34 001D4694 7C 03 00 40 */ cmplw r3, r0 -/* 801D8A38 001D4698 40 80 00 E4 */ bge lbl_801D8B1C -/* 801D8A3C 001D469C 7C 03 00 50 */ subf r0, r3, r0 -/* 801D8A40 001D46A0 38 C0 07 00 */ li r6, 0x700 -/* 801D8A44 001D46A4 7F C0 1A 14 */ add r30, r0, r3 -/* 801D8A48 001D46A8 3B DE FF FF */ addi r30, r30, -1 -/* 801D8A4C 001D46AC 7C 1E 18 40 */ cmplw r30, r3 -/* 801D8A50 001D46B0 40 80 00 08 */ bge lbl_801D8A58 -/* 801D8A54 001D46B4 48 00 00 C4 */ b lbl_801D8B18 -lbl_801D8A58: -/* 801D8A58 001D46B8 80 1F 00 04 */ lwz r0, 4(r31) -/* 801D8A5C 001D46BC 38 A0 00 00 */ li r5, 0 -/* 801D8A60 001D46C0 7C 03 00 40 */ cmplw r3, r0 -/* 801D8A64 001D46C4 41 81 00 B4 */ bgt lbl_801D8B18 -/* 801D8A68 001D46C8 80 1F 00 00 */ lwz r0, 0(r31) -/* 801D8A6C 001D46CC 7C 1E 00 40 */ cmplw r30, r0 -/* 801D8A70 001D46D0 41 80 00 A8 */ blt lbl_801D8B18 -/* 801D8A74 001D46D4 2C 1A 00 00 */ cmpwi r26, 0 -/* 801D8A78 001D46D8 40 82 00 18 */ bne lbl_801D8A90 -/* 801D8A7C 001D46DC 54 A0 20 36 */ slwi r0, r5, 4 -/* 801D8A80 001D46E0 7C 84 02 14 */ add r4, r4, r0 -/* 801D8A84 001D46E4 80 04 00 08 */ lwz r0, 8(r4) -/* 801D8A88 001D46E8 2C 00 00 00 */ cmpwi r0, 0 -/* 801D8A8C 001D46EC 41 82 00 28 */ beq lbl_801D8AB4 -lbl_801D8A90: -/* 801D8A90 001D46F0 2C 1A 00 01 */ cmpwi r26, 1 -/* 801D8A94 001D46F4 40 82 00 28 */ bne lbl_801D8ABC -/* 801D8A98 001D46F8 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha -/* 801D8A9C 001D46FC 54 A0 20 36 */ slwi r0, r5, 4 -/* 801D8AA0 001D4700 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l -/* 801D8AA4 001D4704 7C 84 02 14 */ add r4, r4, r0 -/* 801D8AA8 001D4708 80 04 00 0C */ lwz r0, 0xc(r4) -/* 801D8AAC 001D470C 2C 00 00 00 */ cmpwi r0, 0 -/* 801D8AB0 001D4710 40 82 00 0C */ bne lbl_801D8ABC -lbl_801D8AB4: -/* 801D8AB4 001D4714 38 C0 07 00 */ li r6, 0x700 -/* 801D8AB8 001D4718 48 00 00 60 */ b lbl_801D8B18 -lbl_801D8ABC: -/* 801D8ABC 001D471C 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha -/* 801D8AC0 001D4720 54 BC 20 36 */ slwi r28, r5, 4 -/* 801D8AC4 001D4724 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l -/* 801D8AC8 001D4728 38 C0 00 00 */ li r6, 0 -/* 801D8ACC 001D472C 7C 04 E0 2E */ lwzx r0, r4, r28 -/* 801D8AD0 001D4730 7C 03 00 40 */ cmplw r3, r0 -/* 801D8AD4 001D4734 40 80 00 14 */ bge lbl_801D8AE8 -/* 801D8AD8 001D4738 7F 45 D3 78 */ mr r5, r26 -/* 801D8ADC 001D473C 7C 83 00 50 */ subf r4, r3, r0 -/* 801D8AE0 001D4740 4B FF FE A5 */ bl TRKValidMemory32 -/* 801D8AE4 001D4744 7C 66 1B 78 */ mr r6, r3 -lbl_801D8AE8: -/* 801D8AE8 001D4748 2C 06 00 00 */ cmpwi r6, 0 -/* 801D8AEC 001D474C 40 82 00 2C */ bne lbl_801D8B18 -/* 801D8AF0 001D4750 3C 60 80 40 */ lis r3, lbl_803FD6B8@ha -/* 801D8AF4 001D4754 38 03 D6 B8 */ addi r0, r3, lbl_803FD6B8@l -/* 801D8AF8 001D4758 7C 60 E2 14 */ add r3, r0, r28 -/* 801D8AFC 001D475C 80 63 00 04 */ lwz r3, 4(r3) -/* 801D8B00 001D4760 7C 1E 18 40 */ cmplw r30, r3 -/* 801D8B04 001D4764 40 81 00 14 */ ble lbl_801D8B18 -/* 801D8B08 001D4768 7F 45 D3 78 */ mr r5, r26 -/* 801D8B0C 001D476C 7C 83 F0 50 */ subf r4, r3, r30 -/* 801D8B10 001D4770 4B FF FE 75 */ bl TRKValidMemory32 -/* 801D8B14 001D4774 7C 66 1B 78 */ mr r6, r3 -lbl_801D8B18: -/* 801D8B18 001D4778 7C C5 33 78 */ mr r5, r6 -lbl_801D8B1C: -/* 801D8B1C 001D477C 2C 05 00 00 */ cmpwi r5, 0 -/* 801D8B20 001D4780 40 82 00 F0 */ bne lbl_801D8C10 -/* 801D8B24 001D4784 3C 60 80 40 */ lis r3, lbl_803FD6B8@ha -/* 801D8B28 001D4788 38 83 D6 B8 */ addi r4, r3, lbl_803FD6B8@l -/* 801D8B2C 001D478C 3B 84 00 04 */ addi r28, r4, 4 -/* 801D8B30 001D4790 7C 7C E8 2E */ lwzx r3, r28, r29 -/* 801D8B34 001D4794 7C 1B 18 40 */ cmplw r27, r3 -/* 801D8B38 001D4798 40 81 00 D8 */ ble lbl_801D8C10 -/* 801D8B3C 001D479C 7C 03 D8 50 */ subf r0, r3, r27 -/* 801D8B40 001D47A0 38 C0 07 00 */ li r6, 0x700 -/* 801D8B44 001D47A4 7F C0 1A 14 */ add r30, r0, r3 -/* 801D8B48 001D47A8 3B DE FF FF */ addi r30, r30, -1 -/* 801D8B4C 001D47AC 7C 1E 18 40 */ cmplw r30, r3 -/* 801D8B50 001D47B0 40 80 00 08 */ bge lbl_801D8B58 -/* 801D8B54 001D47B4 48 00 00 B8 */ b lbl_801D8C0C -lbl_801D8B58: -/* 801D8B58 001D47B8 80 1F 00 04 */ lwz r0, 4(r31) -/* 801D8B5C 001D47BC 38 A0 00 00 */ li r5, 0 -/* 801D8B60 001D47C0 7C 03 00 40 */ cmplw r3, r0 -/* 801D8B64 001D47C4 41 81 00 A8 */ bgt lbl_801D8C0C -/* 801D8B68 001D47C8 80 1F 00 00 */ lwz r0, 0(r31) -/* 801D8B6C 001D47CC 7C 1E 00 40 */ cmplw r30, r0 -/* 801D8B70 001D47D0 41 80 00 9C */ blt lbl_801D8C0C -/* 801D8B74 001D47D4 2C 1A 00 00 */ cmpwi r26, 0 -/* 801D8B78 001D47D8 40 82 00 18 */ bne lbl_801D8B90 -/* 801D8B7C 001D47DC 54 A0 20 36 */ slwi r0, r5, 4 -/* 801D8B80 001D47E0 7C 84 02 14 */ add r4, r4, r0 -/* 801D8B84 001D47E4 80 04 00 08 */ lwz r0, 8(r4) -/* 801D8B88 001D47E8 2C 00 00 00 */ cmpwi r0, 0 -/* 801D8B8C 001D47EC 41 82 00 28 */ beq lbl_801D8BB4 -lbl_801D8B90: -/* 801D8B90 001D47F0 2C 1A 00 01 */ cmpwi r26, 1 -/* 801D8B94 001D47F4 40 82 00 28 */ bne lbl_801D8BBC -/* 801D8B98 001D47F8 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha -/* 801D8B9C 001D47FC 54 A0 20 36 */ slwi r0, r5, 4 -/* 801D8BA0 001D4800 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l -/* 801D8BA4 001D4804 7C 84 02 14 */ add r4, r4, r0 -/* 801D8BA8 001D4808 80 04 00 0C */ lwz r0, 0xc(r4) -/* 801D8BAC 001D480C 2C 00 00 00 */ cmpwi r0, 0 -/* 801D8BB0 001D4810 40 82 00 0C */ bne lbl_801D8BBC -lbl_801D8BB4: -/* 801D8BB4 001D4814 38 C0 07 00 */ li r6, 0x700 -/* 801D8BB8 001D4818 48 00 00 54 */ b lbl_801D8C0C -lbl_801D8BBC: -/* 801D8BBC 001D481C 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha -/* 801D8BC0 001D4820 54 BB 20 36 */ slwi r27, r5, 4 -/* 801D8BC4 001D4824 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l -/* 801D8BC8 001D4828 38 C0 00 00 */ li r6, 0 -/* 801D8BCC 001D482C 7C 04 D8 2E */ lwzx r0, r4, r27 -/* 801D8BD0 001D4830 7C 03 00 40 */ cmplw r3, r0 -/* 801D8BD4 001D4834 40 80 00 14 */ bge lbl_801D8BE8 -/* 801D8BD8 001D4838 7F 45 D3 78 */ mr r5, r26 -/* 801D8BDC 001D483C 7C 83 00 50 */ subf r4, r3, r0 -/* 801D8BE0 001D4840 4B FF FD A5 */ bl TRKValidMemory32 -/* 801D8BE4 001D4844 7C 66 1B 78 */ mr r6, r3 -lbl_801D8BE8: -/* 801D8BE8 001D4848 2C 06 00 00 */ cmpwi r6, 0 -/* 801D8BEC 001D484C 40 82 00 20 */ bne lbl_801D8C0C -/* 801D8BF0 001D4850 7C 7C D8 2E */ lwzx r3, r28, r27 -/* 801D8BF4 001D4854 7C 1E 18 40 */ cmplw r30, r3 -/* 801D8BF8 001D4858 40 81 00 14 */ ble lbl_801D8C0C -/* 801D8BFC 001D485C 7F 45 D3 78 */ mr r5, r26 -/* 801D8C00 001D4860 7C 83 F0 50 */ subf r4, r3, r30 -/* 801D8C04 001D4864 4B FF FD 81 */ bl TRKValidMemory32 -/* 801D8C08 001D4868 7C 66 1B 78 */ mr r6, r3 -lbl_801D8C0C: -/* 801D8C0C 001D486C 7C C5 33 78 */ mr r5, r6 -lbl_801D8C10: -/* 801D8C10 001D4870 7C A3 2B 78 */ mr r3, r5 -lbl_801D8C14: -/* 801D8C14 001D4874 BB 41 00 08 */ lmw r26, 8(r1) -/* 801D8C18 001D4878 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D8C1C 001D487C 7C 08 03 A6 */ mtlr r0 -/* 801D8C20 001D4880 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D8C24 001D4884 4E 80 00 20 */ blr -/* 801D8C28 001D4888 00 00 00 00 */ .4byte 0x00000000 /* unknown instruction */ -/* 801D8C2C 001D488C 00 00 00 00 */ .4byte 0x00000000 /* unknown instruction */ - .global func_801D8C30 func_801D8C30: /* 801D8C30 001D4890 0F E0 00 00 */ twui r0, 0 @@ -2132,7 +259,7 @@ func_801D8FC0: /* 801D8FE8 001D4C48 38 60 00 01 */ li r3, 1 /* 801D8FEC 001D4C4C 48 00 00 78 */ b lbl_801D9064 lbl_801D8FF0: -/* 801D8FF0 001D4C50 4B FF D9 A1 */ bl func_801D6990 +/* 801D8FF0 001D4C50 4B FF D9 A1 */ bl GetTRKConnected /* 801D8FF4 001D4C54 2C 03 00 00 */ cmpwi r3, 0 /* 801D8FF8 001D4C58 40 82 00 0C */ bne lbl_801D9004 /* 801D8FFC 001D4C5C 38 60 00 01 */ li r3, 1 @@ -2189,7 +316,7 @@ __TRK_write_console: /* 801D90A4 001D4D04 38 60 00 01 */ li r3, 1 /* 801D90A8 001D4D08 48 00 00 78 */ b lbl_801D9120 lbl_801D90AC: -/* 801D90AC 001D4D0C 4B FF D8 E5 */ bl func_801D6990 +/* 801D90AC 001D4D0C 4B FF D8 E5 */ bl GetTRKConnected /* 801D90B0 001D4D10 2C 03 00 00 */ cmpwi r3, 0 /* 801D90B4 001D4D14 40 82 00 0C */ bne lbl_801D90C0 /* 801D90B8 001D4D18 38 60 00 01 */ li r3, 1 @@ -2323,7 +450,7 @@ TRKInitializeTarget: /* 801D9274 001D4ED4 38 00 00 01 */ li r0, 1 /* 801D9278 001D4ED8 38 63 07 F4 */ addi r3, r3, lbl_804907F4@l /* 801D927C 001D4EDC 90 03 00 98 */ stw r0, 0x98(r3) -/* 801D9280 001D4EE0 4B FF DF 91 */ bl func_801D7210 +/* 801D9280 001D4EE0 4B FF DF 91 */ bl __TRK_get_MSR /* 801D9284 001D4EE4 3C A0 80 49 */ lis r5, lbl_804907F4@ha /* 801D9288 001D4EE8 3C 80 80 49 */ lis r4, lbl_80490D70@ha /* 801D928C 001D4EEC 38 A5 07 F4 */ addi r5, r5, lbl_804907F4@l @@ -2462,7 +589,7 @@ lbl_801D9454: /* 801D9454 001D50B4 94 21 FF F0 */ stwu r1, -0x10(r1) /* 801D9458 001D50B8 7C 08 02 A6 */ mflr r0 /* 801D945C 001D50BC 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9460 001D50C0 4B FF B7 45 */ bl func_801D4BA4 +/* 801D9460 001D50C0 4B FF B7 45 */ bl TRKInitializeNub /* 801D9464 001D50C4 3C 80 80 49 */ lis r4, lbl_80490D78@ha /* 801D9468 001D50C8 2C 03 00 00 */ cmpwi r3, 0 /* 801D946C 001D50CC 90 64 0D 78 */ stw r3, lbl_80490D78@l(r4) @@ -2470,7 +597,7 @@ lbl_801D9454: /* 801D9474 001D50D4 4B FF B6 E5 */ bl TRKNubWelcome /* 801D9478 001D50D8 4B FF B3 C1 */ bl TRKNubMainLoop lbl_801D947C: -/* 801D947C 001D50DC 4B FF B7 05 */ bl func_801D4B80 +/* 801D947C 001D50DC 4B FF B7 05 */ bl TRKTerminateNub /* 801D9480 001D50E0 3C 80 80 49 */ lis r4, lbl_80490D78@ha /* 801D9484 001D50E4 90 64 0D 78 */ stw r3, lbl_80490D78@l(r4) /* 801D9488 001D50E8 80 01 00 14 */ lwz r0, 0x14(r1) @@ -2833,7 +960,7 @@ TRKTargetContinue: /* 801D995C 001D55BC 7C 08 02 A6 */ mflr r0 /* 801D9960 001D55C0 38 60 00 00 */ li r3, 0 /* 801D9964 001D55C4 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9968 001D55C8 4B FF DC AD */ bl func_801D7614 +/* 801D9968 001D55C8 4B FF DC AD */ bl TRKTargetSetStopped /* 801D996C 001D55CC 4B FF FC 41 */ bl func_801D95AC /* 801D9970 001D55D0 4B FF DB 1D */ bl TRKSwapAndGo /* 801D9974 001D55D4 4B FF FC 69 */ bl UnreserveEXI2Port diff --git a/asm/text_8.s b/asm/text_8.s index c04e55b..0ecf1b5 100644 --- a/asm/text_8.s +++ b/asm/text_8.s @@ -77044,8 +77044,8 @@ func_802BD644: /* 802BD64C 002B92AC 90 64 00 88 */ stw r3, 0x88(r4) /* 802BD650 002B92B0 4E 80 00 20 */ blr -.global TRKTargetSetInputPendingPtr -TRKTargetSetInputPendingPtr: +.global func_802BD654 +func_802BD654: /* 802BD654 002B92B4 3C 80 80 57 */ lis r4, lbl_805686D8@ha /* 802BD658 002B92B8 38 84 86 D8 */ addi r4, r4, lbl_805686D8@l /* 802BD65C 002B92BC 90 64 00 84 */ stw r3, 0x84(r4) @@ -80412,7 +80412,7 @@ func_802C05F8: /* 802C0624 002BC284 41 82 00 2C */ beq lbl_802C0650 /* 802C0628 002BC288 3C 60 80 2C */ lis r3, lbl_802C0678@ha /* 802C062C 002BC28C 38 63 06 78 */ addi r3, r3, lbl_802C0678@l -/* 802C0630 002BC290 4B FF D0 25 */ bl TRKTargetSetInputPendingPtr +/* 802C0630 002BC290 4B FF D0 25 */ bl func_802BD654 /* 802C0634 002BC294 3C 80 80 57 */ lis r4, lbl_80568814@ha /* 802C0638 002BC298 3C A0 80 2C */ lis r5, lbl_802C0D78@ha /* 802C063C 002BC29C 38 84 88 14 */ addi r4, r4, lbl_80568814@l diff --git a/obj_files.mk b/obj_files.mk index 80a2230..97e4584 100644 --- a/obj_files.mk +++ b/obj_files.mk @@ -71,9 +71,22 @@ TEXT_O_FILES := \ $(BUILD_DIR)/asm/MSL_C/PPC_EABI/math_ppc.o \ $(BUILD_DIR)/asm/MSL_C/MSL_Common_Embedded/Math/w_sqrt.o \ $(BUILD_DIR)/asm/MetroTRK/mainloop.o \ - $(BUILD_DIR)/asm/text_6.o \ + $(BUILD_DIR)/asm/MetroTRK/nubevent.o \ + $(BUILD_DIR)/asm/MetroTRK/nubinit.o \ + $(BUILD_DIR)/asm/MetroTRK/msg.o \ + $(BUILD_DIR)/asm/MetroTRK/msgbuf.o \ + $(BUILD_DIR)/asm/MetroTRK/serpoll.o \ + $(BUILD_DIR)/asm/MetroTRK/usr_put.o \ + $(BUILD_DIR)/asm/MetroTRK/dispatch.o \ + $(BUILD_DIR)/asm/MetroTRK/msghndlr.o \ + $(BUILD_DIR)/asm/MetroTRK/support.o \ + $(BUILD_DIR)/asm/MetroTRK/mutex_TRK.o \ + $(BUILD_DIR)/asm/MetroTRK/notify.o \ + $(BUILD_DIR)/asm/MetroTRK/flush_cache.o \ $(BUILD_DIR)/asm/MetroTRK/mem_TRK.o \ $(BUILD_DIR)/asm/init.o \ + $(BUILD_DIR)/asm/MetroTRK/string_TRK.o \ + $(BUILD_DIR)/asm/MetroTRK/targimpl.o \ $(BUILD_DIR)/asm/text_6_2.o \ $(BUILD_DIR)/asm/text_7.o \ $(BUILD_DIR)/asm/SDK/OS/OS.o \ |