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-rw-r--r--asm/MetroTRK/flush_cache.s21
-rw-r--r--asm/MetroTRK/msgbuf.s14
-rw-r--r--asm/MetroTRK/mutex_TRK.s18
-rw-r--r--asm/MetroTRK/notify.s (renamed from asm/text_6.s)129
-rw-r--r--asm/MetroTRK/nubevent.s14
-rw-r--r--obj_files.mk4
6 files changed, 104 insertions, 96 deletions
diff --git a/asm/MetroTRK/flush_cache.s b/asm/MetroTRK/flush_cache.s
new file mode 100644
index 0000000..28802b1
--- /dev/null
+++ b/asm/MetroTRK/flush_cache.s
@@ -0,0 +1,21 @@
+.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRK_flush_cache
+TRK_flush_cache:
+/* 801D7104 001D2D64 3C A0 FF FF */ lis r5, 0xFFFFFFF1@h
+/* 801D7108 001D2D68 60 A5 FF F1 */ ori r5, r5, 0xFFFFFFF1@l
+/* 801D710C 001D2D6C 7C A5 18 38 */ and r5, r5, r3
+/* 801D7110 001D2D70 7C 65 18 50 */ subf r3, r5, r3
+/* 801D7114 001D2D74 7C 84 1A 14 */ add r4, r4, r3
+lbl_801D7118:
+/* 801D7118 001D2D78 7C 00 28 6C */ dcbst 0, r5
+/* 801D711C 001D2D7C 7C 00 28 AC */ dcbf 0, r5
+/* 801D7120 001D2D80 7C 00 04 AC */ sync 0
+/* 801D7124 001D2D84 7C 00 2F AC */ icbi 0, r5
+/* 801D7128 001D2D88 30 A5 00 08 */ addic r5, r5, 8
+/* 801D712C 001D2D8C 34 84 FF F8 */ addic. r4, r4, -8
+/* 801D7130 001D2D90 40 80 FF E8 */ bge lbl_801D7118
+/* 801D7134 001D2D94 4C 00 01 2C */ isync
+/* 801D7138 001D2D98 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/msgbuf.s b/asm/MetroTRK/msgbuf.s
index 0d5085f..c1e7092 100644
--- a/asm/MetroTRK/msgbuf.s
+++ b/asm/MetroTRK/msgbuf.s
@@ -505,11 +505,11 @@ TRKReleaseBuffer:
/* 801D53A8 001D1008 38 03 EE 20 */ addi r0, r3, lbl_8048EE20@l
/* 801D53AC 001D100C 7F E0 22 14 */ add r31, r0, r4
/* 801D53B0 001D1010 7F E3 FB 78 */ mr r3, r31
-/* 801D53B4 001D1014 48 00 1C A9 */ bl func_801D705C
+/* 801D53B4 001D1014 48 00 1C A9 */ bl TRKAcquireMutex
/* 801D53B8 001D1018 38 00 00 00 */ li r0, 0
/* 801D53BC 001D101C 7F E3 FB 78 */ mr r3, r31
/* 801D53C0 001D1020 90 1F 00 04 */ stw r0, 4(r31)
-/* 801D53C4 001D1024 48 00 1C 91 */ bl func_801D7054
+/* 801D53C4 001D1024 48 00 1C 91 */ bl TRKReleaseMutex
lbl_801D53C8:
/* 801D53C8 001D1028 80 01 00 14 */ lwz r0, 0x14(r1)
/* 801D53CC 001D102C 83 E1 00 0C */ lwz r31, 0xc(r1)
@@ -557,7 +557,7 @@ lbl_801D5434:
/* 801D5454 001D10B4 7F E0 22 14 */ add r31, r0, r4
lbl_801D5458:
/* 801D5458 001D10B8 7F E3 FB 78 */ mr r3, r31
-/* 801D545C 001D10BC 48 00 1C 01 */ bl func_801D705C
+/* 801D545C 001D10BC 48 00 1C 01 */ bl TRKAcquireMutex
/* 801D5460 001D10C0 80 1F 00 04 */ lwz r0, 4(r31)
/* 801D5464 001D10C4 2C 00 00 00 */ cmpwi r0, 0
/* 801D5468 001D10C8 40 82 00 28 */ bne lbl_801D5490
@@ -572,7 +572,7 @@ lbl_801D5458:
/* 801D548C 001D10EC 3B A0 00 03 */ li r29, 3
lbl_801D5490:
/* 801D5490 001D10F0 7F E3 FB 78 */ mr r3, r31
-/* 801D5494 001D10F4 48 00 1B C1 */ bl func_801D7054
+/* 801D5494 001D10F4 48 00 1B C1 */ bl TRKReleaseMutex
/* 801D5498 001D10F8 3B BD 00 01 */ addi r29, r29, 1
lbl_801D549C:
/* 801D549C 001D10FC 2C 1D 00 03 */ cmpwi r29, 3
@@ -604,12 +604,12 @@ TRKInitializeMessageBuffers:
/* 801D54F4 001D1154 3B A0 00 00 */ li r29, 0
lbl_801D54F8:
/* 801D54F8 001D1158 7F C3 F3 78 */ mr r3, r30
-/* 801D54FC 001D115C 48 00 1B 69 */ bl func_801D7064
+/* 801D54FC 001D115C 48 00 1B 69 */ bl TRKInitializeMutex
/* 801D5500 001D1160 7F C3 F3 78 */ mr r3, r30
-/* 801D5504 001D1164 48 00 1B 59 */ bl func_801D705C
+/* 801D5504 001D1164 48 00 1B 59 */ bl TRKAcquireMutex
/* 801D5508 001D1168 93 FE 00 04 */ stw r31, 4(r30)
/* 801D550C 001D116C 7F C3 F3 78 */ mr r3, r30
-/* 801D5510 001D1170 48 00 1B 45 */ bl func_801D7054
+/* 801D5510 001D1170 48 00 1B 45 */ bl TRKReleaseMutex
/* 801D5514 001D1174 3B BD 00 01 */ addi r29, r29, 1
/* 801D5518 001D1178 3B DE 08 90 */ addi r30, r30, 0x890
/* 801D551C 001D117C 2C 1D 00 03 */ cmpwi r29, 3
diff --git a/asm/MetroTRK/mutex_TRK.s b/asm/MetroTRK/mutex_TRK.s
new file mode 100644
index 0000000..47edac7
--- /dev/null
+++ b/asm/MetroTRK/mutex_TRK.s
@@ -0,0 +1,18 @@
+.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKReleaseMutex
+TRKReleaseMutex:
+/* 801D7054 001D2CB4 38 60 00 00 */ li r3, 0
+/* 801D7058 001D2CB8 4E 80 00 20 */ blr
+
+.global TRKAcquireMutex
+TRKAcquireMutex:
+/* 801D705C 001D2CBC 38 60 00 00 */ li r3, 0
+/* 801D7060 001D2CC0 4E 80 00 20 */ blr
+
+.global TRKInitializeMutex
+TRKInitializeMutex:
+/* 801D7064 001D2CC4 38 60 00 00 */ li r3, 0
+/* 801D7068 001D2CC8 4E 80 00 20 */ blr
diff --git a/asm/text_6.s b/asm/MetroTRK/notify.s
index 931df7e..944d25a 100644
--- a/asm/text_6.s
+++ b/asm/MetroTRK/notify.s
@@ -1,81 +1,48 @@
-.include "macros.inc"
-
-.section .text, "ax" # 0x80006980 - 0x803E1E60
-
-.global func_801D7054
-func_801D7054:
-/* 801D7054 001D2CB4 38 60 00 00 */ li r3, 0
-/* 801D7058 001D2CB8 4E 80 00 20 */ blr
-
-.global func_801D705C
-func_801D705C:
-/* 801D705C 001D2CBC 38 60 00 00 */ li r3, 0
-/* 801D7060 001D2CC0 4E 80 00 20 */ blr
-
-.global func_801D7064
-func_801D7064:
-/* 801D7064 001D2CC4 38 60 00 00 */ li r3, 0
-/* 801D7068 001D2CC8 4E 80 00 20 */ blr
-
-.global TRKDoNotifyStopped
-TRKDoNotifyStopped:
-/* 801D706C 001D2CCC 94 21 FF E0 */ stwu r1, -0x20(r1)
-/* 801D7070 001D2CD0 7C 08 02 A6 */ mflr r0
-/* 801D7074 001D2CD4 90 01 00 24 */ stw r0, 0x24(r1)
-/* 801D7078 001D2CD8 38 81 00 08 */ addi r4, r1, 8
-/* 801D707C 001D2CDC 93 E1 00 1C */ stw r31, 0x1c(r1)
-/* 801D7080 001D2CE0 93 C1 00 18 */ stw r30, 0x18(r1)
-/* 801D7084 001D2CE4 7C 7E 1B 78 */ mr r30, r3
-/* 801D7088 001D2CE8 38 61 00 0C */ addi r3, r1, 0xc
-/* 801D708C 001D2CEC 4B FF E3 7D */ bl TRKGetFreeBuffer
-/* 801D7090 001D2CF0 7C 7F 1B 79 */ or. r31, r3, r3
-/* 801D7094 001D2CF4 40 82 00 54 */ bne lbl_801D70E8
-/* 801D7098 001D2CF8 40 82 00 20 */ bne lbl_801D70B8
-/* 801D709C 001D2CFC 2C 1E 00 90 */ cmpwi r30, 0x90
-/* 801D70A0 001D2D00 40 82 00 10 */ bne lbl_801D70B0
-/* 801D70A4 001D2D04 80 61 00 08 */ lwz r3, 8(r1)
-/* 801D70A8 001D2D08 48 00 09 09 */ bl TRKTargetAddStopInfo
-/* 801D70AC 001D2D0C 48 00 00 0C */ b lbl_801D70B8
-lbl_801D70B0:
-/* 801D70B0 001D2D10 80 61 00 08 */ lwz r3, 8(r1)
-/* 801D70B4 001D2D14 48 00 08 79 */ bl TRKTargetAddExceptionInfo
-lbl_801D70B8:
-/* 801D70B8 001D2D18 80 61 00 08 */ lwz r3, 8(r1)
-/* 801D70BC 001D2D1C 38 81 00 10 */ addi r4, r1, 0x10
-/* 801D70C0 001D2D20 38 A0 00 02 */ li r5, 2
-/* 801D70C4 001D2D24 38 C0 00 03 */ li r6, 3
-/* 801D70C8 001D2D28 38 E0 00 01 */ li r7, 1
-/* 801D70CC 001D2D2C 4B FF FB E9 */ bl TRKRequestSend
-/* 801D70D0 001D2D30 7C 7F 1B 79 */ or. r31, r3, r3
-/* 801D70D4 001D2D34 40 82 00 0C */ bne lbl_801D70E0
-/* 801D70D8 001D2D38 80 61 00 10 */ lwz r3, 0x10(r1)
-/* 801D70DC 001D2D3C 4B FF E2 9D */ bl TRKReleaseBuffer
-lbl_801D70E0:
-/* 801D70E0 001D2D40 80 61 00 0C */ lwz r3, 0xc(r1)
-/* 801D70E4 001D2D44 4B FF E2 95 */ bl TRKReleaseBuffer
-lbl_801D70E8:
-/* 801D70E8 001D2D48 80 01 00 24 */ lwz r0, 0x24(r1)
-/* 801D70EC 001D2D4C 7F E3 FB 78 */ mr r3, r31
-/* 801D70F0 001D2D50 83 E1 00 1C */ lwz r31, 0x1c(r1)
-/* 801D70F4 001D2D54 83 C1 00 18 */ lwz r30, 0x18(r1)
-/* 801D70F8 001D2D58 7C 08 03 A6 */ mtlr r0
-/* 801D70FC 001D2D5C 38 21 00 20 */ addi r1, r1, 0x20
-/* 801D7100 001D2D60 4E 80 00 20 */ blr
-
-.global TRK_flush_cache
-TRK_flush_cache:
-/* 801D7104 001D2D64 3C A0 FF FF */ lis r5, 0xFFFFFFF1@h
-/* 801D7108 001D2D68 60 A5 FF F1 */ ori r5, r5, 0xFFFFFFF1@l
-/* 801D710C 001D2D6C 7C A5 18 38 */ and r5, r5, r3
-/* 801D7110 001D2D70 7C 65 18 50 */ subf r3, r5, r3
-/* 801D7114 001D2D74 7C 84 1A 14 */ add r4, r4, r3
-lbl_801D7118:
-/* 801D7118 001D2D78 7C 00 28 6C */ dcbst 0, r5
-/* 801D711C 001D2D7C 7C 00 28 AC */ dcbf 0, r5
-/* 801D7120 001D2D80 7C 00 04 AC */ sync 0
-/* 801D7124 001D2D84 7C 00 2F AC */ icbi 0, r5
-/* 801D7128 001D2D88 30 A5 00 08 */ addic r5, r5, 8
-/* 801D712C 001D2D8C 34 84 FF F8 */ addic. r4, r4, -8
-/* 801D7130 001D2D90 40 80 FF E8 */ bge lbl_801D7118
-/* 801D7134 001D2D94 4C 00 01 2C */ isync
-/* 801D7138 001D2D98 4E 80 00 20 */ blr
+.include "macros.inc"
+
+.section .text, "ax" # 0x80006980 - 0x803E1E60
+
+.global TRKDoNotifyStopped
+TRKDoNotifyStopped:
+/* 801D706C 001D2CCC 94 21 FF E0 */ stwu r1, -0x20(r1)
+/* 801D7070 001D2CD0 7C 08 02 A6 */ mflr r0
+/* 801D7074 001D2CD4 90 01 00 24 */ stw r0, 0x24(r1)
+/* 801D7078 001D2CD8 38 81 00 08 */ addi r4, r1, 8
+/* 801D707C 001D2CDC 93 E1 00 1C */ stw r31, 0x1c(r1)
+/* 801D7080 001D2CE0 93 C1 00 18 */ stw r30, 0x18(r1)
+/* 801D7084 001D2CE4 7C 7E 1B 78 */ mr r30, r3
+/* 801D7088 001D2CE8 38 61 00 0C */ addi r3, r1, 0xc
+/* 801D708C 001D2CEC 4B FF E3 7D */ bl TRKGetFreeBuffer
+/* 801D7090 001D2CF0 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D7094 001D2CF4 40 82 00 54 */ bne lbl_801D70E8
+/* 801D7098 001D2CF8 40 82 00 20 */ bne lbl_801D70B8
+/* 801D709C 001D2CFC 2C 1E 00 90 */ cmpwi r30, 0x90
+/* 801D70A0 001D2D00 40 82 00 10 */ bne lbl_801D70B0
+/* 801D70A4 001D2D04 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D70A8 001D2D08 48 00 09 09 */ bl TRKTargetAddStopInfo
+/* 801D70AC 001D2D0C 48 00 00 0C */ b lbl_801D70B8
+lbl_801D70B0:
+/* 801D70B0 001D2D10 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D70B4 001D2D14 48 00 08 79 */ bl TRKTargetAddExceptionInfo
+lbl_801D70B8:
+/* 801D70B8 001D2D18 80 61 00 08 */ lwz r3, 8(r1)
+/* 801D70BC 001D2D1C 38 81 00 10 */ addi r4, r1, 0x10
+/* 801D70C0 001D2D20 38 A0 00 02 */ li r5, 2
+/* 801D70C4 001D2D24 38 C0 00 03 */ li r6, 3
+/* 801D70C8 001D2D28 38 E0 00 01 */ li r7, 1
+/* 801D70CC 001D2D2C 4B FF FB E9 */ bl TRKRequestSend
+/* 801D70D0 001D2D30 7C 7F 1B 79 */ or. r31, r3, r3
+/* 801D70D4 001D2D34 40 82 00 0C */ bne lbl_801D70E0
+/* 801D70D8 001D2D38 80 61 00 10 */ lwz r3, 0x10(r1)
+/* 801D70DC 001D2D3C 4B FF E2 9D */ bl TRKReleaseBuffer
+lbl_801D70E0:
+/* 801D70E0 001D2D40 80 61 00 0C */ lwz r3, 0xc(r1)
+/* 801D70E4 001D2D44 4B FF E2 95 */ bl TRKReleaseBuffer
+lbl_801D70E8:
+/* 801D70E8 001D2D48 80 01 00 24 */ lwz r0, 0x24(r1)
+/* 801D70EC 001D2D4C 7F E3 FB 78 */ mr r3, r31
+/* 801D70F0 001D2D50 83 E1 00 1C */ lwz r31, 0x1c(r1)
+/* 801D70F4 001D2D54 83 C1 00 18 */ lwz r30, 0x18(r1)
+/* 801D70F8 001D2D58 7C 08 03 A6 */ mtlr r0
+/* 801D70FC 001D2D5C 38 21 00 20 */ addi r1, r1, 0x20
+/* 801D7100 001D2D60 4E 80 00 20 */ blr
diff --git a/asm/MetroTRK/nubevent.s b/asm/MetroTRK/nubevent.s
index c9a27fa..b0fb0b0 100644
--- a/asm/MetroTRK/nubevent.s
+++ b/asm/MetroTRK/nubevent.s
@@ -35,7 +35,7 @@ TRKPostEvent:
/* 801D4988 001D05E8 93 A1 00 14 */ stw r29, 0x14(r1)
/* 801D498C 001D05EC 7C 7D 1B 78 */ mr r29, r3
/* 801D4990 001D05F0 38 64 ED F0 */ addi r3, r4, lbl_8048EDF0@l
-/* 801D4994 001D05F4 48 00 26 C9 */ bl func_801D705C
+/* 801D4994 001D05F4 48 00 26 C9 */ bl TRKAcquireMutex
/* 801D4998 001D05F8 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D499C 001D05FC 3B C3 ED F0 */ addi r30, r3, lbl_8048EDF0@l
/* 801D49A0 001D0600 80 7E 00 04 */ lwz r3, 4(r30)
@@ -75,7 +75,7 @@ lbl_801D4A14:
lbl_801D4A20:
/* 801D4A20 001D0680 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4A24 001D0684 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
-/* 801D4A28 001D0688 48 00 26 2D */ bl func_801D7054
+/* 801D4A28 001D0688 48 00 26 2D */ bl TRKReleaseMutex
/* 801D4A2C 001D068C 80 01 00 24 */ lwz r0, 0x24(r1)
/* 801D4A30 001D0690 7F E3 FB 78 */ mr r3, r31
/* 801D4A34 001D0694 83 E1 00 1C */ lwz r31, 0x1c(r1)
@@ -97,7 +97,7 @@ TRKGetNextEvent:
/* 801D4A68 001D06C8 93 A1 00 14 */ stw r29, 0x14(r1)
/* 801D4A6C 001D06CC 7C 7D 1B 78 */ mr r29, r3
/* 801D4A70 001D06D0 38 64 ED F0 */ addi r3, r4, lbl_8048EDF0@l
-/* 801D4A74 001D06D4 48 00 25 E9 */ bl func_801D705C
+/* 801D4A74 001D06D4 48 00 25 E9 */ bl TRKAcquireMutex
/* 801D4A78 001D06D8 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4A7C 001D06DC 3B E3 ED F0 */ addi r31, r3, lbl_8048EDF0@l
/* 801D4A80 001D06E0 80 1F 00 04 */ lwz r0, 4(r31)
@@ -125,7 +125,7 @@ lbl_801D4AD0:
lbl_801D4AD4:
/* 801D4AD4 001D0734 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4AD8 001D0738 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
-/* 801D4ADC 001D073C 48 00 25 79 */ bl func_801D7054
+/* 801D4ADC 001D073C 48 00 25 79 */ bl TRKReleaseMutex
/* 801D4AE0 001D0740 80 01 00 24 */ lwz r0, 0x24(r1)
/* 801D4AE4 001D0744 7F C3 F3 78 */ mr r3, r30
/* 801D4AE8 001D0748 83 E1 00 1C */ lwz r31, 0x1c(r1)
@@ -142,10 +142,10 @@ TRKInitializeEventQueue:
/* 801D4B08 001D0768 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4B0C 001D076C 90 01 00 14 */ stw r0, 0x14(r1)
/* 801D4B10 001D0770 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
-/* 801D4B14 001D0774 48 00 25 51 */ bl func_801D7064
+/* 801D4B14 001D0774 48 00 25 51 */ bl TRKInitializeMutex
/* 801D4B18 001D0778 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4B1C 001D077C 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
-/* 801D4B20 001D0780 48 00 25 3D */ bl func_801D705C
+/* 801D4B20 001D0780 48 00 25 3D */ bl TRKAcquireMutex
/* 801D4B24 001D0784 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4B28 001D0788 38 80 00 00 */ li r4, 0
/* 801D4B2C 001D078C 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
@@ -153,7 +153,7 @@ TRKInitializeEventQueue:
/* 801D4B34 001D0794 90 83 00 04 */ stw r4, 4(r3)
/* 801D4B38 001D0798 90 83 00 08 */ stw r4, 8(r3)
/* 801D4B3C 001D079C 90 03 00 24 */ stw r0, 0x24(r3)
-/* 801D4B40 001D07A0 48 00 25 15 */ bl func_801D7054
+/* 801D4B40 001D07A0 48 00 25 15 */ bl TRKReleaseMutex
/* 801D4B44 001D07A4 80 01 00 14 */ lwz r0, 0x14(r1)
/* 801D4B48 001D07A8 38 60 00 00 */ li r3, 0
/* 801D4B4C 001D07AC 7C 08 03 A6 */ mtlr r0
diff --git a/obj_files.mk b/obj_files.mk
index a593b01..5a86c78 100644
--- a/obj_files.mk
+++ b/obj_files.mk
@@ -80,7 +80,9 @@ TEXT_O_FILES := \
$(BUILD_DIR)/asm/MetroTRK/dispatch.o \
$(BUILD_DIR)/asm/MetroTRK/msghndlr.o \
$(BUILD_DIR)/asm/MetroTRK/support.o \
- $(BUILD_DIR)/asm/text_6.o \
+ $(BUILD_DIR)/asm/MetroTRK/mutex_TRK.o \
+ $(BUILD_DIR)/asm/MetroTRK/notify.o \
+ $(BUILD_DIR)/asm/MetroTRK/flush_cache.o \
$(BUILD_DIR)/asm/MetroTRK/mem_TRK.o \
$(BUILD_DIR)/asm/init.o \
$(BUILD_DIR)/asm/text_6_2.o \