From fa4ee0a512a03120599bd41ccb2987a93fb4224d Mon Sep 17 00:00:00 2001 From: Max Date: Wed, 30 Sep 2020 11:06:30 -0400 Subject: add '*' escape sequence to postprocess.py, and split the rest of MetroTRK/ --- asm/MSL_C/PPC_EABI/uart_console_io_gcn.s | 2 +- asm/MetroTRK/CircleBuffer.s | 179 ++++ asm/MetroTRK/MWCriticalSection_gc.s | 34 + asm/MetroTRK/UDP_Stubs.s | 48 + asm/MetroTRK/dolphin_trk.s | 231 +++++ asm/MetroTRK/dolphin_trk_glue.s | 353 ++++++++ asm/MetroTRK/main.s | 229 +++++ asm/MetroTRK/main_TRK.s | 24 + asm/MetroTRK/mpc_7xx_603e.s | 234 +++++ asm/MetroTRK/msg.s | 2 +- asm/MetroTRK/msghndlr.s | 42 +- asm/MetroTRK/mslsupp.s | 117 +++ asm/MetroTRK/serpoll.s | 6 +- asm/MetroTRK/support.s | 2 +- asm/MetroTRK/targcont.s | 19 + asm/MetroTRK/target_options.s | 16 + asm/MetroTRK/targimpl.s | 13 +- asm/SDK/OS/OS.s | 2 +- asm/text_6_2.s | 1424 ------------------------------ obj_files.mk | 11 + tools/postprocess/postprocess.py | 4 +- 21 files changed, 1538 insertions(+), 1454 deletions(-) create mode 100644 asm/MetroTRK/CircleBuffer.s create mode 100644 asm/MetroTRK/MWCriticalSection_gc.s create mode 100644 asm/MetroTRK/UDP_Stubs.s create mode 100644 asm/MetroTRK/dolphin_trk.s create mode 100644 asm/MetroTRK/dolphin_trk_glue.s create mode 100644 asm/MetroTRK/main.s create mode 100644 asm/MetroTRK/main_TRK.s create mode 100644 asm/MetroTRK/mpc_7xx_603e.s create mode 100644 asm/MetroTRK/mslsupp.s create mode 100644 asm/MetroTRK/targcont.s create mode 100644 asm/MetroTRK/target_options.s diff --git a/asm/MSL_C/PPC_EABI/uart_console_io_gcn.s b/asm/MSL_C/PPC_EABI/uart_console_io_gcn.s index eeda9eb..952501d 100644 --- a/asm/MSL_C/PPC_EABI/uart_console_io_gcn.s +++ b/asm/MSL_C/PPC_EABI/uart_console_io_gcn.s @@ -49,7 +49,7 @@ lbl_801D0980: /* 801D0984 001CC5E4 7F A4 EB 78 */ mr r4, r29 /* 801D0988 001CC5E8 7F C5 F3 78 */ mr r5, r30 /* 801D098C 001CC5EC 7F E6 FB 78 */ mr r6, r31 -/* 801D0990 001CC5F0 48 00 86 31 */ bl func_801D8FC0 +/* 801D0990 001CC5F0 48 00 86 31 */ bl __TRK_write_console /* 801D0994 001CC5F4 38 60 00 00 */ li r3, 0 lbl_801D0998: /* 801D0998 001CC5F8 80 01 00 24 */ lwz r0, 0x24(r1) diff --git a/asm/MetroTRK/CircleBuffer.s b/asm/MetroTRK/CircleBuffer.s new file mode 100644 index 0000000..dfd6813 --- /dev/null +++ b/asm/MetroTRK/CircleBuffer.s @@ -0,0 +1,179 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global CircleBufferReadBytes +CircleBufferReadBytes: +/* 801D9CB0 001D5910 94 21 FF E0 */ stwu r1, -0x20(r1) +/* 801D9CB4 001D5914 7C 08 02 A6 */ mflr r0 +/* 801D9CB8 001D5918 90 01 00 24 */ stw r0, 0x24(r1) +/* 801D9CBC 001D591C 93 E1 00 1C */ stw r31, 0x1c(r1) +/* 801D9CC0 001D5920 7C BF 2B 78 */ mr r31, r5 +/* 801D9CC4 001D5924 93 C1 00 18 */ stw r30, 0x18(r1) +/* 801D9CC8 001D5928 7C 7E 1B 78 */ mr r30, r3 +/* 801D9CCC 001D592C 93 A1 00 14 */ stw r29, 0x14(r1) +/* 801D9CD0 001D5930 93 81 00 10 */ stw r28, 0x10(r1) +/* 801D9CD4 001D5934 7C 9C 23 78 */ mr r28, r4 +/* 801D9CD8 001D5938 80 03 00 10 */ lwz r0, 0x10(r3) +/* 801D9CDC 001D593C 7C 1F 00 40 */ cmplw r31, r0 +/* 801D9CE0 001D5940 40 81 00 0C */ ble lbl_801D9CEC +/* 801D9CE4 001D5944 38 60 FF FF */ li r3, -1 +/* 801D9CE8 001D5948 48 00 00 B0 */ b lbl_801D9D98 +lbl_801D9CEC: +/* 801D9CEC 001D594C 38 7E 00 18 */ addi r3, r30, 0x18 +/* 801D9CF0 001D5950 48 00 02 4D */ bl MWEnterCriticalSection +/* 801D9CF4 001D5954 80 7E 00 08 */ lwz r3, 8(r30) +/* 801D9CF8 001D5958 80 9E 00 00 */ lwz r4, 0(r30) +/* 801D9CFC 001D595C 80 1E 00 0C */ lwz r0, 0xc(r30) +/* 801D9D00 001D5960 7C 63 20 50 */ subf r3, r3, r4 +/* 801D9D04 001D5964 7F A3 00 50 */ subf r29, r3, r0 +/* 801D9D08 001D5968 7C 1F E8 40 */ cmplw r31, r29 +/* 801D9D0C 001D596C 40 80 00 20 */ bge lbl_801D9D2C +/* 801D9D10 001D5970 7F 83 E3 78 */ mr r3, r28 +/* 801D9D14 001D5974 7F E5 FB 78 */ mr r5, r31 +/* 801D9D18 001D5978 4B E2 A2 E9 */ bl memcpy +/* 801D9D1C 001D597C 80 1E 00 00 */ lwz r0, 0(r30) +/* 801D9D20 001D5980 7C 00 FA 14 */ add r0, r0, r31 +/* 801D9D24 001D5984 90 1E 00 00 */ stw r0, 0(r30) +/* 801D9D28 001D5988 48 00 00 30 */ b lbl_801D9D58 +lbl_801D9D2C: +/* 801D9D2C 001D598C 7F 83 E3 78 */ mr r3, r28 +/* 801D9D30 001D5990 7F A5 EB 78 */ mr r5, r29 +/* 801D9D34 001D5994 4B E2 A2 CD */ bl memcpy +/* 801D9D38 001D5998 80 9E 00 08 */ lwz r4, 8(r30) +/* 801D9D3C 001D599C 7C 7C EA 14 */ add r3, r28, r29 +/* 801D9D40 001D59A0 7C BD F8 50 */ subf r5, r29, r31 +/* 801D9D44 001D59A4 4B E2 A2 BD */ bl memcpy +/* 801D9D48 001D59A8 80 1E 00 08 */ lwz r0, 8(r30) +/* 801D9D4C 001D59AC 7C 00 FA 14 */ add r0, r0, r31 +/* 801D9D50 001D59B0 7C 1D 00 50 */ subf r0, r29, r0 +/* 801D9D54 001D59B4 90 1E 00 00 */ stw r0, 0(r30) +lbl_801D9D58: +/* 801D9D58 001D59B8 80 9E 00 08 */ lwz r4, 8(r30) +/* 801D9D5C 001D59BC 80 1E 00 00 */ lwz r0, 0(r30) +/* 801D9D60 001D59C0 80 7E 00 0C */ lwz r3, 0xc(r30) +/* 801D9D64 001D59C4 7C 04 00 50 */ subf r0, r4, r0 +/* 801D9D68 001D59C8 7C 03 00 40 */ cmplw r3, r0 +/* 801D9D6C 001D59CC 40 82 00 08 */ bne lbl_801D9D74 +/* 801D9D70 001D59D0 90 9E 00 00 */ stw r4, 0(r30) +lbl_801D9D74: +/* 801D9D74 001D59D4 80 1E 00 14 */ lwz r0, 0x14(r30) +/* 801D9D78 001D59D8 38 7E 00 18 */ addi r3, r30, 0x18 +/* 801D9D7C 001D59DC 7C 00 FA 14 */ add r0, r0, r31 +/* 801D9D80 001D59E0 90 1E 00 14 */ stw r0, 0x14(r30) +/* 801D9D84 001D59E4 80 1E 00 10 */ lwz r0, 0x10(r30) +/* 801D9D88 001D59E8 7C 1F 00 50 */ subf r0, r31, r0 +/* 801D9D8C 001D59EC 90 1E 00 10 */ stw r0, 0x10(r30) +/* 801D9D90 001D59F0 48 00 01 89 */ bl MWExitCriticalSection +/* 801D9D94 001D59F4 38 60 00 00 */ li r3, 0 +lbl_801D9D98: +/* 801D9D98 001D59F8 80 01 00 24 */ lwz r0, 0x24(r1) +/* 801D9D9C 001D59FC 83 E1 00 1C */ lwz r31, 0x1c(r1) +/* 801D9DA0 001D5A00 83 C1 00 18 */ lwz r30, 0x18(r1) +/* 801D9DA4 001D5A04 83 A1 00 14 */ lwz r29, 0x14(r1) +/* 801D9DA8 001D5A08 83 81 00 10 */ lwz r28, 0x10(r1) +/* 801D9DAC 001D5A0C 7C 08 03 A6 */ mtlr r0 +/* 801D9DB0 001D5A10 38 21 00 20 */ addi r1, r1, 0x20 +/* 801D9DB4 001D5A14 4E 80 00 20 */ blr + +.global CircleBufferWriteBytes +CircleBufferWriteBytes: +/* 801D9DB8 001D5A18 94 21 FF E0 */ stwu r1, -0x20(r1) +/* 801D9DBC 001D5A1C 7C 08 02 A6 */ mflr r0 +/* 801D9DC0 001D5A20 90 01 00 24 */ stw r0, 0x24(r1) +/* 801D9DC4 001D5A24 93 E1 00 1C */ stw r31, 0x1c(r1) +/* 801D9DC8 001D5A28 7C BF 2B 78 */ mr r31, r5 +/* 801D9DCC 001D5A2C 93 C1 00 18 */ stw r30, 0x18(r1) +/* 801D9DD0 001D5A30 7C 7E 1B 78 */ mr r30, r3 +/* 801D9DD4 001D5A34 93 A1 00 14 */ stw r29, 0x14(r1) +/* 801D9DD8 001D5A38 93 81 00 10 */ stw r28, 0x10(r1) +/* 801D9DDC 001D5A3C 7C 9C 23 78 */ mr r28, r4 +/* 801D9DE0 001D5A40 80 03 00 14 */ lwz r0, 0x14(r3) +/* 801D9DE4 001D5A44 7C 1F 00 40 */ cmplw r31, r0 +/* 801D9DE8 001D5A48 40 81 00 0C */ ble lbl_801D9DF4 +/* 801D9DEC 001D5A4C 38 60 FF FF */ li r3, -1 +/* 801D9DF0 001D5A50 48 00 00 B0 */ b lbl_801D9EA0 +lbl_801D9DF4: +/* 801D9DF4 001D5A54 38 7E 00 18 */ addi r3, r30, 0x18 +/* 801D9DF8 001D5A58 48 00 01 45 */ bl MWEnterCriticalSection +/* 801D9DFC 001D5A5C 80 9E 00 08 */ lwz r4, 8(r30) +/* 801D9E00 001D5A60 80 7E 00 04 */ lwz r3, 4(r30) +/* 801D9E04 001D5A64 80 1E 00 0C */ lwz r0, 0xc(r30) +/* 801D9E08 001D5A68 7C 84 18 50 */ subf r4, r4, r3 +/* 801D9E0C 001D5A6C 7F A4 00 50 */ subf r29, r4, r0 +/* 801D9E10 001D5A70 7C 1D F8 40 */ cmplw r29, r31 +/* 801D9E14 001D5A74 41 80 00 20 */ blt lbl_801D9E34 +/* 801D9E18 001D5A78 7F 84 E3 78 */ mr r4, r28 +/* 801D9E1C 001D5A7C 7F E5 FB 78 */ mr r5, r31 +/* 801D9E20 001D5A80 4B E2 A1 E1 */ bl memcpy +/* 801D9E24 001D5A84 80 1E 00 04 */ lwz r0, 4(r30) +/* 801D9E28 001D5A88 7C 00 FA 14 */ add r0, r0, r31 +/* 801D9E2C 001D5A8C 90 1E 00 04 */ stw r0, 4(r30) +/* 801D9E30 001D5A90 48 00 00 30 */ b lbl_801D9E60 +lbl_801D9E34: +/* 801D9E34 001D5A94 7F 84 E3 78 */ mr r4, r28 +/* 801D9E38 001D5A98 7F A5 EB 78 */ mr r5, r29 +/* 801D9E3C 001D5A9C 4B E2 A1 C5 */ bl memcpy +/* 801D9E40 001D5AA0 80 7E 00 08 */ lwz r3, 8(r30) +/* 801D9E44 001D5AA4 7C 9C EA 14 */ add r4, r28, r29 +/* 801D9E48 001D5AA8 7C BD F8 50 */ subf r5, r29, r31 +/* 801D9E4C 001D5AAC 4B E2 A1 B5 */ bl memcpy +/* 801D9E50 001D5AB0 80 1E 00 08 */ lwz r0, 8(r30) +/* 801D9E54 001D5AB4 7C 00 FA 14 */ add r0, r0, r31 +/* 801D9E58 001D5AB8 7C 1D 00 50 */ subf r0, r29, r0 +/* 801D9E5C 001D5ABC 90 1E 00 04 */ stw r0, 4(r30) +lbl_801D9E60: +/* 801D9E60 001D5AC0 80 9E 00 08 */ lwz r4, 8(r30) +/* 801D9E64 001D5AC4 80 1E 00 04 */ lwz r0, 4(r30) +/* 801D9E68 001D5AC8 80 7E 00 0C */ lwz r3, 0xc(r30) +/* 801D9E6C 001D5ACC 7C 04 00 50 */ subf r0, r4, r0 +/* 801D9E70 001D5AD0 7C 03 00 40 */ cmplw r3, r0 +/* 801D9E74 001D5AD4 40 82 00 08 */ bne lbl_801D9E7C +/* 801D9E78 001D5AD8 90 9E 00 04 */ stw r4, 4(r30) +lbl_801D9E7C: +/* 801D9E7C 001D5ADC 80 1E 00 14 */ lwz r0, 0x14(r30) +/* 801D9E80 001D5AE0 38 7E 00 18 */ addi r3, r30, 0x18 +/* 801D9E84 001D5AE4 7C 1F 00 50 */ subf r0, r31, r0 +/* 801D9E88 001D5AE8 90 1E 00 14 */ stw r0, 0x14(r30) +/* 801D9E8C 001D5AEC 80 1E 00 10 */ lwz r0, 0x10(r30) +/* 801D9E90 001D5AF0 7C 00 FA 14 */ add r0, r0, r31 +/* 801D9E94 001D5AF4 90 1E 00 10 */ stw r0, 0x10(r30) +/* 801D9E98 001D5AF8 48 00 00 81 */ bl MWExitCriticalSection +/* 801D9E9C 001D5AFC 38 60 00 00 */ li r3, 0 +lbl_801D9EA0: +/* 801D9EA0 001D5B00 80 01 00 24 */ lwz r0, 0x24(r1) +/* 801D9EA4 001D5B04 83 E1 00 1C */ lwz r31, 0x1c(r1) +/* 801D9EA8 001D5B08 83 C1 00 18 */ lwz r30, 0x18(r1) +/* 801D9EAC 001D5B0C 83 A1 00 14 */ lwz r29, 0x14(r1) +/* 801D9EB0 001D5B10 83 81 00 10 */ lwz r28, 0x10(r1) +/* 801D9EB4 001D5B14 7C 08 03 A6 */ mtlr r0 +/* 801D9EB8 001D5B18 38 21 00 20 */ addi r1, r1, 0x20 +/* 801D9EBC 001D5B1C 4E 80 00 20 */ blr + +.global CircleBufferInitialize +CircleBufferInitialize: +/* 801D9EC0 001D5B20 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9EC4 001D5B24 7C 08 02 A6 */ mflr r0 +/* 801D9EC8 001D5B28 7C 66 1B 78 */ mr r6, r3 +/* 801D9ECC 001D5B2C 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9ED0 001D5B30 38 00 00 00 */ li r0, 0 +/* 801D9ED4 001D5B34 90 83 00 08 */ stw r4, 8(r3) +/* 801D9ED8 001D5B38 38 66 00 18 */ addi r3, r6, 0x18 +/* 801D9EDC 001D5B3C 90 A6 00 0C */ stw r5, 0xc(r6) +/* 801D9EE0 001D5B40 80 86 00 08 */ lwz r4, 8(r6) +/* 801D9EE4 001D5B44 90 86 00 00 */ stw r4, 0(r6) +/* 801D9EE8 001D5B48 80 86 00 08 */ lwz r4, 8(r6) +/* 801D9EEC 001D5B4C 90 86 00 04 */ stw r4, 4(r6) +/* 801D9EF0 001D5B50 90 06 00 10 */ stw r0, 0x10(r6) +/* 801D9EF4 001D5B54 80 06 00 0C */ lwz r0, 0xc(r6) +/* 801D9EF8 001D5B58 90 06 00 14 */ stw r0, 0x14(r6) +/* 801D9EFC 001D5B5C 48 00 00 71 */ bl MWInitializeCriticalSection +/* 801D9F00 001D5B60 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9F04 001D5B64 7C 08 03 A6 */ mtlr r0 +/* 801D9F08 001D5B68 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9F0C 001D5B6C 4E 80 00 20 */ blr + +.global CBGetBytesAvailableForRead +CBGetBytesAvailableForRead: +/* 801D9F10 001D5B70 80 63 00 10 */ lwz r3, 0x10(r3) +/* 801D9F14 001D5B74 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/MWCriticalSection_gc.s b/asm/MetroTRK/MWCriticalSection_gc.s new file mode 100644 index 0000000..52de1d3 --- /dev/null +++ b/asm/MetroTRK/MWCriticalSection_gc.s @@ -0,0 +1,34 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global MWExitCriticalSection +MWExitCriticalSection: +/* 801D9F18 001D5B78 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9F1C 001D5B7C 7C 08 02 A6 */ mflr r0 +/* 801D9F20 001D5B80 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9F24 001D5B84 80 63 00 00 */ lwz r3, 0(r3) +/* 801D9F28 001D5B88 48 09 48 5D */ bl OSRestoreInterrupts +/* 801D9F2C 001D5B8C 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9F30 001D5B90 7C 08 03 A6 */ mtlr r0 +/* 801D9F34 001D5B94 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9F38 001D5B98 4E 80 00 20 */ blr + +.global MWEnterCriticalSection +MWEnterCriticalSection: +/* 801D9F3C 001D5B9C 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9F40 001D5BA0 7C 08 02 A6 */ mflr r0 +/* 801D9F44 001D5BA4 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9F48 001D5BA8 93 E1 00 0C */ stw r31, 0xc(r1) +/* 801D9F4C 001D5BAC 7C 7F 1B 78 */ mr r31, r3 +/* 801D9F50 001D5BB0 48 09 48 0D */ bl OSDisableInterrupts +/* 801D9F54 001D5BB4 90 7F 00 00 */ stw r3, 0(r31) +/* 801D9F58 001D5BB8 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9F5C 001D5BBC 83 E1 00 0C */ lwz r31, 0xc(r1) +/* 801D9F60 001D5BC0 7C 08 03 A6 */ mtlr r0 +/* 801D9F64 001D5BC4 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9F68 001D5BC8 4E 80 00 20 */ blr + +.global MWInitializeCriticalSection +MWInitializeCriticalSection: +/* 801D9F6C 001D5BCC 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/UDP_Stubs.s b/asm/MetroTRK/UDP_Stubs.s new file mode 100644 index 0000000..69d1fb2 --- /dev/null +++ b/asm/MetroTRK/UDP_Stubs.s @@ -0,0 +1,48 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global udp_cc_post_stop +udp_cc_post_stop: +/* 801D99A8 001D5608 38 60 FF FF */ li r3, -1 +/* 801D99AC 001D560C 4E 80 00 20 */ blr + +.global udp_cc_pre_continue +udp_cc_pre_continue: +/* 801D99B0 001D5610 38 60 FF FF */ li r3, -1 +/* 801D99B4 001D5614 4E 80 00 20 */ blr + +.global udp_cc_peek +udp_cc_peek: +/* 801D99B8 001D5618 38 60 00 00 */ li r3, 0 +/* 801D99BC 001D561C 4E 80 00 20 */ blr + +.global udp_cc_write +udp_cc_write: +/* 801D99C0 001D5620 38 60 00 00 */ li r3, 0 +/* 801D99C4 001D5624 4E 80 00 20 */ blr + +.global udp_cc_read +udp_cc_read: +/* 801D99C8 001D5628 38 60 00 00 */ li r3, 0 +/* 801D99CC 001D562C 4E 80 00 20 */ blr + +.global udp_cc_close +udp_cc_close: +/* 801D99D0 001D5630 38 60 FF FF */ li r3, -1 +/* 801D99D4 001D5634 4E 80 00 20 */ blr + +.global udp_cc_open +udp_cc_open: +/* 801D99D8 001D5638 38 60 FF FF */ li r3, -1 +/* 801D99DC 001D563C 4E 80 00 20 */ blr + +.global udp_cc_shutdown +udp_cc_shutdown: +/* 801D99E0 001D5640 38 60 FF FF */ li r3, -1 +/* 801D99E4 001D5644 4E 80 00 20 */ blr + +.global udp_cc_initialize +udp_cc_initialize: +/* 801D99E8 001D5648 38 60 FF FF */ li r3, -1 +/* 801D99EC 001D564C 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/dolphin_trk.s b/asm/MetroTRK/dolphin_trk.s new file mode 100644 index 0000000..12def87 --- /dev/null +++ b/asm/MetroTRK/dolphin_trk.s @@ -0,0 +1,231 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global InitMetroTRK +InitMetroTRK: +/* 801D9138 001D4D98 38 21 FF FC */ addi r1, r1, -4 +/* 801D913C 001D4D9C 90 61 00 00 */ stw r3, 0(r1) +/* 801D9140 001D4DA0 3C 60 80 49 */ lis r3, lbl_80490898@h +/* 801D9144 001D4DA4 60 63 08 98 */ ori r3, r3, lbl_80490898@l +/* 801D9148 001D4DA8 BC 03 00 00 */ stmw r0, 0(r3) +/* 801D914C 001D4DAC 80 81 00 00 */ lwz r4, 0(r1) +/* 801D9150 001D4DB0 38 21 00 04 */ addi r1, r1, 4 +/* 801D9154 001D4DB4 90 23 00 04 */ stw r1, 4(r3) +/* 801D9158 001D4DB8 90 83 00 0C */ stw r4, 0xc(r3) +/* 801D915C 001D4DBC 7C 88 02 A6 */ mflr r4 +/* 801D9160 001D4DC0 90 83 00 84 */ stw r4, 0x84(r3) +/* 801D9164 001D4DC4 90 83 00 80 */ stw r4, 0x80(r3) +/* 801D9168 001D4DC8 7C 80 00 26 */ mfcr r4 +/* 801D916C 001D4DCC 90 83 00 88 */ stw r4, 0x88(r3) +/* 801D9170 001D4DD0 7C 80 00 A6 */ mfmsr r4 +/* 801D9174 001D4DD4 60 83 80 00 */ ori r3, r4, 0x8000 +/* 801D9178 001D4DD8 68 63 80 00 */ xori r3, r3, 0x8000 +/* 801D917C 001D4DDC 7C 60 01 24 */ mtmsr r3 +/* 801D9180 001D4DE0 7C 9B 03 A6 */ mtspr 0x1b, r4 +/* 801D9184 001D4DE4 4B FF FA CD */ bl TRKSaveExtended1Block +/* 801D9188 001D4DE8 3C 60 80 49 */ lis r3, lbl_80490898@h +/* 801D918C 001D4DEC 60 63 08 98 */ ori r3, r3, lbl_80490898@l +/* 801D9190 001D4DF0 B8 03 00 00 */ .4byte 0xB8030000 /* illegal lmw r0, 0(r3) */ +/* 801D9194 001D4DF4 38 00 00 00 */ li r0, 0 +/* 801D9198 001D4DF8 7C 12 FB A6 */ mtspr 0x3f2, r0 +/* 801D919C 001D4DFC 7C 15 FB A6 */ mtspr 0x3f5, r0 +/* 801D91A0 001D4E00 3C 20 80 65 */ lis r1, 0x80655050@h +/* 801D91A4 001D4E04 60 21 50 50 */ ori r1, r1, 0x80655050@l +/* 801D91A8 001D4E08 7C A3 2B 78 */ mr r3, r5 +/* 801D91AC 001D4E0C 48 00 05 A1 */ bl InitMetroTRKCommTable +/* 801D91B0 001D4E10 2C 03 00 01 */ cmpwi r3, 1 +/* 801D91B4 001D4E14 40 82 00 14 */ bne lbl_801D91C8 +/* 801D91B8 001D4E18 80 83 00 84 */ lwz r4, 0x84(r3) +/* 801D91BC 001D4E1C 7C 88 03 A6 */ mtlr r4 +/* 801D91C0 001D4E20 B8 03 00 00 */ .4byte 0xB8030000 /* illegal lmw r0, 0(r3) */ +/* 801D91C4 001D4E24 4E 80 00 20 */ blr +lbl_801D91C8: +/* 801D91C8 001D4E28 48 00 02 8C */ b TRK_main +/* 801D91CC 001D4E2C 4E 80 00 20 */ blr + +.global InitMetroTRK_BBA +InitMetroTRK_BBA: +/* 801D91D0 001D4E30 38 21 FF FC */ addi r1, r1, -4 +/* 801D91D4 001D4E34 90 61 00 00 */ stw r3, 0(r1) +/* 801D91D8 001D4E38 3C 60 80 49 */ lis r3, lbl_80490898@h +/* 801D91DC 001D4E3C 60 63 08 98 */ ori r3, r3, lbl_80490898@l +/* 801D91E0 001D4E40 BC 03 00 00 */ stmw r0, 0(r3) +/* 801D91E4 001D4E44 80 81 00 00 */ lwz r4, 0(r1) +/* 801D91E8 001D4E48 38 21 00 04 */ addi r1, r1, 4 +/* 801D91EC 001D4E4C 90 23 00 04 */ stw r1, 4(r3) +/* 801D91F0 001D4E50 90 83 00 0C */ stw r4, 0xc(r3) +/* 801D91F4 001D4E54 7C 88 02 A6 */ mflr r4 +/* 801D91F8 001D4E58 90 83 00 84 */ stw r4, 0x84(r3) +/* 801D91FC 001D4E5C 90 83 00 80 */ stw r4, 0x80(r3) +/* 801D9200 001D4E60 7C 80 00 26 */ mfcr r4 +/* 801D9204 001D4E64 90 83 00 88 */ stw r4, 0x88(r3) +/* 801D9208 001D4E68 7C 80 00 A6 */ mfmsr r4 +/* 801D920C 001D4E6C 60 83 80 00 */ ori r3, r4, 0x8000 +/* 801D9210 001D4E70 7C 60 01 24 */ mtmsr r3 +/* 801D9214 001D4E74 7C 9B 03 A6 */ mtspr 0x1b, r4 +/* 801D9218 001D4E78 4B FF FA 39 */ bl TRKSaveExtended1Block +/* 801D921C 001D4E7C 3C 60 80 49 */ lis r3, lbl_80490898@h +/* 801D9220 001D4E80 60 63 08 98 */ ori r3, r3, lbl_80490898@l +/* 801D9224 001D4E84 B8 03 00 00 */ .4byte 0xB8030000 /* illegal lmw r0, 0(r3) */ +/* 801D9228 001D4E88 38 00 00 00 */ li r0, 0 +/* 801D922C 001D4E8C 7C 12 FB A6 */ mtspr 0x3f2, r0 +/* 801D9230 001D4E90 7C 15 FB A6 */ mtspr 0x3f5, r0 +/* 801D9234 001D4E94 3C 20 80 65 */ lis r1, 0x80655050@h +/* 801D9238 001D4E98 60 21 50 50 */ ori r1, r1, 0x80655050@l +/* 801D923C 001D4E9C 38 60 00 02 */ li r3, 2 +/* 801D9240 001D4EA0 48 00 05 0D */ bl InitMetroTRKCommTable +/* 801D9244 001D4EA4 2C 03 00 01 */ cmpwi r3, 1 +/* 801D9248 001D4EA8 40 82 00 14 */ bne lbl_801D925C +/* 801D924C 001D4EAC 80 83 00 84 */ lwz r4, 0x84(r3) +/* 801D9250 001D4EB0 7C 88 03 A6 */ mtlr r4 +/* 801D9254 001D4EB4 B8 03 00 00 */ .4byte 0xB8030000 /* illegal lmw r0, 0(r3) */ +/* 801D9258 001D4EB8 4E 80 00 20 */ blr +lbl_801D925C: +/* 801D925C 001D4EBC 48 00 01 F8 */ b TRK_main +/* 801D9260 001D4EC0 4E 80 00 20 */ blr + +.global TRKInitializeTarget +TRKInitializeTarget: +/* 801D9264 001D4EC4 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9268 001D4EC8 7C 08 02 A6 */ mflr r0 +/* 801D926C 001D4ECC 3C 60 80 49 */ lis r3, lbl_804907F4@ha +/* 801D9270 001D4ED0 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9274 001D4ED4 38 00 00 01 */ li r0, 1 +/* 801D9278 001D4ED8 38 63 07 F4 */ addi r3, r3, lbl_804907F4@l +/* 801D927C 001D4EDC 90 03 00 98 */ stw r0, 0x98(r3) +/* 801D9280 001D4EE0 4B FF DF 91 */ bl __TRK_get_MSR +/* 801D9284 001D4EE4 3C A0 80 49 */ lis r5, lbl_804907F4@ha +/* 801D9288 001D4EE8 3C 80 80 49 */ lis r4, lbl_80490D70@ha +/* 801D928C 001D4EEC 38 A5 07 F4 */ addi r5, r5, lbl_804907F4@l +/* 801D9290 001D4EF0 3C 00 E0 00 */ lis r0, 0xe000 +/* 801D9294 001D4EF4 90 65 00 8C */ stw r3, 0x8c(r5) +/* 801D9298 001D4EF8 38 60 00 00 */ li r3, 0 +/* 801D929C 001D4EFC 90 04 0D 70 */ stw r0, lbl_80490D70@l(r4) +/* 801D92A0 001D4F00 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D92A4 001D4F04 7C 08 03 A6 */ mtlr r0 +/* 801D92A8 001D4F08 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D92AC 001D4F0C 4E 80 00 20 */ blr + +.global __TRK_copy_vectors +__TRK_copy_vectors: +/* 801D92B0 001D4F10 94 21 FF E0 */ stwu r1, -0x20(r1) +/* 801D92B4 001D4F14 7C 08 02 A6 */ mflr r0 +/* 801D92B8 001D4F18 3C 60 80 49 */ lis r3, lbl_80490D70@ha +/* 801D92BC 001D4F1C 90 01 00 24 */ stw r0, 0x24(r1) +/* 801D92C0 001D4F20 38 63 0D 70 */ addi r3, r3, lbl_80490D70@l +/* 801D92C4 001D4F24 BF 61 00 0C */ stmw r27, 0xc(r1) +/* 801D92C8 001D4F28 80 63 00 00 */ lwz r3, 0(r3) +/* 801D92CC 001D4F2C 28 03 00 44 */ cmplwi r3, 0x44 +/* 801D92D0 001D4F30 41 81 00 2C */ bgt lbl_801D92FC +/* 801D92D4 001D4F34 38 03 40 00 */ addi r0, r3, 0x4000 +/* 801D92D8 001D4F38 28 00 00 44 */ cmplwi r0, 0x44 +/* 801D92DC 001D4F3C 40 81 00 20 */ ble lbl_801D92FC +/* 801D92E0 001D4F40 3C 60 80 49 */ lis r3, lbl_80490898@ha +/* 801D92E4 001D4F44 38 63 08 98 */ addi r3, r3, lbl_80490898@l +/* 801D92E8 001D4F48 80 03 02 38 */ lwz r0, 0x238(r3) +/* 801D92EC 001D4F4C 54 00 07 BF */ clrlwi. r0, r0, 0x1e +/* 801D92F0 001D4F50 41 82 00 0C */ beq lbl_801D92FC +/* 801D92F4 001D4F54 38 A0 00 44 */ li r5, 0x44 +/* 801D92F8 001D4F58 48 00 00 0C */ b lbl_801D9304 +lbl_801D92FC: +/* 801D92FC 001D4F5C 3C 60 80 00 */ lis r3, 0x80000044@ha +/* 801D9300 001D4F60 38 A3 00 44 */ addi r5, r3, 0x80000044@l +lbl_801D9304: +/* 801D9304 001D4F64 3C 80 80 42 */ lis r4, lbl_80423260@ha +/* 801D9308 001D4F68 3C 60 80 49 */ lis r3, lbl_80490898@ha +/* 801D930C 001D4F6C 83 A5 00 00 */ lwz r29, 0(r5) +/* 801D9310 001D4F70 3B E4 32 60 */ addi r31, r4, lbl_80423260@l +/* 801D9314 001D4F74 3B 83 08 98 */ addi r28, r3, lbl_80490898@l +/* 801D9318 001D4F78 3B C0 00 00 */ li r30, 0 +lbl_801D931C: +/* 801D931C 001D4F7C 38 00 00 01 */ li r0, 1 +/* 801D9320 001D4F80 7C 00 F0 30 */ slw r0, r0, r30 +/* 801D9324 001D4F84 7F A0 00 39 */ and. r0, r29, r0 +/* 801D9328 001D4F88 41 82 00 90 */ beq lbl_801D93B8 +/* 801D932C 001D4F8C 2C 1E 00 04 */ cmpwi r30, 4 +/* 801D9330 001D4F90 41 82 00 88 */ beq lbl_801D93B8 +/* 801D9334 001D4F94 3C 60 80 49 */ lis r3, lbl_80490D70@ha +/* 801D9338 001D4F98 80 DF 00 00 */ lwz r6, 0(r31) +/* 801D933C 001D4F9C 38 63 0D 70 */ addi r3, r3, lbl_80490D70@l +/* 801D9340 001D4FA0 80 63 00 00 */ lwz r3, 0(r3) +/* 801D9344 001D4FA4 7C 06 18 40 */ cmplw r6, r3 +/* 801D9348 001D4FA8 41 80 00 24 */ blt lbl_801D936C +/* 801D934C 001D4FAC 38 03 40 00 */ addi r0, r3, 0x4000 +/* 801D9350 001D4FB0 7C 06 00 40 */ cmplw r6, r0 +/* 801D9354 001D4FB4 40 80 00 18 */ bge lbl_801D936C +/* 801D9358 001D4FB8 80 1C 02 38 */ lwz r0, 0x238(r28) +/* 801D935C 001D4FBC 54 00 07 BF */ clrlwi. r0, r0, 0x1e +/* 801D9360 001D4FC0 41 82 00 0C */ beq lbl_801D936C +/* 801D9364 001D4FC4 7C DB 33 78 */ mr r27, r6 +/* 801D9368 001D4FC8 48 00 00 2C */ b lbl_801D9394 +lbl_801D936C: +/* 801D936C 001D4FCC 3C 00 7E 00 */ lis r0, 0x7e00 +/* 801D9370 001D4FD0 7C 06 00 40 */ cmplw r6, r0 +/* 801D9374 001D4FD4 41 80 00 18 */ blt lbl_801D938C +/* 801D9378 001D4FD8 3C 00 80 00 */ lis r0, 0x8000 +/* 801D937C 001D4FDC 7C 06 00 40 */ cmplw r6, r0 +/* 801D9380 001D4FE0 41 81 00 0C */ bgt lbl_801D938C +/* 801D9384 001D4FE4 7C DB 33 78 */ mr r27, r6 +/* 801D9388 001D4FE8 48 00 00 0C */ b lbl_801D9394 +lbl_801D938C: +/* 801D938C 001D4FEC 54 C0 00 BE */ clrlwi r0, r6, 2 +/* 801D9390 001D4FF0 64 1B 80 00 */ oris r27, r0, 0x8000 +lbl_801D9394: +/* 801D9394 001D4FF4 3C 80 80 00 */ lis r4, lbl_80004188@ha +/* 801D9398 001D4FF8 7F 63 DB 78 */ mr r3, r27 +/* 801D939C 001D4FFC 38 04 41 88 */ addi r0, r4, lbl_80004188@l +/* 801D93A0 001D5000 38 A0 01 00 */ li r5, 0x100 +/* 801D93A4 001D5004 7C 80 32 14 */ add r4, r0, r6 +/* 801D93A8 001D5008 4B E2 AD BD */ bl TRK_memcpy +/* 801D93AC 001D500C 7F 63 DB 78 */ mr r3, r27 +/* 801D93B0 001D5010 38 80 01 00 */ li r4, 0x100 +/* 801D93B4 001D5014 4B FF DD 51 */ bl TRK_flush_cache +lbl_801D93B8: +/* 801D93B8 001D5018 3B DE 00 01 */ addi r30, r30, 1 +/* 801D93BC 001D501C 3B FF 00 04 */ addi r31, r31, 4 +/* 801D93C0 001D5020 2C 1E 00 0E */ cmpwi r30, 0xe +/* 801D93C4 001D5024 40 81 FF 58 */ ble lbl_801D931C +/* 801D93C8 001D5028 BB 61 00 0C */ lmw r27, 0xc(r1) +/* 801D93CC 001D502C 80 01 00 24 */ lwz r0, 0x24(r1) +/* 801D93D0 001D5030 7C 08 03 A6 */ mtlr r0 +/* 801D93D4 001D5034 38 21 00 20 */ addi r1, r1, 0x20 +/* 801D93D8 001D5038 4E 80 00 20 */ blr + +.global TRKTargetTranslate +TRKTargetTranslate: +/* 801D93DC 001D503C 3C 80 80 49 */ lis r4, lbl_80490D70@ha +/* 801D93E0 001D5040 38 84 0D 70 */ addi r4, r4, lbl_80490D70@l +/* 801D93E4 001D5044 80 84 00 00 */ lwz r4, 0(r4) +/* 801D93E8 001D5048 7C 03 20 40 */ cmplw r3, r4 +/* 801D93EC 001D504C 41 80 00 24 */ blt lbl_801D9410 +/* 801D93F0 001D5050 38 04 40 00 */ addi r0, r4, 0x4000 +/* 801D93F4 001D5054 7C 03 00 40 */ cmplw r3, r0 +/* 801D93F8 001D5058 40 80 00 18 */ bge lbl_801D9410 +/* 801D93FC 001D505C 3C 80 80 49 */ lis r4, lbl_80490898@ha +/* 801D9400 001D5060 38 84 08 98 */ addi r4, r4, lbl_80490898@l +/* 801D9404 001D5064 80 04 02 38 */ lwz r0, 0x238(r4) +/* 801D9408 001D5068 54 00 07 BF */ clrlwi. r0, r0, 0x1e +/* 801D940C 001D506C 4C 82 00 20 */ bnelr +lbl_801D9410: +/* 801D9410 001D5070 3C 00 7E 00 */ lis r0, 0x7e00 +/* 801D9414 001D5074 7C 03 00 40 */ cmplw r3, r0 +/* 801D9418 001D5078 41 80 00 10 */ blt lbl_801D9428 +/* 801D941C 001D507C 3C 00 80 00 */ lis r0, 0x8000 +/* 801D9420 001D5080 7C 03 00 40 */ cmplw r3, r0 +/* 801D9424 001D5084 4C 81 00 20 */ blelr +lbl_801D9428: +/* 801D9428 001D5088 54 60 00 BE */ clrlwi r0, r3, 2 +/* 801D942C 001D508C 64 03 80 00 */ oris r3, r0, 0x8000 +/* 801D9430 001D5090 4E 80 00 20 */ blr + +.global EnableMetroTRKInterrupts +EnableMetroTRKInterrupts: +/* 801D9434 001D5094 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9438 001D5098 7C 08 02 A6 */ mflr r0 +/* 801D943C 001D509C 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9440 001D50A0 48 00 02 75 */ bl EnableEXI2Interrupts +/* 801D9444 001D50A4 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9448 001D50A8 7C 08 03 A6 */ mtlr r0 +/* 801D944C 001D50AC 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9450 001D50B0 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/dolphin_trk_glue.s b/asm/MetroTRK/dolphin_trk_glue.s new file mode 100644 index 0000000..2a2efdf --- /dev/null +++ b/asm/MetroTRK/dolphin_trk_glue.s @@ -0,0 +1,353 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global TRKLoadContext +TRKLoadContext: +/* 801D9498 001D50F8 80 03 00 00 */ lwz r0, 0(r3) +/* 801D949C 001D50FC 80 23 00 04 */ lwz r1, 4(r3) +/* 801D94A0 001D5100 80 43 00 08 */ lwz r2, 8(r3) +/* 801D94A4 001D5104 A0 A3 01 A2 */ lhz r5, 0x1a2(r3) +/* 801D94A8 001D5108 54 A6 07 BD */ rlwinm. r6, r5, 0, 0x1e, 0x1e +/* 801D94AC 001D510C 41 82 00 14 */ beq lbl_801D94C0 +/* 801D94B0 001D5110 54 A5 07 FA */ rlwinm r5, r5, 0, 0x1f, 0x1d +/* 801D94B4 001D5114 B0 A3 01 A2 */ sth r5, 0x1a2(r3) +/* 801D94B8 001D5118 B8 A3 00 14 */ lmw r5, 0x14(r3) +/* 801D94BC 001D511C 48 00 00 08 */ b lbl_801D94C4 +lbl_801D94C0: +/* 801D94C0 001D5120 B9 A3 00 34 */ lmw r13, 0x34(r3) +lbl_801D94C4: +/* 801D94C4 001D5124 7C 7F 1B 78 */ mr r31, r3 +/* 801D94C8 001D5128 7C 83 23 78 */ mr r3, r4 +/* 801D94CC 001D512C 80 9F 00 80 */ lwz r4, 0x80(r31) +/* 801D94D0 001D5130 7C 8F F1 20 */ mtcrf 0xff, r4 +/* 801D94D4 001D5134 80 9F 00 84 */ lwz r4, 0x84(r31) +/* 801D94D8 001D5138 7C 88 03 A6 */ mtlr r4 +/* 801D94DC 001D513C 80 9F 00 88 */ lwz r4, 0x88(r31) +/* 801D94E0 001D5140 7C 89 03 A6 */ mtctr r4 +/* 801D94E4 001D5144 80 9F 00 8C */ lwz r4, 0x8c(r31) +/* 801D94E8 001D5148 7C 81 03 A6 */ mtxer r4 +/* 801D94EC 001D514C 7C 80 00 A6 */ mfmsr r4 +/* 801D94F0 001D5150 54 84 04 5E */ rlwinm r4, r4, 0, 0x11, 0xf +/* 801D94F4 001D5154 54 84 07 FA */ rlwinm r4, r4, 0, 0x1f, 0x1d +/* 801D94F8 001D5158 7C 80 01 24 */ mtmsr r4 +/* 801D94FC 001D515C 7C 51 43 A6 */ mtspr 0x111, r2 +/* 801D9500 001D5160 80 9F 00 0C */ lwz r4, 0xc(r31) +/* 801D9504 001D5164 7C 92 43 A6 */ mtspr 0x112, r4 +/* 801D9508 001D5168 80 9F 00 10 */ lwz r4, 0x10(r31) +/* 801D950C 001D516C 7C 93 43 A6 */ mtspr 0x113, r4 +/* 801D9510 001D5170 80 5F 01 98 */ lwz r2, 0x198(r31) +/* 801D9514 001D5174 80 9F 01 9C */ lwz r4, 0x19c(r31) +/* 801D9518 001D5178 83 FF 00 7C */ lwz r31, 0x7c(r31) +/* 801D951C 001D517C 4B FF DD 40 */ b TRKInterruptHandler + +.global TRKUARTInterruptHandler +TRKUARTInterruptHandler: +/* 801D9520 001D5180 4E 80 00 20 */ blr + +.global InitializeProgramEndTrap +InitializeProgramEndTrap: +/* 801D9524 001D5184 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9528 001D5188 7C 08 02 A6 */ mflr r0 +/* 801D952C 001D518C 3C 80 80 27 */ lis r4, PPCHalt@ha +/* 801D9530 001D5190 3C 60 80 40 */ lis r3, lbl_803FD740@ha +/* 801D9534 001D5194 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9538 001D5198 38 A0 00 04 */ li r5, 4 +/* 801D953C 001D519C 93 E1 00 0C */ stw r31, 0xc(r1) +/* 801D9540 001D51A0 3B E4 82 68 */ addi r31, r4, PPCHalt@l +/* 801D9544 001D51A4 38 83 D7 40 */ addi r4, r3, lbl_803FD740@l +/* 801D9548 001D51A8 38 7F 00 04 */ addi r3, r31, 4 +/* 801D954C 001D51AC 4B E2 AC 19 */ bl TRK_memcpy +/* 801D9550 001D51B0 38 7F 00 04 */ addi r3, r31, 4 +/* 801D9554 001D51B4 38 80 00 04 */ li r4, 4 +/* 801D9558 001D51B8 48 09 11 E1 */ bl ICInvalidateRange +/* 801D955C 001D51BC 38 7F 00 04 */ addi r3, r31, 4 +/* 801D9560 001D51C0 38 80 00 04 */ li r4, 4 +/* 801D9564 001D51C4 48 09 10 F1 */ bl DCFlushRange +/* 801D9568 001D51C8 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D956C 001D51CC 83 E1 00 0C */ lwz r31, 0xc(r1) +/* 801D9570 001D51D0 7C 08 03 A6 */ mtlr r0 +/* 801D9574 001D51D4 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9578 001D51D8 4E 80 00 20 */ blr + +.global TRK_board_display +TRK_board_display: +/* 801D957C 001D51DC 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9580 001D51E0 7C 08 02 A6 */ mflr r0 +/* 801D9584 001D51E4 3C A0 80 40 */ lis r5, lbl_803FD744@ha +/* 801D9588 001D51E8 7C 64 1B 78 */ mr r4, r3 +/* 801D958C 001D51EC 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9590 001D51F0 38 65 D7 44 */ addi r3, r5, lbl_803FD744@l +/* 801D9594 001D51F4 4C C6 31 82 */ crclr 6 +/* 801D9598 001D51F8 4B E2 E5 2D */ bl func_80007AC4 +/* 801D959C 001D51FC 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D95A0 001D5200 7C 08 03 A6 */ mtlr r0 +/* 801D95A4 001D5204 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D95A8 001D5208 4E 80 00 20 */ blr + +.global UnreserveEXI2Port +UnreserveEXI2Port: +/* 801D95AC 001D520C 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D95B0 001D5210 7C 08 02 A6 */ mflr r0 +/* 801D95B4 001D5214 3C 60 80 42 */ lis r3, lbl_804232A0@ha +/* 801D95B8 001D5218 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D95BC 001D521C 38 63 32 A0 */ addi r3, r3, lbl_804232A0@l +/* 801D95C0 001D5220 81 83 00 20 */ lwz r12, 0x20(r3) +/* 801D95C4 001D5224 7D 89 03 A6 */ mtctr r12 +/* 801D95C8 001D5228 4E 80 04 21 */ bctrl +/* 801D95CC 001D522C 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D95D0 001D5230 7C 08 03 A6 */ mtlr r0 +/* 801D95D4 001D5234 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D95D8 001D5238 4E 80 00 20 */ blr + +.global ReserveEXI2Port +ReserveEXI2Port: +/* 801D95DC 001D523C 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D95E0 001D5240 7C 08 02 A6 */ mflr r0 +/* 801D95E4 001D5244 3C 60 80 42 */ lis r3, lbl_804232A0@ha +/* 801D95E8 001D5248 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D95EC 001D524C 38 63 32 A0 */ addi r3, r3, lbl_804232A0@l +/* 801D95F0 001D5250 81 83 00 24 */ lwz r12, 0x24(r3) +/* 801D95F4 001D5254 7D 89 03 A6 */ mtctr r12 +/* 801D95F8 001D5258 4E 80 04 21 */ bctrl +/* 801D95FC 001D525C 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9600 001D5260 7C 08 03 A6 */ mtlr r0 +/* 801D9604 001D5264 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9608 001D5268 4E 80 00 20 */ blr + +.global TRKWriteUARTN +TRKWriteUARTN: +/* 801D960C 001D526C 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9610 001D5270 7C 08 02 A6 */ mflr r0 +/* 801D9614 001D5274 3C A0 80 42 */ lis r5, lbl_804232A0@ha +/* 801D9618 001D5278 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D961C 001D527C 38 A5 32 A0 */ addi r5, r5, lbl_804232A0@l +/* 801D9620 001D5280 81 85 00 14 */ lwz r12, 0x14(r5) +/* 801D9624 001D5284 7D 89 03 A6 */ mtctr r12 +/* 801D9628 001D5288 4E 80 04 21 */ bctrl +/* 801D962C 001D528C 7C 03 00 D0 */ neg r0, r3 +/* 801D9630 001D5290 7C 00 1B 78 */ or r0, r0, r3 +/* 801D9634 001D5294 7C 03 FE 70 */ srawi r3, r0, 0x1f +/* 801D9638 001D5298 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D963C 001D529C 7C 08 03 A6 */ mtlr r0 +/* 801D9640 001D52A0 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9644 001D52A4 4E 80 00 20 */ blr + + +.global TRKReadUARTN +TRKReadUARTN: +/* 801D9648 001D52A8 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D964C 001D52AC 7C 08 02 A6 */ mflr r0 +/* 801D9650 001D52B0 3C A0 80 42 */ lis r5, lbl_804232A0@ha +/* 801D9654 001D52B4 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9658 001D52B8 38 A5 32 A0 */ addi r5, r5, lbl_804232A0@l +/* 801D965C 001D52BC 81 85 00 10 */ lwz r12, 0x10(r5) +/* 801D9660 001D52C0 7D 89 03 A6 */ mtctr r12 +/* 801D9664 001D52C4 4E 80 04 21 */ bctrl +/* 801D9668 001D52C8 7C 03 00 D0 */ neg r0, r3 +/* 801D966C 001D52CC 7C 00 1B 78 */ or r0, r0, r3 +/* 801D9670 001D52D0 7C 03 FE 70 */ srawi r3, r0, 0x1f +/* 801D9674 001D52D4 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9678 001D52D8 7C 08 03 A6 */ mtlr r0 +/* 801D967C 001D52DC 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9680 001D52E0 4E 80 00 20 */ blr + +.global TRKPollUART +TRKPollUART: +/* 801D9684 001D52E4 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9688 001D52E8 7C 08 02 A6 */ mflr r0 +/* 801D968C 001D52EC 3C 60 80 42 */ lis r3, lbl_804232A0@ha +/* 801D9690 001D52F0 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9694 001D52F4 38 63 32 A0 */ addi r3, r3, lbl_804232A0@l +/* 801D9698 001D52F8 81 83 00 0C */ lwz r12, 0xc(r3) +/* 801D969C 001D52FC 7D 89 03 A6 */ mtctr r12 +/* 801D96A0 001D5300 4E 80 04 21 */ bctrl +/* 801D96A4 001D5304 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D96A8 001D5308 7C 08 03 A6 */ mtlr r0 +/* 801D96AC 001D530C 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D96B0 001D5310 4E 80 00 20 */ blr + +.global EnableEXI2Interrupts +EnableEXI2Interrupts: +/* 801D96B4 001D5314 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D96B8 001D5318 7C 08 02 A6 */ mflr r0 +/* 801D96BC 001D531C 3C 60 80 49 */ lis r3, lbl_80490D80@ha +/* 801D96C0 001D5320 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D96C4 001D5324 88 03 0D 80 */ lbz r0, lbl_80490D80@l(r3) +/* 801D96C8 001D5328 28 00 00 00 */ cmplwi r0, 0 +/* 801D96CC 001D532C 40 82 00 20 */ bne lbl_801D96EC +/* 801D96D0 001D5330 3C 60 80 42 */ lis r3, lbl_804232A0@ha +/* 801D96D4 001D5334 38 63 32 A0 */ addi r3, r3, lbl_804232A0@l +/* 801D96D8 001D5338 81 83 00 04 */ lwz r12, 4(r3) +/* 801D96DC 001D533C 28 0C 00 00 */ cmplwi r12, 0 +/* 801D96E0 001D5340 41 82 00 0C */ beq lbl_801D96EC +/* 801D96E4 001D5344 7D 89 03 A6 */ mtctr r12 +/* 801D96E8 001D5348 4E 80 04 21 */ bctrl +lbl_801D96EC: +/* 801D96EC 001D534C 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D96F0 001D5350 7C 08 03 A6 */ mtlr r0 +/* 801D96F4 001D5354 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D96F8 001D5358 4E 80 00 20 */ blr + +.global TRKInitializeIntDrivenUART +TRKInitializeIntDrivenUART: +/* 801D96FC 001D535C 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9700 001D5360 7C 08 02 A6 */ mflr r0 +/* 801D9704 001D5364 3C 80 80 1E */ lis r4, TRKEXICallBack@ha +/* 801D9708 001D5368 3C 60 80 42 */ lis r3, lbl_804232A0@ha +/* 801D970C 001D536C 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9710 001D5370 38 84 99 20 */ addi r4, r4, TRKEXICallBack@l +/* 801D9714 001D5374 81 83 32 A0 */ lwz r12, lbl_804232A0@l(r3) +/* 801D9718 001D5378 7C C3 33 78 */ mr r3, r6 +/* 801D971C 001D537C 7D 89 03 A6 */ mtctr r12 +/* 801D9720 001D5380 4E 80 04 21 */ bctrl +/* 801D9724 001D5384 3C 60 80 42 */ lis r3, lbl_804232A0@ha +/* 801D9728 001D5388 38 63 32 A0 */ addi r3, r3, lbl_804232A0@l +/* 801D972C 001D538C 81 83 00 18 */ lwz r12, 0x18(r3) +/* 801D9730 001D5390 7D 89 03 A6 */ mtctr r12 +/* 801D9734 001D5394 4E 80 04 21 */ bctrl +/* 801D9738 001D5398 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D973C 001D539C 38 60 00 00 */ li r3, 0 +/* 801D9740 001D53A0 7C 08 03 A6 */ mtlr r0 +/* 801D9744 001D53A4 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9748 001D53A8 4E 80 00 20 */ blr + +.global InitMetroTRKCommTable +InitMetroTRKCommTable: +/* 801D974C 001D53AC 94 21 FF E0 */ stwu r1, -0x20(r1) +/* 801D9750 001D53B0 7C 08 02 A6 */ mflr r0 +/* 801D9754 001D53B4 3C 80 80 40 */ lis r4, lbl_803FD740@ha +/* 801D9758 001D53B8 90 01 00 24 */ stw r0, 0x24(r1) +/* 801D975C 001D53BC 93 E1 00 1C */ stw r31, 0x1c(r1) +/* 801D9760 001D53C0 93 C1 00 18 */ stw r30, 0x18(r1) +/* 801D9764 001D53C4 7C 7E 1B 78 */ mr r30, r3 +/* 801D9768 001D53C8 93 A1 00 14 */ stw r29, 0x14(r1) +/* 801D976C 001D53CC 3B A4 D7 40 */ addi r29, r4, lbl_803FD740@l +/* 801D9770 001D53D0 7F C4 F3 78 */ mr r4, r30 +/* 801D9774 001D53D4 38 7D 00 08 */ addi r3, r29, 8 +/* 801D9778 001D53D8 4C C6 31 82 */ crclr 6 +/* 801D977C 001D53DC 4B E2 E3 49 */ bl func_80007AC4 +/* 801D9780 001D53E0 38 7D 00 20 */ addi r3, r29, 0x20 +/* 801D9784 001D53E4 38 80 00 40 */ li r4, 0x40 +/* 801D9788 001D53E8 4C C6 31 82 */ crclr 6 +/* 801D978C 001D53EC 4B E2 E3 39 */ bl func_80007AC4 +/* 801D9790 001D53F0 3C 60 80 49 */ lis r3, lbl_80490D80@ha +/* 801D9794 001D53F4 38 00 00 00 */ li r0, 0 +/* 801D9798 001D53F8 2C 1E 00 02 */ cmpwi r30, 2 +/* 801D979C 001D53FC 98 03 0D 80 */ stb r0, lbl_80490D80@l(r3) +/* 801D97A0 001D5400 40 82 00 A0 */ bne lbl_801D9840 +/* 801D97A4 001D5404 38 7D 00 48 */ addi r3, r29, 0x48 +/* 801D97A8 001D5408 4C C6 31 82 */ crclr 6 +/* 801D97AC 001D540C 4B E2 E3 19 */ bl func_80007AC4 +/* 801D97B0 001D5410 3D 80 80 1E */ lis r12, udp_cc_initialize@ha +/* 801D97B4 001D5414 3D 60 80 42 */ lis r11, lbl_804232A0@ha +/* 801D97B8 001D5418 3B EC 99 E8 */ addi r31, r12, udp_cc_initialize@l +/* 801D97BC 001D541C 3D 40 80 1E */ lis r10, udp_cc_open@ha +/* 801D97C0 001D5420 39 8B 32 A0 */ addi r12, r11, lbl_804232A0@l +/* 801D97C4 001D5424 38 00 00 00 */ li r0, 0 +/* 801D97C8 001D5428 39 6A 99 D8 */ addi r11, r10, udp_cc_open@l +/* 801D97CC 001D542C 3D 20 80 1E */ lis r9, udp_cc_close@ha +/* 801D97D0 001D5430 39 49 99 D0 */ addi r10, r9, udp_cc_close@l +/* 801D97D4 001D5434 3D 00 80 1E */ lis r8, udp_cc_read@ha +/* 801D97D8 001D5438 39 28 99 C8 */ addi r9, r8, udp_cc_read@l +/* 801D97DC 001D543C 3C E0 80 1E */ lis r7, udp_cc_write@ha +/* 801D97E0 001D5440 39 07 99 C0 */ addi r8, r7, udp_cc_write@l +/* 801D97E4 001D5444 3C C0 80 1E */ lis r6, udp_cc_shutdown@ha +/* 801D97E8 001D5448 38 E6 99 E0 */ addi r7, r6, udp_cc_shutdown@l +/* 801D97EC 001D544C 3C A0 80 1E */ lis r5, udp_cc_peek@ha +/* 801D97F0 001D5450 38 C5 99 B8 */ addi r6, r5, udp_cc_peek@l +/* 801D97F4 001D5454 3C 80 80 1E */ lis r4, udp_cc_pre_continue@ha +/* 801D97F8 001D5458 38 A4 99 B0 */ addi r5, r4, udp_cc_pre_continue@l +/* 801D97FC 001D545C 3C 60 80 1E */ lis r3, udp_cc_post_stop@ha +/* 801D9800 001D5460 38 83 99 A8 */ addi r4, r3, udp_cc_post_stop@l +/* 801D9804 001D5464 3F C0 80 49 */ lis r30, lbl_80490D80@ha +/* 801D9808 001D5468 3B A0 00 01 */ li r29, 1 +/* 801D980C 001D546C 93 EC 00 00 */ stw r31, 0(r12) +/* 801D9810 001D5470 38 60 00 00 */ li r3, 0 +/* 801D9814 001D5474 9B BE 0D 80 */ stb r29, lbl_80490D80@l(r30) +/* 801D9818 001D5478 91 6C 00 18 */ stw r11, 0x18(r12) +/* 801D981C 001D547C 91 4C 00 1C */ stw r10, 0x1c(r12) +/* 801D9820 001D5480 91 2C 00 10 */ stw r9, 0x10(r12) +/* 801D9824 001D5484 91 0C 00 14 */ stw r8, 0x14(r12) +/* 801D9828 001D5488 90 EC 00 08 */ stw r7, 8(r12) +/* 801D982C 001D548C 90 CC 00 0C */ stw r6, 0xc(r12) +/* 801D9830 001D5490 90 AC 00 20 */ stw r5, 0x20(r12) +/* 801D9834 001D5494 90 8C 00 24 */ stw r4, 0x24(r12) +/* 801D9838 001D5498 90 0C 00 04 */ stw r0, 4(r12) +/* 801D983C 001D549C 48 00 00 C8 */ b lbl_801D9904 +lbl_801D9840: +/* 801D9840 001D54A0 2C 1E 00 01 */ cmpwi r30, 1 +/* 801D9844 001D54A4 40 82 00 94 */ bne lbl_801D98D8 +/* 801D9848 001D54A8 38 7D 00 60 */ addi r3, r29, 0x60 +/* 801D984C 001D54AC 4C C6 31 82 */ crclr 6 +/* 801D9850 001D54B0 4B E2 E2 75 */ bl func_80007AC4 +/* 801D9854 001D54B4 3F E0 80 1E */ lis r31, gdev_cc_initialize@ha +/* 801D9858 001D54B8 3D 60 80 1E */ lis r11, gdev_cc_open@ha +/* 801D985C 001D54BC 3B FF 9C 28 */ addi r31, r31, gdev_cc_initialize@l +/* 801D9860 001D54C0 3D 80 80 42 */ lis r12, lbl_804232A0@ha +/* 801D9864 001D54C4 3D 40 80 1E */ lis r10, gdev_cc_close@ha +/* 801D9868 001D54C8 3D 20 80 1E */ lis r9, gdev_cc_read@ha +/* 801D986C 001D54CC 3D 00 80 1E */ lis r8, gdev_cc_write@ha +/* 801D9870 001D54D0 3C E0 80 1E */ lis r7, gdev_cc_shutdown@ha +/* 801D9874 001D54D4 3C C0 80 1E */ lis r6, gdev_cc_peek@ha +/* 801D9878 001D54D8 3C A0 80 1E */ lis r5, gdev_cc_pre_continue@ha +/* 801D987C 001D54DC 3C 80 80 1E */ lis r4, gdev_cc_post_stop@ha +/* 801D9880 001D54E0 3C 60 80 1E */ lis r3, gdev_cc_initinterrupts@ha +/* 801D9884 001D54E4 38 03 99 F0 */ addi r0, r3, gdev_cc_initinterrupts@l +/* 801D9888 001D54E8 97 EC 32 A0 */ stwu r31, lbl_804232A0@l(r12) +/* 801D988C 001D54EC 39 6B 9B FC */ addi r11, r11, gdev_cc_open@l +/* 801D9890 001D54F0 39 4A 9B F4 */ addi r10, r10, gdev_cc_close@l +/* 801D9894 001D54F4 39 29 9B 40 */ addi r9, r9, gdev_cc_read@l +/* 801D9898 001D54F8 39 08 9A CC */ addi r8, r8, gdev_cc_write@l +/* 801D989C 001D54FC 38 E7 9C 20 */ addi r7, r7, gdev_cc_shutdown@l +/* 801D98A0 001D5500 38 C6 9A 14 */ addi r6, r6, gdev_cc_peek@l +/* 801D98A4 001D5504 38 A5 9A A8 */ addi r5, r5, gdev_cc_pre_continue@l +/* 801D98A8 001D5508 38 84 9A 84 */ addi r4, r4, gdev_cc_post_stop@l +/* 801D98AC 001D550C 91 6C 00 18 */ stw r11, 0x18(r12) +/* 801D98B0 001D5510 38 60 00 00 */ li r3, 0 +/* 801D98B4 001D5514 91 4C 00 1C */ stw r10, 0x1c(r12) +/* 801D98B8 001D5518 91 2C 00 10 */ stw r9, 0x10(r12) +/* 801D98BC 001D551C 91 0C 00 14 */ stw r8, 0x14(r12) +/* 801D98C0 001D5520 90 EC 00 08 */ stw r7, 8(r12) +/* 801D98C4 001D5524 90 CC 00 0C */ stw r6, 0xc(r12) +/* 801D98C8 001D5528 90 AC 00 20 */ stw r5, 0x20(r12) +/* 801D98CC 001D552C 90 8C 00 24 */ stw r4, 0x24(r12) +/* 801D98D0 001D5530 90 0C 00 04 */ stw r0, 4(r12) +/* 801D98D4 001D5534 48 00 00 30 */ b lbl_801D9904 +lbl_801D98D8: +/* 801D98D8 001D5538 7F C4 F3 78 */ mr r4, r30 +/* 801D98DC 001D553C 38 7D 00 84 */ addi r3, r29, 0x84 +/* 801D98E0 001D5540 4C C6 31 82 */ crclr 6 +/* 801D98E4 001D5544 4B E2 E1 E1 */ bl func_80007AC4 +/* 801D98E8 001D5548 38 7D 00 B0 */ addi r3, r29, 0xb0 +/* 801D98EC 001D554C 4C C6 31 82 */ crclr 6 +/* 801D98F0 001D5550 4B E2 E1 D5 */ bl func_80007AC4 +/* 801D98F4 001D5554 38 7D 00 E0 */ addi r3, r29, 0xe0 +/* 801D98F8 001D5558 4C C6 31 82 */ crclr 6 +/* 801D98FC 001D555C 4B E2 E1 C9 */ bl func_80007AC4 +/* 801D9900 001D5560 38 60 00 01 */ li r3, 1 +lbl_801D9904: +/* 801D9904 001D5564 80 01 00 24 */ lwz r0, 0x24(r1) +/* 801D9908 001D5568 83 E1 00 1C */ lwz r31, 0x1c(r1) +/* 801D990C 001D556C 83 C1 00 18 */ lwz r30, 0x18(r1) +/* 801D9910 001D5570 83 A1 00 14 */ lwz r29, 0x14(r1) +/* 801D9914 001D5574 7C 08 03 A6 */ mtlr r0 +/* 801D9918 001D5578 38 21 00 20 */ addi r1, r1, 0x20 +/* 801D991C 001D557C 4E 80 00 20 */ blr + +.global TRKEXICallBack +TRKEXICallBack: +/* 801D9920 001D5580 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9924 001D5584 7C 08 02 A6 */ mflr r0 +/* 801D9928 001D5588 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D992C 001D558C 93 E1 00 0C */ stw r31, 0xc(r1) +/* 801D9930 001D5590 7C 9F 23 78 */ mr r31, r4 +/* 801D9934 001D5594 48 09 7A 4D */ bl func_80271380 +/* 801D9938 001D5598 7F E3 FB 78 */ mr r3, r31 +/* 801D993C 001D559C 38 80 05 00 */ li r4, 0x500 +/* 801D9940 001D55A0 4B FF FB 59 */ bl TRKLoadContext +/* 801D9944 001D55A4 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9948 001D55A8 83 E1 00 0C */ lwz r31, 0xc(r1) +/* 801D994C 001D55AC 7C 08 03 A6 */ mtlr r0 +/* 801D9950 001D55B0 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9954 001D55B4 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/main.s b/asm/MetroTRK/main.s new file mode 100644 index 0000000..02bc38a --- /dev/null +++ b/asm/MetroTRK/main.s @@ -0,0 +1,229 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global gdev_cc_initinterrupts +gdev_cc_initinterrupts: +/* 801D99F0 001D5650 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D99F4 001D5654 7C 08 02 A6 */ mflr r0 +/* 801D99F8 001D5658 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D99FC 001D565C 48 00 06 19 */ bl func_801DA014 +/* 801D9A00 001D5660 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9A04 001D5664 38 60 00 00 */ li r3, 0 +/* 801D9A08 001D5668 7C 08 03 A6 */ mtlr r0 +/* 801D9A0C 001D566C 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9A10 001D5670 4E 80 00 20 */ blr + +.global gdev_cc_peek +gdev_cc_peek: +/* 801D9A14 001D5674 94 21 FA F0 */ stwu r1, -0x510(r1) +/* 801D9A18 001D5678 7C 08 02 A6 */ mflr r0 +/* 801D9A1C 001D567C 90 01 05 14 */ stw r0, 0x514(r1) +/* 801D9A20 001D5680 93 E1 05 0C */ stw r31, 0x50c(r1) +/* 801D9A24 001D5684 48 00 06 45 */ bl func_801DA068 +/* 801D9A28 001D5688 7C 7F 1B 79 */ or. r31, r3, r3 +/* 801D9A2C 001D568C 41 81 00 0C */ bgt lbl_801D9A38 +/* 801D9A30 001D5690 38 60 00 00 */ li r3, 0 +/* 801D9A34 001D5694 48 00 00 3C */ b lbl_801D9A70 +lbl_801D9A38: +/* 801D9A38 001D5698 7F E4 FB 78 */ mr r4, r31 +/* 801D9A3C 001D569C 38 61 00 08 */ addi r3, r1, 8 +/* 801D9A40 001D56A0 48 00 06 CD */ bl func_801DA10C +/* 801D9A44 001D56A4 2C 03 00 00 */ cmpwi r3, 0 +/* 801D9A48 001D56A8 40 82 00 1C */ bne lbl_801D9A64 +/* 801D9A4C 001D56AC 3C 60 80 49 */ lis r3, lbl_80491290@ha +/* 801D9A50 001D56B0 7F E5 FB 78 */ mr r5, r31 +/* 801D9A54 001D56B4 38 63 12 90 */ addi r3, r3, lbl_80491290@l +/* 801D9A58 001D56B8 38 81 00 08 */ addi r4, r1, 8 +/* 801D9A5C 001D56BC 48 00 03 5D */ bl CircleBufferWriteBytes +/* 801D9A60 001D56C0 48 00 00 0C */ b lbl_801D9A6C +lbl_801D9A64: +/* 801D9A64 001D56C4 38 60 D8 E7 */ li r3, -10009 +/* 801D9A68 001D56C8 48 00 00 08 */ b lbl_801D9A70 +lbl_801D9A6C: +/* 801D9A6C 001D56CC 7F E3 FB 78 */ mr r3, r31 +lbl_801D9A70: +/* 801D9A70 001D56D0 80 01 05 14 */ lwz r0, 0x514(r1) +/* 801D9A74 001D56D4 83 E1 05 0C */ lwz r31, 0x50c(r1) +/* 801D9A78 001D56D8 7C 08 03 A6 */ mtlr r0 +/* 801D9A7C 001D56DC 38 21 05 10 */ addi r1, r1, 0x510 +/* 801D9A80 001D56E0 4E 80 00 20 */ blr + +.global gdev_cc_post_stop +gdev_cc_post_stop: +/* 801D9A84 001D56E4 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9A88 001D56E8 7C 08 02 A6 */ mflr r0 +/* 801D9A8C 001D56EC 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9A90 001D56F0 48 00 08 0D */ bl func_801DA29C +/* 801D9A94 001D56F4 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9A98 001D56F8 38 60 00 00 */ li r3, 0 +/* 801D9A9C 001D56FC 7C 08 03 A6 */ mtlr r0 +/* 801D9AA0 001D5700 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9AA4 001D5704 4E 80 00 20 */ blr + +.global gdev_cc_pre_continue +gdev_cc_pre_continue: +/* 801D9AA8 001D5708 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9AAC 001D570C 7C 08 02 A6 */ mflr r0 +/* 801D9AB0 001D5710 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9AB4 001D5714 48 00 07 ED */ bl func_801DA2A0 +/* 801D9AB8 001D5718 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9ABC 001D571C 38 60 00 00 */ li r3, 0 +/* 801D9AC0 001D5720 7C 08 03 A6 */ mtlr r0 +/* 801D9AC4 001D5724 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9AC8 001D5728 4E 80 00 20 */ blr + +.global gdev_cc_write +gdev_cc_write: +/* 801D9ACC 001D572C 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9AD0 001D5730 7C 08 02 A6 */ mflr r0 +/* 801D9AD4 001D5734 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9AD8 001D5738 93 E1 00 0C */ stw r31, 0xc(r1) +/* 801D9ADC 001D573C 7C 9F 23 78 */ mr r31, r4 +/* 801D9AE0 001D5740 93 C1 00 08 */ stw r30, 8(r1) +/* 801D9AE4 001D5744 7C 7E 1B 78 */ mr r30, r3 +/* 801D9AE8 001D5748 80 0D 9F E8 */ lwz r0, lbl_8063F2A8-_SDA_BASE_(r13) +/* 801D9AEC 001D574C 2C 00 00 00 */ cmpwi r0, 0 +/* 801D9AF0 001D5750 40 82 00 2C */ bne lbl_801D9B1C +/* 801D9AF4 001D5754 38 60 D8 EF */ li r3, -10001 +/* 801D9AF8 001D5758 48 00 00 30 */ b lbl_801D9B28 +/* 801D9AFC 001D575C 48 00 00 20 */ b lbl_801D9B1C +lbl_801D9B00: +/* 801D9B00 001D5760 7F C3 F3 78 */ mr r3, r30 +/* 801D9B04 001D5764 7F E4 FB 78 */ mr r4, r31 +/* 801D9B08 001D5768 48 00 06 85 */ bl func_801DA18C +/* 801D9B0C 001D576C 2C 03 00 00 */ cmpwi r3, 0 +/* 801D9B10 001D5770 41 82 00 14 */ beq lbl_801D9B24 +/* 801D9B14 001D5774 7F DE 1A 14 */ add r30, r30, r3 +/* 801D9B18 001D5778 7F E3 F8 50 */ subf r31, r3, r31 +lbl_801D9B1C: +/* 801D9B1C 001D577C 2C 1F 00 00 */ cmpwi r31, 0 +/* 801D9B20 001D5780 41 81 FF E0 */ bgt lbl_801D9B00 +lbl_801D9B24: +/* 801D9B24 001D5784 38 60 00 00 */ li r3, 0 +lbl_801D9B28: +/* 801D9B28 001D5788 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9B2C 001D578C 83 E1 00 0C */ lwz r31, 0xc(r1) +/* 801D9B30 001D5790 83 C1 00 08 */ lwz r30, 8(r1) +/* 801D9B34 001D5794 7C 08 03 A6 */ mtlr r0 +/* 801D9B38 001D5798 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9B3C 001D579C 4E 80 00 20 */ blr + +.global gdev_cc_read +gdev_cc_read: +/* 801D9B40 001D57A0 94 21 FA E0 */ stwu r1, -0x520(r1) +/* 801D9B44 001D57A4 7C 08 02 A6 */ mflr r0 +/* 801D9B48 001D57A8 90 01 05 24 */ stw r0, 0x524(r1) +/* 801D9B4C 001D57AC BF 61 05 0C */ stmw r27, 0x50c(r1) +/* 801D9B50 001D57B0 7C 7B 1B 78 */ mr r27, r3 +/* 801D9B54 001D57B4 3B A0 00 00 */ li r29, 0 +/* 801D9B58 001D57B8 80 0D 9F E8 */ lwz r0, lbl_8063F2A8-_SDA_BASE_(r13) +/* 801D9B5C 001D57BC 2C 00 00 00 */ cmpwi r0, 0 +/* 801D9B60 001D57C0 40 82 00 0C */ bne lbl_801D9B6C +/* 801D9B64 001D57C4 38 60 D8 EF */ li r3, -10001 +/* 801D9B68 001D57C8 48 00 00 78 */ b lbl_801D9BE0 +lbl_801D9B6C: +/* 801D9B6C 001D57CC 3C 60 80 49 */ lis r3, lbl_80491290@ha +/* 801D9B70 001D57D0 7C 9E 23 78 */ mr r30, r4 +/* 801D9B74 001D57D4 3B E3 12 90 */ addi r31, r3, lbl_80491290@l +/* 801D9B78 001D57D8 48 00 00 38 */ b lbl_801D9BB0 +lbl_801D9B7C: +/* 801D9B7C 001D57DC 3B A0 00 00 */ li r29, 0 +/* 801D9B80 001D57E0 48 00 04 E9 */ bl func_801DA068 +/* 801D9B84 001D57E4 7C 7C 1B 79 */ or. r28, r3, r3 +/* 801D9B88 001D57E8 41 82 00 28 */ beq lbl_801D9BB0 +/* 801D9B8C 001D57EC 7F C4 F3 78 */ mr r4, r30 +/* 801D9B90 001D57F0 38 61 00 08 */ addi r3, r1, 8 +/* 801D9B94 001D57F4 48 00 05 79 */ bl func_801DA10C +/* 801D9B98 001D57F8 7C 7D 1B 79 */ or. r29, r3, r3 +/* 801D9B9C 001D57FC 40 82 00 14 */ bne lbl_801D9BB0 +/* 801D9BA0 001D5800 7F E3 FB 78 */ mr r3, r31 +/* 801D9BA4 001D5804 7F 85 E3 78 */ mr r5, r28 +/* 801D9BA8 001D5808 38 81 00 08 */ addi r4, r1, 8 +/* 801D9BAC 001D580C 48 00 02 0D */ bl CircleBufferWriteBytes +lbl_801D9BB0: +/* 801D9BB0 001D5810 7F E3 FB 78 */ mr r3, r31 +/* 801D9BB4 001D5814 48 00 03 5D */ bl CBGetBytesAvailableForRead +/* 801D9BB8 001D5818 7C 03 F0 40 */ cmplw r3, r30 +/* 801D9BBC 001D581C 41 80 FF C0 */ blt lbl_801D9B7C +/* 801D9BC0 001D5820 28 1D 00 00 */ cmplwi r29, 0 +/* 801D9BC4 001D5824 40 82 00 18 */ bne lbl_801D9BDC +/* 801D9BC8 001D5828 3C 60 80 49 */ lis r3, lbl_80491290@ha +/* 801D9BCC 001D582C 7F 64 DB 78 */ mr r4, r27 +/* 801D9BD0 001D5830 38 63 12 90 */ addi r3, r3, lbl_80491290@l +/* 801D9BD4 001D5834 7F C5 F3 78 */ mr r5, r30 +/* 801D9BD8 001D5838 48 00 00 D9 */ bl CircleBufferReadBytes +lbl_801D9BDC: +/* 801D9BDC 001D583C 7F A3 EB 78 */ mr r3, r29 +lbl_801D9BE0: +/* 801D9BE0 001D5840 BB 61 05 0C */ lmw r27, 0x50c(r1) +/* 801D9BE4 001D5844 80 01 05 24 */ lwz r0, 0x524(r1) +/* 801D9BE8 001D5848 7C 08 03 A6 */ mtlr r0 +/* 801D9BEC 001D584C 38 21 05 20 */ addi r1, r1, 0x520 +/* 801D9BF0 001D5850 4E 80 00 20 */ blr + +.global gdev_cc_close +gdev_cc_close: +/* 801D9BF4 001D5854 38 60 00 00 */ li r3, 0 +/* 801D9BF8 001D5858 4E 80 00 20 */ blr + +.global gdev_cc_open +gdev_cc_open: +/* 801D9BFC 001D585C 80 0D 9F E8 */ lwz r0, lbl_8063F2A8-_SDA_BASE_(r13) +/* 801D9C00 001D5860 2C 00 00 00 */ cmpwi r0, 0 +/* 801D9C04 001D5864 41 82 00 0C */ beq lbl_801D9C10 +/* 801D9C08 001D5868 38 60 D8 EB */ li r3, -10005 +/* 801D9C0C 001D586C 4E 80 00 20 */ blr +lbl_801D9C10: +/* 801D9C10 001D5870 38 00 00 01 */ li r0, 1 +/* 801D9C14 001D5874 38 60 00 00 */ li r3, 0 +/* 801D9C18 001D5878 90 0D 9F E8 */ stw r0, lbl_8063F2A8-_SDA_BASE_(r13) +/* 801D9C1C 001D587C 4E 80 00 20 */ blr + +.global gdev_cc_shutdown +gdev_cc_shutdown: +/* 801D9C20 001D5880 38 60 00 00 */ li r3, 0 +/* 801D9C24 001D5884 4E 80 00 20 */ blr + +.global gdev_cc_initialize +gdev_cc_initialize: +/* 801D9C28 001D5888 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9C2C 001D588C 7C 08 02 A6 */ mflr r0 +/* 801D9C30 001D5890 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9C34 001D5894 48 00 03 85 */ bl func_801D9FB8 +/* 801D9C38 001D5898 3C 60 80 49 */ lis r3, lbl_80491290@ha +/* 801D9C3C 001D589C 3C 80 80 49 */ lis r4, lbl_80490D90@ha +/* 801D9C40 001D58A0 38 63 12 90 */ addi r3, r3, lbl_80491290@l +/* 801D9C44 001D58A4 38 A0 05 00 */ li r5, 0x500 +/* 801D9C48 001D58A8 38 84 0D 90 */ addi r4, r4, lbl_80490D90@l +/* 801D9C4C 001D58AC 48 00 02 75 */ bl CircleBufferInitialize +/* 801D9C50 001D58B0 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D9C54 001D58B4 38 60 00 00 */ li r3, 0 +/* 801D9C58 001D58B8 7C 08 03 A6 */ mtlr r0 +/* 801D9C5C 001D58BC 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9C60 001D58C0 4E 80 00 20 */ blr + +.global OutputData +OutputData: +/* 801D9C64 001D58C4 2C 04 00 00 */ cmpwi r4, 0 +/* 801D9C68 001D58C8 38 A0 00 00 */ li r5, 0 +/* 801D9C6C 001D58CC 4C 81 00 20 */ blelr +/* 801D9C70 001D58D0 2C 04 00 08 */ cmpwi r4, 8 +/* 801D9C74 001D58D4 38 64 FF F8 */ addi r3, r4, -8 +/* 801D9C78 001D58D8 40 81 00 20 */ ble lbl_801D9C98 +/* 801D9C7C 001D58DC 38 03 00 07 */ addi r0, r3, 7 +/* 801D9C80 001D58E0 54 00 E8 FE */ srwi r0, r0, 3 +/* 801D9C84 001D58E4 7C 09 03 A6 */ mtctr r0 +/* 801D9C88 001D58E8 2C 03 00 00 */ cmpwi r3, 0 +/* 801D9C8C 001D58EC 40 81 00 0C */ ble lbl_801D9C98 +lbl_801D9C90: +/* 801D9C90 001D58F0 38 A5 00 08 */ addi r5, r5, 8 +/* 801D9C94 001D58F4 42 00 FF FC */ bdnz lbl_801D9C90 +lbl_801D9C98: +/* 801D9C98 001D58F8 7C 05 20 50 */ subf r0, r5, r4 +/* 801D9C9C 001D58FC 7C 09 03 A6 */ mtctr r0 +/* 801D9CA0 001D5900 7C 05 20 00 */ cmpw r5, r4 +/* 801D9CA4 001D5904 4C 80 00 20 */ bgelr +lbl_801D9CA8: +/* 801D9CA8 001D5908 42 00 00 00 */ bdnz lbl_801D9CA8 +/* 801D9CAC 001D590C 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/main_TRK.s b/asm/MetroTRK/main_TRK.s new file mode 100644 index 0000000..6748452 --- /dev/null +++ b/asm/MetroTRK/main_TRK.s @@ -0,0 +1,24 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global TRK_main +TRK_main: +/* 801D9454 001D50B4 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D9458 001D50B8 7C 08 02 A6 */ mflr r0 +/* 801D945C 001D50BC 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9460 001D50C0 4B FF B7 45 */ bl TRKInitializeNub +/* 801D9464 001D50C4 3C 80 80 49 */ lis r4, lbl_80490D78@ha +/* 801D9468 001D50C8 2C 03 00 00 */ cmpwi r3, 0 +/* 801D946C 001D50CC 90 64 0D 78 */ stw r3, lbl_80490D78@l(r4) +/* 801D9470 001D50D0 40 82 00 0C */ bne lbl_801D947C +/* 801D9474 001D50D4 4B FF B6 E5 */ bl TRKNubWelcome +/* 801D9478 001D50D8 4B FF B3 C1 */ bl TRKNubMainLoop +lbl_801D947C: +/* 801D947C 001D50DC 4B FF B7 05 */ bl TRKTerminateNub +/* 801D9480 001D50E0 3C 80 80 49 */ lis r4, lbl_80490D78@ha +/* 801D9484 001D50E4 90 64 0D 78 */ stw r3, lbl_80490D78@l(r4) +/* 801D9488 001D50E8 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D948C 001D50EC 7C 08 03 A6 */ mtlr r0 +/* 801D9490 001D50F0 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9494 001D50F4 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/mpc_7xx_603e.s b/asm/MetroTRK/mpc_7xx_603e.s new file mode 100644 index 0000000..a93c6be --- /dev/null +++ b/asm/MetroTRK/mpc_7xx_603e.s @@ -0,0 +1,234 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global TRKSaveExtended1Block +TRKSaveExtended1Block: +/* 801D8C50 001D48B0 3C 40 80 49 */ lis r2, lbl_80490898@h +/* 801D8C54 001D48B4 60 42 08 98 */ ori r2, r2, lbl_80490898@l +/* 801D8C58 001D48B8 7E 00 04 A6 */ mfsr r16, 0 +/* 801D8C5C 001D48BC 7E 21 04 A6 */ mfsr r17, 1 +/* 801D8C60 001D48C0 7E 42 04 A6 */ mfsr r18, 2 +/* 801D8C64 001D48C4 7E 63 04 A6 */ mfsr r19, 3 +/* 801D8C68 001D48C8 7E 84 04 A6 */ mfsr r20, 4 +/* 801D8C6C 001D48CC 7E A5 04 A6 */ mfsr r21, 5 +/* 801D8C70 001D48D0 7E C6 04 A6 */ mfsr r22, 6 +/* 801D8C74 001D48D4 7E E7 04 A6 */ mfsr r23, 7 +/* 801D8C78 001D48D8 7F 08 04 A6 */ mfsr r24, 8 +/* 801D8C7C 001D48DC 7F 29 04 A6 */ mfsr r25, 9 +/* 801D8C80 001D48E0 7F 4A 04 A6 */ mfsr r26, 0xa +/* 801D8C84 001D48E4 7F 6B 04 A6 */ mfsr r27, 0xb +/* 801D8C88 001D48E8 7F 8C 04 A6 */ mfsr r28, 0xc +/* 801D8C8C 001D48EC 7F AD 04 A6 */ mfsr r29, 0xd +/* 801D8C90 001D48F0 7F CE 04 A6 */ mfsr r30, 0xe +/* 801D8C94 001D48F4 7F EF 04 A6 */ mfsr r31, 0xf +/* 801D8C98 001D48F8 BE 02 01 A8 */ stmw r16, 0x1a8(r2) +/* 801D8C9C 001D48FC 7D 4C 42 E6 */ mftb r10, 0x10c +/* 801D8CA0 001D4900 7D 6D 42 E6 */ mftbu r11 +/* 801D8CA4 001D4904 7D 90 FA A6 */ mfspr r12, 0x3f0 +/* 801D8CA8 001D4908 7D B1 FA A6 */ mfspr r13, 0x3f1 +/* 801D8CAC 001D490C 7D DB 02 A6 */ mfspr r14, 0x1b +/* 801D8CB0 001D4910 7D FF 42 A6 */ mfpvr r15 +/* 801D8CB4 001D4914 7E 10 82 A6 */ mfibatu r16, 0 +/* 801D8CB8 001D4918 7E 31 82 A6 */ mfibatl r17, 0 +/* 801D8CBC 001D491C 7E 52 82 A6 */ mfibatu r18, 1 +/* 801D8CC0 001D4920 7E 73 82 A6 */ mfibatl r19, 1 +/* 801D8CC4 001D4924 7E 94 82 A6 */ mfibatu r20, 2 +/* 801D8CC8 001D4928 7E B5 82 A6 */ mfibatl r21, 2 +/* 801D8CCC 001D492C 7E D6 82 A6 */ mfibatu r22, 3 +/* 801D8CD0 001D4930 7E F7 82 A6 */ mfibatl r23, 3 +/* 801D8CD4 001D4934 7F 18 82 A6 */ mfdbatu r24, 0 +/* 801D8CD8 001D4938 7F 39 82 A6 */ mfdbatl r25, 0 +/* 801D8CDC 001D493C 7F 5A 82 A6 */ mfdbatu r26, 1 +/* 801D8CE0 001D4940 7F 7B 82 A6 */ mfdbatl r27, 1 +/* 801D8CE4 001D4944 7F 9C 82 A6 */ mfdbatu r28, 2 +/* 801D8CE8 001D4948 7F BD 82 A6 */ mfdbatl r29, 2 +/* 801D8CEC 001D494C 7F DE 82 A6 */ mfdbatu r30, 3 +/* 801D8CF0 001D4950 7F FF 82 A6 */ mfdbatl r31, 3 +/* 801D8CF4 001D4954 BD 42 01 E8 */ stmw r10, 0x1e8(r2) +/* 801D8CF8 001D4958 7E D9 02 A6 */ mfspr r22, 0x19 +/* 801D8CFC 001D495C 7E F3 02 A6 */ mfdar r23 +/* 801D8D00 001D4960 7F 12 02 A6 */ mfdsisr r24 +/* 801D8D04 001D4964 7F 30 42 A6 */ mfspr r25, 0x110 +/* 801D8D08 001D4968 7F 51 42 A6 */ mfspr r26, 0x111 +/* 801D8D0C 001D496C 7F 72 42 A6 */ mfspr r27, 0x112 +/* 801D8D10 001D4970 7F 93 42 A6 */ mfspr r28, 0x113 +/* 801D8D14 001D4974 3B A0 00 00 */ li r29, 0 +/* 801D8D18 001D4978 7F D2 FA A6 */ mfspr r30, 0x3f2 +/* 801D8D1C 001D497C 7F FA 42 A6 */ mfspr r31, 0x11a +/* 801D8D20 001D4980 BE C2 02 5C */ stmw r22, 0x25c(r2) +/* 801D8D24 001D4984 7E 90 E2 A6 */ mfspr r20, 0x390 +/* 801D8D28 001D4988 7E B1 E2 A6 */ mfspr r21, 0x391 +/* 801D8D2C 001D498C 7E D2 E2 A6 */ mfspr r22, 0x392 +/* 801D8D30 001D4990 7E F3 E2 A6 */ mfspr r23, 0x393 +/* 801D8D34 001D4994 7F 14 E2 A6 */ mfspr r24, 0x394 +/* 801D8D38 001D4998 7F 35 E2 A6 */ mfspr r25, 0x395 +/* 801D8D3C 001D499C 7F 56 E2 A6 */ mfspr r26, 0x396 +/* 801D8D40 001D49A0 7F 77 E2 A6 */ mfspr r27, 0x397 +/* 801D8D44 001D49A4 7F 98 E2 A6 */ mfspr r28, 0x398 +/* 801D8D48 001D49A8 7F B9 E2 A6 */ mfspr r29, 0x399 +/* 801D8D4C 001D49AC 7F DA E2 A6 */ mfspr r30, 0x39a +/* 801D8D50 001D49B0 7F FB E2 A6 */ mfspr r31, 0x39b +/* 801D8D54 001D49B4 BE 82 02 FC */ stmw r20, 0x2fc(r2) +/* 801D8D58 001D49B8 48 00 00 48 */ b lbl_801D8DA0 +/* 801D8D5C 001D49BC 7E 00 EA A6 */ mfspr r16, 0x3a0 +/* 801D8D60 001D49C0 7E 27 EA A6 */ mfspr r17, 0x3a7 +/* 801D8D64 001D49C4 7E 48 EA A6 */ mfspr r18, 0x3a8 +/* 801D8D68 001D49C8 7E 69 EA A6 */ mfspr r19, 0x3a9 +/* 801D8D6C 001D49CC 7E 8A EA A6 */ mfspr r20, 0x3aa +/* 801D8D70 001D49D0 7E AB EA A6 */ mfspr r21, 0x3ab +/* 801D8D74 001D49D4 7E CC EA A6 */ mfspr r22, 0x3ac +/* 801D8D78 001D49D8 7E ED EA A6 */ mfspr r23, 0x3ad +/* 801D8D7C 001D49DC 7F 0E EA A6 */ mfspr r24, 0x3ae +/* 801D8D80 001D49E0 7F 2F EA A6 */ mfspr r25, 0x3af +/* 801D8D84 001D49E4 7F 50 EA A6 */ mfspr r26, 0x3b0 +/* 801D8D88 001D49E8 7F 77 EA A6 */ mfspr r27, 0x3b7 +/* 801D8D8C 001D49EC 7F 9F EA A6 */ mfspr r28, 0x3bf +/* 801D8D90 001D49F0 7F B6 FA A6 */ mfspr r29, 0x3f6 +/* 801D8D94 001D49F4 7F D7 FA A6 */ mfspr r30, 0x3f7 +/* 801D8D98 001D49F8 7F FF FA A6 */ mfspr r31, 0x3ff +/* 801D8D9C 001D49FC BE 02 02 B8 */ stmw r16, 0x2b8(r2) +lbl_801D8DA0: +/* 801D8DA0 001D4A00 7E 75 FA A6 */ mfspr r19, 0x3f5 +/* 801D8DA4 001D4A04 7E 99 EA A6 */ mfspr r20, 0x3b9 +/* 801D8DA8 001D4A08 7E BA EA A6 */ mfspr r21, 0x3ba +/* 801D8DAC 001D4A0C 7E DD EA A6 */ mfspr r22, 0x3bd +/* 801D8DB0 001D4A10 7E FE EA A6 */ mfspr r23, 0x3be +/* 801D8DB4 001D4A14 7F 1B EA A6 */ mfspr r24, 0x3bb +/* 801D8DB8 001D4A18 7F 38 EA A6 */ mfspr r25, 0x3b8 +/* 801D8DBC 001D4A1C 7F 5C EA A6 */ mfspr r26, 0x3bc +/* 801D8DC0 001D4A20 7F 7C FA A6 */ mfspr r27, 0x3fc +/* 801D8DC4 001D4A24 7F 9D FA A6 */ mfspr r28, 0x3fd +/* 801D8DC8 001D4A28 7F BE FA A6 */ mfspr r29, 0x3fe +/* 801D8DCC 001D4A2C 7F DB FA A6 */ mfspr r30, 0x3FB +/* 801D8DD0 001D4A30 7F F9 FA A6 */ mfspr r31, 0x3f9 +/* 801D8DD4 001D4A34 BE 62 02 84 */ stmw r19, 0x284(r2) +/* 801D8DD8 001D4A38 4E 80 00 20 */ blr +/* 801D8DDC 001D4A3C 7F 30 F2 A6 */ mfspr r25, 0x3d0 +/* 801D8DE0 001D4A40 7F 51 F2 A6 */ mfspr r26, 0x3d1 +/* 801D8DE4 001D4A44 7F 72 F2 A6 */ mfspr r27, 0x3d2 +/* 801D8DE8 001D4A48 7F 93 F2 A6 */ mfspr r28, 0x3d3 +/* 801D8DEC 001D4A4C 7F B4 F2 A6 */ mfspr r29, 0x3D4 +/* 801D8DF0 001D4A50 7F D5 F2 A6 */ mfspr r30, 0x3D5 +/* 801D8DF4 001D4A54 7F F6 F2 A6 */ mfspr r31, 0x3d6 +/* 801D8DF8 001D4A58 BF 22 02 40 */ stmw r25, 0x240(r2) +/* 801D8DFC 001D4A5C 7F F6 02 A6 */ mfspr r31, 0x16 +/* 801D8E00 001D4A60 93 E2 02 78 */ stw r31, 0x278(r2) +/* 801D8E04 001D4A64 4E 80 00 20 */ blr + +.global TRKRestoreExtended1Block +TRKRestoreExtended1Block: +/* 801D8E08 001D4A68 3C 40 80 49 */ lis r2, lbl_80490898@h +/* 801D8E0C 001D4A6C 60 42 08 98 */ ori r2, r2, lbl_80490898@l +/* 801D8E10 001D4A70 3C A0 80 42 */ lis r5, lbl_80423230@h +/* 801D8E14 001D4A74 60 A5 32 30 */ ori r5, r5, lbl_80423230@l +/* 801D8E18 001D4A78 88 65 00 00 */ lbz r3, 0(r5) +/* 801D8E1C 001D4A7C 88 C5 00 01 */ lbz r6, 1(r5) +/* 801D8E20 001D4A80 38 00 00 00 */ li r0, 0 +/* 801D8E24 001D4A84 98 05 00 00 */ stb r0, 0(r5) +/* 801D8E28 001D4A88 98 05 00 01 */ stb r0, 1(r5) +/* 801D8E2C 001D4A8C 2C 03 00 00 */ cmpwi r3, 0 +/* 801D8E30 001D4A90 41 82 00 14 */ beq lbl_801D8E44 +/* 801D8E34 001D4A94 83 02 01 E8 */ lwz r24, 0x1e8(r2) +/* 801D8E38 001D4A98 83 22 01 EC */ lwz r25, 0x1ec(r2) +/* 801D8E3C 001D4A9C 7F 1C 43 A6 */ mttbl r24 +/* 801D8E40 001D4AA0 7F 3D 43 A6 */ mttbu r25 +lbl_801D8E44: +/* 801D8E44 001D4AA4 BA 82 02 FC */ lmw r20, 0x2fc(r2) +/* 801D8E48 001D4AA8 7E 90 E3 A6 */ mtspr 0x390, r20 +/* 801D8E4C 001D4AAC 7E B1 E3 A6 */ mtspr 0x391, r21 +/* 801D8E50 001D4AB0 7E D2 E3 A6 */ mtspr 0x392, r22 +/* 801D8E54 001D4AB4 7E F3 E3 A6 */ mtspr 0x393, r23 +/* 801D8E58 001D4AB8 7F 14 E3 A6 */ mtspr 0x394, r24 +/* 801D8E5C 001D4ABC 7F 35 E3 A6 */ mtspr 0x395, r25 +/* 801D8E60 001D4AC0 7F 56 E3 A6 */ mtspr 0x396, r26 +/* 801D8E64 001D4AC4 7F 77 E3 A6 */ mtspr 0x397, r27 +/* 801D8E68 001D4AC8 7F 98 E3 A6 */ mtspr 0x398, r28 +/* 801D8E6C 001D4ACC 7F DA E3 A6 */ mtspr 0x39a, r30 +/* 801D8E70 001D4AD0 7F FB E3 A6 */ mtspr 0x39b, r31 +/* 801D8E74 001D4AD4 48 00 00 1C */ b lbl_801D8E90 +/* 801D8E78 001D4AD8 BB 42 02 E0 */ lmw r26, 0x2e0(r2) +/* 801D8E7C 001D4ADC 7F 50 EB A6 */ mtspr 0x3b0, r26 +/* 801D8E80 001D4AE0 7F 77 EB A6 */ mtspr 0x3b7, r27 +/* 801D8E84 001D4AE4 7F B6 FB A6 */ mtspr 0x3f6, r29 +/* 801D8E88 001D4AE8 7F D7 FB A6 */ mtspr 0x3f7, r30 +/* 801D8E8C 001D4AEC 7F FF FB A6 */ mtspr 0x3ff, r31 +lbl_801D8E90: +/* 801D8E90 001D4AF0 BA 62 02 84 */ lmw r19, 0x284(r2) +/* 801D8E94 001D4AF4 7E 75 FB A6 */ mtspr 0x3f5, r19 +/* 801D8E98 001D4AF8 7E 99 EB A6 */ mtspr 0x3b9, r20 +/* 801D8E9C 001D4AFC 7E BA EB A6 */ mtspr 0x3ba, r21 +/* 801D8EA0 001D4B00 7E DD EB A6 */ mtspr 0x3bd, r22 +/* 801D8EA4 001D4B04 7E FE EB A6 */ mtspr 0x3be, r23 +/* 801D8EA8 001D4B08 7F 1B EB A6 */ mtspr 0x3bb, r24 +/* 801D8EAC 001D4B0C 7F 38 EB A6 */ mtspr 0x3b8, r25 +/* 801D8EB0 001D4B10 7F 5C EB A6 */ mtspr 0x3bc, r26 +/* 801D8EB4 001D4B14 7F 7C FB A6 */ mtspr 0x3fc, r27 +/* 801D8EB8 001D4B18 7F 9D FB A6 */ mtspr 0x3fd, r28 +/* 801D8EBC 001D4B1C 7F BE FB A6 */ mtspr 0x3fe, r29 +/* 801D8EC0 001D4B20 7F DB FB A6 */ mtictc r30 +/* 801D8EC4 001D4B24 7F F9 FB A6 */ mtspr 0x3f9, r31 +/* 801D8EC8 001D4B28 48 00 00 34 */ b lbl_801D8EFC +/* 801D8ECC 001D4B2C 2C 06 00 00 */ cmpwi r6, 0 +/* 801D8ED0 001D4B30 41 82 00 0C */ beq lbl_801D8EDC +/* 801D8ED4 001D4B34 83 42 02 78 */ lwz r26, 0x278(r2) +/* 801D8ED8 001D4B38 7F 56 03 A6 */ mtspr 0x16, r26 +lbl_801D8EDC: +/* 801D8EDC 001D4B3C BB 22 02 40 */ lmw r25, 0x240(r2) +/* 801D8EE0 001D4B40 7F 30 F3 A6 */ mtspr 0x3d0, r25 +/* 801D8EE4 001D4B44 7F 51 F3 A6 */ mtspr 0x3d1, r26 +/* 801D8EE8 001D4B48 7F 72 F3 A6 */ mtspr 0x3d2, r27 +/* 801D8EEC 001D4B4C 7F 93 F3 A6 */ mtspr 0x3d3, r28 +/* 801D8EF0 001D4B50 7F B4 F3 A6 */ mtspr 0x3D4, r29 +/* 801D8EF4 001D4B54 7F D5 F3 A6 */ mtspr 0x3D5, r30 +/* 801D8EF8 001D4B58 7F F6 F3 A6 */ mtspr 0x3d6, r31 +lbl_801D8EFC: +/* 801D8EFC 001D4B5C BA 02 01 A8 */ lmw r16, 0x1a8(r2) +/* 801D8F00 001D4B60 7E 00 01 A4 */ mtsr 0, r16 +/* 801D8F04 001D4B64 7E 21 01 A4 */ mtsr 1, r17 +/* 801D8F08 001D4B68 7E 42 01 A4 */ mtsr 2, r18 +/* 801D8F0C 001D4B6C 7E 63 01 A4 */ mtsr 3, r19 +/* 801D8F10 001D4B70 7E 84 01 A4 */ mtsr 4, r20 +/* 801D8F14 001D4B74 7E A5 01 A4 */ mtsr 5, r21 +/* 801D8F18 001D4B78 7E C6 01 A4 */ mtsr 6, r22 +/* 801D8F1C 001D4B7C 7E E7 01 A4 */ mtsr 7, r23 +/* 801D8F20 001D4B80 7F 08 01 A4 */ mtsr 8, r24 +/* 801D8F24 001D4B84 7F 29 01 A4 */ mtsr 9, r25 +/* 801D8F28 001D4B88 7F 4A 01 A4 */ mtsr 0xa, r26 +/* 801D8F2C 001D4B8C 7F 6B 01 A4 */ mtsr 0xb, r27 +/* 801D8F30 001D4B90 7F 8C 01 A4 */ mtsr 0xc, r28 +/* 801D8F34 001D4B94 7F AD 01 A4 */ mtsr 0xd, r29 +/* 801D8F38 001D4B98 7F CE 01 A4 */ mtsr 0xe, r30 +/* 801D8F3C 001D4B9C 7F EF 01 A4 */ mtsr 0xf, r31 +/* 801D8F40 001D4BA0 B9 82 01 F0 */ lmw r12, 0x1f0(r2) +/* 801D8F44 001D4BA4 7D 90 FB A6 */ mtspr 0x3f0, r12 +/* 801D8F48 001D4BA8 7D B1 FB A6 */ mtspr 0x3f1, r13 +/* 801D8F4C 001D4BAC 7D DB 03 A6 */ mtspr 0x1b, r14 +/* 801D8F50 001D4BB0 7D FF 43 A6 */ mtspr 0x11f, r15 +/* 801D8F54 001D4BB4 7E 10 83 A6 */ mtibatu 0, r16 +/* 801D8F58 001D4BB8 7E 31 83 A6 */ mtibatl 0, r17 +/* 801D8F5C 001D4BBC 7E 52 83 A6 */ mtibatu 1, r18 +/* 801D8F60 001D4BC0 7E 73 83 A6 */ mtibatl 1, r19 +/* 801D8F64 001D4BC4 7E 94 83 A6 */ mtibatu 2, r20 +/* 801D8F68 001D4BC8 7E B5 83 A6 */ mtibatl 2, r21 +/* 801D8F6C 001D4BCC 7E D6 83 A6 */ mtibatu 3, r22 +/* 801D8F70 001D4BD0 7E F7 83 A6 */ mtibatl 3, r23 +/* 801D8F74 001D4BD4 7F 18 83 A6 */ mtdbatu 0, r24 +/* 801D8F78 001D4BD8 7F 39 83 A6 */ mtdbatl 0, r25 +/* 801D8F7C 001D4BDC 7F 5A 83 A6 */ mtdbatu 1, r26 +/* 801D8F80 001D4BE0 7F 7B 83 A6 */ mtdbatl 1, r27 +/* 801D8F84 001D4BE4 7F 9C 83 A6 */ mtdbatu 2, r28 +/* 801D8F88 001D4BE8 7F BD 83 A6 */ mtdbatl 2, r29 +/* 801D8F8C 001D4BEC 7F DE 83 A6 */ mtdbatu 3, r30 +/* 801D8F90 001D4BF0 7F FF 83 A6 */ mtdbatl 3, r31 +/* 801D8F94 001D4BF4 BA C2 02 5C */ lmw r22, 0x25c(r2) +/* 801D8F98 001D4BF8 7E D9 03 A6 */ mtspr 0x19, r22 +/* 801D8F9C 001D4BFC 7E F3 03 A6 */ mtdar r23 +/* 801D8FA0 001D4C00 7F 12 03 A6 */ mtdsisr r24 +/* 801D8FA4 001D4C04 7F 30 43 A6 */ mtspr 0x110, r25 +/* 801D8FA8 001D4C08 7F 51 43 A6 */ mtspr 0x111, r26 +/* 801D8FAC 001D4C0C 7F 72 43 A6 */ mtspr 0x112, r27 +/* 801D8FB0 001D4C10 7F 93 43 A6 */ mtspr 0x113, r28 +/* 801D8FB4 001D4C14 7F D2 FB A6 */ mtspr 0x3f2, r30 +/* 801D8FB8 001D4C18 7F FA 43 A6 */ mtspr 0x11a, r31 +/* 801D8FBC 001D4C1C 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/msg.s b/asm/MetroTRK/msg.s index 2f5a89c..74591d9 100644 --- a/asm/MetroTRK/msg.s +++ b/asm/MetroTRK/msg.s @@ -9,7 +9,7 @@ TRKMessageSend: /* 801D4CE4 001D0944 90 01 00 14 */ stw r0, 0x14(r1) /* 801D4CE8 001D0948 80 83 00 08 */ lwz r4, 8(r3) /* 801D4CEC 001D094C 38 63 00 10 */ addi r3, r3, 0x10 -/* 801D4CF0 001D0950 48 00 49 1D */ bl func_801D960C +/* 801D4CF0 001D0950 48 00 49 1D */ bl TRKWriteUARTN /* 801D4CF4 001D0954 80 01 00 14 */ lwz r0, 0x14(r1) /* 801D4CF8 001D0958 38 60 00 00 */ li r3, 0 /* 801D4CFC 001D095C 7C 08 03 A6 */ mtlr r0 diff --git a/asm/MetroTRK/msghndlr.s b/asm/MetroTRK/msghndlr.s index 49e388c..67ed25f 100644 --- a/asm/MetroTRK/msghndlr.s +++ b/asm/MetroTRK/msghndlr.s @@ -50,7 +50,7 @@ lbl_801D591C: /* 801D5964 001D15C4 98 A1 00 10 */ stb r5, 0x10(r1) /* 801D5968 001D15C8 90 09 00 00 */ stw r0, 0(r9) /* 801D596C 001D15CC 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D5970 001D15D0 48 00 3C 9D */ bl func_801D960C +/* 801D5970 001D15D0 48 00 3C 9D */ bl TRKWriteUARTN /* 801D5974 001D15D4 80 01 00 54 */ lwz r0, 0x54(r1) /* 801D5978 001D15D8 38 60 00 00 */ li r3, 0 /* 801D597C 001D15DC 83 E1 00 4C */ lwz r31, 0x4c(r1) @@ -112,7 +112,7 @@ lbl_801D59F0: /* 801D5A34 001D1694 9B E1 00 10 */ stb r31, 0x10(r1) /* 801D5A38 001D1698 90 08 00 00 */ stw r0, 0(r8) /* 801D5A3C 001D169C 90 C1 00 14 */ stw r6, 0x14(r1) -/* 801D5A40 001D16A0 48 00 3B CD */ bl func_801D960C +/* 801D5A40 001D16A0 48 00 3B CD */ bl TRKWriteUARTN /* 801D5A44 001D16A4 80 01 00 54 */ lwz r0, 0x54(r1) /* 801D5A48 001D16A8 38 60 00 00 */ li r3, 0 /* 801D5A4C 001D16AC 83 E1 00 4C */ lwz r31, 0x4c(r1) @@ -170,7 +170,7 @@ lbl_801D5AB4: /* 801D5B08 001D1768 98 A1 01 10 */ stb r5, 0x110(r1) /* 801D5B0C 001D176C 90 09 00 00 */ stw r0, 0(r9) /* 801D5B10 001D1770 90 E1 01 14 */ stw r7, 0x114(r1) -/* 801D5B14 001D1774 48 00 3A F9 */ bl func_801D960C +/* 801D5B14 001D1774 48 00 3A F9 */ bl TRKWriteUARTN /* 801D5B18 001D1778 38 60 00 00 */ li r3, 0 /* 801D5B1C 001D177C 48 00 02 00 */ b lbl_801D5D1C lbl_801D5B20: @@ -201,7 +201,7 @@ lbl_801D5B34: /* 801D5B7C 001D17DC 98 A1 00 D0 */ stb r5, 0xd0(r1) /* 801D5B80 001D17E0 90 09 00 00 */ stw r0, 0(r9) /* 801D5B84 001D17E4 90 E1 00 D4 */ stw r7, 0xd4(r1) -/* 801D5B88 001D17E8 48 00 3A 85 */ bl func_801D960C +/* 801D5B88 001D17E8 48 00 3A 85 */ bl TRKWriteUARTN /* 801D5B8C 001D17EC 38 60 00 00 */ li r3, 0 /* 801D5B90 001D17F0 48 00 01 8C */ b lbl_801D5D1C lbl_801D5B94: @@ -226,7 +226,7 @@ lbl_801D5B94: /* 801D5BDC 001D183C 98 A1 00 90 */ stb r5, 0x90(r1) /* 801D5BE0 001D1840 90 09 00 00 */ stw r0, 0(r9) /* 801D5BE4 001D1844 90 E1 00 94 */ stw r7, 0x94(r1) -/* 801D5BE8 001D1848 48 00 3A 25 */ bl func_801D960C +/* 801D5BE8 001D1848 48 00 3A 25 */ bl TRKWriteUARTN /* 801D5BEC 001D184C 38 60 00 00 */ li r3, 0 /* 801D5BF0 001D1850 48 00 01 2C */ b lbl_801D5D1C lbl_801D5BF4: @@ -254,7 +254,7 @@ lbl_801D5BF4: /* 801D5C48 001D18A8 98 A1 00 50 */ stb r5, 0x50(r1) /* 801D5C4C 001D18AC 90 09 00 00 */ stw r0, 0(r9) /* 801D5C50 001D18B0 90 E1 00 54 */ stw r7, 0x54(r1) -/* 801D5C54 001D18B4 48 00 39 B9 */ bl func_801D960C +/* 801D5C54 001D18B4 48 00 39 B9 */ bl TRKWriteUARTN /* 801D5C58 001D18B8 38 60 00 00 */ li r3, 0 /* 801D5C5C 001D18BC 48 00 00 C0 */ b lbl_801D5D1C lbl_801D5C60: @@ -279,7 +279,7 @@ lbl_801D5C60: /* 801D5CA8 001D1908 98 A1 00 10 */ stb r5, 0x10(r1) /* 801D5CAC 001D190C 90 09 00 00 */ stw r0, 0(r9) /* 801D5CB0 001D1910 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D5CB4 001D1914 48 00 39 59 */ bl func_801D960C +/* 801D5CB4 001D1914 48 00 39 59 */ bl TRKWriteUARTN /* 801D5CB8 001D1918 2C 1F 00 10 */ cmpwi r31, 0x10 /* 801D5CBC 001D191C 38 60 00 00 */ li r3, 0 /* 801D5CC0 001D1920 41 82 00 2C */ beq lbl_801D5CEC @@ -344,7 +344,7 @@ TRKDoContinue: /* 801D5D90 001D19F0 98 A1 00 50 */ stb r5, 0x50(r1) /* 801D5D94 001D19F4 90 09 00 00 */ stw r0, 0(r9) /* 801D5D98 001D19F8 90 E1 00 54 */ stw r7, 0x54(r1) -/* 801D5D9C 001D19FC 48 00 38 71 */ bl func_801D960C +/* 801D5D9C 001D19FC 48 00 38 71 */ bl TRKWriteUARTN /* 801D5DA0 001D1A00 38 60 00 00 */ li r3, 0 /* 801D5DA4 001D1A04 48 00 00 60 */ b lbl_801D5E04 lbl_801D5DA8: @@ -369,7 +369,7 @@ lbl_801D5DA8: /* 801D5DF0 001D1A50 98 A1 00 10 */ stb r5, 0x10(r1) /* 801D5DF4 001D1A54 90 09 00 00 */ stw r0, 0(r9) /* 801D5DF8 001D1A58 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D5DFC 001D1A5C 48 00 38 11 */ bl func_801D960C +/* 801D5DFC 001D1A5C 48 00 38 11 */ bl TRKWriteUARTN /* 801D5E00 001D1A60 48 00 3B 59 */ bl TRKTargetContinue lbl_801D5E04: /* 801D5E04 001D1A64 80 01 00 94 */ lwz r0, 0x94(r1) @@ -415,7 +415,7 @@ TRKDoWriteRegisters: /* 801D5E98 001D1AF8 98 A1 00 54 */ stb r5, 0x54(r1) /* 801D5E9C 001D1AFC 90 09 00 00 */ stw r0, 0(r9) /* 801D5EA0 001D1B00 90 E1 00 58 */ stw r7, 0x58(r1) -/* 801D5EA4 001D1B04 48 00 37 69 */ bl func_801D960C +/* 801D5EA4 001D1B04 48 00 37 69 */ bl TRKWriteUARTN /* 801D5EA8 001D1B08 38 60 00 00 */ li r3, 0 /* 801D5EAC 001D1B0C 48 00 02 04 */ b lbl_801D60B0 lbl_801D5EB0: @@ -560,7 +560,7 @@ lbl_801D604C: /* 801D6090 001D1CF0 9B E1 00 14 */ stb r31, 0x14(r1) /* 801D6094 001D1CF4 90 08 00 00 */ stw r0, 0(r8) /* 801D6098 001D1CF8 90 C1 00 18 */ stw r6, 0x18(r1) -/* 801D609C 001D1CFC 48 00 35 71 */ bl func_801D960C +/* 801D609C 001D1CFC 48 00 35 71 */ bl TRKWriteUARTN /* 801D60A0 001D1D00 38 60 00 00 */ li r3, 0 /* 801D60A4 001D1D04 48 00 00 0C */ b lbl_801D60B0 lbl_801D60A8: @@ -608,7 +608,7 @@ TRKDoReadRegisters: /* 801D613C 001D1D9C 98 A1 00 54 */ stb r5, 0x54(r1) /* 801D6140 001D1DA0 90 09 00 00 */ stw r0, 0(r9) /* 801D6144 001D1DA4 90 E1 00 58 */ stw r7, 0x58(r1) -/* 801D6148 001D1DA8 48 00 34 C5 */ bl func_801D960C +/* 801D6148 001D1DA8 48 00 34 C5 */ bl TRKWriteUARTN /* 801D614C 001D1DAC 38 60 00 00 */ li r3, 0 /* 801D6150 001D1DB0 48 00 01 90 */ b lbl_801D62E0 lbl_801D6154: @@ -718,7 +718,7 @@ lbl_801D627C: /* 801D62C0 001D1F20 9B E1 00 14 */ stb r31, 0x14(r1) /* 801D62C4 001D1F24 90 08 00 00 */ stw r0, 0(r8) /* 801D62C8 001D1F28 90 C1 00 18 */ stw r6, 0x18(r1) -/* 801D62CC 001D1F2C 48 00 33 41 */ bl func_801D960C +/* 801D62CC 001D1F2C 48 00 33 41 */ bl TRKWriteUARTN /* 801D62D0 001D1F30 38 60 00 00 */ li r3, 0 /* 801D62D4 001D1F34 48 00 00 0C */ b lbl_801D62E0 lbl_801D62D8: @@ -769,7 +769,7 @@ TRKDoWriteMemory: /* 801D6378 001D1FD8 98 A1 00 6C */ stb r5, 0x6c(r1) /* 801D637C 001D1FDC 90 09 00 00 */ stw r0, 0(r9) /* 801D6380 001D1FE0 90 E1 00 70 */ stw r7, 0x70(r1) -/* 801D6384 001D1FE4 48 00 32 89 */ bl func_801D960C +/* 801D6384 001D1FE4 48 00 32 89 */ bl TRKWriteUARTN /* 801D6388 001D1FE8 38 60 00 00 */ li r3, 0 /* 801D638C 001D1FEC 48 00 01 64 */ b lbl_801D64F0 lbl_801D6390: @@ -859,7 +859,7 @@ lbl_801D648C: /* 801D64D0 001D2130 9B E1 00 2C */ stb r31, 0x2c(r1) /* 801D64D4 001D2134 90 08 00 00 */ stw r0, 0(r8) /* 801D64D8 001D2138 90 C1 00 30 */ stw r6, 0x30(r1) -/* 801D64DC 001D213C 48 00 31 31 */ bl func_801D960C +/* 801D64DC 001D213C 48 00 31 31 */ bl TRKWriteUARTN /* 801D64E0 001D2140 38 60 00 00 */ li r3, 0 /* 801D64E4 001D2144 48 00 00 0C */ b lbl_801D64F0 lbl_801D64E8: @@ -914,7 +914,7 @@ TRKDoReadMemory: /* 801D6598 001D21F8 98 A1 00 6C */ stb r5, 0x6c(r1) /* 801D659C 001D21FC 90 09 00 00 */ stw r0, 0(r9) /* 801D65A0 001D2200 90 E1 00 70 */ stw r7, 0x70(r1) -/* 801D65A4 001D2204 48 00 30 69 */ bl func_801D960C +/* 801D65A4 001D2204 48 00 30 69 */ bl TRKWriteUARTN /* 801D65A8 001D2208 38 60 00 00 */ li r3, 0 /* 801D65AC 001D220C 48 00 01 88 */ b lbl_801D6734 lbl_801D65B0: @@ -1014,7 +1014,7 @@ lbl_801D66D0: /* 801D6714 001D2374 9B A1 00 2C */ stb r29, 0x2c(r1) /* 801D6718 001D2378 90 08 00 00 */ stw r0, 0(r8) /* 801D671C 001D237C 90 C1 00 30 */ stw r6, 0x30(r1) -/* 801D6720 001D2380 48 00 2E ED */ bl func_801D960C +/* 801D6720 001D2380 48 00 2E ED */ bl TRKWriteUARTN /* 801D6724 001D2384 38 60 00 00 */ li r3, 0 /* 801D6728 001D2388 48 00 00 0C */ b lbl_801D6734 lbl_801D672C: @@ -1067,7 +1067,7 @@ TRKDoOverride: /* 801D67BC 001D241C 98 A1 00 10 */ stb r5, 0x10(r1) /* 801D67C0 001D2420 90 09 00 00 */ stw r0, 0(r9) /* 801D67C4 001D2424 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D67C8 001D2428 48 00 2E 45 */ bl func_801D960C +/* 801D67C8 001D2428 48 00 2E 45 */ bl TRKWriteUARTN /* 801D67CC 001D242C 48 00 2A E5 */ bl __TRK_copy_vectors /* 801D67D0 001D2430 80 01 00 54 */ lwz r0, 0x54(r1) /* 801D67D4 001D2434 38 60 00 00 */ li r3, 0 @@ -1101,7 +1101,7 @@ TRKDoReset: /* 801D6838 001D2498 98 A1 00 10 */ stb r5, 0x10(r1) /* 801D683C 001D249C 90 09 00 00 */ stw r0, 0(r9) /* 801D6840 001D24A0 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D6844 001D24A4 48 00 2D C9 */ bl func_801D960C +/* 801D6844 001D24A4 48 00 2D C9 */ bl TRKWriteUARTN /* 801D6848 001D24A8 4B E2 F8 75 */ bl __TRK_reset /* 801D684C 001D24AC 80 01 00 54 */ lwz r0, 0x54(r1) /* 801D6850 001D24B0 38 60 00 00 */ li r3, 0 @@ -1139,7 +1139,7 @@ TRKDoDisconnect: /* 801D68C4 001D2524 98 A1 00 1C */ stb r5, 0x1c(r1) /* 801D68C8 001D2528 90 09 00 00 */ stw r0, 0(r9) /* 801D68CC 001D252C 90 E1 00 20 */ stw r7, 0x20(r1) -/* 801D68D0 001D2530 48 00 2D 3D */ bl func_801D960C +/* 801D68D0 001D2530 48 00 2D 3D */ bl TRKWriteUARTN /* 801D68D4 001D2534 38 61 00 08 */ addi r3, r1, 8 /* 801D68D8 001D2538 38 80 00 01 */ li r4, 1 /* 801D68DC 001D253C 4B FF E0 79 */ bl TRKConstructEvent @@ -1181,7 +1181,7 @@ TRKDoConnect: /* 801D6960 001D25C0 98 A1 00 10 */ stb r5, 0x10(r1) /* 801D6964 001D25C4 90 09 00 00 */ stw r0, 0(r9) /* 801D6968 001D25C8 90 E1 00 14 */ stw r7, 0x14(r1) -/* 801D696C 001D25CC 48 00 2C A1 */ bl func_801D960C +/* 801D696C 001D25CC 48 00 2C A1 */ bl TRKWriteUARTN /* 801D6970 001D25D0 80 01 00 54 */ lwz r0, 0x54(r1) /* 801D6974 001D25D4 38 60 00 00 */ li r3, 0 /* 801D6978 001D25D8 7C 08 03 A6 */ mtlr r0 diff --git a/asm/MetroTRK/mslsupp.s b/asm/MetroTRK/mslsupp.s new file mode 100644 index 0000000..36fb110 --- /dev/null +++ b/asm/MetroTRK/mslsupp.s @@ -0,0 +1,117 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global __TRK_write_console +__TRK_write_console: +/* 801D8FC0 001D4C20 94 21 FF E0 */ stwu r1, -0x20(r1) +/* 801D8FC4 001D4C24 7C 08 02 A6 */ mflr r0 +/* 801D8FC8 001D4C28 90 01 00 24 */ stw r0, 0x24(r1) +/* 801D8FCC 001D4C2C 93 E1 00 1C */ stw r31, 0x1c(r1) +/* 801D8FD0 001D4C30 7C BF 2B 78 */ mr r31, r5 +/* 801D8FD4 001D4C34 93 C1 00 18 */ stw r30, 0x18(r1) +/* 801D8FD8 001D4C38 7C 9E 23 78 */ mr r30, r4 +/* 801D8FDC 001D4C3C 48 00 09 B1 */ bl GetUseSerialIO +/* 801D8FE0 001D4C40 54 60 06 3F */ clrlwi. r0, r3, 0x18 +/* 801D8FE4 001D4C44 40 82 00 0C */ bne lbl_801D8FF0 +/* 801D8FE8 001D4C48 38 60 00 01 */ li r3, 1 +/* 801D8FEC 001D4C4C 48 00 00 78 */ b lbl_801D9064 +lbl_801D8FF0: +/* 801D8FF0 001D4C50 4B FF D9 A1 */ bl GetTRKConnected +/* 801D8FF4 001D4C54 2C 03 00 00 */ cmpwi r3, 0 +/* 801D8FF8 001D4C58 40 82 00 0C */ bne lbl_801D9004 +/* 801D8FFC 001D4C5C 38 60 00 01 */ li r3, 1 +/* 801D9000 001D4C60 48 00 00 64 */ b lbl_801D9064 +lbl_801D9004: +/* 801D9004 001D4C64 80 1F 00 00 */ lwz r0, 0(r31) +/* 801D9008 001D4C68 7F C6 F3 78 */ mr r6, r30 +/* 801D900C 001D4C6C 38 A1 00 08 */ addi r5, r1, 8 +/* 801D9010 001D4C70 38 60 00 D0 */ li r3, 0xd0 +/* 801D9014 001D4C74 90 01 00 08 */ stw r0, 8(r1) +/* 801D9018 001D4C78 38 80 00 01 */ li r4, 1 +/* 801D901C 001D4C7C 4B FF FC 15 */ bl $6fill$6 +/* 801D9020 001D4C80 54 60 06 3E */ clrlwi r0, r3, 0x18 +/* 801D9024 001D4C84 80 61 00 08 */ lwz r3, 8(r1) +/* 801D9028 001D4C88 2C 00 00 01 */ cmpwi r0, 1 +/* 801D902C 001D4C8C 90 7F 00 00 */ stw r3, 0(r31) +/* 801D9030 001D4C90 41 82 00 30 */ beq lbl_801D9060 +/* 801D9034 001D4C94 40 80 00 10 */ bge lbl_801D9044 +/* 801D9038 001D4C98 2C 00 00 00 */ cmpwi r0, 0 +/* 801D903C 001D4C9C 40 80 00 14 */ bge lbl_801D9050 +/* 801D9040 001D4CA0 48 00 00 20 */ b lbl_801D9060 +lbl_801D9044: +/* 801D9044 001D4CA4 2C 00 00 03 */ cmpwi r0, 3 +/* 801D9048 001D4CA8 40 80 00 18 */ bge lbl_801D9060 +/* 801D904C 001D4CAC 48 00 00 0C */ b lbl_801D9058 +lbl_801D9050: +/* 801D9050 001D4CB0 38 60 00 00 */ li r3, 0 +/* 801D9054 001D4CB4 48 00 00 10 */ b lbl_801D9064 +lbl_801D9058: +/* 801D9058 001D4CB8 38 60 00 02 */ li r3, 2 +/* 801D905C 001D4CBC 48 00 00 08 */ b lbl_801D9064 +lbl_801D9060: +/* 801D9060 001D4CC0 38 60 00 01 */ li r3, 1 +lbl_801D9064: +/* 801D9064 001D4CC4 80 01 00 24 */ lwz r0, 0x24(r1) +/* 801D9068 001D4CC8 83 E1 00 1C */ lwz r31, 0x1c(r1) +/* 801D906C 001D4CCC 83 C1 00 18 */ lwz r30, 0x18(r1) +/* 801D9070 001D4CD0 7C 08 03 A6 */ mtlr r0 +/* 801D9074 001D4CD4 38 21 00 20 */ addi r1, r1, 0x20 +/* 801D9078 001D4CD8 4E 80 00 20 */ blr + +.global __read_console +__read_console: +/* 801D907C 001D4CDC 94 21 FF E0 */ stwu r1, -0x20(r1) +/* 801D9080 001D4CE0 7C 08 02 A6 */ mflr r0 +/* 801D9084 001D4CE4 90 01 00 24 */ stw r0, 0x24(r1) +/* 801D9088 001D4CE8 93 E1 00 1C */ stw r31, 0x1c(r1) +/* 801D908C 001D4CEC 7C BF 2B 78 */ mr r31, r5 +/* 801D9090 001D4CF0 93 C1 00 18 */ stw r30, 0x18(r1) +/* 801D9094 001D4CF4 7C 9E 23 78 */ mr r30, r4 +/* 801D9098 001D4CF8 48 00 08 F5 */ bl GetUseSerialIO +/* 801D909C 001D4CFC 54 60 06 3F */ clrlwi. r0, r3, 0x18 +/* 801D90A0 001D4D00 40 82 00 0C */ bne lbl_801D90AC +/* 801D90A4 001D4D04 38 60 00 01 */ li r3, 1 +/* 801D90A8 001D4D08 48 00 00 78 */ b lbl_801D9120 +lbl_801D90AC: +/* 801D90AC 001D4D0C 4B FF D8 E5 */ bl GetTRKConnected +/* 801D90B0 001D4D10 2C 03 00 00 */ cmpwi r3, 0 +/* 801D90B4 001D4D14 40 82 00 0C */ bne lbl_801D90C0 +/* 801D90B8 001D4D18 38 60 00 01 */ li r3, 1 +/* 801D90BC 001D4D1C 48 00 00 64 */ b lbl_801D9120 +lbl_801D90C0: +/* 801D90C0 001D4D20 80 1F 00 00 */ lwz r0, 0(r31) +/* 801D90C4 001D4D24 7F C6 F3 78 */ mr r6, r30 +/* 801D90C8 001D4D28 38 A1 00 08 */ addi r5, r1, 8 +/* 801D90CC 001D4D2C 38 60 00 D1 */ li r3, 0xd1 +/* 801D90D0 001D4D30 90 01 00 08 */ stw r0, 8(r1) +/* 801D90D4 001D4D34 38 80 00 00 */ li r4, 0 +/* 801D90D8 001D4D38 4B FF FB 59 */ bl $6fill$6 +/* 801D90DC 001D4D3C 54 60 06 3E */ clrlwi r0, r3, 0x18 +/* 801D90E0 001D4D40 80 61 00 08 */ lwz r3, 8(r1) +/* 801D90E4 001D4D44 2C 00 00 01 */ cmpwi r0, 1 +/* 801D90E8 001D4D48 90 7F 00 00 */ stw r3, 0(r31) +/* 801D90EC 001D4D4C 41 82 00 30 */ beq lbl_801D911C +/* 801D90F0 001D4D50 40 80 00 10 */ bge lbl_801D9100 +/* 801D90F4 001D4D54 2C 00 00 00 */ cmpwi r0, 0 +/* 801D90F8 001D4D58 40 80 00 14 */ bge lbl_801D910C +/* 801D90FC 001D4D5C 48 00 00 20 */ b lbl_801D911C +lbl_801D9100: +/* 801D9100 001D4D60 2C 00 00 03 */ cmpwi r0, 3 +/* 801D9104 001D4D64 40 80 00 18 */ bge lbl_801D911C +/* 801D9108 001D4D68 48 00 00 0C */ b lbl_801D9114 +lbl_801D910C: +/* 801D910C 001D4D6C 38 60 00 00 */ li r3, 0 +/* 801D9110 001D4D70 48 00 00 10 */ b lbl_801D9120 +lbl_801D9114: +/* 801D9114 001D4D74 38 60 00 02 */ li r3, 2 +/* 801D9118 001D4D78 48 00 00 08 */ b lbl_801D9120 +lbl_801D911C: +/* 801D911C 001D4D7C 38 60 00 01 */ li r3, 1 +lbl_801D9120: +/* 801D9120 001D4D80 80 01 00 24 */ lwz r0, 0x24(r1) +/* 801D9124 001D4D84 83 E1 00 1C */ lwz r31, 0x1c(r1) +/* 801D9128 001D4D88 83 C1 00 18 */ lwz r30, 0x18(r1) +/* 801D912C 001D4D8C 7C 08 03 A6 */ mtlr r0 +/* 801D9130 001D4D90 38 21 00 20 */ addi r1, r1, 0x20 +/* 801D9134 001D4D94 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/serpoll.s b/asm/MetroTRK/serpoll.s index 5aa893b..03d6581 100644 --- a/asm/MetroTRK/serpoll.s +++ b/asm/MetroTRK/serpoll.s @@ -76,7 +76,7 @@ TRKTestForPacket: /* 801D5624 001D1284 7C 08 02 A6 */ mflr r0 /* 801D5628 001D1288 90 01 08 E4 */ stw r0, 0x8e4(r1) /* 801D562C 001D128C 93 E1 08 DC */ stw r31, 0x8dc(r1) -/* 801D5630 001D1290 48 00 40 55 */ bl func_801D9684 +/* 801D5630 001D1290 48 00 40 55 */ bl TRKPollUART /* 801D5634 001D1294 2C 03 00 00 */ cmpwi r3, 0 /* 801D5638 001D1298 41 81 00 0C */ bgt lbl_801D5644 /* 801D563C 001D129C 38 60 FF FF */ li r3, -1 @@ -92,7 +92,7 @@ lbl_801D5644: /* 801D5660 001D12C0 4B FF FC A9 */ bl TRKSetBufferPosition /* 801D5664 001D12C4 38 61 00 10 */ addi r3, r1, 0x10 /* 801D5668 001D12C8 38 80 00 40 */ li r4, 0x40 -/* 801D566C 001D12CC 48 00 3F DD */ bl TRKWriteUARTN +/* 801D566C 001D12CC 48 00 3F DD */ bl TRKReadUARTN /* 801D5670 001D12D0 2C 03 00 00 */ cmpwi r3, 0 /* 801D5674 001D12D4 40 82 00 58 */ bne lbl_801D56CC /* 801D5678 001D12D8 80 61 00 08 */ lwz r3, 8(r1) @@ -104,7 +104,7 @@ lbl_801D5644: /* 801D5690 001D12F0 34 83 FF C0 */ addic. r4, r3, -64 /* 801D5694 001D12F4 40 81 00 44 */ ble lbl_801D56D8 /* 801D5698 001D12F8 38 61 00 50 */ addi r3, r1, 0x50 -/* 801D569C 001D12FC 48 00 3F AD */ bl TRKWriteUARTN +/* 801D569C 001D12FC 48 00 3F AD */ bl TRKReadUARTN /* 801D56A0 001D1300 2C 03 00 00 */ cmpwi r3, 0 /* 801D56A4 001D1304 40 82 00 18 */ bne lbl_801D56BC /* 801D56A8 001D1308 80 61 00 08 */ lwz r3, 8(r1) diff --git a/asm/MetroTRK/support.s b/asm/MetroTRK/support.s index d58dcbe..014d4b3 100644 --- a/asm/MetroTRK/support.s +++ b/asm/MetroTRK/support.s @@ -264,7 +264,7 @@ lbl_801D6D34: /* 801D6D4C 001D29AC 4B FF E5 BD */ bl TRKSetBufferPosition /* 801D6D50 001D29B0 80 9E 00 08 */ lwz r4, 8(r30) /* 801D6D54 001D29B4 38 7E 00 10 */ addi r3, r30, 0x10 -/* 801D6D58 001D29B8 48 00 2F 0D */ bl func_801D9C64 +/* 801D6D58 001D29B8 48 00 2F 0D */ bl OutputData /* 801D6D5C 001D29BC 8B 7E 00 14 */ lbz r27, 0x14(r30) /* 801D6D60 001D29C0 28 1B 00 80 */ cmplwi r27, 0x80 /* 801D6D64 001D29C4 40 80 00 18 */ bge lbl_801D6D7C diff --git a/asm/MetroTRK/targcont.s b/asm/MetroTRK/targcont.s new file mode 100644 index 0000000..f5f6ba8 --- /dev/null +++ b/asm/MetroTRK/targcont.s @@ -0,0 +1,19 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global TRKTargetContinue +TRKTargetContinue: +/* 801D9958 001D55B8 94 21 FF F0 */ stwu r1, -0x10(r1) +/* 801D995C 001D55BC 7C 08 02 A6 */ mflr r0 +/* 801D9960 001D55C0 38 60 00 00 */ li r3, 0 +/* 801D9964 001D55C4 90 01 00 14 */ stw r0, 0x14(r1) +/* 801D9968 001D55C8 4B FF DC AD */ bl TRKTargetSetStopped +/* 801D996C 001D55CC 4B FF FC 41 */ bl UnreserveEXI2Port +/* 801D9970 001D55D0 4B FF DB 1D */ bl TRKSwapAndGo +/* 801D9974 001D55D4 4B FF FC 69 */ bl ReserveEXI2Port +/* 801D9978 001D55D8 80 01 00 14 */ lwz r0, 0x14(r1) +/* 801D997C 001D55DC 38 60 00 00 */ li r3, 0 +/* 801D9980 001D55E0 7C 08 03 A6 */ mtlr r0 +/* 801D9984 001D55E4 38 21 00 10 */ addi r1, r1, 0x10 +/* 801D9988 001D55E8 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/target_options.s b/asm/MetroTRK/target_options.s new file mode 100644 index 0000000..eac0d48 --- /dev/null +++ b/asm/MetroTRK/target_options.s @@ -0,0 +1,16 @@ +.include "macros.inc" + +.section .text, "ax" # 0x80006980 - 0x803E1E60 + +.global GetUseSerialIO +GetUseSerialIO: +/* 801D998C 001D55EC 3C 60 80 49 */ lis r3, lbl_80490D88@ha +/* 801D9990 001D55F0 38 63 0D 88 */ addi r3, r3, lbl_80490D88@l +/* 801D9994 001D55F4 88 63 00 00 */ lbz r3, 0(r3) +/* 801D9998 001D55F8 4E 80 00 20 */ blr + +.global SetUseSerialIO +SetUseSerialIO: +/* 801D999C 001D55FC 3C 80 80 49 */ lis r4, lbl_80490D88@ha +/* 801D99A0 001D5600 98 64 0D 88 */ stb r3, lbl_80490D88@l(r4) +/* 801D99A4 001D5604 4E 80 00 20 */ blr diff --git a/asm/MetroTRK/targimpl.s b/asm/MetroTRK/targimpl.s index 5355556..47e43d4 100644 --- a/asm/MetroTRK/targimpl.s +++ b/asm/MetroTRK/targimpl.s @@ -56,7 +56,7 @@ TRKInterruptHandler: /* 801D72A8 001D2F08 60 42 08 98 */ ori r2, r2, lbl_80490898@l /* 801D72AC 001D2F0C 7C 68 02 A6 */ mflr r3 /* 801D72B0 001D2F10 90 62 04 2C */ stw r3, 0x42c(r2) -/* 801D72B4 001D2F14 48 00 22 6D */ bl func_801D9520 +/* 801D72B4 001D2F14 48 00 22 6D */ bl TRKUARTInterruptHandler /* 801D72B8 001D2F18 3C 40 80 49 */ lis r2, lbl_80490898@h /* 801D72BC 001D2F1C 60 42 08 98 */ ori r2, r2, lbl_80490898@l /* 801D72C0 001D2F20 80 62 04 2C */ lwz r3, 0x42c(r2) @@ -1867,3 +1867,14 @@ lbl_801D8C14: /* 801D8C24 001D4884 4E 80 00 20 */ blr /* 801D8C28 001D4888 00 00 00 00 */ .4byte 0x00000000 /* unknown instruction */ /* 801D8C2C 001D488C 00 00 00 00 */ .4byte 0x00000000 /* unknown instruction */ + +.global $6fill$6 +$6fill$6: +/* 801D8C30 001D4890 0F E0 00 00 */ twui r0, 0 +/* 801D8C34 001D4894 4E 80 00 20 */ blr +/* 801D8C38 001D4898 0F E0 00 00 */ twui r0, 0 +/* 801D8C3C 001D489C 4E 80 00 20 */ blr +/* 801D8C40 001D48A0 0F E0 00 00 */ twui r0, 0 +/* 801D8C44 001D48A4 4E 80 00 20 */ blr +/* 801D8C48 001D48A8 0F E0 00 00 */ twui r0, 0 +/* 801D8C4C 001D48AC 4E 80 00 20 */ blr diff --git a/asm/SDK/OS/OS.s b/asm/SDK/OS/OS.s index e8a8187..7958cf4 100644 --- a/asm/SDK/OS/OS.s +++ b/asm/SDK/OS/OS.s @@ -959,7 +959,7 @@ lbl_802690AC: /* 802690CC 00264D2C 80 03 00 00 */ lwz r0, 0(r3) /* 802690D0 00264D30 28 00 00 02 */ cmplwi r0, 2 /* 802690D4 00264D34 41 80 00 08 */ blt lbl_802690DC -/* 802690D8 00264D38 4B F7 03 5D */ bl func_801D9434 +/* 802690D8 00264D38 4B F7 03 5D */ bl EnableMetroTRKInterrupts lbl_802690DC: /* 802690DC 00264D3C 4B FF F6 C1 */ bl ClearArena /* 802690E0 00264D40 4B FF F8 99 */ bl ClearMEM2Arena diff --git a/asm/text_6_2.s b/asm/text_6_2.s index 8c3c9dc..334e528 100644 --- a/asm/text_6_2.s +++ b/asm/text_6_2.s @@ -2,1430 +2,6 @@ .section .text, "ax" # 0x80006980 - 0x803E1E60 -.global func_801D8C30 -func_801D8C30: -/* 801D8C30 001D4890 0F E0 00 00 */ twui r0, 0 -/* 801D8C34 001D4894 4E 80 00 20 */ blr -/* 801D8C38 001D4898 0F E0 00 00 */ twui r0, 0 -/* 801D8C3C 001D489C 4E 80 00 20 */ blr -/* 801D8C40 001D48A0 0F E0 00 00 */ twui r0, 0 -/* 801D8C44 001D48A4 4E 80 00 20 */ blr -/* 801D8C48 001D48A8 0F E0 00 00 */ twui r0, 0 -/* 801D8C4C 001D48AC 4E 80 00 20 */ blr - -.global TRKSaveExtended1Block -TRKSaveExtended1Block: -/* 801D8C50 001D48B0 3C 40 80 49 */ lis r2, lbl_80490898@h -/* 801D8C54 001D48B4 60 42 08 98 */ ori r2, r2, lbl_80490898@l -/* 801D8C58 001D48B8 7E 00 04 A6 */ mfsr r16, 0 -/* 801D8C5C 001D48BC 7E 21 04 A6 */ mfsr r17, 1 -/* 801D8C60 001D48C0 7E 42 04 A6 */ mfsr r18, 2 -/* 801D8C64 001D48C4 7E 63 04 A6 */ mfsr r19, 3 -/* 801D8C68 001D48C8 7E 84 04 A6 */ mfsr r20, 4 -/* 801D8C6C 001D48CC 7E A5 04 A6 */ mfsr r21, 5 -/* 801D8C70 001D48D0 7E C6 04 A6 */ mfsr r22, 6 -/* 801D8C74 001D48D4 7E E7 04 A6 */ mfsr r23, 7 -/* 801D8C78 001D48D8 7F 08 04 A6 */ mfsr r24, 8 -/* 801D8C7C 001D48DC 7F 29 04 A6 */ mfsr r25, 9 -/* 801D8C80 001D48E0 7F 4A 04 A6 */ mfsr r26, 0xa -/* 801D8C84 001D48E4 7F 6B 04 A6 */ mfsr r27, 0xb -/* 801D8C88 001D48E8 7F 8C 04 A6 */ mfsr r28, 0xc -/* 801D8C8C 001D48EC 7F AD 04 A6 */ mfsr r29, 0xd -/* 801D8C90 001D48F0 7F CE 04 A6 */ mfsr r30, 0xe -/* 801D8C94 001D48F4 7F EF 04 A6 */ mfsr r31, 0xf -/* 801D8C98 001D48F8 BE 02 01 A8 */ stmw r16, 0x1a8(r2) -/* 801D8C9C 001D48FC 7D 4C 42 E6 */ mftb r10, 0x10c -/* 801D8CA0 001D4900 7D 6D 42 E6 */ mftbu r11 -/* 801D8CA4 001D4904 7D 90 FA A6 */ mfspr r12, 0x3f0 -/* 801D8CA8 001D4908 7D B1 FA A6 */ mfspr r13, 0x3f1 -/* 801D8CAC 001D490C 7D DB 02 A6 */ mfspr r14, 0x1b -/* 801D8CB0 001D4910 7D FF 42 A6 */ mfpvr r15 -/* 801D8CB4 001D4914 7E 10 82 A6 */ mfibatu r16, 0 -/* 801D8CB8 001D4918 7E 31 82 A6 */ mfibatl r17, 0 -/* 801D8CBC 001D491C 7E 52 82 A6 */ mfibatu r18, 1 -/* 801D8CC0 001D4920 7E 73 82 A6 */ mfibatl r19, 1 -/* 801D8CC4 001D4924 7E 94 82 A6 */ mfibatu r20, 2 -/* 801D8CC8 001D4928 7E B5 82 A6 */ mfibatl r21, 2 -/* 801D8CCC 001D492C 7E D6 82 A6 */ mfibatu r22, 3 -/* 801D8CD0 001D4930 7E F7 82 A6 */ mfibatl r23, 3 -/* 801D8CD4 001D4934 7F 18 82 A6 */ mfdbatu r24, 0 -/* 801D8CD8 001D4938 7F 39 82 A6 */ mfdbatl r25, 0 -/* 801D8CDC 001D493C 7F 5A 82 A6 */ mfdbatu r26, 1 -/* 801D8CE0 001D4940 7F 7B 82 A6 */ mfdbatl r27, 1 -/* 801D8CE4 001D4944 7F 9C 82 A6 */ mfdbatu r28, 2 -/* 801D8CE8 001D4948 7F BD 82 A6 */ mfdbatl r29, 2 -/* 801D8CEC 001D494C 7F DE 82 A6 */ mfdbatu r30, 3 -/* 801D8CF0 001D4950 7F FF 82 A6 */ mfdbatl r31, 3 -/* 801D8CF4 001D4954 BD 42 01 E8 */ stmw r10, 0x1e8(r2) -/* 801D8CF8 001D4958 7E D9 02 A6 */ mfspr r22, 0x19 -/* 801D8CFC 001D495C 7E F3 02 A6 */ mfdar r23 -/* 801D8D00 001D4960 7F 12 02 A6 */ mfdsisr r24 -/* 801D8D04 001D4964 7F 30 42 A6 */ mfspr r25, 0x110 -/* 801D8D08 001D4968 7F 51 42 A6 */ mfspr r26, 0x111 -/* 801D8D0C 001D496C 7F 72 42 A6 */ mfspr r27, 0x112 -/* 801D8D10 001D4970 7F 93 42 A6 */ mfspr r28, 0x113 -/* 801D8D14 001D4974 3B A0 00 00 */ li r29, 0 -/* 801D8D18 001D4978 7F D2 FA A6 */ mfspr r30, 0x3f2 -/* 801D8D1C 001D497C 7F FA 42 A6 */ mfspr r31, 0x11a -/* 801D8D20 001D4980 BE C2 02 5C */ stmw r22, 0x25c(r2) -/* 801D8D24 001D4984 7E 90 E2 A6 */ mfspr r20, 0x390 -/* 801D8D28 001D4988 7E B1 E2 A6 */ mfspr r21, 0x391 -/* 801D8D2C 001D498C 7E D2 E2 A6 */ mfspr r22, 0x392 -/* 801D8D30 001D4990 7E F3 E2 A6 */ mfspr r23, 0x393 -/* 801D8D34 001D4994 7F 14 E2 A6 */ mfspr r24, 0x394 -/* 801D8D38 001D4998 7F 35 E2 A6 */ mfspr r25, 0x395 -/* 801D8D3C 001D499C 7F 56 E2 A6 */ mfspr r26, 0x396 -/* 801D8D40 001D49A0 7F 77 E2 A6 */ mfspr r27, 0x397 -/* 801D8D44 001D49A4 7F 98 E2 A6 */ mfspr r28, 0x398 -/* 801D8D48 001D49A8 7F B9 E2 A6 */ mfspr r29, 0x399 -/* 801D8D4C 001D49AC 7F DA E2 A6 */ mfspr r30, 0x39a -/* 801D8D50 001D49B0 7F FB E2 A6 */ mfspr r31, 0x39b -/* 801D8D54 001D49B4 BE 82 02 FC */ stmw r20, 0x2fc(r2) -/* 801D8D58 001D49B8 48 00 00 48 */ b lbl_801D8DA0 -/* 801D8D5C 001D49BC 7E 00 EA A6 */ mfspr r16, 0x3a0 -/* 801D8D60 001D49C0 7E 27 EA A6 */ mfspr r17, 0x3a7 -/* 801D8D64 001D49C4 7E 48 EA A6 */ mfspr r18, 0x3a8 -/* 801D8D68 001D49C8 7E 69 EA A6 */ mfspr r19, 0x3a9 -/* 801D8D6C 001D49CC 7E 8A EA A6 */ mfspr r20, 0x3aa -/* 801D8D70 001D49D0 7E AB EA A6 */ mfspr r21, 0x3ab -/* 801D8D74 001D49D4 7E CC EA A6 */ mfspr r22, 0x3ac -/* 801D8D78 001D49D8 7E ED EA A6 */ mfspr r23, 0x3ad -/* 801D8D7C 001D49DC 7F 0E EA A6 */ mfspr r24, 0x3ae -/* 801D8D80 001D49E0 7F 2F EA A6 */ mfspr r25, 0x3af -/* 801D8D84 001D49E4 7F 50 EA A6 */ mfspr r26, 0x3b0 -/* 801D8D88 001D49E8 7F 77 EA A6 */ mfspr r27, 0x3b7 -/* 801D8D8C 001D49EC 7F 9F EA A6 */ mfspr r28, 0x3bf -/* 801D8D90 001D49F0 7F B6 FA A6 */ mfspr r29, 0x3f6 -/* 801D8D94 001D49F4 7F D7 FA A6 */ mfspr r30, 0x3f7 -/* 801D8D98 001D49F8 7F FF FA A6 */ mfspr r31, 0x3ff -/* 801D8D9C 001D49FC BE 02 02 B8 */ stmw r16, 0x2b8(r2) -lbl_801D8DA0: -/* 801D8DA0 001D4A00 7E 75 FA A6 */ mfspr r19, 0x3f5 -/* 801D8DA4 001D4A04 7E 99 EA A6 */ mfspr r20, 0x3b9 -/* 801D8DA8 001D4A08 7E BA EA A6 */ mfspr r21, 0x3ba -/* 801D8DAC 001D4A0C 7E DD EA A6 */ mfspr r22, 0x3bd -/* 801D8DB0 001D4A10 7E FE EA A6 */ mfspr r23, 0x3be -/* 801D8DB4 001D4A14 7F 1B EA A6 */ mfspr r24, 0x3bb -/* 801D8DB8 001D4A18 7F 38 EA A6 */ mfspr r25, 0x3b8 -/* 801D8DBC 001D4A1C 7F 5C EA A6 */ mfspr r26, 0x3bc -/* 801D8DC0 001D4A20 7F 7C FA A6 */ mfspr r27, 0x3fc -/* 801D8DC4 001D4A24 7F 9D FA A6 */ mfspr r28, 0x3fd -/* 801D8DC8 001D4A28 7F BE FA A6 */ mfspr r29, 0x3fe -/* 801D8DCC 001D4A2C 7F DB FA A6 */ mfspr r30, 0x3FB -/* 801D8DD0 001D4A30 7F F9 FA A6 */ mfspr r31, 0x3f9 -/* 801D8DD4 001D4A34 BE 62 02 84 */ stmw r19, 0x284(r2) -/* 801D8DD8 001D4A38 4E 80 00 20 */ blr -/* 801D8DDC 001D4A3C 7F 30 F2 A6 */ mfspr r25, 0x3d0 -/* 801D8DE0 001D4A40 7F 51 F2 A6 */ mfspr r26, 0x3d1 -/* 801D8DE4 001D4A44 7F 72 F2 A6 */ mfspr r27, 0x3d2 -/* 801D8DE8 001D4A48 7F 93 F2 A6 */ mfspr r28, 0x3d3 -/* 801D8DEC 001D4A4C 7F B4 F2 A6 */ mfspr r29, 0x3D4 -/* 801D8DF0 001D4A50 7F D5 F2 A6 */ mfspr r30, 0x3D5 -/* 801D8DF4 001D4A54 7F F6 F2 A6 */ mfspr r31, 0x3d6 -/* 801D8DF8 001D4A58 BF 22 02 40 */ stmw r25, 0x240(r2) -/* 801D8DFC 001D4A5C 7F F6 02 A6 */ mfspr r31, 0x16 -/* 801D8E00 001D4A60 93 E2 02 78 */ stw r31, 0x278(r2) -/* 801D8E04 001D4A64 4E 80 00 20 */ blr - -.global TRKRestoreExtended1Block -TRKRestoreExtended1Block: -/* 801D8E08 001D4A68 3C 40 80 49 */ lis r2, lbl_80490898@h -/* 801D8E0C 001D4A6C 60 42 08 98 */ ori r2, r2, lbl_80490898@l -/* 801D8E10 001D4A70 3C A0 80 42 */ lis r5, lbl_80423230@h -/* 801D8E14 001D4A74 60 A5 32 30 */ ori r5, r5, lbl_80423230@l -/* 801D8E18 001D4A78 88 65 00 00 */ lbz r3, 0(r5) -/* 801D8E1C 001D4A7C 88 C5 00 01 */ lbz r6, 1(r5) -/* 801D8E20 001D4A80 38 00 00 00 */ li r0, 0 -/* 801D8E24 001D4A84 98 05 00 00 */ stb r0, 0(r5) -/* 801D8E28 001D4A88 98 05 00 01 */ stb r0, 1(r5) -/* 801D8E2C 001D4A8C 2C 03 00 00 */ cmpwi r3, 0 -/* 801D8E30 001D4A90 41 82 00 14 */ beq lbl_801D8E44 -/* 801D8E34 001D4A94 83 02 01 E8 */ lwz r24, 0x1e8(r2) -/* 801D8E38 001D4A98 83 22 01 EC */ lwz r25, 0x1ec(r2) -/* 801D8E3C 001D4A9C 7F 1C 43 A6 */ mttbl r24 -/* 801D8E40 001D4AA0 7F 3D 43 A6 */ mttbu r25 -lbl_801D8E44: -/* 801D8E44 001D4AA4 BA 82 02 FC */ lmw r20, 0x2fc(r2) -/* 801D8E48 001D4AA8 7E 90 E3 A6 */ mtspr 0x390, r20 -/* 801D8E4C 001D4AAC 7E B1 E3 A6 */ mtspr 0x391, r21 -/* 801D8E50 001D4AB0 7E D2 E3 A6 */ mtspr 0x392, r22 -/* 801D8E54 001D4AB4 7E F3 E3 A6 */ mtspr 0x393, r23 -/* 801D8E58 001D4AB8 7F 14 E3 A6 */ mtspr 0x394, r24 -/* 801D8E5C 001D4ABC 7F 35 E3 A6 */ mtspr 0x395, r25 -/* 801D8E60 001D4AC0 7F 56 E3 A6 */ mtspr 0x396, r26 -/* 801D8E64 001D4AC4 7F 77 E3 A6 */ mtspr 0x397, r27 -/* 801D8E68 001D4AC8 7F 98 E3 A6 */ mtspr 0x398, r28 -/* 801D8E6C 001D4ACC 7F DA E3 A6 */ mtspr 0x39a, r30 -/* 801D8E70 001D4AD0 7F FB E3 A6 */ mtspr 0x39b, r31 -/* 801D8E74 001D4AD4 48 00 00 1C */ b lbl_801D8E90 -/* 801D8E78 001D4AD8 BB 42 02 E0 */ lmw r26, 0x2e0(r2) -/* 801D8E7C 001D4ADC 7F 50 EB A6 */ mtspr 0x3b0, r26 -/* 801D8E80 001D4AE0 7F 77 EB A6 */ mtspr 0x3b7, r27 -/* 801D8E84 001D4AE4 7F B6 FB A6 */ mtspr 0x3f6, r29 -/* 801D8E88 001D4AE8 7F D7 FB A6 */ mtspr 0x3f7, r30 -/* 801D8E8C 001D4AEC 7F FF FB A6 */ mtspr 0x3ff, r31 -lbl_801D8E90: -/* 801D8E90 001D4AF0 BA 62 02 84 */ lmw r19, 0x284(r2) -/* 801D8E94 001D4AF4 7E 75 FB A6 */ mtspr 0x3f5, r19 -/* 801D8E98 001D4AF8 7E 99 EB A6 */ mtspr 0x3b9, r20 -/* 801D8E9C 001D4AFC 7E BA EB A6 */ mtspr 0x3ba, r21 -/* 801D8EA0 001D4B00 7E DD EB A6 */ mtspr 0x3bd, r22 -/* 801D8EA4 001D4B04 7E FE EB A6 */ mtspr 0x3be, r23 -/* 801D8EA8 001D4B08 7F 1B EB A6 */ mtspr 0x3bb, r24 -/* 801D8EAC 001D4B0C 7F 38 EB A6 */ mtspr 0x3b8, r25 -/* 801D8EB0 001D4B10 7F 5C EB A6 */ mtspr 0x3bc, r26 -/* 801D8EB4 001D4B14 7F 7C FB A6 */ mtspr 0x3fc, r27 -/* 801D8EB8 001D4B18 7F 9D FB A6 */ mtspr 0x3fd, r28 -/* 801D8EBC 001D4B1C 7F BE FB A6 */ mtspr 0x3fe, r29 -/* 801D8EC0 001D4B20 7F DB FB A6 */ mtictc r30 -/* 801D8EC4 001D4B24 7F F9 FB A6 */ mtspr 0x3f9, r31 -/* 801D8EC8 001D4B28 48 00 00 34 */ b lbl_801D8EFC -/* 801D8ECC 001D4B2C 2C 06 00 00 */ cmpwi r6, 0 -/* 801D8ED0 001D4B30 41 82 00 0C */ beq lbl_801D8EDC -/* 801D8ED4 001D4B34 83 42 02 78 */ lwz r26, 0x278(r2) -/* 801D8ED8 001D4B38 7F 56 03 A6 */ mtspr 0x16, r26 -lbl_801D8EDC: -/* 801D8EDC 001D4B3C BB 22 02 40 */ lmw r25, 0x240(r2) -/* 801D8EE0 001D4B40 7F 30 F3 A6 */ mtspr 0x3d0, r25 -/* 801D8EE4 001D4B44 7F 51 F3 A6 */ mtspr 0x3d1, r26 -/* 801D8EE8 001D4B48 7F 72 F3 A6 */ mtspr 0x3d2, r27 -/* 801D8EEC 001D4B4C 7F 93 F3 A6 */ mtspr 0x3d3, r28 -/* 801D8EF0 001D4B50 7F B4 F3 A6 */ mtspr 0x3D4, r29 -/* 801D8EF4 001D4B54 7F D5 F3 A6 */ mtspr 0x3D5, r30 -/* 801D8EF8 001D4B58 7F F6 F3 A6 */ mtspr 0x3d6, r31 -lbl_801D8EFC: -/* 801D8EFC 001D4B5C BA 02 01 A8 */ lmw r16, 0x1a8(r2) -/* 801D8F00 001D4B60 7E 00 01 A4 */ mtsr 0, r16 -/* 801D8F04 001D4B64 7E 21 01 A4 */ mtsr 1, r17 -/* 801D8F08 001D4B68 7E 42 01 A4 */ mtsr 2, r18 -/* 801D8F0C 001D4B6C 7E 63 01 A4 */ mtsr 3, r19 -/* 801D8F10 001D4B70 7E 84 01 A4 */ mtsr 4, r20 -/* 801D8F14 001D4B74 7E A5 01 A4 */ mtsr 5, r21 -/* 801D8F18 001D4B78 7E C6 01 A4 */ mtsr 6, r22 -/* 801D8F1C 001D4B7C 7E E7 01 A4 */ mtsr 7, r23 -/* 801D8F20 001D4B80 7F 08 01 A4 */ mtsr 8, r24 -/* 801D8F24 001D4B84 7F 29 01 A4 */ mtsr 9, r25 -/* 801D8F28 001D4B88 7F 4A 01 A4 */ mtsr 0xa, r26 -/* 801D8F2C 001D4B8C 7F 6B 01 A4 */ mtsr 0xb, r27 -/* 801D8F30 001D4B90 7F 8C 01 A4 */ mtsr 0xc, r28 -/* 801D8F34 001D4B94 7F AD 01 A4 */ mtsr 0xd, r29 -/* 801D8F38 001D4B98 7F CE 01 A4 */ mtsr 0xe, r30 -/* 801D8F3C 001D4B9C 7F EF 01 A4 */ mtsr 0xf, r31 -/* 801D8F40 001D4BA0 B9 82 01 F0 */ lmw r12, 0x1f0(r2) -/* 801D8F44 001D4BA4 7D 90 FB A6 */ mtspr 0x3f0, r12 -/* 801D8F48 001D4BA8 7D B1 FB A6 */ mtspr 0x3f1, r13 -/* 801D8F4C 001D4BAC 7D DB 03 A6 */ mtspr 0x1b, r14 -/* 801D8F50 001D4BB0 7D FF 43 A6 */ mtspr 0x11f, r15 -/* 801D8F54 001D4BB4 7E 10 83 A6 */ mtibatu 0, r16 -/* 801D8F58 001D4BB8 7E 31 83 A6 */ mtibatl 0, r17 -/* 801D8F5C 001D4BBC 7E 52 83 A6 */ mtibatu 1, r18 -/* 801D8F60 001D4BC0 7E 73 83 A6 */ mtibatl 1, r19 -/* 801D8F64 001D4BC4 7E 94 83 A6 */ mtibatu 2, r20 -/* 801D8F68 001D4BC8 7E B5 83 A6 */ mtibatl 2, r21 -/* 801D8F6C 001D4BCC 7E D6 83 A6 */ mtibatu 3, r22 -/* 801D8F70 001D4BD0 7E F7 83 A6 */ mtibatl 3, r23 -/* 801D8F74 001D4BD4 7F 18 83 A6 */ mtdbatu 0, r24 -/* 801D8F78 001D4BD8 7F 39 83 A6 */ mtdbatl 0, r25 -/* 801D8F7C 001D4BDC 7F 5A 83 A6 */ mtdbatu 1, r26 -/* 801D8F80 001D4BE0 7F 7B 83 A6 */ mtdbatl 1, r27 -/* 801D8F84 001D4BE4 7F 9C 83 A6 */ mtdbatu 2, r28 -/* 801D8F88 001D4BE8 7F BD 83 A6 */ mtdbatl 2, r29 -/* 801D8F8C 001D4BEC 7F DE 83 A6 */ mtdbatu 3, r30 -/* 801D8F90 001D4BF0 7F FF 83 A6 */ mtdbatl 3, r31 -/* 801D8F94 001D4BF4 BA C2 02 5C */ lmw r22, 0x25c(r2) -/* 801D8F98 001D4BF8 7E D9 03 A6 */ mtspr 0x19, r22 -/* 801D8F9C 001D4BFC 7E F3 03 A6 */ mtdar r23 -/* 801D8FA0 001D4C00 7F 12 03 A6 */ mtdsisr r24 -/* 801D8FA4 001D4C04 7F 30 43 A6 */ mtspr 0x110, r25 -/* 801D8FA8 001D4C08 7F 51 43 A6 */ mtspr 0x111, r26 -/* 801D8FAC 001D4C0C 7F 72 43 A6 */ mtspr 0x112, r27 -/* 801D8FB0 001D4C10 7F 93 43 A6 */ mtspr 0x113, r28 -/* 801D8FB4 001D4C14 7F D2 FB A6 */ mtspr 0x3f2, r30 -/* 801D8FB8 001D4C18 7F FA 43 A6 */ mtspr 0x11a, r31 -/* 801D8FBC 001D4C1C 4E 80 00 20 */ blr - -.global func_801D8FC0 -func_801D8FC0: -/* 801D8FC0 001D4C20 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D8FC4 001D4C24 7C 08 02 A6 */ mflr r0 -/* 801D8FC8 001D4C28 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D8FCC 001D4C2C 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D8FD0 001D4C30 7C BF 2B 78 */ mr r31, r5 -/* 801D8FD4 001D4C34 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D8FD8 001D4C38 7C 9E 23 78 */ mr r30, r4 -/* 801D8FDC 001D4C3C 48 00 09 B1 */ bl func_801D998C -/* 801D8FE0 001D4C40 54 60 06 3F */ clrlwi. r0, r3, 0x18 -/* 801D8FE4 001D4C44 40 82 00 0C */ bne lbl_801D8FF0 -/* 801D8FE8 001D4C48 38 60 00 01 */ li r3, 1 -/* 801D8FEC 001D4C4C 48 00 00 78 */ b lbl_801D9064 -lbl_801D8FF0: -/* 801D8FF0 001D4C50 4B FF D9 A1 */ bl GetTRKConnected -/* 801D8FF4 001D4C54 2C 03 00 00 */ cmpwi r3, 0 -/* 801D8FF8 001D4C58 40 82 00 0C */ bne lbl_801D9004 -/* 801D8FFC 001D4C5C 38 60 00 01 */ li r3, 1 -/* 801D9000 001D4C60 48 00 00 64 */ b lbl_801D9064 -lbl_801D9004: -/* 801D9004 001D4C64 80 1F 00 00 */ lwz r0, 0(r31) -/* 801D9008 001D4C68 7F C6 F3 78 */ mr r6, r30 -/* 801D900C 001D4C6C 38 A1 00 08 */ addi r5, r1, 8 -/* 801D9010 001D4C70 38 60 00 D0 */ li r3, 0xd0 -/* 801D9014 001D4C74 90 01 00 08 */ stw r0, 8(r1) -/* 801D9018 001D4C78 38 80 00 01 */ li r4, 1 -/* 801D901C 001D4C7C 4B FF FC 15 */ bl func_801D8C30 -/* 801D9020 001D4C80 54 60 06 3E */ clrlwi r0, r3, 0x18 -/* 801D9024 001D4C84 80 61 00 08 */ lwz r3, 8(r1) -/* 801D9028 001D4C88 2C 00 00 01 */ cmpwi r0, 1 -/* 801D902C 001D4C8C 90 7F 00 00 */ stw r3, 0(r31) -/* 801D9030 001D4C90 41 82 00 30 */ beq lbl_801D9060 -/* 801D9034 001D4C94 40 80 00 10 */ bge lbl_801D9044 -/* 801D9038 001D4C98 2C 00 00 00 */ cmpwi r0, 0 -/* 801D903C 001D4C9C 40 80 00 14 */ bge lbl_801D9050 -/* 801D9040 001D4CA0 48 00 00 20 */ b lbl_801D9060 -lbl_801D9044: -/* 801D9044 001D4CA4 2C 00 00 03 */ cmpwi r0, 3 -/* 801D9048 001D4CA8 40 80 00 18 */ bge lbl_801D9060 -/* 801D904C 001D4CAC 48 00 00 0C */ b lbl_801D9058 -lbl_801D9050: -/* 801D9050 001D4CB0 38 60 00 00 */ li r3, 0 -/* 801D9054 001D4CB4 48 00 00 10 */ b lbl_801D9064 -lbl_801D9058: -/* 801D9058 001D4CB8 38 60 00 02 */ li r3, 2 -/* 801D905C 001D4CBC 48 00 00 08 */ b lbl_801D9064 -lbl_801D9060: -/* 801D9060 001D4CC0 38 60 00 01 */ li r3, 1 -lbl_801D9064: -/* 801D9064 001D4CC4 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D9068 001D4CC8 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D906C 001D4CCC 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D9070 001D4CD0 7C 08 03 A6 */ mtlr r0 -/* 801D9074 001D4CD4 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D9078 001D4CD8 4E 80 00 20 */ blr - -.global __TRK_write_console -__TRK_write_console: -/* 801D907C 001D4CDC 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D9080 001D4CE0 7C 08 02 A6 */ mflr r0 -/* 801D9084 001D4CE4 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D9088 001D4CE8 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D908C 001D4CEC 7C BF 2B 78 */ mr r31, r5 -/* 801D9090 001D4CF0 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D9094 001D4CF4 7C 9E 23 78 */ mr r30, r4 -/* 801D9098 001D4CF8 48 00 08 F5 */ bl func_801D998C -/* 801D909C 001D4CFC 54 60 06 3F */ clrlwi. r0, r3, 0x18 -/* 801D90A0 001D4D00 40 82 00 0C */ bne lbl_801D90AC -/* 801D90A4 001D4D04 38 60 00 01 */ li r3, 1 -/* 801D90A8 001D4D08 48 00 00 78 */ b lbl_801D9120 -lbl_801D90AC: -/* 801D90AC 001D4D0C 4B FF D8 E5 */ bl GetTRKConnected -/* 801D90B0 001D4D10 2C 03 00 00 */ cmpwi r3, 0 -/* 801D90B4 001D4D14 40 82 00 0C */ bne lbl_801D90C0 -/* 801D90B8 001D4D18 38 60 00 01 */ li r3, 1 -/* 801D90BC 001D4D1C 48 00 00 64 */ b lbl_801D9120 -lbl_801D90C0: -/* 801D90C0 001D4D20 80 1F 00 00 */ lwz r0, 0(r31) -/* 801D90C4 001D4D24 7F C6 F3 78 */ mr r6, r30 -/* 801D90C8 001D4D28 38 A1 00 08 */ addi r5, r1, 8 -/* 801D90CC 001D4D2C 38 60 00 D1 */ li r3, 0xd1 -/* 801D90D0 001D4D30 90 01 00 08 */ stw r0, 8(r1) -/* 801D90D4 001D4D34 38 80 00 00 */ li r4, 0 -/* 801D90D8 001D4D38 4B FF FB 59 */ bl func_801D8C30 -/* 801D90DC 001D4D3C 54 60 06 3E */ clrlwi r0, r3, 0x18 -/* 801D90E0 001D4D40 80 61 00 08 */ lwz r3, 8(r1) -/* 801D90E4 001D4D44 2C 00 00 01 */ cmpwi r0, 1 -/* 801D90E8 001D4D48 90 7F 00 00 */ stw r3, 0(r31) -/* 801D90EC 001D4D4C 41 82 00 30 */ beq lbl_801D911C -/* 801D90F0 001D4D50 40 80 00 10 */ bge lbl_801D9100 -/* 801D90F4 001D4D54 2C 00 00 00 */ cmpwi r0, 0 -/* 801D90F8 001D4D58 40 80 00 14 */ bge lbl_801D910C -/* 801D90FC 001D4D5C 48 00 00 20 */ b lbl_801D911C -lbl_801D9100: -/* 801D9100 001D4D60 2C 00 00 03 */ cmpwi r0, 3 -/* 801D9104 001D4D64 40 80 00 18 */ bge lbl_801D911C -/* 801D9108 001D4D68 48 00 00 0C */ b lbl_801D9114 -lbl_801D910C: -/* 801D910C 001D4D6C 38 60 00 00 */ li r3, 0 -/* 801D9110 001D4D70 48 00 00 10 */ b lbl_801D9120 -lbl_801D9114: -/* 801D9114 001D4D74 38 60 00 02 */ li r3, 2 -/* 801D9118 001D4D78 48 00 00 08 */ b lbl_801D9120 -lbl_801D911C: -/* 801D911C 001D4D7C 38 60 00 01 */ li r3, 1 -lbl_801D9120: -/* 801D9120 001D4D80 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D9124 001D4D84 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D9128 001D4D88 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D912C 001D4D8C 7C 08 03 A6 */ mtlr r0 -/* 801D9130 001D4D90 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D9134 001D4D94 4E 80 00 20 */ blr - -.global InitMetroTRK -InitMetroTRK: -/* 801D9138 001D4D98 38 21 FF FC */ addi r1, r1, -4 -/* 801D913C 001D4D9C 90 61 00 00 */ stw r3, 0(r1) -/* 801D9140 001D4DA0 3C 60 80 49 */ lis r3, lbl_80490898@h -/* 801D9144 001D4DA4 60 63 08 98 */ ori r3, r3, lbl_80490898@l -/* 801D9148 001D4DA8 BC 03 00 00 */ stmw r0, 0(r3) -/* 801D914C 001D4DAC 80 81 00 00 */ lwz r4, 0(r1) -/* 801D9150 001D4DB0 38 21 00 04 */ addi r1, r1, 4 -/* 801D9154 001D4DB4 90 23 00 04 */ stw r1, 4(r3) -/* 801D9158 001D4DB8 90 83 00 0C */ stw r4, 0xc(r3) -/* 801D915C 001D4DBC 7C 88 02 A6 */ mflr r4 -/* 801D9160 001D4DC0 90 83 00 84 */ stw r4, 0x84(r3) -/* 801D9164 001D4DC4 90 83 00 80 */ stw r4, 0x80(r3) -/* 801D9168 001D4DC8 7C 80 00 26 */ mfcr r4 -/* 801D916C 001D4DCC 90 83 00 88 */ stw r4, 0x88(r3) -/* 801D9170 001D4DD0 7C 80 00 A6 */ mfmsr r4 -/* 801D9174 001D4DD4 60 83 80 00 */ ori r3, r4, 0x8000 -/* 801D9178 001D4DD8 68 63 80 00 */ xori r3, r3, 0x8000 -/* 801D917C 001D4DDC 7C 60 01 24 */ mtmsr r3 -/* 801D9180 001D4DE0 7C 9B 03 A6 */ mtspr 0x1b, r4 -/* 801D9184 001D4DE4 4B FF FA CD */ bl TRKSaveExtended1Block -/* 801D9188 001D4DE8 3C 60 80 49 */ lis r3, lbl_80490898@h -/* 801D918C 001D4DEC 60 63 08 98 */ ori r3, r3, lbl_80490898@l -/* 801D9190 001D4DF0 B8 03 00 00 */ .4byte 0xB8030000 /* illegal lmw r0, 0(r3) */ -/* 801D9194 001D4DF4 38 00 00 00 */ li r0, 0 -/* 801D9198 001D4DF8 7C 12 FB A6 */ mtspr 0x3f2, r0 -/* 801D919C 001D4DFC 7C 15 FB A6 */ mtspr 0x3f5, r0 -/* 801D91A0 001D4E00 3C 20 80 65 */ lis r1, 0x80655050@h -/* 801D91A4 001D4E04 60 21 50 50 */ ori r1, r1, 0x80655050@l -/* 801D91A8 001D4E08 7C A3 2B 78 */ mr r3, r5 -/* 801D91AC 001D4E0C 48 00 05 A1 */ bl func_801D974C -/* 801D91B0 001D4E10 2C 03 00 01 */ cmpwi r3, 1 -/* 801D91B4 001D4E14 40 82 00 14 */ bne lbl_801D91C8 -/* 801D91B8 001D4E18 80 83 00 84 */ lwz r4, 0x84(r3) -/* 801D91BC 001D4E1C 7C 88 03 A6 */ mtlr r4 -/* 801D91C0 001D4E20 B8 03 00 00 */ .4byte 0xB8030000 /* illegal lmw r0, 0(r3) */ -/* 801D91C4 001D4E24 4E 80 00 20 */ blr -lbl_801D91C8: -/* 801D91C8 001D4E28 48 00 02 8C */ b lbl_801D9454 -/* 801D91CC 001D4E2C 4E 80 00 20 */ blr - -.global InitMetroTRK_BBA -InitMetroTRK_BBA: -/* 801D91D0 001D4E30 38 21 FF FC */ addi r1, r1, -4 -/* 801D91D4 001D4E34 90 61 00 00 */ stw r3, 0(r1) -/* 801D91D8 001D4E38 3C 60 80 49 */ lis r3, lbl_80490898@h -/* 801D91DC 001D4E3C 60 63 08 98 */ ori r3, r3, lbl_80490898@l -/* 801D91E0 001D4E40 BC 03 00 00 */ stmw r0, 0(r3) -/* 801D91E4 001D4E44 80 81 00 00 */ lwz r4, 0(r1) -/* 801D91E8 001D4E48 38 21 00 04 */ addi r1, r1, 4 -/* 801D91EC 001D4E4C 90 23 00 04 */ stw r1, 4(r3) -/* 801D91F0 001D4E50 90 83 00 0C */ stw r4, 0xc(r3) -/* 801D91F4 001D4E54 7C 88 02 A6 */ mflr r4 -/* 801D91F8 001D4E58 90 83 00 84 */ stw r4, 0x84(r3) -/* 801D91FC 001D4E5C 90 83 00 80 */ stw r4, 0x80(r3) -/* 801D9200 001D4E60 7C 80 00 26 */ mfcr r4 -/* 801D9204 001D4E64 90 83 00 88 */ stw r4, 0x88(r3) -/* 801D9208 001D4E68 7C 80 00 A6 */ mfmsr r4 -/* 801D920C 001D4E6C 60 83 80 00 */ ori r3, r4, 0x8000 -/* 801D9210 001D4E70 7C 60 01 24 */ mtmsr r3 -/* 801D9214 001D4E74 7C 9B 03 A6 */ mtspr 0x1b, r4 -/* 801D9218 001D4E78 4B FF FA 39 */ bl TRKSaveExtended1Block -/* 801D921C 001D4E7C 3C 60 80 49 */ lis r3, lbl_80490898@h -/* 801D9220 001D4E80 60 63 08 98 */ ori r3, r3, lbl_80490898@l -/* 801D9224 001D4E84 B8 03 00 00 */ .4byte 0xB8030000 /* illegal lmw r0, 0(r3) */ -/* 801D9228 001D4E88 38 00 00 00 */ li r0, 0 -/* 801D922C 001D4E8C 7C 12 FB A6 */ mtspr 0x3f2, r0 -/* 801D9230 001D4E90 7C 15 FB A6 */ mtspr 0x3f5, r0 -/* 801D9234 001D4E94 3C 20 80 65 */ lis r1, 0x80655050@h -/* 801D9238 001D4E98 60 21 50 50 */ ori r1, r1, 0x80655050@l -/* 801D923C 001D4E9C 38 60 00 02 */ li r3, 2 -/* 801D9240 001D4EA0 48 00 05 0D */ bl func_801D974C -/* 801D9244 001D4EA4 2C 03 00 01 */ cmpwi r3, 1 -/* 801D9248 001D4EA8 40 82 00 14 */ bne lbl_801D925C -/* 801D924C 001D4EAC 80 83 00 84 */ lwz r4, 0x84(r3) -/* 801D9250 001D4EB0 7C 88 03 A6 */ mtlr r4 -/* 801D9254 001D4EB4 B8 03 00 00 */ .4byte 0xB8030000 /* illegal lmw r0, 0(r3) */ -/* 801D9258 001D4EB8 4E 80 00 20 */ blr -lbl_801D925C: -/* 801D925C 001D4EBC 48 00 01 F8 */ b lbl_801D9454 -/* 801D9260 001D4EC0 4E 80 00 20 */ blr - -.global TRKInitializeTarget -TRKInitializeTarget: -/* 801D9264 001D4EC4 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9268 001D4EC8 7C 08 02 A6 */ mflr r0 -/* 801D926C 001D4ECC 3C 60 80 49 */ lis r3, lbl_804907F4@ha -/* 801D9270 001D4ED0 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9274 001D4ED4 38 00 00 01 */ li r0, 1 -/* 801D9278 001D4ED8 38 63 07 F4 */ addi r3, r3, lbl_804907F4@l -/* 801D927C 001D4EDC 90 03 00 98 */ stw r0, 0x98(r3) -/* 801D9280 001D4EE0 4B FF DF 91 */ bl __TRK_get_MSR -/* 801D9284 001D4EE4 3C A0 80 49 */ lis r5, lbl_804907F4@ha -/* 801D9288 001D4EE8 3C 80 80 49 */ lis r4, lbl_80490D70@ha -/* 801D928C 001D4EEC 38 A5 07 F4 */ addi r5, r5, lbl_804907F4@l -/* 801D9290 001D4EF0 3C 00 E0 00 */ lis r0, 0xe000 -/* 801D9294 001D4EF4 90 65 00 8C */ stw r3, 0x8c(r5) -/* 801D9298 001D4EF8 38 60 00 00 */ li r3, 0 -/* 801D929C 001D4EFC 90 04 0D 70 */ stw r0, lbl_80490D70@l(r4) -/* 801D92A0 001D4F00 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D92A4 001D4F04 7C 08 03 A6 */ mtlr r0 -/* 801D92A8 001D4F08 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D92AC 001D4F0C 4E 80 00 20 */ blr - -.global __TRK_copy_vectors -__TRK_copy_vectors: -/* 801D92B0 001D4F10 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D92B4 001D4F14 7C 08 02 A6 */ mflr r0 -/* 801D92B8 001D4F18 3C 60 80 49 */ lis r3, lbl_80490D70@ha -/* 801D92BC 001D4F1C 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D92C0 001D4F20 38 63 0D 70 */ addi r3, r3, lbl_80490D70@l -/* 801D92C4 001D4F24 BF 61 00 0C */ stmw r27, 0xc(r1) -/* 801D92C8 001D4F28 80 63 00 00 */ lwz r3, 0(r3) -/* 801D92CC 001D4F2C 28 03 00 44 */ cmplwi r3, 0x44 -/* 801D92D0 001D4F30 41 81 00 2C */ bgt lbl_801D92FC -/* 801D92D4 001D4F34 38 03 40 00 */ addi r0, r3, 0x4000 -/* 801D92D8 001D4F38 28 00 00 44 */ cmplwi r0, 0x44 -/* 801D92DC 001D4F3C 40 81 00 20 */ ble lbl_801D92FC -/* 801D92E0 001D4F40 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D92E4 001D4F44 38 63 08 98 */ addi r3, r3, lbl_80490898@l -/* 801D92E8 001D4F48 80 03 02 38 */ lwz r0, 0x238(r3) -/* 801D92EC 001D4F4C 54 00 07 BF */ clrlwi. r0, r0, 0x1e -/* 801D92F0 001D4F50 41 82 00 0C */ beq lbl_801D92FC -/* 801D92F4 001D4F54 38 A0 00 44 */ li r5, 0x44 -/* 801D92F8 001D4F58 48 00 00 0C */ b lbl_801D9304 -lbl_801D92FC: -/* 801D92FC 001D4F5C 3C 60 80 00 */ lis r3, 0x80000044@ha -/* 801D9300 001D4F60 38 A3 00 44 */ addi r5, r3, 0x80000044@l -lbl_801D9304: -/* 801D9304 001D4F64 3C 80 80 42 */ lis r4, lbl_80423260@ha -/* 801D9308 001D4F68 3C 60 80 49 */ lis r3, lbl_80490898@ha -/* 801D930C 001D4F6C 83 A5 00 00 */ lwz r29, 0(r5) -/* 801D9310 001D4F70 3B E4 32 60 */ addi r31, r4, lbl_80423260@l -/* 801D9314 001D4F74 3B 83 08 98 */ addi r28, r3, lbl_80490898@l -/* 801D9318 001D4F78 3B C0 00 00 */ li r30, 0 -lbl_801D931C: -/* 801D931C 001D4F7C 38 00 00 01 */ li r0, 1 -/* 801D9320 001D4F80 7C 00 F0 30 */ slw r0, r0, r30 -/* 801D9324 001D4F84 7F A0 00 39 */ and. r0, r29, r0 -/* 801D9328 001D4F88 41 82 00 90 */ beq lbl_801D93B8 -/* 801D932C 001D4F8C 2C 1E 00 04 */ cmpwi r30, 4 -/* 801D9330 001D4F90 41 82 00 88 */ beq lbl_801D93B8 -/* 801D9334 001D4F94 3C 60 80 49 */ lis r3, lbl_80490D70@ha -/* 801D9338 001D4F98 80 DF 00 00 */ lwz r6, 0(r31) -/* 801D933C 001D4F9C 38 63 0D 70 */ addi r3, r3, lbl_80490D70@l -/* 801D9340 001D4FA0 80 63 00 00 */ lwz r3, 0(r3) -/* 801D9344 001D4FA4 7C 06 18 40 */ cmplw r6, r3 -/* 801D9348 001D4FA8 41 80 00 24 */ blt lbl_801D936C -/* 801D934C 001D4FAC 38 03 40 00 */ addi r0, r3, 0x4000 -/* 801D9350 001D4FB0 7C 06 00 40 */ cmplw r6, r0 -/* 801D9354 001D4FB4 40 80 00 18 */ bge lbl_801D936C -/* 801D9358 001D4FB8 80 1C 02 38 */ lwz r0, 0x238(r28) -/* 801D935C 001D4FBC 54 00 07 BF */ clrlwi. r0, r0, 0x1e -/* 801D9360 001D4FC0 41 82 00 0C */ beq lbl_801D936C -/* 801D9364 001D4FC4 7C DB 33 78 */ mr r27, r6 -/* 801D9368 001D4FC8 48 00 00 2C */ b lbl_801D9394 -lbl_801D936C: -/* 801D936C 001D4FCC 3C 00 7E 00 */ lis r0, 0x7e00 -/* 801D9370 001D4FD0 7C 06 00 40 */ cmplw r6, r0 -/* 801D9374 001D4FD4 41 80 00 18 */ blt lbl_801D938C -/* 801D9378 001D4FD8 3C 00 80 00 */ lis r0, 0x8000 -/* 801D937C 001D4FDC 7C 06 00 40 */ cmplw r6, r0 -/* 801D9380 001D4FE0 41 81 00 0C */ bgt lbl_801D938C -/* 801D9384 001D4FE4 7C DB 33 78 */ mr r27, r6 -/* 801D9388 001D4FE8 48 00 00 0C */ b lbl_801D9394 -lbl_801D938C: -/* 801D938C 001D4FEC 54 C0 00 BE */ clrlwi r0, r6, 2 -/* 801D9390 001D4FF0 64 1B 80 00 */ oris r27, r0, 0x8000 -lbl_801D9394: -/* 801D9394 001D4FF4 3C 80 80 00 */ lis r4, lbl_80004188@ha -/* 801D9398 001D4FF8 7F 63 DB 78 */ mr r3, r27 -/* 801D939C 001D4FFC 38 04 41 88 */ addi r0, r4, lbl_80004188@l -/* 801D93A0 001D5000 38 A0 01 00 */ li r5, 0x100 -/* 801D93A4 001D5004 7C 80 32 14 */ add r4, r0, r6 -/* 801D93A8 001D5008 4B E2 AD BD */ bl TRK_memcpy -/* 801D93AC 001D500C 7F 63 DB 78 */ mr r3, r27 -/* 801D93B0 001D5010 38 80 01 00 */ li r4, 0x100 -/* 801D93B4 001D5014 4B FF DD 51 */ bl TRK_flush_cache -lbl_801D93B8: -/* 801D93B8 001D5018 3B DE 00 01 */ addi r30, r30, 1 -/* 801D93BC 001D501C 3B FF 00 04 */ addi r31, r31, 4 -/* 801D93C0 001D5020 2C 1E 00 0E */ cmpwi r30, 0xe -/* 801D93C4 001D5024 40 81 FF 58 */ ble lbl_801D931C -/* 801D93C8 001D5028 BB 61 00 0C */ lmw r27, 0xc(r1) -/* 801D93CC 001D502C 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D93D0 001D5030 7C 08 03 A6 */ mtlr r0 -/* 801D93D4 001D5034 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D93D8 001D5038 4E 80 00 20 */ blr - -.global TRKTargetTranslate -TRKTargetTranslate: -/* 801D93DC 001D503C 3C 80 80 49 */ lis r4, lbl_80490D70@ha -/* 801D93E0 001D5040 38 84 0D 70 */ addi r4, r4, lbl_80490D70@l -/* 801D93E4 001D5044 80 84 00 00 */ lwz r4, 0(r4) -/* 801D93E8 001D5048 7C 03 20 40 */ cmplw r3, r4 -/* 801D93EC 001D504C 41 80 00 24 */ blt lbl_801D9410 -/* 801D93F0 001D5050 38 04 40 00 */ addi r0, r4, 0x4000 -/* 801D93F4 001D5054 7C 03 00 40 */ cmplw r3, r0 -/* 801D93F8 001D5058 40 80 00 18 */ bge lbl_801D9410 -/* 801D93FC 001D505C 3C 80 80 49 */ lis r4, lbl_80490898@ha -/* 801D9400 001D5060 38 84 08 98 */ addi r4, r4, lbl_80490898@l -/* 801D9404 001D5064 80 04 02 38 */ lwz r0, 0x238(r4) -/* 801D9408 001D5068 54 00 07 BF */ clrlwi. r0, r0, 0x1e -/* 801D940C 001D506C 4C 82 00 20 */ bnelr -lbl_801D9410: -/* 801D9410 001D5070 3C 00 7E 00 */ lis r0, 0x7e00 -/* 801D9414 001D5074 7C 03 00 40 */ cmplw r3, r0 -/* 801D9418 001D5078 41 80 00 10 */ blt lbl_801D9428 -/* 801D941C 001D507C 3C 00 80 00 */ lis r0, 0x8000 -/* 801D9420 001D5080 7C 03 00 40 */ cmplw r3, r0 -/* 801D9424 001D5084 4C 81 00 20 */ blelr -lbl_801D9428: -/* 801D9428 001D5088 54 60 00 BE */ clrlwi r0, r3, 2 -/* 801D942C 001D508C 64 03 80 00 */ oris r3, r0, 0x8000 -/* 801D9430 001D5090 4E 80 00 20 */ blr - -.global func_801D9434 -func_801D9434: -/* 801D9434 001D5094 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9438 001D5098 7C 08 02 A6 */ mflr r0 -/* 801D943C 001D509C 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9440 001D50A0 48 00 02 75 */ bl EnableEXI2Interrupts -/* 801D9444 001D50A4 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9448 001D50A8 7C 08 03 A6 */ mtlr r0 -/* 801D944C 001D50AC 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9450 001D50B0 4E 80 00 20 */ blr -lbl_801D9454: -/* 801D9454 001D50B4 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9458 001D50B8 7C 08 02 A6 */ mflr r0 -/* 801D945C 001D50BC 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9460 001D50C0 4B FF B7 45 */ bl TRKInitializeNub -/* 801D9464 001D50C4 3C 80 80 49 */ lis r4, lbl_80490D78@ha -/* 801D9468 001D50C8 2C 03 00 00 */ cmpwi r3, 0 -/* 801D946C 001D50CC 90 64 0D 78 */ stw r3, lbl_80490D78@l(r4) -/* 801D9470 001D50D0 40 82 00 0C */ bne lbl_801D947C -/* 801D9474 001D50D4 4B FF B6 E5 */ bl TRKNubWelcome -/* 801D9478 001D50D8 4B FF B3 C1 */ bl TRKNubMainLoop -lbl_801D947C: -/* 801D947C 001D50DC 4B FF B7 05 */ bl TRKTerminateNub -/* 801D9480 001D50E0 3C 80 80 49 */ lis r4, lbl_80490D78@ha -/* 801D9484 001D50E4 90 64 0D 78 */ stw r3, lbl_80490D78@l(r4) -/* 801D9488 001D50E8 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D948C 001D50EC 7C 08 03 A6 */ mtlr r0 -/* 801D9490 001D50F0 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9494 001D50F4 4E 80 00 20 */ blr - -.global TRKLoadContext -TRKLoadContext: -/* 801D9498 001D50F8 80 03 00 00 */ lwz r0, 0(r3) -/* 801D949C 001D50FC 80 23 00 04 */ lwz r1, 4(r3) -/* 801D94A0 001D5100 80 43 00 08 */ lwz r2, 8(r3) -/* 801D94A4 001D5104 A0 A3 01 A2 */ lhz r5, 0x1a2(r3) -/* 801D94A8 001D5108 54 A6 07 BD */ rlwinm. r6, r5, 0, 0x1e, 0x1e -/* 801D94AC 001D510C 41 82 00 14 */ beq lbl_801D94C0 -/* 801D94B0 001D5110 54 A5 07 FA */ rlwinm r5, r5, 0, 0x1f, 0x1d -/* 801D94B4 001D5114 B0 A3 01 A2 */ sth r5, 0x1a2(r3) -/* 801D94B8 001D5118 B8 A3 00 14 */ lmw r5, 0x14(r3) -/* 801D94BC 001D511C 48 00 00 08 */ b lbl_801D94C4 -lbl_801D94C0: -/* 801D94C0 001D5120 B9 A3 00 34 */ lmw r13, 0x34(r3) -lbl_801D94C4: -/* 801D94C4 001D5124 7C 7F 1B 78 */ mr r31, r3 -/* 801D94C8 001D5128 7C 83 23 78 */ mr r3, r4 -/* 801D94CC 001D512C 80 9F 00 80 */ lwz r4, 0x80(r31) -/* 801D94D0 001D5130 7C 8F F1 20 */ mtcrf 0xff, r4 -/* 801D94D4 001D5134 80 9F 00 84 */ lwz r4, 0x84(r31) -/* 801D94D8 001D5138 7C 88 03 A6 */ mtlr r4 -/* 801D94DC 001D513C 80 9F 00 88 */ lwz r4, 0x88(r31) -/* 801D94E0 001D5140 7C 89 03 A6 */ mtctr r4 -/* 801D94E4 001D5144 80 9F 00 8C */ lwz r4, 0x8c(r31) -/* 801D94E8 001D5148 7C 81 03 A6 */ mtxer r4 -/* 801D94EC 001D514C 7C 80 00 A6 */ mfmsr r4 -/* 801D94F0 001D5150 54 84 04 5E */ rlwinm r4, r4, 0, 0x11, 0xf -/* 801D94F4 001D5154 54 84 07 FA */ rlwinm r4, r4, 0, 0x1f, 0x1d -/* 801D94F8 001D5158 7C 80 01 24 */ mtmsr r4 -/* 801D94FC 001D515C 7C 51 43 A6 */ mtspr 0x111, r2 -/* 801D9500 001D5160 80 9F 00 0C */ lwz r4, 0xc(r31) -/* 801D9504 001D5164 7C 92 43 A6 */ mtspr 0x112, r4 -/* 801D9508 001D5168 80 9F 00 10 */ lwz r4, 0x10(r31) -/* 801D950C 001D516C 7C 93 43 A6 */ mtspr 0x113, r4 -/* 801D9510 001D5170 80 5F 01 98 */ lwz r2, 0x198(r31) -/* 801D9514 001D5174 80 9F 01 9C */ lwz r4, 0x19c(r31) -/* 801D9518 001D5178 83 FF 00 7C */ lwz r31, 0x7c(r31) -/* 801D951C 001D517C 4B FF DD 40 */ b TRKInterruptHandler - -.global func_801D9520 -func_801D9520: -/* 801D9520 001D5180 4E 80 00 20 */ blr - -.global InitializeProgramEndTrap -InitializeProgramEndTrap: -/* 801D9524 001D5184 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9528 001D5188 7C 08 02 A6 */ mflr r0 -/* 801D952C 001D518C 3C 80 80 27 */ lis r4, PPCHalt@ha -/* 801D9530 001D5190 3C 60 80 40 */ lis r3, lbl_803FD740@ha -/* 801D9534 001D5194 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9538 001D5198 38 A0 00 04 */ li r5, 4 -/* 801D953C 001D519C 93 E1 00 0C */ stw r31, 0xc(r1) -/* 801D9540 001D51A0 3B E4 82 68 */ addi r31, r4, PPCHalt@l -/* 801D9544 001D51A4 38 83 D7 40 */ addi r4, r3, lbl_803FD740@l -/* 801D9548 001D51A8 38 7F 00 04 */ addi r3, r31, 4 -/* 801D954C 001D51AC 4B E2 AC 19 */ bl TRK_memcpy -/* 801D9550 001D51B0 38 7F 00 04 */ addi r3, r31, 4 -/* 801D9554 001D51B4 38 80 00 04 */ li r4, 4 -/* 801D9558 001D51B8 48 09 11 E1 */ bl ICInvalidateRange -/* 801D955C 001D51BC 38 7F 00 04 */ addi r3, r31, 4 -/* 801D9560 001D51C0 38 80 00 04 */ li r4, 4 -/* 801D9564 001D51C4 48 09 10 F1 */ bl DCFlushRange -/* 801D9568 001D51C8 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D956C 001D51CC 83 E1 00 0C */ lwz r31, 0xc(r1) -/* 801D9570 001D51D0 7C 08 03 A6 */ mtlr r0 -/* 801D9574 001D51D4 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9578 001D51D8 4E 80 00 20 */ blr - -.global TRK_board_display -TRK_board_display: -/* 801D957C 001D51DC 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9580 001D51E0 7C 08 02 A6 */ mflr r0 -/* 801D9584 001D51E4 3C A0 80 40 */ lis r5, lbl_803FD744@ha -/* 801D9588 001D51E8 7C 64 1B 78 */ mr r4, r3 -/* 801D958C 001D51EC 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9590 001D51F0 38 65 D7 44 */ addi r3, r5, lbl_803FD744@l -/* 801D9594 001D51F4 4C C6 31 82 */ crclr 6 -/* 801D9598 001D51F8 4B E2 E5 2D */ bl func_80007AC4 -/* 801D959C 001D51FC 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D95A0 001D5200 7C 08 03 A6 */ mtlr r0 -/* 801D95A4 001D5204 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D95A8 001D5208 4E 80 00 20 */ blr - -.global func_801D95AC -func_801D95AC: -/* 801D95AC 001D520C 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D95B0 001D5210 7C 08 02 A6 */ mflr r0 -/* 801D95B4 001D5214 3C 60 80 42 */ lis r3, lbl_804232A0@ha -/* 801D95B8 001D5218 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D95BC 001D521C 38 63 32 A0 */ addi r3, r3, lbl_804232A0@l -/* 801D95C0 001D5220 81 83 00 20 */ lwz r12, 0x20(r3) -/* 801D95C4 001D5224 7D 89 03 A6 */ mtctr r12 -/* 801D95C8 001D5228 4E 80 04 21 */ bctrl -/* 801D95CC 001D522C 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D95D0 001D5230 7C 08 03 A6 */ mtlr r0 -/* 801D95D4 001D5234 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D95D8 001D5238 4E 80 00 20 */ blr - -.global UnreserveEXI2Port -UnreserveEXI2Port: -/* 801D95DC 001D523C 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D95E0 001D5240 7C 08 02 A6 */ mflr r0 -/* 801D95E4 001D5244 3C 60 80 42 */ lis r3, lbl_804232A0@ha -/* 801D95E8 001D5248 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D95EC 001D524C 38 63 32 A0 */ addi r3, r3, lbl_804232A0@l -/* 801D95F0 001D5250 81 83 00 24 */ lwz r12, 0x24(r3) -/* 801D95F4 001D5254 7D 89 03 A6 */ mtctr r12 -/* 801D95F8 001D5258 4E 80 04 21 */ bctrl -/* 801D95FC 001D525C 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9600 001D5260 7C 08 03 A6 */ mtlr r0 -/* 801D9604 001D5264 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9608 001D5268 4E 80 00 20 */ blr - -.global func_801D960C -func_801D960C: -/* 801D960C 001D526C 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9610 001D5270 7C 08 02 A6 */ mflr r0 -/* 801D9614 001D5274 3C A0 80 42 */ lis r5, lbl_804232A0@ha -/* 801D9618 001D5278 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D961C 001D527C 38 A5 32 A0 */ addi r5, r5, lbl_804232A0@l -/* 801D9620 001D5280 81 85 00 14 */ lwz r12, 0x14(r5) -/* 801D9624 001D5284 7D 89 03 A6 */ mtctr r12 -/* 801D9628 001D5288 4E 80 04 21 */ bctrl -/* 801D962C 001D528C 7C 03 00 D0 */ neg r0, r3 -/* 801D9630 001D5290 7C 00 1B 78 */ or r0, r0, r3 -/* 801D9634 001D5294 7C 03 FE 70 */ srawi r3, r0, 0x1f -/* 801D9638 001D5298 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D963C 001D529C 7C 08 03 A6 */ mtlr r0 -/* 801D9640 001D52A0 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9644 001D52A4 4E 80 00 20 */ blr - -.global TRKWriteUARTN -TRKWriteUARTN: -/* 801D9648 001D52A8 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D964C 001D52AC 7C 08 02 A6 */ mflr r0 -/* 801D9650 001D52B0 3C A0 80 42 */ lis r5, lbl_804232A0@ha -/* 801D9654 001D52B4 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9658 001D52B8 38 A5 32 A0 */ addi r5, r5, lbl_804232A0@l -/* 801D965C 001D52BC 81 85 00 10 */ lwz r12, 0x10(r5) -/* 801D9660 001D52C0 7D 89 03 A6 */ mtctr r12 -/* 801D9664 001D52C4 4E 80 04 21 */ bctrl -/* 801D9668 001D52C8 7C 03 00 D0 */ neg r0, r3 -/* 801D966C 001D52CC 7C 00 1B 78 */ or r0, r0, r3 -/* 801D9670 001D52D0 7C 03 FE 70 */ srawi r3, r0, 0x1f -/* 801D9674 001D52D4 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9678 001D52D8 7C 08 03 A6 */ mtlr r0 -/* 801D967C 001D52DC 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9680 001D52E0 4E 80 00 20 */ blr - -.global func_801D9684 -func_801D9684: -/* 801D9684 001D52E4 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9688 001D52E8 7C 08 02 A6 */ mflr r0 -/* 801D968C 001D52EC 3C 60 80 42 */ lis r3, lbl_804232A0@ha -/* 801D9690 001D52F0 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9694 001D52F4 38 63 32 A0 */ addi r3, r3, lbl_804232A0@l -/* 801D9698 001D52F8 81 83 00 0C */ lwz r12, 0xc(r3) -/* 801D969C 001D52FC 7D 89 03 A6 */ mtctr r12 -/* 801D96A0 001D5300 4E 80 04 21 */ bctrl -/* 801D96A4 001D5304 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D96A8 001D5308 7C 08 03 A6 */ mtlr r0 -/* 801D96AC 001D530C 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D96B0 001D5310 4E 80 00 20 */ blr - -.global EnableEXI2Interrupts -EnableEXI2Interrupts: -/* 801D96B4 001D5314 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D96B8 001D5318 7C 08 02 A6 */ mflr r0 -/* 801D96BC 001D531C 3C 60 80 49 */ lis r3, lbl_80490D80@ha -/* 801D96C0 001D5320 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D96C4 001D5324 88 03 0D 80 */ lbz r0, lbl_80490D80@l(r3) -/* 801D96C8 001D5328 28 00 00 00 */ cmplwi r0, 0 -/* 801D96CC 001D532C 40 82 00 20 */ bne lbl_801D96EC -/* 801D96D0 001D5330 3C 60 80 42 */ lis r3, lbl_804232A0@ha -/* 801D96D4 001D5334 38 63 32 A0 */ addi r3, r3, lbl_804232A0@l -/* 801D96D8 001D5338 81 83 00 04 */ lwz r12, 4(r3) -/* 801D96DC 001D533C 28 0C 00 00 */ cmplwi r12, 0 -/* 801D96E0 001D5340 41 82 00 0C */ beq lbl_801D96EC -/* 801D96E4 001D5344 7D 89 03 A6 */ mtctr r12 -/* 801D96E8 001D5348 4E 80 04 21 */ bctrl -lbl_801D96EC: -/* 801D96EC 001D534C 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D96F0 001D5350 7C 08 03 A6 */ mtlr r0 -/* 801D96F4 001D5354 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D96F8 001D5358 4E 80 00 20 */ blr - -.global TRKInitializeIntDrivenUART -TRKInitializeIntDrivenUART: -/* 801D96FC 001D535C 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9700 001D5360 7C 08 02 A6 */ mflr r0 -/* 801D9704 001D5364 3C 80 80 1E */ lis r4, TRKEXICallBack@ha -/* 801D9708 001D5368 3C 60 80 42 */ lis r3, lbl_804232A0@ha -/* 801D970C 001D536C 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9710 001D5370 38 84 99 20 */ addi r4, r4, TRKEXICallBack@l -/* 801D9714 001D5374 81 83 32 A0 */ lwz r12, lbl_804232A0@l(r3) -/* 801D9718 001D5378 7C C3 33 78 */ mr r3, r6 -/* 801D971C 001D537C 7D 89 03 A6 */ mtctr r12 -/* 801D9720 001D5380 4E 80 04 21 */ bctrl -/* 801D9724 001D5384 3C 60 80 42 */ lis r3, lbl_804232A0@ha -/* 801D9728 001D5388 38 63 32 A0 */ addi r3, r3, lbl_804232A0@l -/* 801D972C 001D538C 81 83 00 18 */ lwz r12, 0x18(r3) -/* 801D9730 001D5390 7D 89 03 A6 */ mtctr r12 -/* 801D9734 001D5394 4E 80 04 21 */ bctrl -/* 801D9738 001D5398 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D973C 001D539C 38 60 00 00 */ li r3, 0 -/* 801D9740 001D53A0 7C 08 03 A6 */ mtlr r0 -/* 801D9744 001D53A4 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9748 001D53A8 4E 80 00 20 */ blr - -.global func_801D974C -func_801D974C: -/* 801D974C 001D53AC 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D9750 001D53B0 7C 08 02 A6 */ mflr r0 -/* 801D9754 001D53B4 3C 80 80 40 */ lis r4, lbl_803FD740@ha -/* 801D9758 001D53B8 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D975C 001D53BC 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D9760 001D53C0 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D9764 001D53C4 7C 7E 1B 78 */ mr r30, r3 -/* 801D9768 001D53C8 93 A1 00 14 */ stw r29, 0x14(r1) -/* 801D976C 001D53CC 3B A4 D7 40 */ addi r29, r4, lbl_803FD740@l -/* 801D9770 001D53D0 7F C4 F3 78 */ mr r4, r30 -/* 801D9774 001D53D4 38 7D 00 08 */ addi r3, r29, 8 -/* 801D9778 001D53D8 4C C6 31 82 */ crclr 6 -/* 801D977C 001D53DC 4B E2 E3 49 */ bl func_80007AC4 -/* 801D9780 001D53E0 38 7D 00 20 */ addi r3, r29, 0x20 -/* 801D9784 001D53E4 38 80 00 40 */ li r4, 0x40 -/* 801D9788 001D53E8 4C C6 31 82 */ crclr 6 -/* 801D978C 001D53EC 4B E2 E3 39 */ bl func_80007AC4 -/* 801D9790 001D53F0 3C 60 80 49 */ lis r3, lbl_80490D80@ha -/* 801D9794 001D53F4 38 00 00 00 */ li r0, 0 -/* 801D9798 001D53F8 2C 1E 00 02 */ cmpwi r30, 2 -/* 801D979C 001D53FC 98 03 0D 80 */ stb r0, lbl_80490D80@l(r3) -/* 801D97A0 001D5400 40 82 00 A0 */ bne lbl_801D9840 -/* 801D97A4 001D5404 38 7D 00 48 */ addi r3, r29, 0x48 -/* 801D97A8 001D5408 4C C6 31 82 */ crclr 6 -/* 801D97AC 001D540C 4B E2 E3 19 */ bl func_80007AC4 -/* 801D97B0 001D5410 3D 80 80 1E */ lis r12, lbl_801D99E8@ha -/* 801D97B4 001D5414 3D 60 80 42 */ lis r11, lbl_804232A0@ha -/* 801D97B8 001D5418 3B EC 99 E8 */ addi r31, r12, lbl_801D99E8@l -/* 801D97BC 001D541C 3D 40 80 1E */ lis r10, lbl_801D99D8@ha -/* 801D97C0 001D5420 39 8B 32 A0 */ addi r12, r11, lbl_804232A0@l -/* 801D97C4 001D5424 38 00 00 00 */ li r0, 0 -/* 801D97C8 001D5428 39 6A 99 D8 */ addi r11, r10, lbl_801D99D8@l -/* 801D97CC 001D542C 3D 20 80 1E */ lis r9, lbl_801D99D0@ha -/* 801D97D0 001D5430 39 49 99 D0 */ addi r10, r9, lbl_801D99D0@l -/* 801D97D4 001D5434 3D 00 80 1E */ lis r8, lbl_801D99C8@ha -/* 801D97D8 001D5438 39 28 99 C8 */ addi r9, r8, lbl_801D99C8@l -/* 801D97DC 001D543C 3C E0 80 1E */ lis r7, lbl_801D99C0@ha -/* 801D97E0 001D5440 39 07 99 C0 */ addi r8, r7, lbl_801D99C0@l -/* 801D97E4 001D5444 3C C0 80 1E */ lis r6, lbl_801D99E0@ha -/* 801D97E8 001D5448 38 E6 99 E0 */ addi r7, r6, lbl_801D99E0@l -/* 801D97EC 001D544C 3C A0 80 1E */ lis r5, lbl_801D99B8@ha -/* 801D97F0 001D5450 38 C5 99 B8 */ addi r6, r5, lbl_801D99B8@l -/* 801D97F4 001D5454 3C 80 80 1E */ lis r4, lbl_801D99B0@ha -/* 801D97F8 001D5458 38 A4 99 B0 */ addi r5, r4, lbl_801D99B0@l -/* 801D97FC 001D545C 3C 60 80 1E */ lis r3, lbl_801D99A8@ha -/* 801D9800 001D5460 38 83 99 A8 */ addi r4, r3, lbl_801D99A8@l -/* 801D9804 001D5464 3F C0 80 49 */ lis r30, lbl_80490D80@ha -/* 801D9808 001D5468 3B A0 00 01 */ li r29, 1 -/* 801D980C 001D546C 93 EC 00 00 */ stw r31, 0(r12) -/* 801D9810 001D5470 38 60 00 00 */ li r3, 0 -/* 801D9814 001D5474 9B BE 0D 80 */ stb r29, lbl_80490D80@l(r30) -/* 801D9818 001D5478 91 6C 00 18 */ stw r11, 0x18(r12) -/* 801D981C 001D547C 91 4C 00 1C */ stw r10, 0x1c(r12) -/* 801D9820 001D5480 91 2C 00 10 */ stw r9, 0x10(r12) -/* 801D9824 001D5484 91 0C 00 14 */ stw r8, 0x14(r12) -/* 801D9828 001D5488 90 EC 00 08 */ stw r7, 8(r12) -/* 801D982C 001D548C 90 CC 00 0C */ stw r6, 0xc(r12) -/* 801D9830 001D5490 90 AC 00 20 */ stw r5, 0x20(r12) -/* 801D9834 001D5494 90 8C 00 24 */ stw r4, 0x24(r12) -/* 801D9838 001D5498 90 0C 00 04 */ stw r0, 4(r12) -/* 801D983C 001D549C 48 00 00 C8 */ b lbl_801D9904 -lbl_801D9840: -/* 801D9840 001D54A0 2C 1E 00 01 */ cmpwi r30, 1 -/* 801D9844 001D54A4 40 82 00 94 */ bne lbl_801D98D8 -/* 801D9848 001D54A8 38 7D 00 60 */ addi r3, r29, 0x60 -/* 801D984C 001D54AC 4C C6 31 82 */ crclr 6 -/* 801D9850 001D54B0 4B E2 E2 75 */ bl func_80007AC4 -/* 801D9854 001D54B4 3F E0 80 1E */ lis r31, lbl_801D9C28@ha -/* 801D9858 001D54B8 3D 60 80 1E */ lis r11, ddh_cc_open@ha -/* 801D985C 001D54BC 3B FF 9C 28 */ addi r31, r31, lbl_801D9C28@l -/* 801D9860 001D54C0 3D 80 80 42 */ lis r12, lbl_804232A0@ha -/* 801D9864 001D54C4 3D 40 80 1E */ lis r10, lbl_801D9BF4@ha -/* 801D9868 001D54C8 3D 20 80 1E */ lis r9, lbl_801D9B40@ha -/* 801D986C 001D54CC 3D 00 80 1E */ lis r8, lbl_801D9ACC@ha -/* 801D9870 001D54D0 3C E0 80 1E */ lis r7, lbl_801D9C20@ha -/* 801D9874 001D54D4 3C C0 80 1E */ lis r6, ddh_cc_peek@ha -/* 801D9878 001D54D8 3C A0 80 1E */ lis r5, lbl_801D9AA8@ha -/* 801D987C 001D54DC 3C 80 80 1E */ lis r4, lbl_801D9A84@ha -/* 801D9880 001D54E0 3C 60 80 1E */ lis r3, lbl_801D99F0@ha -/* 801D9884 001D54E4 38 03 99 F0 */ addi r0, r3, lbl_801D99F0@l -/* 801D9888 001D54E8 97 EC 32 A0 */ stwu r31, lbl_804232A0@l(r12) -/* 801D988C 001D54EC 39 6B 9B FC */ addi r11, r11, ddh_cc_open@l -/* 801D9890 001D54F0 39 4A 9B F4 */ addi r10, r10, lbl_801D9BF4@l -/* 801D9894 001D54F4 39 29 9B 40 */ addi r9, r9, lbl_801D9B40@l -/* 801D9898 001D54F8 39 08 9A CC */ addi r8, r8, lbl_801D9ACC@l -/* 801D989C 001D54FC 38 E7 9C 20 */ addi r7, r7, lbl_801D9C20@l -/* 801D98A0 001D5500 38 C6 9A 14 */ addi r6, r6, ddh_cc_peek@l -/* 801D98A4 001D5504 38 A5 9A A8 */ addi r5, r5, lbl_801D9AA8@l -/* 801D98A8 001D5508 38 84 9A 84 */ addi r4, r4, lbl_801D9A84@l -/* 801D98AC 001D550C 91 6C 00 18 */ stw r11, 0x18(r12) -/* 801D98B0 001D5510 38 60 00 00 */ li r3, 0 -/* 801D98B4 001D5514 91 4C 00 1C */ stw r10, 0x1c(r12) -/* 801D98B8 001D5518 91 2C 00 10 */ stw r9, 0x10(r12) -/* 801D98BC 001D551C 91 0C 00 14 */ stw r8, 0x14(r12) -/* 801D98C0 001D5520 90 EC 00 08 */ stw r7, 8(r12) -/* 801D98C4 001D5524 90 CC 00 0C */ stw r6, 0xc(r12) -/* 801D98C8 001D5528 90 AC 00 20 */ stw r5, 0x20(r12) -/* 801D98CC 001D552C 90 8C 00 24 */ stw r4, 0x24(r12) -/* 801D98D0 001D5530 90 0C 00 04 */ stw r0, 4(r12) -/* 801D98D4 001D5534 48 00 00 30 */ b lbl_801D9904 -lbl_801D98D8: -/* 801D98D8 001D5538 7F C4 F3 78 */ mr r4, r30 -/* 801D98DC 001D553C 38 7D 00 84 */ addi r3, r29, 0x84 -/* 801D98E0 001D5540 4C C6 31 82 */ crclr 6 -/* 801D98E4 001D5544 4B E2 E1 E1 */ bl func_80007AC4 -/* 801D98E8 001D5548 38 7D 00 B0 */ addi r3, r29, 0xb0 -/* 801D98EC 001D554C 4C C6 31 82 */ crclr 6 -/* 801D98F0 001D5550 4B E2 E1 D5 */ bl func_80007AC4 -/* 801D98F4 001D5554 38 7D 00 E0 */ addi r3, r29, 0xe0 -/* 801D98F8 001D5558 4C C6 31 82 */ crclr 6 -/* 801D98FC 001D555C 4B E2 E1 C9 */ bl func_80007AC4 -/* 801D9900 001D5560 38 60 00 01 */ li r3, 1 -lbl_801D9904: -/* 801D9904 001D5564 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D9908 001D5568 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D990C 001D556C 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D9910 001D5570 83 A1 00 14 */ lwz r29, 0x14(r1) -/* 801D9914 001D5574 7C 08 03 A6 */ mtlr r0 -/* 801D9918 001D5578 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D991C 001D557C 4E 80 00 20 */ blr - -.global TRKEXICallBack -TRKEXICallBack: -/* 801D9920 001D5580 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9924 001D5584 7C 08 02 A6 */ mflr r0 -/* 801D9928 001D5588 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D992C 001D558C 93 E1 00 0C */ stw r31, 0xc(r1) -/* 801D9930 001D5590 7C 9F 23 78 */ mr r31, r4 -/* 801D9934 001D5594 48 09 7A 4D */ bl func_80271380 -/* 801D9938 001D5598 7F E3 FB 78 */ mr r3, r31 -/* 801D993C 001D559C 38 80 05 00 */ li r4, 0x500 -/* 801D9940 001D55A0 4B FF FB 59 */ bl TRKLoadContext -/* 801D9944 001D55A4 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9948 001D55A8 83 E1 00 0C */ lwz r31, 0xc(r1) -/* 801D994C 001D55AC 7C 08 03 A6 */ mtlr r0 -/* 801D9950 001D55B0 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9954 001D55B4 4E 80 00 20 */ blr - -.global TRKTargetContinue -TRKTargetContinue: -/* 801D9958 001D55B8 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D995C 001D55BC 7C 08 02 A6 */ mflr r0 -/* 801D9960 001D55C0 38 60 00 00 */ li r3, 0 -/* 801D9964 001D55C4 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9968 001D55C8 4B FF DC AD */ bl TRKTargetSetStopped -/* 801D996C 001D55CC 4B FF FC 41 */ bl func_801D95AC -/* 801D9970 001D55D0 4B FF DB 1D */ bl TRKSwapAndGo -/* 801D9974 001D55D4 4B FF FC 69 */ bl UnreserveEXI2Port -/* 801D9978 001D55D8 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D997C 001D55DC 38 60 00 00 */ li r3, 0 -/* 801D9980 001D55E0 7C 08 03 A6 */ mtlr r0 -/* 801D9984 001D55E4 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9988 001D55E8 4E 80 00 20 */ blr - -.global func_801D998C -func_801D998C: -/* 801D998C 001D55EC 3C 60 80 49 */ lis r3, lbl_80490D88@ha -/* 801D9990 001D55F0 38 63 0D 88 */ addi r3, r3, lbl_80490D88@l -/* 801D9994 001D55F4 88 63 00 00 */ lbz r3, 0(r3) -/* 801D9998 001D55F8 4E 80 00 20 */ blr - -.global SetUseSerialIO -SetUseSerialIO: -/* 801D999C 001D55FC 3C 80 80 49 */ lis r4, lbl_80490D88@ha -/* 801D99A0 001D5600 98 64 0D 88 */ stb r3, lbl_80490D88@l(r4) -/* 801D99A4 001D5604 4E 80 00 20 */ blr -lbl_801D99A8: -/* 801D99A8 001D5608 38 60 FF FF */ li r3, -1 -/* 801D99AC 001D560C 4E 80 00 20 */ blr -lbl_801D99B0: -/* 801D99B0 001D5610 38 60 FF FF */ li r3, -1 -/* 801D99B4 001D5614 4E 80 00 20 */ blr -lbl_801D99B8: -/* 801D99B8 001D5618 38 60 00 00 */ li r3, 0 -/* 801D99BC 001D561C 4E 80 00 20 */ blr -lbl_801D99C0: -/* 801D99C0 001D5620 38 60 00 00 */ li r3, 0 -/* 801D99C4 001D5624 4E 80 00 20 */ blr -lbl_801D99C8: -/* 801D99C8 001D5628 38 60 00 00 */ li r3, 0 -/* 801D99CC 001D562C 4E 80 00 20 */ blr -lbl_801D99D0: -/* 801D99D0 001D5630 38 60 FF FF */ li r3, -1 -/* 801D99D4 001D5634 4E 80 00 20 */ blr -lbl_801D99D8: -/* 801D99D8 001D5638 38 60 FF FF */ li r3, -1 -/* 801D99DC 001D563C 4E 80 00 20 */ blr -lbl_801D99E0: -/* 801D99E0 001D5640 38 60 FF FF */ li r3, -1 -/* 801D99E4 001D5644 4E 80 00 20 */ blr -lbl_801D99E8: -/* 801D99E8 001D5648 38 60 FF FF */ li r3, -1 -/* 801D99EC 001D564C 4E 80 00 20 */ blr -lbl_801D99F0: -/* 801D99F0 001D5650 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D99F4 001D5654 7C 08 02 A6 */ mflr r0 -/* 801D99F8 001D5658 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D99FC 001D565C 48 00 06 19 */ bl func_801DA014 -/* 801D9A00 001D5660 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9A04 001D5664 38 60 00 00 */ li r3, 0 -/* 801D9A08 001D5668 7C 08 03 A6 */ mtlr r0 -/* 801D9A0C 001D566C 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9A10 001D5670 4E 80 00 20 */ blr - -.global ddh_cc_peek -ddh_cc_peek: -/* 801D9A14 001D5674 94 21 FA F0 */ stwu r1, -0x510(r1) -/* 801D9A18 001D5678 7C 08 02 A6 */ mflr r0 -/* 801D9A1C 001D567C 90 01 05 14 */ stw r0, 0x514(r1) -/* 801D9A20 001D5680 93 E1 05 0C */ stw r31, 0x50c(r1) -/* 801D9A24 001D5684 48 00 06 45 */ bl func_801DA068 -/* 801D9A28 001D5688 7C 7F 1B 79 */ or. r31, r3, r3 -/* 801D9A2C 001D568C 41 81 00 0C */ bgt lbl_801D9A38 -/* 801D9A30 001D5690 38 60 00 00 */ li r3, 0 -/* 801D9A34 001D5694 48 00 00 3C */ b lbl_801D9A70 -lbl_801D9A38: -/* 801D9A38 001D5698 7F E4 FB 78 */ mr r4, r31 -/* 801D9A3C 001D569C 38 61 00 08 */ addi r3, r1, 8 -/* 801D9A40 001D56A0 48 00 06 CD */ bl func_801DA10C -/* 801D9A44 001D56A4 2C 03 00 00 */ cmpwi r3, 0 -/* 801D9A48 001D56A8 40 82 00 1C */ bne lbl_801D9A64 -/* 801D9A4C 001D56AC 3C 60 80 49 */ lis r3, lbl_80491290@ha -/* 801D9A50 001D56B0 7F E5 FB 78 */ mr r5, r31 -/* 801D9A54 001D56B4 38 63 12 90 */ addi r3, r3, lbl_80491290@l -/* 801D9A58 001D56B8 38 81 00 08 */ addi r4, r1, 8 -/* 801D9A5C 001D56BC 48 00 03 5D */ bl CircleBufferWriteBytes -/* 801D9A60 001D56C0 48 00 00 0C */ b lbl_801D9A6C -lbl_801D9A64: -/* 801D9A64 001D56C4 38 60 D8 E7 */ li r3, -10009 -/* 801D9A68 001D56C8 48 00 00 08 */ b lbl_801D9A70 -lbl_801D9A6C: -/* 801D9A6C 001D56CC 7F E3 FB 78 */ mr r3, r31 -lbl_801D9A70: -/* 801D9A70 001D56D0 80 01 05 14 */ lwz r0, 0x514(r1) -/* 801D9A74 001D56D4 83 E1 05 0C */ lwz r31, 0x50c(r1) -/* 801D9A78 001D56D8 7C 08 03 A6 */ mtlr r0 -/* 801D9A7C 001D56DC 38 21 05 10 */ addi r1, r1, 0x510 -/* 801D9A80 001D56E0 4E 80 00 20 */ blr -lbl_801D9A84: -/* 801D9A84 001D56E4 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9A88 001D56E8 7C 08 02 A6 */ mflr r0 -/* 801D9A8C 001D56EC 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9A90 001D56F0 48 00 08 0D */ bl func_801DA29C -/* 801D9A94 001D56F4 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9A98 001D56F8 38 60 00 00 */ li r3, 0 -/* 801D9A9C 001D56FC 7C 08 03 A6 */ mtlr r0 -/* 801D9AA0 001D5700 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9AA4 001D5704 4E 80 00 20 */ blr -lbl_801D9AA8: -/* 801D9AA8 001D5708 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9AAC 001D570C 7C 08 02 A6 */ mflr r0 -/* 801D9AB0 001D5710 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9AB4 001D5714 48 00 07 ED */ bl func_801DA2A0 -/* 801D9AB8 001D5718 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9ABC 001D571C 38 60 00 00 */ li r3, 0 -/* 801D9AC0 001D5720 7C 08 03 A6 */ mtlr r0 -/* 801D9AC4 001D5724 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9AC8 001D5728 4E 80 00 20 */ blr -lbl_801D9ACC: -/* 801D9ACC 001D572C 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9AD0 001D5730 7C 08 02 A6 */ mflr r0 -/* 801D9AD4 001D5734 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9AD8 001D5738 93 E1 00 0C */ stw r31, 0xc(r1) -/* 801D9ADC 001D573C 7C 9F 23 78 */ mr r31, r4 -/* 801D9AE0 001D5740 93 C1 00 08 */ stw r30, 8(r1) -/* 801D9AE4 001D5744 7C 7E 1B 78 */ mr r30, r3 -/* 801D9AE8 001D5748 80 0D 9F E8 */ lwz r0, lbl_8063F2A8-_SDA_BASE_(r13) -/* 801D9AEC 001D574C 2C 00 00 00 */ cmpwi r0, 0 -/* 801D9AF0 001D5750 40 82 00 2C */ bne lbl_801D9B1C -/* 801D9AF4 001D5754 38 60 D8 EF */ li r3, -10001 -/* 801D9AF8 001D5758 48 00 00 30 */ b lbl_801D9B28 -/* 801D9AFC 001D575C 48 00 00 20 */ b lbl_801D9B1C -lbl_801D9B00: -/* 801D9B00 001D5760 7F C3 F3 78 */ mr r3, r30 -/* 801D9B04 001D5764 7F E4 FB 78 */ mr r4, r31 -/* 801D9B08 001D5768 48 00 06 85 */ bl func_801DA18C -/* 801D9B0C 001D576C 2C 03 00 00 */ cmpwi r3, 0 -/* 801D9B10 001D5770 41 82 00 14 */ beq lbl_801D9B24 -/* 801D9B14 001D5774 7F DE 1A 14 */ add r30, r30, r3 -/* 801D9B18 001D5778 7F E3 F8 50 */ subf r31, r3, r31 -lbl_801D9B1C: -/* 801D9B1C 001D577C 2C 1F 00 00 */ cmpwi r31, 0 -/* 801D9B20 001D5780 41 81 FF E0 */ bgt lbl_801D9B00 -lbl_801D9B24: -/* 801D9B24 001D5784 38 60 00 00 */ li r3, 0 -lbl_801D9B28: -/* 801D9B28 001D5788 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9B2C 001D578C 83 E1 00 0C */ lwz r31, 0xc(r1) -/* 801D9B30 001D5790 83 C1 00 08 */ lwz r30, 8(r1) -/* 801D9B34 001D5794 7C 08 03 A6 */ mtlr r0 -/* 801D9B38 001D5798 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9B3C 001D579C 4E 80 00 20 */ blr -lbl_801D9B40: -/* 801D9B40 001D57A0 94 21 FA E0 */ stwu r1, -0x520(r1) -/* 801D9B44 001D57A4 7C 08 02 A6 */ mflr r0 -/* 801D9B48 001D57A8 90 01 05 24 */ stw r0, 0x524(r1) -/* 801D9B4C 001D57AC BF 61 05 0C */ stmw r27, 0x50c(r1) -/* 801D9B50 001D57B0 7C 7B 1B 78 */ mr r27, r3 -/* 801D9B54 001D57B4 3B A0 00 00 */ li r29, 0 -/* 801D9B58 001D57B8 80 0D 9F E8 */ lwz r0, lbl_8063F2A8-_SDA_BASE_(r13) -/* 801D9B5C 001D57BC 2C 00 00 00 */ cmpwi r0, 0 -/* 801D9B60 001D57C0 40 82 00 0C */ bne lbl_801D9B6C -/* 801D9B64 001D57C4 38 60 D8 EF */ li r3, -10001 -/* 801D9B68 001D57C8 48 00 00 78 */ b lbl_801D9BE0 -lbl_801D9B6C: -/* 801D9B6C 001D57CC 3C 60 80 49 */ lis r3, lbl_80491290@ha -/* 801D9B70 001D57D0 7C 9E 23 78 */ mr r30, r4 -/* 801D9B74 001D57D4 3B E3 12 90 */ addi r31, r3, lbl_80491290@l -/* 801D9B78 001D57D8 48 00 00 38 */ b lbl_801D9BB0 -lbl_801D9B7C: -/* 801D9B7C 001D57DC 3B A0 00 00 */ li r29, 0 -/* 801D9B80 001D57E0 48 00 04 E9 */ bl func_801DA068 -/* 801D9B84 001D57E4 7C 7C 1B 79 */ or. r28, r3, r3 -/* 801D9B88 001D57E8 41 82 00 28 */ beq lbl_801D9BB0 -/* 801D9B8C 001D57EC 7F C4 F3 78 */ mr r4, r30 -/* 801D9B90 001D57F0 38 61 00 08 */ addi r3, r1, 8 -/* 801D9B94 001D57F4 48 00 05 79 */ bl func_801DA10C -/* 801D9B98 001D57F8 7C 7D 1B 79 */ or. r29, r3, r3 -/* 801D9B9C 001D57FC 40 82 00 14 */ bne lbl_801D9BB0 -/* 801D9BA0 001D5800 7F E3 FB 78 */ mr r3, r31 -/* 801D9BA4 001D5804 7F 85 E3 78 */ mr r5, r28 -/* 801D9BA8 001D5808 38 81 00 08 */ addi r4, r1, 8 -/* 801D9BAC 001D580C 48 00 02 0D */ bl CircleBufferWriteBytes -lbl_801D9BB0: -/* 801D9BB0 001D5810 7F E3 FB 78 */ mr r3, r31 -/* 801D9BB4 001D5814 48 00 03 5D */ bl func_801D9F10 -/* 801D9BB8 001D5818 7C 03 F0 40 */ cmplw r3, r30 -/* 801D9BBC 001D581C 41 80 FF C0 */ blt lbl_801D9B7C -/* 801D9BC0 001D5820 28 1D 00 00 */ cmplwi r29, 0 -/* 801D9BC4 001D5824 40 82 00 18 */ bne lbl_801D9BDC -/* 801D9BC8 001D5828 3C 60 80 49 */ lis r3, lbl_80491290@ha -/* 801D9BCC 001D582C 7F 64 DB 78 */ mr r4, r27 -/* 801D9BD0 001D5830 38 63 12 90 */ addi r3, r3, lbl_80491290@l -/* 801D9BD4 001D5834 7F C5 F3 78 */ mr r5, r30 -/* 801D9BD8 001D5838 48 00 00 D9 */ bl CircleBufferReadBytes -lbl_801D9BDC: -/* 801D9BDC 001D583C 7F A3 EB 78 */ mr r3, r29 -lbl_801D9BE0: -/* 801D9BE0 001D5840 BB 61 05 0C */ lmw r27, 0x50c(r1) -/* 801D9BE4 001D5844 80 01 05 24 */ lwz r0, 0x524(r1) -/* 801D9BE8 001D5848 7C 08 03 A6 */ mtlr r0 -/* 801D9BEC 001D584C 38 21 05 20 */ addi r1, r1, 0x520 -/* 801D9BF0 001D5850 4E 80 00 20 */ blr -lbl_801D9BF4: -/* 801D9BF4 001D5854 38 60 00 00 */ li r3, 0 -/* 801D9BF8 001D5858 4E 80 00 20 */ blr - -.global ddh_cc_open -ddh_cc_open: -/* 801D9BFC 001D585C 80 0D 9F E8 */ lwz r0, lbl_8063F2A8-_SDA_BASE_(r13) -/* 801D9C00 001D5860 2C 00 00 00 */ cmpwi r0, 0 -/* 801D9C04 001D5864 41 82 00 0C */ beq lbl_801D9C10 -/* 801D9C08 001D5868 38 60 D8 EB */ li r3, -10005 -/* 801D9C0C 001D586C 4E 80 00 20 */ blr -lbl_801D9C10: -/* 801D9C10 001D5870 38 00 00 01 */ li r0, 1 -/* 801D9C14 001D5874 38 60 00 00 */ li r3, 0 -/* 801D9C18 001D5878 90 0D 9F E8 */ stw r0, lbl_8063F2A8-_SDA_BASE_(r13) -/* 801D9C1C 001D587C 4E 80 00 20 */ blr -lbl_801D9C20: -/* 801D9C20 001D5880 38 60 00 00 */ li r3, 0 -/* 801D9C24 001D5884 4E 80 00 20 */ blr -lbl_801D9C28: -/* 801D9C28 001D5888 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9C2C 001D588C 7C 08 02 A6 */ mflr r0 -/* 801D9C30 001D5890 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9C34 001D5894 48 00 03 85 */ bl func_801D9FB8 -/* 801D9C38 001D5898 3C 60 80 49 */ lis r3, lbl_80491290@ha -/* 801D9C3C 001D589C 3C 80 80 49 */ lis r4, lbl_80490D90@ha -/* 801D9C40 001D58A0 38 63 12 90 */ addi r3, r3, lbl_80491290@l -/* 801D9C44 001D58A4 38 A0 05 00 */ li r5, 0x500 -/* 801D9C48 001D58A8 38 84 0D 90 */ addi r4, r4, lbl_80490D90@l -/* 801D9C4C 001D58AC 48 00 02 75 */ bl CircleBufferInitialize -/* 801D9C50 001D58B0 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9C54 001D58B4 38 60 00 00 */ li r3, 0 -/* 801D9C58 001D58B8 7C 08 03 A6 */ mtlr r0 -/* 801D9C5C 001D58BC 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9C60 001D58C0 4E 80 00 20 */ blr - -.global func_801D9C64 -func_801D9C64: -/* 801D9C64 001D58C4 2C 04 00 00 */ cmpwi r4, 0 -/* 801D9C68 001D58C8 38 A0 00 00 */ li r5, 0 -/* 801D9C6C 001D58CC 4C 81 00 20 */ blelr -/* 801D9C70 001D58D0 2C 04 00 08 */ cmpwi r4, 8 -/* 801D9C74 001D58D4 38 64 FF F8 */ addi r3, r4, -8 -/* 801D9C78 001D58D8 40 81 00 20 */ ble lbl_801D9C98 -/* 801D9C7C 001D58DC 38 03 00 07 */ addi r0, r3, 7 -/* 801D9C80 001D58E0 54 00 E8 FE */ srwi r0, r0, 3 -/* 801D9C84 001D58E4 7C 09 03 A6 */ mtctr r0 -/* 801D9C88 001D58E8 2C 03 00 00 */ cmpwi r3, 0 -/* 801D9C8C 001D58EC 40 81 00 0C */ ble lbl_801D9C98 -lbl_801D9C90: -/* 801D9C90 001D58F0 38 A5 00 08 */ addi r5, r5, 8 -/* 801D9C94 001D58F4 42 00 FF FC */ bdnz lbl_801D9C90 -lbl_801D9C98: -/* 801D9C98 001D58F8 7C 05 20 50 */ subf r0, r5, r4 -/* 801D9C9C 001D58FC 7C 09 03 A6 */ mtctr r0 -/* 801D9CA0 001D5900 7C 05 20 00 */ cmpw r5, r4 -/* 801D9CA4 001D5904 4C 80 00 20 */ bgelr -lbl_801D9CA8: -/* 801D9CA8 001D5908 42 00 00 00 */ bdnz lbl_801D9CA8 -/* 801D9CAC 001D590C 4E 80 00 20 */ blr - -.global CircleBufferReadBytes -CircleBufferReadBytes: -/* 801D9CB0 001D5910 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D9CB4 001D5914 7C 08 02 A6 */ mflr r0 -/* 801D9CB8 001D5918 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D9CBC 001D591C 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D9CC0 001D5920 7C BF 2B 78 */ mr r31, r5 -/* 801D9CC4 001D5924 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D9CC8 001D5928 7C 7E 1B 78 */ mr r30, r3 -/* 801D9CCC 001D592C 93 A1 00 14 */ stw r29, 0x14(r1) -/* 801D9CD0 001D5930 93 81 00 10 */ stw r28, 0x10(r1) -/* 801D9CD4 001D5934 7C 9C 23 78 */ mr r28, r4 -/* 801D9CD8 001D5938 80 03 00 10 */ lwz r0, 0x10(r3) -/* 801D9CDC 001D593C 7C 1F 00 40 */ cmplw r31, r0 -/* 801D9CE0 001D5940 40 81 00 0C */ ble lbl_801D9CEC -/* 801D9CE4 001D5944 38 60 FF FF */ li r3, -1 -/* 801D9CE8 001D5948 48 00 00 B0 */ b lbl_801D9D98 -lbl_801D9CEC: -/* 801D9CEC 001D594C 38 7E 00 18 */ addi r3, r30, 0x18 -/* 801D9CF0 001D5950 48 00 02 4D */ bl MWEnterCriticalSection -/* 801D9CF4 001D5954 80 7E 00 08 */ lwz r3, 8(r30) -/* 801D9CF8 001D5958 80 9E 00 00 */ lwz r4, 0(r30) -/* 801D9CFC 001D595C 80 1E 00 0C */ lwz r0, 0xc(r30) -/* 801D9D00 001D5960 7C 63 20 50 */ subf r3, r3, r4 -/* 801D9D04 001D5964 7F A3 00 50 */ subf r29, r3, r0 -/* 801D9D08 001D5968 7C 1F E8 40 */ cmplw r31, r29 -/* 801D9D0C 001D596C 40 80 00 20 */ bge lbl_801D9D2C -/* 801D9D10 001D5970 7F 83 E3 78 */ mr r3, r28 -/* 801D9D14 001D5974 7F E5 FB 78 */ mr r5, r31 -/* 801D9D18 001D5978 4B E2 A2 E9 */ bl memcpy -/* 801D9D1C 001D597C 80 1E 00 00 */ lwz r0, 0(r30) -/* 801D9D20 001D5980 7C 00 FA 14 */ add r0, r0, r31 -/* 801D9D24 001D5984 90 1E 00 00 */ stw r0, 0(r30) -/* 801D9D28 001D5988 48 00 00 30 */ b lbl_801D9D58 -lbl_801D9D2C: -/* 801D9D2C 001D598C 7F 83 E3 78 */ mr r3, r28 -/* 801D9D30 001D5990 7F A5 EB 78 */ mr r5, r29 -/* 801D9D34 001D5994 4B E2 A2 CD */ bl memcpy -/* 801D9D38 001D5998 80 9E 00 08 */ lwz r4, 8(r30) -/* 801D9D3C 001D599C 7C 7C EA 14 */ add r3, r28, r29 -/* 801D9D40 001D59A0 7C BD F8 50 */ subf r5, r29, r31 -/* 801D9D44 001D59A4 4B E2 A2 BD */ bl memcpy -/* 801D9D48 001D59A8 80 1E 00 08 */ lwz r0, 8(r30) -/* 801D9D4C 001D59AC 7C 00 FA 14 */ add r0, r0, r31 -/* 801D9D50 001D59B0 7C 1D 00 50 */ subf r0, r29, r0 -/* 801D9D54 001D59B4 90 1E 00 00 */ stw r0, 0(r30) -lbl_801D9D58: -/* 801D9D58 001D59B8 80 9E 00 08 */ lwz r4, 8(r30) -/* 801D9D5C 001D59BC 80 1E 00 00 */ lwz r0, 0(r30) -/* 801D9D60 001D59C0 80 7E 00 0C */ lwz r3, 0xc(r30) -/* 801D9D64 001D59C4 7C 04 00 50 */ subf r0, r4, r0 -/* 801D9D68 001D59C8 7C 03 00 40 */ cmplw r3, r0 -/* 801D9D6C 001D59CC 40 82 00 08 */ bne lbl_801D9D74 -/* 801D9D70 001D59D0 90 9E 00 00 */ stw r4, 0(r30) -lbl_801D9D74: -/* 801D9D74 001D59D4 80 1E 00 14 */ lwz r0, 0x14(r30) -/* 801D9D78 001D59D8 38 7E 00 18 */ addi r3, r30, 0x18 -/* 801D9D7C 001D59DC 7C 00 FA 14 */ add r0, r0, r31 -/* 801D9D80 001D59E0 90 1E 00 14 */ stw r0, 0x14(r30) -/* 801D9D84 001D59E4 80 1E 00 10 */ lwz r0, 0x10(r30) -/* 801D9D88 001D59E8 7C 1F 00 50 */ subf r0, r31, r0 -/* 801D9D8C 001D59EC 90 1E 00 10 */ stw r0, 0x10(r30) -/* 801D9D90 001D59F0 48 00 01 89 */ bl cFielder_UpdatePlay -/* 801D9D94 001D59F4 38 60 00 00 */ li r3, 0 -lbl_801D9D98: -/* 801D9D98 001D59F8 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D9D9C 001D59FC 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D9DA0 001D5A00 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D9DA4 001D5A04 83 A1 00 14 */ lwz r29, 0x14(r1) -/* 801D9DA8 001D5A08 83 81 00 10 */ lwz r28, 0x10(r1) -/* 801D9DAC 001D5A0C 7C 08 03 A6 */ mtlr r0 -/* 801D9DB0 001D5A10 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D9DB4 001D5A14 4E 80 00 20 */ blr - -.global CircleBufferWriteBytes -CircleBufferWriteBytes: -/* 801D9DB8 001D5A18 94 21 FF E0 */ stwu r1, -0x20(r1) -/* 801D9DBC 001D5A1C 7C 08 02 A6 */ mflr r0 -/* 801D9DC0 001D5A20 90 01 00 24 */ stw r0, 0x24(r1) -/* 801D9DC4 001D5A24 93 E1 00 1C */ stw r31, 0x1c(r1) -/* 801D9DC8 001D5A28 7C BF 2B 78 */ mr r31, r5 -/* 801D9DCC 001D5A2C 93 C1 00 18 */ stw r30, 0x18(r1) -/* 801D9DD0 001D5A30 7C 7E 1B 78 */ mr r30, r3 -/* 801D9DD4 001D5A34 93 A1 00 14 */ stw r29, 0x14(r1) -/* 801D9DD8 001D5A38 93 81 00 10 */ stw r28, 0x10(r1) -/* 801D9DDC 001D5A3C 7C 9C 23 78 */ mr r28, r4 -/* 801D9DE0 001D5A40 80 03 00 14 */ lwz r0, 0x14(r3) -/* 801D9DE4 001D5A44 7C 1F 00 40 */ cmplw r31, r0 -/* 801D9DE8 001D5A48 40 81 00 0C */ ble lbl_801D9DF4 -/* 801D9DEC 001D5A4C 38 60 FF FF */ li r3, -1 -/* 801D9DF0 001D5A50 48 00 00 B0 */ b lbl_801D9EA0 -lbl_801D9DF4: -/* 801D9DF4 001D5A54 38 7E 00 18 */ addi r3, r30, 0x18 -/* 801D9DF8 001D5A58 48 00 01 45 */ bl MWEnterCriticalSection -/* 801D9DFC 001D5A5C 80 9E 00 08 */ lwz r4, 8(r30) -/* 801D9E00 001D5A60 80 7E 00 04 */ lwz r3, 4(r30) -/* 801D9E04 001D5A64 80 1E 00 0C */ lwz r0, 0xc(r30) -/* 801D9E08 001D5A68 7C 84 18 50 */ subf r4, r4, r3 -/* 801D9E0C 001D5A6C 7F A4 00 50 */ subf r29, r4, r0 -/* 801D9E10 001D5A70 7C 1D F8 40 */ cmplw r29, r31 -/* 801D9E14 001D5A74 41 80 00 20 */ blt lbl_801D9E34 -/* 801D9E18 001D5A78 7F 84 E3 78 */ mr r4, r28 -/* 801D9E1C 001D5A7C 7F E5 FB 78 */ mr r5, r31 -/* 801D9E20 001D5A80 4B E2 A1 E1 */ bl memcpy -/* 801D9E24 001D5A84 80 1E 00 04 */ lwz r0, 4(r30) -/* 801D9E28 001D5A88 7C 00 FA 14 */ add r0, r0, r31 -/* 801D9E2C 001D5A8C 90 1E 00 04 */ stw r0, 4(r30) -/* 801D9E30 001D5A90 48 00 00 30 */ b lbl_801D9E60 -lbl_801D9E34: -/* 801D9E34 001D5A94 7F 84 E3 78 */ mr r4, r28 -/* 801D9E38 001D5A98 7F A5 EB 78 */ mr r5, r29 -/* 801D9E3C 001D5A9C 4B E2 A1 C5 */ bl memcpy -/* 801D9E40 001D5AA0 80 7E 00 08 */ lwz r3, 8(r30) -/* 801D9E44 001D5AA4 7C 9C EA 14 */ add r4, r28, r29 -/* 801D9E48 001D5AA8 7C BD F8 50 */ subf r5, r29, r31 -/* 801D9E4C 001D5AAC 4B E2 A1 B5 */ bl memcpy -/* 801D9E50 001D5AB0 80 1E 00 08 */ lwz r0, 8(r30) -/* 801D9E54 001D5AB4 7C 00 FA 14 */ add r0, r0, r31 -/* 801D9E58 001D5AB8 7C 1D 00 50 */ subf r0, r29, r0 -/* 801D9E5C 001D5ABC 90 1E 00 04 */ stw r0, 4(r30) -lbl_801D9E60: -/* 801D9E60 001D5AC0 80 9E 00 08 */ lwz r4, 8(r30) -/* 801D9E64 001D5AC4 80 1E 00 04 */ lwz r0, 4(r30) -/* 801D9E68 001D5AC8 80 7E 00 0C */ lwz r3, 0xc(r30) -/* 801D9E6C 001D5ACC 7C 04 00 50 */ subf r0, r4, r0 -/* 801D9E70 001D5AD0 7C 03 00 40 */ cmplw r3, r0 -/* 801D9E74 001D5AD4 40 82 00 08 */ bne lbl_801D9E7C -/* 801D9E78 001D5AD8 90 9E 00 04 */ stw r4, 4(r30) -lbl_801D9E7C: -/* 801D9E7C 001D5ADC 80 1E 00 14 */ lwz r0, 0x14(r30) -/* 801D9E80 001D5AE0 38 7E 00 18 */ addi r3, r30, 0x18 -/* 801D9E84 001D5AE4 7C 1F 00 50 */ subf r0, r31, r0 -/* 801D9E88 001D5AE8 90 1E 00 14 */ stw r0, 0x14(r30) -/* 801D9E8C 001D5AEC 80 1E 00 10 */ lwz r0, 0x10(r30) -/* 801D9E90 001D5AF0 7C 00 FA 14 */ add r0, r0, r31 -/* 801D9E94 001D5AF4 90 1E 00 10 */ stw r0, 0x10(r30) -/* 801D9E98 001D5AF8 48 00 00 81 */ bl cFielder_UpdatePlay -/* 801D9E9C 001D5AFC 38 60 00 00 */ li r3, 0 -lbl_801D9EA0: -/* 801D9EA0 001D5B00 80 01 00 24 */ lwz r0, 0x24(r1) -/* 801D9EA4 001D5B04 83 E1 00 1C */ lwz r31, 0x1c(r1) -/* 801D9EA8 001D5B08 83 C1 00 18 */ lwz r30, 0x18(r1) -/* 801D9EAC 001D5B0C 83 A1 00 14 */ lwz r29, 0x14(r1) -/* 801D9EB0 001D5B10 83 81 00 10 */ lwz r28, 0x10(r1) -/* 801D9EB4 001D5B14 7C 08 03 A6 */ mtlr r0 -/* 801D9EB8 001D5B18 38 21 00 20 */ addi r1, r1, 0x20 -/* 801D9EBC 001D5B1C 4E 80 00 20 */ blr - -.global CircleBufferInitialize -CircleBufferInitialize: -/* 801D9EC0 001D5B20 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9EC4 001D5B24 7C 08 02 A6 */ mflr r0 -/* 801D9EC8 001D5B28 7C 66 1B 78 */ mr r6, r3 -/* 801D9ECC 001D5B2C 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9ED0 001D5B30 38 00 00 00 */ li r0, 0 -/* 801D9ED4 001D5B34 90 83 00 08 */ stw r4, 8(r3) -/* 801D9ED8 001D5B38 38 66 00 18 */ addi r3, r6, 0x18 -/* 801D9EDC 001D5B3C 90 A6 00 0C */ stw r5, 0xc(r6) -/* 801D9EE0 001D5B40 80 86 00 08 */ lwz r4, 8(r6) -/* 801D9EE4 001D5B44 90 86 00 00 */ stw r4, 0(r6) -/* 801D9EE8 001D5B48 80 86 00 08 */ lwz r4, 8(r6) -/* 801D9EEC 001D5B4C 90 86 00 04 */ stw r4, 4(r6) -/* 801D9EF0 001D5B50 90 06 00 10 */ stw r0, 0x10(r6) -/* 801D9EF4 001D5B54 80 06 00 0C */ lwz r0, 0xc(r6) -/* 801D9EF8 001D5B58 90 06 00 14 */ stw r0, 0x14(r6) -/* 801D9EFC 001D5B5C 48 00 00 71 */ bl func_801D9F6C -/* 801D9F00 001D5B60 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9F04 001D5B64 7C 08 03 A6 */ mtlr r0 -/* 801D9F08 001D5B68 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9F0C 001D5B6C 4E 80 00 20 */ blr - -.global func_801D9F10 -func_801D9F10: -/* 801D9F10 001D5B70 80 63 00 10 */ lwz r3, 0x10(r3) -/* 801D9F14 001D5B74 4E 80 00 20 */ blr - -.global cFielder_UpdatePlay -cFielder_UpdatePlay: -/* 801D9F18 001D5B78 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9F1C 001D5B7C 7C 08 02 A6 */ mflr r0 -/* 801D9F20 001D5B80 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9F24 001D5B84 80 63 00 00 */ lwz r3, 0(r3) -/* 801D9F28 001D5B88 48 09 48 5D */ bl OSRestoreInterrupts -/* 801D9F2C 001D5B8C 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9F30 001D5B90 7C 08 03 A6 */ mtlr r0 -/* 801D9F34 001D5B94 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9F38 001D5B98 4E 80 00 20 */ blr - -.global MWEnterCriticalSection -MWEnterCriticalSection: -/* 801D9F3C 001D5B9C 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 801D9F40 001D5BA0 7C 08 02 A6 */ mflr r0 -/* 801D9F44 001D5BA4 90 01 00 14 */ stw r0, 0x14(r1) -/* 801D9F48 001D5BA8 93 E1 00 0C */ stw r31, 0xc(r1) -/* 801D9F4C 001D5BAC 7C 7F 1B 78 */ mr r31, r3 -/* 801D9F50 001D5BB0 48 09 48 0D */ bl OSDisableInterrupts -/* 801D9F54 001D5BB4 90 7F 00 00 */ stw r3, 0(r31) -/* 801D9F58 001D5BB8 80 01 00 14 */ lwz r0, 0x14(r1) -/* 801D9F5C 001D5BBC 83 E1 00 0C */ lwz r31, 0xc(r1) -/* 801D9F60 001D5BC0 7C 08 03 A6 */ mtlr r0 -/* 801D9F64 001D5BC4 38 21 00 10 */ addi r1, r1, 0x10 -/* 801D9F68 001D5BC8 4E 80 00 20 */ blr - -.global func_801D9F6C -func_801D9F6C: -/* 801D9F6C 001D5BCC 4E 80 00 20 */ blr lbl_801D9F70: /* 801D9F70 001D5BD0 81 8D 9F F0 */ lwz r12, lbl_8063F2B0-_SDA_BASE_(r13) /* 801D9F74 001D5BD4 38 00 00 01 */ li r0, 1 diff --git a/obj_files.mk b/obj_files.mk index 97e4584..c4fec51 100644 --- a/obj_files.mk +++ b/obj_files.mk @@ -87,6 +87,17 @@ TEXT_O_FILES := \ $(BUILD_DIR)/asm/init.o \ $(BUILD_DIR)/asm/MetroTRK/string_TRK.o \ $(BUILD_DIR)/asm/MetroTRK/targimpl.o \ + $(BUILD_DIR)/asm/MetroTRK/mpc_7xx_603e.o \ + $(BUILD_DIR)/asm/MetroTRK/mslsupp.o \ + $(BUILD_DIR)/asm/MetroTRK/dolphin_trk.o \ + $(BUILD_DIR)/asm/MetroTRK/main_TRK.o \ + $(BUILD_DIR)/asm/MetroTRK/dolphin_trk_glue.o \ + $(BUILD_DIR)/asm/MetroTRK/targcont.o \ + $(BUILD_DIR)/asm/MetroTRK/target_options.o \ + $(BUILD_DIR)/asm/MetroTRK/UDP_Stubs.o \ + $(BUILD_DIR)/asm/MetroTRK/main.o \ + $(BUILD_DIR)/asm/MetroTRK/CircleBuffer.o \ + $(BUILD_DIR)/asm/MetroTRK/MWCriticalSection_gc.o \ $(BUILD_DIR)/asm/text_6_2.o \ $(BUILD_DIR)/asm/text_7.o \ $(BUILD_DIR)/asm/SDK/OS/OS.o \ diff --git a/tools/postprocess/postprocess.py b/tools/postprocess/postprocess.py index c45ec16..3c757e4 100644 --- a/tools/postprocess/postprocess.py +++ b/tools/postprocess/postprocess.py @@ -22,6 +22,7 @@ BANNER = """ # 3: \\ # 4: , # 5: - +# 6: * # # This option is enabled with -fsymbol-fixup, and disabled by default with -fno-symbol-fixup # @@ -39,7 +40,8 @@ substitutions = ( ('@', '$2'), ('\\', '$3'), (',', '$4'), - ('-', '$5') + ('-', '$5'), + ('*', '$6') ) def format(symbol): -- cgit v1.2.3