.include "macros.inc"

.section .text, "ax"  # 0x80006980 - 0x803E1E60

.global __write_console
__write_console:
/* 801D08E8 001CC548  94 21 FF E0 */	stwu r1, -0x20(r1)
/* 801D08EC 001CC54C  7C 08 02 A6 */	mflr r0
/* 801D08F0 001CC550  90 01 00 24 */	stw r0, 0x24(r1)
/* 801D08F4 001CC554  93 E1 00 1C */	stw r31, 0x1c(r1)
/* 801D08F8 001CC558  7C DF 33 78 */	mr r31, r6
/* 801D08FC 001CC55C  93 C1 00 18 */	stw r30, 0x18(r1)
/* 801D0900 001CC560  7C BE 2B 78 */	mr r30, r5
/* 801D0904 001CC564  93 A1 00 14 */	stw r29, 0x14(r1)
/* 801D0908 001CC568  7C 9D 23 78 */	mr r29, r4
/* 801D090C 001CC56C  93 81 00 10 */	stw r28, 0x10(r1)
/* 801D0910 001CC570  7C 7C 1B 78 */	mr r28, r3
/* 801D0914 001CC574  48 09 7C 19 */	bl OSGetConsoleType
/* 801D0918 001CC578  54 60 00 85 */	rlwinm. r0, r3, 0, 2, 2
/* 801D091C 001CC57C  40 82 00 64 */	bne lbl_801D0980
/* 801D0920 001CC580  80 0D 9F D0 */	lwz r0, lbl_8063F290-_SDA_BASE_(r13)
/* 801D0924 001CC584  38 60 00 00 */	li r3, 0
/* 801D0928 001CC588  2C 00 00 00 */	cmpwi r0, 0
/* 801D092C 001CC58C  40 82 00 20 */	bne lbl_801D094C
/* 801D0930 001CC590  3C 60 00 01 */	lis r3, 0x0000E100@ha
/* 801D0934 001CC594  38 63 E1 00 */	addi r3, r3, 0x0000E100@l
/* 801D0938 001CC598  48 0E 30 75 */	bl InitializeUART
/* 801D093C 001CC59C  2C 03 00 00 */	cmpwi r3, 0
/* 801D0940 001CC5A0  40 82 00 0C */	bne lbl_801D094C
/* 801D0944 001CC5A4  38 00 00 01 */	li r0, 1
/* 801D0948 001CC5A8  90 0D 9F D0 */	stw r0, lbl_8063F290-_SDA_BASE_(r13)
lbl_801D094C:
/* 801D094C 001CC5AC  2C 03 00 00 */	cmpwi r3, 0
/* 801D0950 001CC5B0  41 82 00 0C */	beq lbl_801D095C
/* 801D0954 001CC5B4  38 60 00 01 */	li r3, 1
/* 801D0958 001CC5B8  48 00 00 40 */	b lbl_801D0998
lbl_801D095C:
/* 801D095C 001CC5BC  80 9E 00 00 */	lwz r4, 0(r30)
/* 801D0960 001CC5C0  7F A3 EB 78 */	mr r3, r29
/* 801D0964 001CC5C4  48 0E 30 91 */	bl WriteUARTN
/* 801D0968 001CC5C8  2C 03 00 00 */	cmpwi r3, 0
/* 801D096C 001CC5CC  41 82 00 14 */	beq lbl_801D0980
/* 801D0970 001CC5D0  38 00 00 00 */	li r0, 0
/* 801D0974 001CC5D4  38 60 00 01 */	li r3, 1
/* 801D0978 001CC5D8  90 1E 00 00 */	stw r0, 0(r30)
/* 801D097C 001CC5DC  48 00 00 1C */	b lbl_801D0998
lbl_801D0980:
/* 801D0980 001CC5E0  7F 83 E3 78 */	mr r3, r28
/* 801D0984 001CC5E4  7F A4 EB 78 */	mr r4, r29
/* 801D0988 001CC5E8  7F C5 F3 78 */	mr r5, r30
/* 801D098C 001CC5EC  7F E6 FB 78 */	mr r6, r31
/* 801D0990 001CC5F0  48 00 86 31 */	bl __TRK_write_console
/* 801D0994 001CC5F4  38 60 00 00 */	li r3, 0
lbl_801D0998:
/* 801D0998 001CC5F8  80 01 00 24 */	lwz r0, 0x24(r1)
/* 801D099C 001CC5FC  83 E1 00 1C */	lwz r31, 0x1c(r1)
/* 801D09A0 001CC600  83 C1 00 18 */	lwz r30, 0x18(r1)
/* 801D09A4 001CC604  83 A1 00 14 */	lwz r29, 0x14(r1)
/* 801D09A8 001CC608  83 81 00 10 */	lwz r28, 0x10(r1)
/* 801D09AC 001CC60C  7C 08 03 A6 */	mtlr r0
/* 801D09B0 001CC610  38 21 00 20 */	addi r1, r1, 0x20
/* 801D09B4 001CC614  4E 80 00 20 */	blr

.global __close_console
__close_console:
/* 801D09B8 001CC618  38 60 00 00 */	li r3, 0
/* 801D09BC 001CC61C  4E 80 00 20 */	blr