.include "macros.inc" .section .text, "ax" # 0x80006980 - 0x803E1E60 .global __TRK_get_MSR __TRK_get_MSR: /* 801D7210 001D2E70 7C 60 00 A6 */ mfmsr r3 /* 801D7214 001D2E74 4E 80 00 20 */ blr .global __TRK_set_MSR __TRK_set_MSR: /* 801D7218 001D2E78 7C 60 01 24 */ mtmsr r3 /* 801D721C 001D2E7C 4E 80 00 20 */ blr .global TRK_ppc_memcpy TRK_ppc_memcpy: /* 801D7220 001D2E80 7D 00 00 A6 */ mfmsr r8 /* 801D7224 001D2E84 39 40 00 00 */ li r10, 0 lbl_801D7228: /* 801D7228 001D2E88 7C 0A 28 00 */ cmpw r10, r5 /* 801D722C 001D2E8C 41 82 00 24 */ beq lbl_801D7250 /* 801D7230 001D2E90 7C E0 01 24 */ mtmsr r7 /* 801D7234 001D2E94 7C 00 04 AC */ sync 0 /* 801D7238 001D2E98 7D 2A 20 AE */ lbzx r9, r10, r4 /* 801D723C 001D2E9C 7C C0 01 24 */ mtmsr r6 /* 801D7240 001D2EA0 7C 00 04 AC */ sync 0 /* 801D7244 001D2EA4 7D 2A 19 AE */ stbx r9, r10, r3 /* 801D7248 001D2EA8 39 4A 00 01 */ addi r10, r10, 1 /* 801D724C 001D2EAC 4B FF FF DC */ b lbl_801D7228 lbl_801D7250: /* 801D7250 001D2EB0 7D 00 01 24 */ mtmsr r8 /* 801D7254 001D2EB4 7C 00 04 AC */ sync 0 /* 801D7258 001D2EB8 4E 80 00 20 */ blr .global TRKInterruptHandler TRKInterruptHandler: /* 801D725C 001D2EBC 7C 5A 03 A6 */ mtspr 0x1a, r2 /* 801D7260 001D2EC0 7C 9B 03 A6 */ mtspr 0x1b, r4 /* 801D7264 001D2EC4 7C 93 42 A6 */ mfspr r4, 0x113 /* 801D7268 001D2EC8 7C 40 00 26 */ mfcr r2 /* 801D726C 001D2ECC 7C 53 43 A6 */ mtspr 0x113, r2 /* 801D7270 001D2ED0 3C 40 80 49 */ lis r2, lbl_804907F4@h /* 801D7274 001D2ED4 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l /* 801D7278 001D2ED8 80 42 00 8C */ lwz r2, 0x8c(r2) /* 801D727C 001D2EDC 60 42 80 02 */ ori r2, r2, 0x8002 /* 801D7280 001D2EE0 68 42 80 02 */ xori r2, r2, 0x8002 /* 801D7284 001D2EE4 7C 00 04 AC */ sync 0 /* 801D7288 001D2EE8 7C 40 01 24 */ mtmsr r2 /* 801D728C 001D2EEC 7C 00 04 AC */ sync 0 /* 801D7290 001D2EF0 3C 40 80 49 */ lis r2, lbl_804907F0@h /* 801D7294 001D2EF4 60 42 07 F0 */ ori r2, r2, lbl_804907F0@l /* 801D7298 001D2EF8 B0 62 00 00 */ sth r3, 0(r2) /* 801D729C 001D2EFC 2C 03 05 00 */ cmpwi r3, 0x500 /* 801D72A0 001D2F00 40 82 00 84 */ bne lbl_801D7324 /* 801D72A4 001D2F04 3C 40 80 49 */ lis r2, lbl_80490898@h /* 801D72A8 001D2F08 60 42 08 98 */ ori r2, r2, lbl_80490898@l /* 801D72AC 001D2F0C 7C 68 02 A6 */ mflr r3 /* 801D72B0 001D2F10 90 62 04 2C */ stw r3, 0x42c(r2) /* 801D72B4 001D2F14 48 00 22 6D */ bl TRKUARTInterruptHandler /* 801D72B8 001D2F18 3C 40 80 49 */ lis r2, lbl_80490898@h /* 801D72BC 001D2F1C 60 42 08 98 */ ori r2, r2, lbl_80490898@l /* 801D72C0 001D2F20 80 62 04 2C */ lwz r3, 0x42c(r2) /* 801D72C4 001D2F24 7C 68 03 A6 */ mtlr r3 /* 801D72C8 001D2F28 3C 40 80 49 */ lis r2, lbl_804907F4@h /* 801D72CC 001D2F2C 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l /* 801D72D0 001D2F30 80 42 00 A0 */ lwz r2, 0xa0(r2) /* 801D72D4 001D2F34 88 42 00 00 */ lbz r2, 0(r2) /* 801D72D8 001D2F38 2C 02 00 00 */ cmpwi r2, 0 /* 801D72DC 001D2F3C 41 82 00 2C */ beq lbl_801D7308 /* 801D72E0 001D2F40 3C 40 80 42 */ lis r2, lbl_8042323C@h /* 801D72E4 001D2F44 60 42 32 3C */ ori r2, r2, lbl_8042323C@l /* 801D72E8 001D2F48 88 42 00 0C */ lbz r2, 0xc(r2) /* 801D72EC 001D2F4C 2C 02 00 01 */ cmpwi r2, 1 /* 801D72F0 001D2F50 41 82 00 18 */ beq lbl_801D7308 /* 801D72F4 001D2F54 3C 40 80 49 */ lis r2, lbl_804907F4@h /* 801D72F8 001D2F58 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l /* 801D72FC 001D2F5C 38 60 00 01 */ li r3, 1 /* 801D7300 001D2F60 98 62 00 9C */ stb r3, 0x9c(r2) /* 801D7304 001D2F64 48 00 00 20 */ b lbl_801D7324 lbl_801D7308: /* 801D7308 001D2F68 3C 40 80 49 */ lis r2, lbl_80490CC8@h /* 801D730C 001D2F6C 60 42 0C C8 */ ori r2, r2, lbl_80490CC8@l /* 801D7310 001D2F70 80 62 00 88 */ lwz r3, 0x88(r2) /* 801D7314 001D2F74 7C 6F F1 20 */ mtcrf 0xff, r3 /* 801D7318 001D2F78 80 62 00 0C */ lwz r3, 0xc(r2) /* 801D731C 001D2F7C 80 42 00 08 */ lwz r2, 8(r2) /* 801D7320 001D2F80 4C 00 00 64 */ rfi lbl_801D7324: /* 801D7324 001D2F84 3C 40 80 49 */ lis r2, lbl_804907F0@h /* 801D7328 001D2F88 60 42 07 F0 */ ori r2, r2, lbl_804907F0@l /* 801D732C 001D2F8C A0 62 00 00 */ lhz r3, 0(r2) /* 801D7330 001D2F90 3C 40 80 42 */ lis r2, lbl_8042323C@h /* 801D7334 001D2F94 60 42 32 3C */ ori r2, r2, lbl_8042323C@l /* 801D7338 001D2F98 88 42 00 0C */ lbz r2, 0xc(r2) /* 801D733C 001D2F9C 2C 02 00 00 */ cmpwi r2, 0 /* 801D7340 001D2FA0 40 82 00 B0 */ bne TRKExceptionHandler /* 801D7344 001D2FA4 3C 40 80 49 */ lis r2, lbl_80490898@h /* 801D7348 001D2FA8 60 42 08 98 */ ori r2, r2, lbl_80490898@l /* 801D734C 001D2FAC 90 02 00 00 */ stw r0, 0(r2) /* 801D7350 001D2FB0 90 22 00 04 */ stw r1, 4(r2) /* 801D7354 001D2FB4 7C 11 42 A6 */ mfspr r0, 0x111 /* 801D7358 001D2FB8 90 02 00 08 */ stw r0, 8(r2) /* 801D735C 001D2FBC B0 62 02 F8 */ sth r3, 0x2f8(r2) /* 801D7360 001D2FC0 B0 62 02 FA */ sth r3, 0x2fa(r2) /* 801D7364 001D2FC4 7C 12 42 A6 */ mfspr r0, 0x112 /* 801D7368 001D2FC8 90 02 00 0C */ stw r0, 0xc(r2) /* 801D736C 001D2FCC BC 82 00 10 */ stmw r4, 0x10(r2) /* 801D7370 001D2FD0 7F 7A 02 A6 */ mfspr r27, 0x1a /* 801D7374 001D2FD4 7F 88 02 A6 */ mflr r28 /* 801D7378 001D2FD8 7F B3 42 A6 */ mfspr r29, 0x113 /* 801D737C 001D2FDC 7F C9 02 A6 */ mfctr r30 /* 801D7380 001D2FE0 7F E1 02 A6 */ mfxer r31 /* 801D7384 001D2FE4 BF 62 00 80 */ stmw r27, 0x80(r2) /* 801D7388 001D2FE8 48 00 18 C9 */ bl TRKSaveExtended1Block /* 801D738C 001D2FEC 3C 40 80 42 */ lis r2, lbl_8042323C@h /* 801D7390 001D2FF0 60 42 32 3C */ ori r2, r2, lbl_8042323C@l /* 801D7394 001D2FF4 38 60 00 01 */ li r3, 1 /* 801D7398 001D2FF8 98 62 00 0C */ stb r3, 0xc(r2) /* 801D739C 001D2FFC 3C 40 80 49 */ lis r2, lbl_804907F4@h /* 801D73A0 001D3000 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l /* 801D73A4 001D3004 80 02 00 8C */ lwz r0, 0x8c(r2) /* 801D73A8 001D3008 7C 00 04 AC */ sync 0 /* 801D73AC 001D300C 7C 00 01 24 */ mtmsr r0 /* 801D73B0 001D3010 7C 00 04 AC */ sync 0 /* 801D73B4 001D3014 80 02 00 80 */ lwz r0, 0x80(r2) /* 801D73B8 001D3018 7C 08 03 A6 */ mtlr r0 /* 801D73BC 001D301C 80 02 00 84 */ lwz r0, 0x84(r2) /* 801D73C0 001D3020 7C 09 03 A6 */ mtctr r0 /* 801D73C4 001D3024 80 02 00 88 */ lwz r0, 0x88(r2) /* 801D73C8 001D3028 7C 01 03 A6 */ mtxer r0 /* 801D73CC 001D302C 80 02 00 94 */ lwz r0, 0x94(r2) /* 801D73D0 001D3030 7C 12 03 A6 */ mtdsisr r0 /* 801D73D4 001D3034 80 02 00 90 */ lwz r0, 0x90(r2) /* 801D73D8 001D3038 7C 13 03 A6 */ mtdar r0 /* 801D73DC 001D303C B8 62 00 0C */ lmw r3, 0xc(r2) /* 801D73E0 001D3040 80 02 00 00 */ lwz r0, 0(r2) /* 801D73E4 001D3044 80 22 00 04 */ lwz r1, 4(r2) /* 801D73E8 001D3048 80 42 00 08 */ lwz r2, 8(r2) /* 801D73EC 001D304C 48 00 07 AC */ b TRKPostInterruptEvent .global TRKExceptionHandler TRKExceptionHandler: /* 801D73F0 001D3050 3C 40 80 42 */ lis r2, lbl_8042323C@h /* 801D73F4 001D3054 60 42 32 3C */ ori r2, r2, lbl_8042323C@l /* 801D73F8 001D3058 B0 62 00 08 */ sth r3, 8(r2) /* 801D73FC 001D305C 7C 7A 02 A6 */ mfspr r3, 0x1a /* 801D7400 001D3060 90 62 00 00 */ stw r3, 0(r2) /* 801D7404 001D3064 A0 62 00 08 */ lhz r3, 8(r2) /* 801D7408 001D3068 2C 03 02 00 */ cmpwi r3, 0x200 /* 801D740C 001D306C 41 82 00 50 */ beq lbl_801D745C /* 801D7410 001D3070 2C 03 03 00 */ cmpwi r3, 0x300 /* 801D7414 001D3074 41 82 00 48 */ beq lbl_801D745C /* 801D7418 001D3078 2C 03 04 00 */ cmpwi r3, 0x400 /* 801D741C 001D307C 41 82 00 40 */ beq lbl_801D745C /* 801D7420 001D3080 2C 03 06 00 */ cmpwi r3, 0x600 /* 801D7424 001D3084 41 82 00 38 */ beq lbl_801D745C /* 801D7428 001D3088 2C 03 07 00 */ cmpwi r3, 0x700 /* 801D742C 001D308C 41 82 00 30 */ beq lbl_801D745C /* 801D7430 001D3090 2C 03 08 00 */ cmpwi r3, 0x800 /* 801D7434 001D3094 41 82 00 28 */ beq lbl_801D745C /* 801D7438 001D3098 2C 03 10 00 */ cmpwi r3, 0x1000 /* 801D743C 001D309C 41 82 00 20 */ beq lbl_801D745C /* 801D7440 001D30A0 2C 03 11 00 */ cmpwi r3, 0x1100 /* 801D7444 001D30A4 41 82 00 18 */ beq lbl_801D745C /* 801D7448 001D30A8 2C 03 12 00 */ cmpwi r3, 0x1200 /* 801D744C 001D30AC 41 82 00 10 */ beq lbl_801D745C /* 801D7450 001D30B0 2C 03 13 00 */ cmpwi r3, 0x1300 /* 801D7454 001D30B4 41 82 00 08 */ beq lbl_801D745C /* 801D7458 001D30B8 48 00 00 10 */ b lbl_801D7468 lbl_801D745C: /* 801D745C 001D30BC 7C 7A 02 A6 */ mfspr r3, 0x1a /* 801D7460 001D30C0 38 63 00 04 */ addi r3, r3, 4 /* 801D7464 001D30C4 7C 7A 03 A6 */ mtspr 0x1a, r3 lbl_801D7468: /* 801D7468 001D30C8 3C 40 80 42 */ lis r2, lbl_8042323C@h /* 801D746C 001D30CC 60 42 32 3C */ ori r2, r2, lbl_8042323C@l /* 801D7470 001D30D0 38 60 00 01 */ li r3, 1 /* 801D7474 001D30D4 98 62 00 0D */ stb r3, 0xd(r2) /* 801D7478 001D30D8 7C 73 42 A6 */ mfspr r3, 0x113 /* 801D747C 001D30DC 7C 6F F1 20 */ mtcrf 0xff, r3 /* 801D7480 001D30E0 7C 51 42 A6 */ mfspr r2, 0x111 /* 801D7484 001D30E4 7C 72 42 A6 */ mfspr r3, 0x112 /* 801D7488 001D30E8 4C 00 00 64 */ rfi .global TRKSwapAndGo TRKSwapAndGo: /* 801D748C 001D30EC 3C 60 80 49 */ lis r3, lbl_804907F4@h /* 801D7490 001D30F0 60 63 07 F4 */ ori r3, r3, lbl_804907F4@l /* 801D7494 001D30F4 BC 03 00 00 */ stmw r0, 0(r3) /* 801D7498 001D30F8 7C 00 00 A6 */ mfmsr r0 /* 801D749C 001D30FC 90 03 00 8C */ stw r0, 0x8c(r3) /* 801D74A0 001D3100 7C 08 02 A6 */ mflr r0 /* 801D74A4 001D3104 90 03 00 80 */ stw r0, 0x80(r3) /* 801D74A8 001D3108 7C 09 02 A6 */ mfctr r0 /* 801D74AC 001D310C 90 03 00 84 */ stw r0, 0x84(r3) /* 801D74B0 001D3110 7C 01 02 A6 */ mfxer r0 /* 801D74B4 001D3114 90 03 00 88 */ stw r0, 0x88(r3) /* 801D74B8 001D3118 7C 12 02 A6 */ mfdsisr r0 /* 801D74BC 001D311C 90 03 00 94 */ stw r0, 0x94(r3) /* 801D74C0 001D3120 7C 13 02 A6 */ mfdar r0 /* 801D74C4 001D3124 90 03 00 90 */ stw r0, 0x90(r3) /* 801D74C8 001D3128 38 20 80 02 */ li r1, -32766 /* 801D74CC 001D312C 7C 21 08 F8 */ nor r1, r1, r1 /* 801D74D0 001D3130 7C 60 00 A6 */ mfmsr r3 /* 801D74D4 001D3134 7C 63 08 38 */ and r3, r3, r1 /* 801D74D8 001D3138 7C 60 01 24 */ mtmsr r3 /* 801D74DC 001D313C 3C 40 80 49 */ lis r2, lbl_804907F4@h /* 801D74E0 001D3140 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l /* 801D74E4 001D3144 80 42 00 A0 */ lwz r2, 0xa0(r2) /* 801D74E8 001D3148 88 42 00 00 */ lbz r2, 0(r2) /* 801D74EC 001D314C 2C 02 00 00 */ cmpwi r2, 0 /* 801D74F0 001D3150 41 82 00 18 */ beq lbl_801D7508 /* 801D74F4 001D3154 3C 40 80 49 */ lis r2, lbl_804907F4@h /* 801D74F8 001D3158 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l /* 801D74FC 001D315C 38 60 00 01 */ li r3, 1 /* 801D7500 001D3160 98 62 00 9C */ stb r3, 0x9c(r2) /* 801D7504 001D3164 48 00 00 4C */ b TRKInterruptHandlerEnableInterrupts lbl_801D7508: /* 801D7508 001D3168 3C 40 80 42 */ lis r2, lbl_8042323C@h /* 801D750C 001D316C 60 42 32 3C */ ori r2, r2, lbl_8042323C@l /* 801D7510 001D3170 38 60 00 00 */ li r3, 0 /* 801D7514 001D3174 98 62 00 0C */ stb r3, 0xc(r2) /* 801D7518 001D3178 48 00 18 F1 */ bl TRKRestoreExtended1Block /* 801D751C 001D317C 3C 40 80 49 */ lis r2, lbl_80490898@h /* 801D7520 001D3180 60 42 08 98 */ ori r2, r2, lbl_80490898@l /* 801D7524 001D3184 BB 62 00 80 */ lmw r27, 0x80(r2) /* 801D7528 001D3188 7F 7A 03 A6 */ mtspr 0x1a, r27 /* 801D752C 001D318C 7F 88 03 A6 */ mtlr r28 /* 801D7530 001D3190 7F AF F1 20 */ mtcrf 0xff, r29 /* 801D7534 001D3194 7F C9 03 A6 */ mtctr r30 /* 801D7538 001D3198 7F E1 03 A6 */ mtxer r31 /* 801D753C 001D319C B8 62 00 0C */ lmw r3, 0xc(r2) /* 801D7540 001D31A0 80 02 00 00 */ lwz r0, 0(r2) /* 801D7544 001D31A4 80 22 00 04 */ lwz r1, 4(r2) /* 801D7548 001D31A8 80 42 00 08 */ lwz r2, 8(r2) /* 801D754C 001D31AC 4C 00 00 64 */ rfi .global TRKInterruptHandlerEnableInterrupts TRKInterruptHandlerEnableInterrupts: /* 801D7550 001D31B0 3C 40 80 49 */ lis r2, lbl_804907F4@h /* 801D7554 001D31B4 60 42 07 F4 */ ori r2, r2, lbl_804907F4@l /* 801D7558 001D31B8 80 02 00 8C */ lwz r0, 0x8c(r2) /* 801D755C 001D31BC 7C 00 04 AC */ sync 0 /* 801D7560 001D31C0 7C 00 01 24 */ mtmsr r0 /* 801D7564 001D31C4 7C 00 04 AC */ sync 0 /* 801D7568 001D31C8 80 02 00 80 */ lwz r0, 0x80(r2) /* 801D756C 001D31CC 7C 08 03 A6 */ mtlr r0 /* 801D7570 001D31D0 80 02 00 84 */ lwz r0, 0x84(r2) /* 801D7574 001D31D4 7C 09 03 A6 */ mtctr r0 /* 801D7578 001D31D8 80 02 00 88 */ lwz r0, 0x88(r2) /* 801D757C 001D31DC 7C 01 03 A6 */ mtxer r0 /* 801D7580 001D31E0 80 02 00 94 */ lwz r0, 0x94(r2) /* 801D7584 001D31E4 7C 12 03 A6 */ mtdsisr r0 /* 801D7588 001D31E8 80 02 00 90 */ lwz r0, 0x90(r2) /* 801D758C 001D31EC 7C 13 03 A6 */ mtdar r0 /* 801D7590 001D31F0 B8 62 00 0C */ lmw r3, 0xc(r2) /* 801D7594 001D31F4 80 02 00 00 */ lwz r0, 0(r2) /* 801D7598 001D31F8 80 22 00 04 */ lwz r1, 4(r2) /* 801D759C 001D31FC 80 42 00 08 */ lwz r2, 8(r2) /* 801D75A0 001D3200 48 00 05 F8 */ b TRKPostInterruptEvent .global ReadFPSCR ReadFPSCR: /* 801D75A4 001D3204 94 21 FF C0 */ stwu r1, -0x40(r1) /* 801D75A8 001D3208 DB E1 00 10 */ stfd f31, 0x10(r1) /* 801D75AC 001D320C F3 E1 00 20 */ psq_st f31, 32(r1), 0, qr0 /* 801D75B0 001D3210 FF E0 04 8E */ mffs f31 /* 801D75B4 001D3214 DB E3 00 00 */ stfd f31, 0(r3) /* 801D75B8 001D3218 E3 E1 00 20 */ psq_l f31, 32(r1), 0, qr0 /* 801D75BC 001D321C CB E1 00 10 */ lfd f31, 0x10(r1) /* 801D75C0 001D3220 38 21 00 40 */ addi r1, r1, 0x40 /* 801D75C4 001D3224 4E 80 00 20 */ blr .global WriteFPSCR WriteFPSCR: /* 801D75C8 001D3228 94 21 FF C0 */ stwu r1, -0x40(r1) /* 801D75CC 001D322C DB E1 00 10 */ stfd f31, 0x10(r1) /* 801D75D0 001D3230 F3 E1 00 20 */ psq_st f31, 32(r1), 0, qr0 /* 801D75D4 001D3234 CB E3 00 00 */ lfd f31, 0(r3) /* 801D75D8 001D3238 FD FE FD 8E */ mtfsf 0xff, f31 /* 801D75DC 001D323C E3 E1 00 20 */ psq_l f31, 32(r1), 0, qr0 /* 801D75E0 001D3240 CB E1 00 10 */ lfd f31, 0x10(r1) /* 801D75E4 001D3244 38 21 00 40 */ addi r1, r1, 0x40 /* 801D75E8 001D3248 4E 80 00 20 */ blr .global TRKTargetSetInputPendingPtr TRKTargetSetInputPendingPtr: /* 801D75EC 001D324C 3C 80 80 49 */ lis r4, lbl_804907F4@ha /* 801D75F0 001D3250 38 84 07 F4 */ addi r4, r4, lbl_804907F4@l /* 801D75F4 001D3254 90 64 00 A0 */ stw r3, 0xa0(r4) /* 801D75F8 001D3258 4E 80 00 20 */ blr .global TRKTargetStop TRKTargetStop: /* 801D75FC 001D325C 3C 60 80 49 */ lis r3, lbl_804907F4@ha /* 801D7600 001D3260 38 00 00 01 */ li r0, 1 /* 801D7604 001D3264 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l /* 801D7608 001D3268 38 60 00 00 */ li r3, 0 /* 801D760C 001D326C 90 04 00 98 */ stw r0, 0x98(r4) /* 801D7610 001D3270 4E 80 00 20 */ blr .global TRKTargetSetStopped TRKTargetSetStopped: /* 801D7614 001D3274 3C 80 80 49 */ lis r4, lbl_804907F4@ha /* 801D7618 001D3278 38 84 07 F4 */ addi r4, r4, lbl_804907F4@l /* 801D761C 001D327C 90 64 00 98 */ stw r3, 0x98(r4) /* 801D7620 001D3280 4E 80 00 20 */ blr .global TRKTargetStopped TRKTargetStopped: /* 801D7624 001D3284 3C 60 80 49 */ lis r3, lbl_804907F4@ha /* 801D7628 001D3288 38 63 07 F4 */ addi r3, r3, lbl_804907F4@l /* 801D762C 001D328C 80 63 00 98 */ lwz r3, 0x98(r3) /* 801D7630 001D3290 4E 80 00 20 */ blr .global TRKTargetSupportRequest TRKTargetSupportRequest: /* 801D7634 001D3294 94 21 FF C0 */ stwu r1, -0x40(r1) /* 801D7638 001D3298 7C 08 02 A6 */ mflr r0 /* 801D763C 001D329C 3C 60 80 49 */ lis r3, lbl_80490898@ha /* 801D7640 001D32A0 90 01 00 44 */ stw r0, 0x44(r1) /* 801D7644 001D32A4 BF 61 00 2C */ stmw r27, 0x2c(r1) /* 801D7648 001D32A8 3B E3 08 98 */ addi r31, r3, lbl_80490898@l /* 801D764C 001D32AC 83 7F 00 0C */ lwz r27, 0xc(r31) /* 801D7650 001D32B0 2C 1B 00 D1 */ cmpwi r27, 0xd1 /* 801D7654 001D32B4 41 82 00 40 */ beq lbl_801D7694 /* 801D7658 001D32B8 2C 1B 00 D0 */ cmpwi r27, 0xd0 /* 801D765C 001D32BC 41 82 00 38 */ beq lbl_801D7694 /* 801D7660 001D32C0 2C 1B 00 D2 */ cmpwi r27, 0xd2 /* 801D7664 001D32C4 41 82 00 30 */ beq lbl_801D7694 /* 801D7668 001D32C8 2C 1B 00 D3 */ cmpwi r27, 0xd3 /* 801D766C 001D32CC 41 82 00 28 */ beq lbl_801D7694 /* 801D7670 001D32D0 2C 1B 00 D4 */ cmpwi r27, 0xd4 /* 801D7674 001D32D4 41 82 00 20 */ beq lbl_801D7694 /* 801D7678 001D32D8 38 61 00 10 */ addi r3, r1, 0x10 /* 801D767C 001D32DC 38 80 00 04 */ li r4, 4 /* 801D7680 001D32E0 4B FF D2 D5 */ bl TRKConstructEvent /* 801D7684 001D32E4 38 61 00 10 */ addi r3, r1, 0x10 /* 801D7688 001D32E8 4B FF D2 E5 */ bl TRKPostEvent /* 801D768C 001D32EC 38 60 00 00 */ li r3, 0 /* 801D7690 001D32F0 48 00 01 90 */ b lbl_801D7820 lbl_801D7694: /* 801D7694 001D32F4 2C 1B 00 D2 */ cmpwi r27, 0xd2 /* 801D7698 001D32F8 40 82 00 50 */ bne lbl_801D76E8 /* 801D769C 001D32FC 3C 60 80 49 */ lis r3, lbl_80490898@ha /* 801D76A0 001D3300 38 C1 00 0C */ addi r6, r1, 0xc /* 801D76A4 001D3304 38 83 08 98 */ addi r4, r3, lbl_80490898@l /* 801D76A8 001D3308 80 04 00 14 */ lwz r0, 0x14(r4) /* 801D76AC 001D330C 80 64 00 10 */ lwz r3, 0x10(r4) /* 801D76B0 001D3310 80 A4 00 18 */ lwz r5, 0x18(r4) /* 801D76B4 001D3314 54 04 06 3E */ clrlwi r4, r0, 0x18 /* 801D76B8 001D3318 4B FF F4 E1 */ bl HandleOpenFileSupportRequest /* 801D76BC 001D331C 80 01 00 0C */ lwz r0, 0xc(r1) /* 801D76C0 001D3320 7C 7E 1B 78 */ mr r30, r3 /* 801D76C4 001D3324 2C 00 00 00 */ cmpwi r0, 0 /* 801D76C8 001D3328 40 82 00 14 */ bne lbl_801D76DC /* 801D76CC 001D332C 2C 1E 00 00 */ cmpwi r30, 0 /* 801D76D0 001D3330 41 82 00 0C */ beq lbl_801D76DC /* 801D76D4 001D3334 38 00 00 01 */ li r0, 1 /* 801D76D8 001D3338 90 01 00 0C */ stw r0, 0xc(r1) lbl_801D76DC: /* 801D76DC 001D333C 80 01 00 0C */ lwz r0, 0xc(r1) /* 801D76E0 001D3340 90 1F 00 0C */ stw r0, 0xc(r31) /* 801D76E4 001D3344 48 00 01 24 */ b lbl_801D7808 lbl_801D76E8: /* 801D76E8 001D3348 2C 1B 00 D3 */ cmpwi r27, 0xd3 /* 801D76EC 001D334C 40 82 00 44 */ bne lbl_801D7730 /* 801D76F0 001D3350 3C 60 80 49 */ lis r3, lbl_80490898@ha /* 801D76F4 001D3354 38 81 00 0C */ addi r4, r1, 0xc /* 801D76F8 001D3358 38 63 08 98 */ addi r3, r3, lbl_80490898@l /* 801D76FC 001D335C 80 63 00 10 */ lwz r3, 0x10(r3) /* 801D7700 001D3360 4B FF F3 B1 */ bl HandleCloseFileSupportRequest /* 801D7704 001D3364 80 01 00 0C */ lwz r0, 0xc(r1) /* 801D7708 001D3368 7C 7E 1B 78 */ mr r30, r3 /* 801D770C 001D336C 2C 00 00 00 */ cmpwi r0, 0 /* 801D7710 001D3370 40 82 00 14 */ bne lbl_801D7724 /* 801D7714 001D3374 2C 1E 00 00 */ cmpwi r30, 0 /* 801D7718 001D3378 41 82 00 0C */ beq lbl_801D7724 /* 801D771C 001D337C 38 00 00 01 */ li r0, 1 /* 801D7720 001D3380 90 01 00 0C */ stw r0, 0xc(r1) lbl_801D7724: /* 801D7724 001D3384 80 01 00 0C */ lwz r0, 0xc(r1) /* 801D7728 001D3388 90 1F 00 0C */ stw r0, 0xc(r31) /* 801D772C 001D338C 48 00 00 DC */ b lbl_801D7808 lbl_801D7730: /* 801D7730 001D3390 2C 1B 00 D4 */ cmpwi r27, 0xd4 /* 801D7734 001D3394 40 82 00 68 */ bne lbl_801D779C /* 801D7738 001D3398 3C 60 80 49 */ lis r3, lbl_80490898@ha /* 801D773C 001D339C 38 81 00 08 */ addi r4, r1, 8 /* 801D7740 001D33A0 3B A3 08 98 */ addi r29, r3, lbl_80490898@l /* 801D7744 001D33A4 38 C1 00 0C */ addi r6, r1, 0xc /* 801D7748 001D33A8 80 7D 00 14 */ lwz r3, 0x14(r29) /* 801D774C 001D33AC 80 1D 00 18 */ lwz r0, 0x18(r29) /* 801D7750 001D33B0 80 E3 00 00 */ lwz r7, 0(r3) /* 801D7754 001D33B4 80 7D 00 10 */ lwz r3, 0x10(r29) /* 801D7758 001D33B8 54 05 06 3E */ clrlwi r5, r0, 0x18 /* 801D775C 001D33BC 90 E1 00 08 */ stw r7, 8(r1) /* 801D7760 001D33C0 4B FF F2 41 */ bl HandlePositionFileSupportRequest /* 801D7764 001D33C4 80 01 00 0C */ lwz r0, 0xc(r1) /* 801D7768 001D33C8 7C 7E 1B 78 */ mr r30, r3 /* 801D776C 001D33CC 2C 00 00 00 */ cmpwi r0, 0 /* 801D7770 001D33D0 40 82 00 14 */ bne lbl_801D7784 /* 801D7774 001D33D4 2C 1E 00 00 */ cmpwi r30, 0 /* 801D7778 001D33D8 41 82 00 0C */ beq lbl_801D7784 /* 801D777C 001D33DC 38 00 00 01 */ li r0, 1 /* 801D7780 001D33E0 90 01 00 0C */ stw r0, 0xc(r1) lbl_801D7784: /* 801D7784 001D33E4 80 61 00 0C */ lwz r3, 0xc(r1) /* 801D7788 001D33E8 80 01 00 08 */ lwz r0, 8(r1) /* 801D778C 001D33EC 90 7F 00 0C */ stw r3, 0xc(r31) /* 801D7790 001D33F0 80 7D 00 14 */ lwz r3, 0x14(r29) /* 801D7794 001D33F4 90 03 00 00 */ stw r0, 0(r3) /* 801D7798 001D33F8 48 00 00 70 */ b lbl_801D7808 lbl_801D779C: /* 801D779C 001D33FC 3C 60 80 49 */ lis r3, lbl_80490898@ha /* 801D77A0 001D3400 20 1B 00 D1 */ subfic r0, r27, 0xd1 /* 801D77A4 001D3404 3B A3 08 98 */ addi r29, r3, lbl_80490898@l /* 801D77A8 001D3408 38 C1 00 0C */ addi r6, r1, 0xc /* 801D77AC 001D340C 83 9D 00 14 */ lwz r28, 0x14(r29) /* 801D77B0 001D3410 7C 00 00 34 */ cntlzw r0, r0 /* 801D77B4 001D3414 80 7D 00 10 */ lwz r3, 0x10(r29) /* 801D77B8 001D3418 54 08 D9 7E */ srwi r8, r0, 5 /* 801D77BC 001D341C 80 9D 00 18 */ lwz r4, 0x18(r29) /* 801D77C0 001D3420 7F 85 E3 78 */ mr r5, r28 /* 801D77C4 001D3424 38 E0 00 01 */ li r7, 1 /* 801D77C8 001D3428 4B FF F6 6D */ bl TRKSuppAccessFile /* 801D77CC 001D342C 80 01 00 0C */ lwz r0, 0xc(r1) /* 801D77D0 001D3430 7C 7E 1B 78 */ mr r30, r3 /* 801D77D4 001D3434 2C 00 00 00 */ cmpwi r0, 0 /* 801D77D8 001D3438 40 82 00 14 */ bne lbl_801D77EC /* 801D77DC 001D343C 2C 1E 00 00 */ cmpwi r30, 0 /* 801D77E0 001D3440 41 82 00 0C */ beq lbl_801D77EC /* 801D77E4 001D3444 38 00 00 01 */ li r0, 1 /* 801D77E8 001D3448 90 01 00 0C */ stw r0, 0xc(r1) lbl_801D77EC: /* 801D77EC 001D344C 80 01 00 0C */ lwz r0, 0xc(r1) /* 801D77F0 001D3450 2C 1B 00 D1 */ cmpwi r27, 0xd1 /* 801D77F4 001D3454 90 1F 00 0C */ stw r0, 0xc(r31) /* 801D77F8 001D3458 40 82 00 10 */ bne lbl_801D7808 /* 801D77FC 001D345C 80 7D 00 18 */ lwz r3, 0x18(r29) /* 801D7800 001D3460 80 9C 00 00 */ lwz r4, 0(r28) /* 801D7804 001D3464 4B FF F9 01 */ bl TRK_flush_cache lbl_801D7808: /* 801D7808 001D3468 3C 80 80 49 */ lis r4, lbl_80490898@ha /* 801D780C 001D346C 7F C3 F3 78 */ mr r3, r30 /* 801D7810 001D3470 38 A4 08 98 */ addi r5, r4, lbl_80490898@l /* 801D7814 001D3474 80 85 00 80 */ lwz r4, 0x80(r5) /* 801D7818 001D3478 38 04 00 04 */ addi r0, r4, 4 /* 801D781C 001D347C 90 05 00 80 */ stw r0, 0x80(r5) lbl_801D7820: /* 801D7820 001D3480 BB 61 00 2C */ lmw r27, 0x2c(r1) /* 801D7824 001D3484 80 01 00 44 */ lwz r0, 0x44(r1) /* 801D7828 001D3488 7C 08 03 A6 */ mtlr r0 /* 801D782C 001D348C 38 21 00 40 */ addi r1, r1, 0x40 /* 801D7830 001D3490 4E 80 00 20 */ blr .global TRKTargetGetPC TRKTargetGetPC: /* 801D7834 001D3494 3C 60 80 49 */ lis r3, lbl_80490898@ha /* 801D7838 001D3498 38 63 08 98 */ addi r3, r3, lbl_80490898@l /* 801D783C 001D349C 80 63 00 80 */ lwz r3, 0x80(r3) /* 801D7840 001D34A0 4E 80 00 20 */ blr .global TRKTargetStepOutOfRange TRKTargetStepOutOfRange: /* 801D7844 001D34A4 2C 05 00 00 */ cmpwi r5, 0 /* 801D7848 001D34A8 41 82 00 0C */ beq lbl_801D7854 /* 801D784C 001D34AC 38 60 07 03 */ li r3, 0x703 /* 801D7850 001D34B0 4E 80 00 20 */ blr lbl_801D7854: /* 801D7854 001D34B4 3C A0 80 49 */ lis r5, lbl_80490898@ha /* 801D7858 001D34B8 38 E0 00 01 */ li r7, 1 /* 801D785C 001D34BC 38 A5 08 98 */ addi r5, r5, lbl_80490898@l /* 801D7860 001D34C0 3C C0 80 42 */ lis r6, lbl_8042324C@ha /* 801D7864 001D34C4 80 05 01 F8 */ lwz r0, 0x1f8(r5) /* 801D7868 001D34C8 38 C6 32 4C */ addi r6, r6, lbl_8042324C@l /* 801D786C 001D34CC 2C 07 00 00 */ cmpwi r7, 0 /* 801D7870 001D34D0 90 E6 00 04 */ stw r7, 4(r6) /* 801D7874 001D34D4 60 00 04 00 */ ori r0, r0, 0x400 /* 801D7878 001D34D8 90 66 00 0C */ stw r3, 0xc(r6) /* 801D787C 001D34DC 90 86 00 10 */ stw r4, 0x10(r6) /* 801D7880 001D34E0 90 E6 00 00 */ stw r7, 0(r6) /* 801D7884 001D34E4 90 05 01 F8 */ stw r0, 0x1f8(r5) /* 801D7888 001D34E8 41 82 00 0C */ beq lbl_801D7894 /* 801D788C 001D34EC 2C 07 00 10 */ cmpwi r7, 0x10 /* 801D7890 001D34F0 40 82 00 18 */ bne lbl_801D78A8 lbl_801D7894: /* 801D7894 001D34F4 3C 60 80 42 */ lis r3, lbl_8042324C@ha /* 801D7898 001D34F8 38 83 32 4C */ addi r4, r3, lbl_8042324C@l /* 801D789C 001D34FC 80 64 00 08 */ lwz r3, 8(r4) /* 801D78A0 001D3500 38 03 FF FF */ addi r0, r3, -1 /* 801D78A4 001D3504 90 04 00 08 */ stw r0, 8(r4) lbl_801D78A8: /* 801D78A8 001D3508 3C 60 80 49 */ lis r3, lbl_804907F4@ha /* 801D78AC 001D350C 38 00 00 00 */ li r0, 0 /* 801D78B0 001D3510 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l /* 801D78B4 001D3514 38 60 00 00 */ li r3, 0 /* 801D78B8 001D3518 90 04 00 98 */ stw r0, 0x98(r4) /* 801D78BC 001D351C 4E 80 00 20 */ blr .global TRKTargetSingleStep TRKTargetSingleStep: /* 801D78C0 001D3520 2C 04 00 00 */ cmpwi r4, 0 /* 801D78C4 001D3524 41 82 00 0C */ beq lbl_801D78D0 /* 801D78C8 001D3528 38 60 07 03 */ li r3, 0x703 /* 801D78CC 001D352C 4E 80 00 20 */ blr lbl_801D78D0: /* 801D78D0 001D3530 3C 80 80 49 */ lis r4, lbl_80490898@ha /* 801D78D4 001D3534 3C A0 80 42 */ lis r5, lbl_8042324C@ha /* 801D78D8 001D3538 38 84 08 98 */ addi r4, r4, lbl_80490898@l /* 801D78DC 001D353C 38 E0 00 00 */ li r7, 0 /* 801D78E0 001D3540 80 04 01 F8 */ lwz r0, 0x1f8(r4) /* 801D78E4 001D3544 38 C5 32 4C */ addi r6, r5, lbl_8042324C@l /* 801D78E8 001D3548 38 A0 00 01 */ li r5, 1 /* 801D78EC 001D354C 90 E6 00 04 */ stw r7, 4(r6) /* 801D78F0 001D3550 60 00 04 00 */ ori r0, r0, 0x400 /* 801D78F4 001D3554 90 66 00 08 */ stw r3, 8(r6) /* 801D78F8 001D3558 90 A6 00 00 */ stw r5, 0(r6) /* 801D78FC 001D355C 90 04 01 F8 */ stw r0, 0x1f8(r4) /* 801D7900 001D3560 48 00 00 08 */ b lbl_801D7908 /* 801D7904 001D3564 40 82 00 10 */ bne lbl_801D7914 lbl_801D7908: /* 801D7908 001D3568 80 66 00 08 */ lwz r3, 8(r6) /* 801D790C 001D356C 38 03 FF FF */ addi r0, r3, -1 /* 801D7910 001D3570 90 06 00 08 */ stw r0, 8(r6) lbl_801D7914: /* 801D7914 001D3574 3C 60 80 49 */ lis r3, lbl_804907F4@ha /* 801D7918 001D3578 38 00 00 00 */ li r0, 0 /* 801D791C 001D357C 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l /* 801D7920 001D3580 38 60 00 00 */ li r3, 0 /* 801D7924 001D3584 90 04 00 98 */ stw r0, 0x98(r4) /* 801D7928 001D3588 4E 80 00 20 */ blr .global TRKTargetAddExceptionInfo TRKTargetAddExceptionInfo: /* 801D792C 001D358C 94 21 FF A0 */ stwu r1, -0x60(r1) /* 801D7930 001D3590 7C 08 02 A6 */ mflr r0 /* 801D7934 001D3594 38 80 00 00 */ li r4, 0 /* 801D7938 001D3598 38 A0 00 40 */ li r5, 0x40 /* 801D793C 001D359C 90 01 00 64 */ stw r0, 0x64(r1) /* 801D7940 001D35A0 93 E1 00 5C */ stw r31, 0x5c(r1) /* 801D7944 001D35A4 7C 7F 1B 78 */ mr r31, r3 /* 801D7948 001D35A8 38 61 00 0C */ addi r3, r1, 0xc /* 801D794C 001D35AC 4B E2 C7 E9 */ bl TRK_memset /* 801D7950 001D35B0 3C 60 80 42 */ lis r3, lbl_8042323C@ha /* 801D7954 001D35B4 38 A0 00 40 */ li r5, 0x40 /* 801D7958 001D35B8 80 83 32 3C */ lwz r4, lbl_8042323C@l(r3) /* 801D795C 001D35BC 38 00 00 91 */ li r0, 0x91 /* 801D7960 001D35C0 90 A1 00 0C */ stw r5, 0xc(r1) /* 801D7964 001D35C4 38 61 00 08 */ addi r3, r1, 8 /* 801D7968 001D35C8 98 01 00 10 */ stb r0, 0x10(r1) /* 801D796C 001D35CC 90 81 00 14 */ stw r4, 0x14(r1) /* 801D7970 001D35D0 48 00 0E 7D */ bl TRKTargetReadInstruction /* 801D7974 001D35D4 3C 60 80 42 */ lis r3, lbl_8042323C@ha /* 801D7978 001D35D8 80 A1 00 08 */ lwz r5, 8(r1) /* 801D797C 001D35DC 38 83 32 3C */ addi r4, r3, lbl_8042323C@l /* 801D7980 001D35E0 7F E3 FB 78 */ mr r3, r31 /* 801D7984 001D35E4 A0 04 00 08 */ lhz r0, 8(r4) /* 801D7988 001D35E8 38 81 00 0C */ addi r4, r1, 0xc /* 801D798C 001D35EC 90 A1 00 18 */ stw r5, 0x18(r1) /* 801D7990 001D35F0 38 A0 00 40 */ li r5, 0x40 /* 801D7994 001D35F4 90 01 00 1C */ stw r0, 0x1c(r1) /* 801D7998 001D35F8 4B FF D6 DD */ bl TRKAppendBuffer_ui8 /* 801D799C 001D35FC 80 01 00 64 */ lwz r0, 0x64(r1) /* 801D79A0 001D3600 83 E1 00 5C */ lwz r31, 0x5c(r1) /* 801D79A4 001D3604 7C 08 03 A6 */ mtlr r0 /* 801D79A8 001D3608 38 21 00 60 */ addi r1, r1, 0x60 /* 801D79AC 001D360C 4E 80 00 20 */ blr .global TRKTargetAddStopInfo TRKTargetAddStopInfo: /* 801D79B0 001D3610 94 21 FF A0 */ stwu r1, -0x60(r1) /* 801D79B4 001D3614 7C 08 02 A6 */ mflr r0 /* 801D79B8 001D3618 38 80 00 00 */ li r4, 0 /* 801D79BC 001D361C 38 A0 00 40 */ li r5, 0x40 /* 801D79C0 001D3620 90 01 00 64 */ stw r0, 0x64(r1) /* 801D79C4 001D3624 93 E1 00 5C */ stw r31, 0x5c(r1) /* 801D79C8 001D3628 7C 7F 1B 78 */ mr r31, r3 /* 801D79CC 001D362C 38 61 00 0C */ addi r3, r1, 0xc /* 801D79D0 001D3630 4B E2 C7 65 */ bl TRK_memset /* 801D79D4 001D3634 3C 60 80 49 */ lis r3, lbl_80490898@ha /* 801D79D8 001D3638 38 A0 00 40 */ li r5, 0x40 /* 801D79DC 001D363C 38 63 08 98 */ addi r3, r3, lbl_80490898@l /* 801D79E0 001D3640 38 00 00 90 */ li r0, 0x90 /* 801D79E4 001D3644 80 83 00 80 */ lwz r4, 0x80(r3) /* 801D79E8 001D3648 38 61 00 08 */ addi r3, r1, 8 /* 801D79EC 001D364C 90 A1 00 0C */ stw r5, 0xc(r1) /* 801D79F0 001D3650 98 01 00 10 */ stb r0, 0x10(r1) /* 801D79F4 001D3654 90 81 00 14 */ stw r4, 0x14(r1) /* 801D79F8 001D3658 48 00 0D F5 */ bl TRKTargetReadInstruction /* 801D79FC 001D365C 3C 60 80 49 */ lis r3, lbl_80490898@ha /* 801D7A00 001D3660 80 A1 00 08 */ lwz r5, 8(r1) /* 801D7A04 001D3664 38 83 08 98 */ addi r4, r3, lbl_80490898@l /* 801D7A08 001D3668 7F E3 FB 78 */ mr r3, r31 /* 801D7A0C 001D366C 80 04 02 F8 */ lwz r0, 0x2f8(r4) /* 801D7A10 001D3670 38 81 00 0C */ addi r4, r1, 0xc /* 801D7A14 001D3674 90 A1 00 18 */ stw r5, 0x18(r1) /* 801D7A18 001D3678 38 A0 00 40 */ li r5, 0x40 /* 801D7A1C 001D367C 54 00 04 3E */ clrlwi r0, r0, 0x10 /* 801D7A20 001D3680 90 01 00 1C */ stw r0, 0x1c(r1) /* 801D7A24 001D3684 4B FF D6 51 */ bl TRKAppendBuffer_ui8 /* 801D7A28 001D3688 80 01 00 64 */ lwz r0, 0x64(r1) /* 801D7A2C 001D368C 83 E1 00 5C */ lwz r31, 0x5c(r1) /* 801D7A30 001D3690 7C 08 03 A6 */ mtlr r0 /* 801D7A34 001D3694 38 21 00 60 */ addi r1, r1, 0x60 /* 801D7A38 001D3698 4E 80 00 20 */ blr .global TRKTargetInterrupt TRKTargetInterrupt: /* 801D7A3C 001D369C 94 21 FF F0 */ stwu r1, -0x10(r1) /* 801D7A40 001D36A0 7C 08 02 A6 */ mflr r0 /* 801D7A44 001D36A4 90 01 00 14 */ stw r0, 0x14(r1) /* 801D7A48 001D36A8 80 03 00 00 */ lwz r0, 0(r3) /* 801D7A4C 001D36AC 38 60 00 00 */ li r3, 0 /* 801D7A50 001D36B0 2C 00 00 05 */ cmpwi r0, 5 /* 801D7A54 001D36B4 40 80 01 34 */ bge lbl_801D7B88 /* 801D7A58 001D36B8 2C 00 00 03 */ cmpwi r0, 3 /* 801D7A5C 001D36BC 40 80 00 08 */ bge lbl_801D7A64 /* 801D7A60 001D36C0 48 00 01 28 */ b lbl_801D7B88 lbl_801D7A64: /* 801D7A64 001D36C4 3C 80 80 42 */ lis r4, lbl_8042324C@ha /* 801D7A68 001D36C8 38 A4 32 4C */ addi r5, r4, lbl_8042324C@l /* 801D7A6C 001D36CC 80 05 00 00 */ lwz r0, 0(r5) /* 801D7A70 001D36D0 2C 00 00 00 */ cmpwi r0, 0 /* 801D7A74 001D36D4 41 82 00 EC */ beq lbl_801D7B60 /* 801D7A78 001D36D8 3C 80 80 49 */ lis r4, lbl_80490898@ha /* 801D7A7C 001D36DC 38 E0 00 01 */ li r7, 1 /* 801D7A80 001D36E0 38 C4 08 98 */ addi r6, r4, lbl_80490898@l /* 801D7A84 001D36E4 80 06 01 F8 */ lwz r0, 0x1f8(r6) /* 801D7A88 001D36E8 54 00 05 A8 */ rlwinm r0, r0, 0, 0x16, 0x14 /* 801D7A8C 001D36EC 90 06 01 F8 */ stw r0, 0x1f8(r6) /* 801D7A90 001D36F0 41 82 00 64 */ beq lbl_801D7AF4 /* 801D7A94 001D36F4 80 06 02 F8 */ lwz r0, 0x2f8(r6) /* 801D7A98 001D36F8 54 00 04 3E */ clrlwi r0, r0, 0x10 /* 801D7A9C 001D36FC 28 00 0D 00 */ cmplwi r0, 0xd00 /* 801D7AA0 001D3700 40 82 00 54 */ bne lbl_801D7AF4 /* 801D7AA4 001D3704 80 05 00 04 */ lwz r0, 4(r5) /* 801D7AA8 001D3708 2C 00 00 01 */ cmpwi r0, 1 /* 801D7AAC 001D370C 41 82 00 28 */ beq lbl_801D7AD4 /* 801D7AB0 001D3710 40 80 00 44 */ bge lbl_801D7AF4 /* 801D7AB4 001D3714 2C 00 00 00 */ cmpwi r0, 0 /* 801D7AB8 001D3718 40 80 00 08 */ bge lbl_801D7AC0 /* 801D7ABC 001D371C 48 00 00 38 */ b lbl_801D7AF4 lbl_801D7AC0: /* 801D7AC0 001D3720 80 05 00 08 */ lwz r0, 8(r5) /* 801D7AC4 001D3724 28 00 00 00 */ cmplwi r0, 0 /* 801D7AC8 001D3728 41 82 00 2C */ beq lbl_801D7AF4 /* 801D7ACC 001D372C 38 E0 00 00 */ li r7, 0 /* 801D7AD0 001D3730 48 00 00 24 */ b lbl_801D7AF4 lbl_801D7AD4: /* 801D7AD4 001D3734 80 86 00 80 */ lwz r4, 0x80(r6) /* 801D7AD8 001D3738 80 05 00 0C */ lwz r0, 0xc(r5) /* 801D7ADC 001D373C 7C 04 00 40 */ cmplw r4, r0 /* 801D7AE0 001D3740 41 80 00 14 */ blt lbl_801D7AF4 /* 801D7AE4 001D3744 80 05 00 10 */ lwz r0, 0x10(r5) /* 801D7AE8 001D3748 7C 04 00 40 */ cmplw r4, r0 /* 801D7AEC 001D374C 41 81 00 08 */ bgt lbl_801D7AF4 /* 801D7AF0 001D3750 38 E0 00 00 */ li r7, 0 lbl_801D7AF4: /* 801D7AF4 001D3754 2C 07 00 00 */ cmpwi r7, 0 /* 801D7AF8 001D3758 41 82 00 14 */ beq lbl_801D7B0C /* 801D7AFC 001D375C 3C 80 80 42 */ lis r4, lbl_8042324C@ha /* 801D7B00 001D3760 38 00 00 00 */ li r0, 0 /* 801D7B04 001D3764 90 04 32 4C */ stw r0, lbl_8042324C@l(r4) /* 801D7B08 001D3768 48 00 00 58 */ b lbl_801D7B60 lbl_801D7B0C: /* 801D7B0C 001D376C 3C 80 80 42 */ lis r4, lbl_8042324C@ha /* 801D7B10 001D3770 80 06 01 F8 */ lwz r0, 0x1f8(r6) /* 801D7B14 001D3774 38 84 32 4C */ addi r4, r4, lbl_8042324C@l /* 801D7B18 001D3778 38 A0 00 01 */ li r5, 1 /* 801D7B1C 001D377C 80 E4 00 04 */ lwz r7, 4(r4) /* 801D7B20 001D3780 60 00 04 00 */ ori r0, r0, 0x400 /* 801D7B24 001D3784 90 A4 00 00 */ stw r5, 0(r4) /* 801D7B28 001D3788 2C 07 00 00 */ cmpwi r7, 0 /* 801D7B2C 001D378C 90 06 01 F8 */ stw r0, 0x1f8(r6) /* 801D7B30 001D3790 41 82 00 0C */ beq lbl_801D7B3C /* 801D7B34 001D3794 2C 07 00 10 */ cmpwi r7, 0x10 /* 801D7B38 001D3798 40 82 00 18 */ bne lbl_801D7B50 lbl_801D7B3C: /* 801D7B3C 001D379C 3C 80 80 42 */ lis r4, lbl_8042324C@ha /* 801D7B40 001D37A0 38 A4 32 4C */ addi r5, r4, lbl_8042324C@l /* 801D7B44 001D37A4 80 85 00 08 */ lwz r4, 8(r5) /* 801D7B48 001D37A8 38 04 FF FF */ addi r0, r4, -1 /* 801D7B4C 001D37AC 90 05 00 08 */ stw r0, 8(r5) lbl_801D7B50: /* 801D7B50 001D37B0 3C 80 80 49 */ lis r4, lbl_804907F4@ha /* 801D7B54 001D37B4 38 00 00 00 */ li r0, 0 /* 801D7B58 001D37B8 38 84 07 F4 */ addi r4, r4, lbl_804907F4@l /* 801D7B5C 001D37BC 90 04 00 98 */ stw r0, 0x98(r4) lbl_801D7B60: /* 801D7B60 001D37C0 3C 80 80 42 */ lis r4, lbl_8042324C@ha /* 801D7B64 001D37C4 80 04 32 4C */ lwz r0, lbl_8042324C@l(r4) /* 801D7B68 001D37C8 2C 00 00 00 */ cmpwi r0, 0 /* 801D7B6C 001D37CC 40 82 00 1C */ bne lbl_801D7B88 /* 801D7B70 001D37D0 3C 60 80 49 */ lis r3, lbl_804907F4@ha /* 801D7B74 001D37D4 38 00 00 01 */ li r0, 1 /* 801D7B78 001D37D8 38 83 07 F4 */ addi r4, r3, lbl_804907F4@l /* 801D7B7C 001D37DC 38 60 00 90 */ li r3, 0x90 /* 801D7B80 001D37E0 90 04 00 98 */ stw r0, 0x98(r4) /* 801D7B84 001D37E4 4B FF F4 E9 */ bl TRKDoNotifyStopped lbl_801D7B88: /* 801D7B88 001D37E8 80 01 00 14 */ lwz r0, 0x14(r1) /* 801D7B8C 001D37EC 7C 08 03 A6 */ mtlr r0 /* 801D7B90 001D37F0 38 21 00 10 */ addi r1, r1, 0x10 /* 801D7B94 001D37F4 4E 80 00 20 */ blr .global TRKPostInterruptEvent TRKPostInterruptEvent: /* 801D7B98 001D37F8 94 21 FF E0 */ stwu r1, -0x20(r1) /* 801D7B9C 001D37FC 7C 08 02 A6 */ mflr r0 /* 801D7BA0 001D3800 3C 60 80 49 */ lis r3, lbl_804907F4@ha /* 801D7BA4 001D3804 90 01 00 24 */ stw r0, 0x24(r1) /* 801D7BA8 001D3808 38 63 07 F4 */ addi r3, r3, lbl_804907F4@l /* 801D7BAC 001D380C 80 03 00 9C */ lwz r0, 0x9c(r3) /* 801D7BB0 001D3810 2C 00 00 00 */ cmpwi r0, 0 /* 801D7BB4 001D3814 41 82 00 10 */ beq lbl_801D7BC4 /* 801D7BB8 001D3818 38 00 00 00 */ li r0, 0 /* 801D7BBC 001D381C 90 03 00 9C */ stw r0, 0x9c(r3) /* 801D7BC0 001D3820 48 00 00 74 */ b lbl_801D7C34 lbl_801D7BC4: /* 801D7BC4 001D3824 3C 60 80 49 */ lis r3, lbl_80490898@ha /* 801D7BC8 001D3828 38 63 08 98 */ addi r3, r3, lbl_80490898@l /* 801D7BCC 001D382C 80 03 02 F8 */ lwz r0, 0x2f8(r3) /* 801D7BD0 001D3830 54 00 04 3E */ clrlwi r0, r0, 0x10 /* 801D7BD4 001D3834 2C 00 0D 00 */ cmpwi r0, 0xd00 /* 801D7BD8 001D3838 41 82 00 14 */ beq lbl_801D7BEC /* 801D7BDC 001D383C 40 80 00 44 */ bge lbl_801D7C20 /* 801D7BE0 001D3840 2C 00 07 00 */ cmpwi r0, 0x700 /* 801D7BE4 001D3844 41 82 00 08 */ beq lbl_801D7BEC /* 801D7BE8 001D3848 48 00 00 38 */ b lbl_801D7C20 lbl_801D7BEC: /* 801D7BEC 001D384C 3C 80 80 49 */ lis r4, lbl_80490898@ha /* 801D7BF0 001D3850 38 61 00 08 */ addi r3, r1, 8 /* 801D7BF4 001D3854 38 84 08 98 */ addi r4, r4, lbl_80490898@l /* 801D7BF8 001D3858 80 84 00 80 */ lwz r4, 0x80(r4) /* 801D7BFC 001D385C 48 00 0B F1 */ bl TRKTargetReadInstruction /* 801D7C00 001D3860 80 61 00 08 */ lwz r3, 8(r1) /* 801D7C04 001D3864 3C 03 F0 20 */ addis r0, r3, 0xf020 /* 801D7C08 001D3868 28 00 00 00 */ cmplwi r0, 0 /* 801D7C0C 001D386C 40 82 00 0C */ bne lbl_801D7C18 /* 801D7C10 001D3870 38 80 00 05 */ li r4, 5 /* 801D7C14 001D3874 48 00 00 10 */ b lbl_801D7C24 lbl_801D7C18: /* 801D7C18 001D3878 38 80 00 03 */ li r4, 3 /* 801D7C1C 001D387C 48 00 00 08 */ b lbl_801D7C24 lbl_801D7C20: /* 801D7C20 001D3880 38 80 00 04 */ li r4, 4 lbl_801D7C24: /* 801D7C24 001D3884 38 61 00 0C */ addi r3, r1, 0xc /* 801D7C28 001D3888 4B FF CD 2D */ bl TRKConstructEvent /* 801D7C2C 001D388C 38 61 00 0C */ addi r3, r1, 0xc /* 801D7C30 001D3890 4B FF CD 3D */ bl TRKPostEvent lbl_801D7C34: /* 801D7C34 001D3894 80 01 00 24 */ lwz r0, 0x24(r1) /* 801D7C38 001D3898 7C 08 03 A6 */ mtlr r0 /* 801D7C3C 001D389C 38 21 00 20 */ addi r1, r1, 0x20 /* 801D7C40 001D38A0 4E 80 00 20 */ blr .global TRKTargetAccessExtended2 TRKTargetAccessExtended2: /* 801D7C44 001D38A4 94 21 FE D0 */ stwu r1, -0x130(r1) /* 801D7C48 001D38A8 7C 08 02 A6 */ mflr r0 /* 801D7C4C 001D38AC 90 01 01 34 */ stw r0, 0x134(r1) /* 801D7C50 001D38B0 BE 61 00 FC */ stmw r19, 0xfc(r1) /* 801D7C54 001D38B4 7C 97 23 78 */ mr r23, r4 /* 801D7C58 001D38B8 28 17 00 1F */ cmplwi r23, 0x1f /* 801D7C5C 001D38BC 7C 7B 1B 78 */ mr r27, r3 /* 801D7C60 001D38C0 7C B8 2B 78 */ mr r24, r5 /* 801D7C64 001D38C4 7C D9 33 78 */ mr r25, r6 /* 801D7C68 001D38C8 7C FA 3B 78 */ mr r26, r7 /* 801D7C6C 001D38CC 40 81 00 0C */ ble lbl_801D7C78 /* 801D7C70 001D38D0 38 60 07 01 */ li r3, 0x701 /* 801D7C74 001D38D4 48 00 03 F4 */ b lbl_801D8068 lbl_801D7C78: /* 801D7C78 001D38D8 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha /* 801D7C7C 001D38DC 3C A0 80 42 */ lis r5, lbl_8042323C@ha /* 801D7C80 001D38E0 3B A3 D6 C8 */ addi r29, r3, lbl_803FD6C8@l /* 801D7C84 001D38E4 3C 80 7C 99 */ lis r4, 0x7C98E2A6@ha /* 801D7C88 001D38E8 80 1D 00 00 */ lwz r0, 0(r29) /* 801D7C8C 001D38EC 3B E5 32 3C */ addi r31, r5, lbl_8042323C@l /* 801D7C90 001D38F0 81 1D 00 04 */ lwz r8, 4(r29) /* 801D7C94 001D38F4 3C 60 4E 80 */ lis r3, 0x4E800020@ha /* 801D7C98 001D38F8 80 FD 00 24 */ lwz r7, 0x24(r29) /* 801D7C9C 001D38FC 38 C4 E2 A6 */ addi r6, r4, 0x7C98E2A6@l /* 801D7CA0 001D3900 90 01 00 C4 */ stw r0, 0xc4(r1) /* 801D7CA4 001D3904 38 03 00 20 */ addi r0, r3, 0x4E800020@l /* 801D7CA8 001D3908 82 7F 00 00 */ lwz r19, 0(r31) /* 801D7CAC 001D390C 3B C0 00 00 */ li r30, 0 /* 801D7CB0 001D3910 82 DF 00 0C */ lwz r22, 0xc(r31) /* 801D7CB4 001D3914 3C A0 90 83 */ lis r5, 0x9083 /* 801D7CB8 001D3918 91 01 00 C8 */ stw r8, 0xc8(r1) /* 801D7CBC 001D391C 38 61 00 C4 */ addi r3, r1, 0xc4 /* 801D7CC0 001D3920 82 9F 00 04 */ lwz r20, 4(r31) /* 801D7CC4 001D3924 38 80 00 28 */ li r4, 0x28 /* 801D7CC8 001D3928 90 E1 00 E8 */ stw r7, 0xe8(r1) /* 801D7CCC 001D392C 82 BF 00 08 */ lwz r21, 8(r31) /* 801D7CD0 001D3930 83 9D 00 08 */ lwz r28, 8(r29) /* 801D7CD4 001D3934 81 9D 00 0C */ lwz r12, 0xc(r29) /* 801D7CD8 001D3938 81 7D 00 10 */ lwz r11, 0x10(r29) /* 801D7CDC 001D393C 81 5D 00 14 */ lwz r10, 0x14(r29) /* 801D7CE0 001D3940 81 3D 00 18 */ lwz r9, 0x18(r29) /* 801D7CE4 001D3944 81 1D 00 1C */ lwz r8, 0x1c(r29) /* 801D7CE8 001D3948 80 FD 00 20 */ lwz r7, 0x20(r29) /* 801D7CEC 001D394C 92 61 00 14 */ stw r19, 0x14(r1) /* 801D7CF0 001D3950 92 81 00 18 */ stw r20, 0x18(r1) /* 801D7CF4 001D3954 92 A1 00 1C */ stw r21, 0x1c(r1) /* 801D7CF8 001D3958 92 C1 00 20 */ stw r22, 0x20(r1) /* 801D7CFC 001D395C 9B DF 00 0D */ stb r30, 0xd(r31) /* 801D7D00 001D3960 93 81 00 CC */ stw r28, 0xcc(r1) /* 801D7D04 001D3964 91 81 00 D0 */ stw r12, 0xd0(r1) /* 801D7D08 001D3968 91 61 00 D4 */ stw r11, 0xd4(r1) /* 801D7D0C 001D396C 91 41 00 D8 */ stw r10, 0xd8(r1) /* 801D7D10 001D3970 91 21 00 DC */ stw r9, 0xdc(r1) /* 801D7D14 001D3974 91 01 00 E0 */ stw r8, 0xe0(r1) /* 801D7D18 001D3978 90 E1 00 E4 */ stw r7, 0xe4(r1) /* 801D7D1C 001D397C 90 C1 00 C4 */ stw r6, 0xc4(r1) /* 801D7D20 001D3980 90 A1 00 C8 */ stw r5, 0xc8(r1) /* 801D7D24 001D3984 90 01 00 E8 */ stw r0, 0xe8(r1) /* 801D7D28 001D3988 4B FF F3 DD */ bl TRK_flush_cache /* 801D7D2C 001D398C 3C 60 80 49 */ lis r3, lbl_80490D5C@ha /* 801D7D30 001D3990 39 81 00 C4 */ addi r12, r1, 0xc4 /* 801D7D34 001D3994 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l /* 801D7D38 001D3998 38 61 00 08 */ addi r3, r1, 8 /* 801D7D3C 001D399C 7D 89 03 A6 */ mtctr r12 /* 801D7D40 001D39A0 4E 80 04 21 */ bctrl /* 801D7D44 001D39A4 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha /* 801D7D48 001D39A8 80 A1 00 08 */ lwz r5, 8(r1) /* 801D7D4C 001D39AC 3B A3 D6 C8 */ addi r29, r3, lbl_803FD6C8@l /* 801D7D50 001D39B0 3C 80 7C 99 */ lis r4, 0x7C98E3A6@ha /* 801D7D54 001D39B4 81 1D 00 00 */ lwz r8, 0(r29) /* 801D7D58 001D39B8 3C 60 4E 80 */ lis r3, 0x4E800020@ha /* 801D7D5C 001D39BC 80 1D 00 04 */ lwz r0, 4(r29) /* 801D7D60 001D39C0 64 BE A0 00 */ oris r30, r5, 0xa000 /* 801D7D64 001D39C4 80 FD 00 24 */ lwz r7, 0x24(r29) /* 801D7D68 001D39C8 38 A4 E3 A6 */ addi r5, r4, 0x7C98E3A6@l /* 801D7D6C 001D39CC 90 01 00 A0 */ stw r0, 0xa0(r1) /* 801D7D70 001D39D0 38 03 00 20 */ addi r0, r3, 0x4E800020@l /* 801D7D74 001D39D4 83 9D 00 08 */ lwz r28, 8(r29) /* 801D7D78 001D39D8 3C C0 80 83 */ lis r6, 0x8083 /* 801D7D7C 001D39DC 91 01 00 9C */ stw r8, 0x9c(r1) /* 801D7D80 001D39E0 38 61 00 9C */ addi r3, r1, 0x9c /* 801D7D84 001D39E4 81 9D 00 0C */ lwz r12, 0xc(r29) /* 801D7D88 001D39E8 38 80 00 28 */ li r4, 0x28 /* 801D7D8C 001D39EC 90 E1 00 C0 */ stw r7, 0xc0(r1) /* 801D7D90 001D39F0 81 7D 00 10 */ lwz r11, 0x10(r29) /* 801D7D94 001D39F4 81 5D 00 14 */ lwz r10, 0x14(r29) /* 801D7D98 001D39F8 81 3D 00 18 */ lwz r9, 0x18(r29) /* 801D7D9C 001D39FC 81 1D 00 1C */ lwz r8, 0x1c(r29) /* 801D7DA0 001D3A00 80 FD 00 20 */ lwz r7, 0x20(r29) /* 801D7DA4 001D3A04 93 C1 00 08 */ stw r30, 8(r1) /* 801D7DA8 001D3A08 93 81 00 A4 */ stw r28, 0xa4(r1) /* 801D7DAC 001D3A0C 91 81 00 A8 */ stw r12, 0xa8(r1) /* 801D7DB0 001D3A10 91 61 00 AC */ stw r11, 0xac(r1) /* 801D7DB4 001D3A14 91 41 00 B0 */ stw r10, 0xb0(r1) /* 801D7DB8 001D3A18 91 21 00 B4 */ stw r9, 0xb4(r1) /* 801D7DBC 001D3A1C 91 01 00 B8 */ stw r8, 0xb8(r1) /* 801D7DC0 001D3A20 90 E1 00 BC */ stw r7, 0xbc(r1) /* 801D7DC4 001D3A24 90 C1 00 9C */ stw r6, 0x9c(r1) /* 801D7DC8 001D3A28 90 A1 00 A0 */ stw r5, 0xa0(r1) /* 801D7DCC 001D3A2C 90 01 00 C0 */ stw r0, 0xc0(r1) /* 801D7DD0 001D3A30 4B FF F3 35 */ bl TRK_flush_cache /* 801D7DD4 001D3A34 3C 60 80 49 */ lis r3, lbl_80490D5C@ha /* 801D7DD8 001D3A38 39 81 00 9C */ addi r12, r1, 0x9c /* 801D7DDC 001D3A3C 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l /* 801D7DE0 001D3A40 38 61 00 08 */ addi r3, r1, 8 /* 801D7DE4 001D3A44 7D 89 03 A6 */ mtctr r12 /* 801D7DE8 001D3A48 4E 80 04 21 */ bctrl /* 801D7DEC 001D3A4C 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha /* 801D7DF0 001D3A50 3C 80 7C 91 */ lis r4, 0x7C90E3A6@ha /* 801D7DF4 001D3A54 3B A3 D6 C8 */ addi r29, r3, lbl_803FD6C8@l /* 801D7DF8 001D3A58 3C 60 4E 80 */ lis r3, 0x4E800020@ha /* 801D7DFC 001D3A5C 81 1D 00 00 */ lwz r8, 0(r29) /* 801D7E00 001D3A60 3B C0 00 00 */ li r30, 0 /* 801D7E04 001D3A64 80 DD 00 04 */ lwz r6, 4(r29) /* 801D7E08 001D3A68 38 A4 E3 A6 */ addi r5, r4, 0x7C90E3A6@l /* 801D7E0C 001D3A6C 80 FD 00 24 */ lwz r7, 0x24(r29) /* 801D7E10 001D3A70 38 03 00 20 */ addi r0, r3, 0x4E800020@l /* 801D7E14 001D3A74 90 C1 00 78 */ stw r6, 0x78(r1) /* 801D7E18 001D3A78 3C C0 80 83 */ lis r6, 0x8083 /* 801D7E1C 001D3A7C 83 9D 00 08 */ lwz r28, 8(r29) /* 801D7E20 001D3A80 38 61 00 74 */ addi r3, r1, 0x74 /* 801D7E24 001D3A84 91 01 00 74 */ stw r8, 0x74(r1) /* 801D7E28 001D3A88 38 80 00 28 */ li r4, 0x28 /* 801D7E2C 001D3A8C 81 9D 00 0C */ lwz r12, 0xc(r29) /* 801D7E30 001D3A90 90 E1 00 98 */ stw r7, 0x98(r1) /* 801D7E34 001D3A94 81 7D 00 10 */ lwz r11, 0x10(r29) /* 801D7E38 001D3A98 81 5D 00 14 */ lwz r10, 0x14(r29) /* 801D7E3C 001D3A9C 81 3D 00 18 */ lwz r9, 0x18(r29) /* 801D7E40 001D3AA0 81 1D 00 1C */ lwz r8, 0x1c(r29) /* 801D7E44 001D3AA4 80 FD 00 20 */ lwz r7, 0x20(r29) /* 801D7E48 001D3AA8 93 C1 00 08 */ stw r30, 8(r1) /* 801D7E4C 001D3AAC 93 81 00 7C */ stw r28, 0x7c(r1) /* 801D7E50 001D3AB0 91 81 00 80 */ stw r12, 0x80(r1) /* 801D7E54 001D3AB4 91 61 00 84 */ stw r11, 0x84(r1) /* 801D7E58 001D3AB8 91 41 00 88 */ stw r10, 0x88(r1) /* 801D7E5C 001D3ABC 91 21 00 8C */ stw r9, 0x8c(r1) /* 801D7E60 001D3AC0 91 01 00 90 */ stw r8, 0x90(r1) /* 801D7E64 001D3AC4 90 E1 00 94 */ stw r7, 0x94(r1) /* 801D7E68 001D3AC8 90 C1 00 74 */ stw r6, 0x74(r1) /* 801D7E6C 001D3ACC 90 A1 00 78 */ stw r5, 0x78(r1) /* 801D7E70 001D3AD0 90 01 00 98 */ stw r0, 0x98(r1) /* 801D7E74 001D3AD4 4B FF F2 91 */ bl TRK_flush_cache /* 801D7E78 001D3AD8 3C 60 80 49 */ lis r3, lbl_80490D5C@ha /* 801D7E7C 001D3ADC 39 81 00 74 */ addi r12, r1, 0x74 /* 801D7E80 001D3AE0 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l /* 801D7E84 001D3AE4 38 61 00 08 */ addi r3, r1, 8 /* 801D7E88 001D3AE8 7D 89 03 A6 */ mtctr r12 /* 801D7E8C 001D3AEC 4E 80 04 21 */ bctrl /* 801D7E90 001D3AF0 38 00 00 00 */ li r0, 0 /* 801D7E94 001D3AF4 57 7E A8 14 */ slwi r30, r27, 0x15 /* 801D7E98 001D3AF8 90 19 00 00 */ stw r0, 0(r25) /* 801D7E9C 001D3AFC 3B A1 00 4C */ addi r29, r1, 0x4c /* 801D7EA0 001D3B00 3B 81 00 24 */ addi r28, r1, 0x24 /* 801D7EA4 001D3B04 38 60 00 00 */ li r3, 0 /* 801D7EA8 001D3B08 48 00 01 70 */ b lbl_801D8018 lbl_801D7EAC: /* 801D7EAC 001D3B0C 2C 1A 00 00 */ cmpwi r26, 0 /* 801D7EB0 001D3B10 41 82 00 AC */ beq lbl_801D7F5C /* 801D7EB4 001D3B14 3C 60 80 40 */ lis r3, lbl_80400004@ha /* 801D7EB8 001D3B18 85 83 D6 F0 */ lwzu r12, -0x2910(r3) /* 801D7EBC 001D3B1C 67 C0 E0 03 */ oris r0, r30, 0xe003 /* 801D7EC0 001D3B20 81 63 00 04 */ lwz r11, lbl_80400004@l(r3) /* 801D7EC4 001D3B24 81 43 00 08 */ lwz r10, 8(r3) /* 801D7EC8 001D3B28 81 23 00 0C */ lwz r9, 0xc(r3) /* 801D7ECC 001D3B2C 81 03 00 10 */ lwz r8, 0x10(r3) /* 801D7ED0 001D3B30 80 E3 00 14 */ lwz r7, 0x14(r3) /* 801D7ED4 001D3B34 80 C3 00 18 */ lwz r6, 0x18(r3) /* 801D7ED8 001D3B38 80 A3 00 1C */ lwz r5, 0x1c(r3) /* 801D7EDC 001D3B3C 80 83 00 20 */ lwz r4, 0x20(r3) /* 801D7EE0 001D3B40 80 63 00 24 */ lwz r3, 0x24(r3) /* 801D7EE4 001D3B44 91 81 00 4C */ stw r12, 0x4c(r1) /* 801D7EE8 001D3B48 91 61 00 50 */ stw r11, 0x50(r1) /* 801D7EEC 001D3B4C 91 41 00 54 */ stw r10, 0x54(r1) /* 801D7EF0 001D3B50 91 21 00 58 */ stw r9, 0x58(r1) /* 801D7EF4 001D3B54 91 01 00 5C */ stw r8, 0x5c(r1) /* 801D7EF8 001D3B58 90 E1 00 60 */ stw r7, 0x60(r1) /* 801D7EFC 001D3B5C 90 C1 00 64 */ stw r6, 0x64(r1) /* 801D7F00 001D3B60 90 A1 00 68 */ stw r5, 0x68(r1) /* 801D7F04 001D3B64 90 81 00 6C */ stw r4, 0x6c(r1) /* 801D7F08 001D3B68 90 61 00 70 */ stw r3, 0x70(r1) /* 801D7F0C 001D3B6C 41 82 00 08 */ beq lbl_801D7F14 /* 801D7F10 001D3B70 67 C0 F0 03 */ oris r0, r30, 0xf003 lbl_801D7F14: /* 801D7F14 001D3B74 3C 60 4E 80 */ lis r3, 0x4E800020@ha /* 801D7F18 001D3B78 90 01 00 4C */ stw r0, 0x4c(r1) /* 801D7F1C 001D3B7C 38 03 00 20 */ addi r0, r3, 0x4E800020@l /* 801D7F20 001D3B80 7F A3 EB 78 */ mr r3, r29 /* 801D7F24 001D3B84 90 01 00 70 */ stw r0, 0x70(r1) /* 801D7F28 001D3B88 38 80 00 28 */ li r4, 0x28 /* 801D7F2C 001D3B8C 4B FF F1 D9 */ bl TRK_flush_cache /* 801D7F30 001D3B90 3C 60 80 49 */ lis r3, lbl_80490D5C@ha /* 801D7F34 001D3B94 39 81 00 4C */ addi r12, r1, 0x4c /* 801D7F38 001D3B98 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l /* 801D7F3C 001D3B9C 38 61 00 0C */ addi r3, r1, 0xc /* 801D7F40 001D3BA0 7D 89 03 A6 */ mtctr r12 /* 801D7F44 001D3BA4 4E 80 04 21 */ bctrl /* 801D7F48 001D3BA8 80 A1 00 0C */ lwz r5, 0xc(r1) /* 801D7F4C 001D3BAC 7F 03 C3 78 */ mr r3, r24 /* 801D7F50 001D3BB0 80 C1 00 10 */ lwz r6, 0x10(r1) /* 801D7F54 001D3BB4 4B FF D1 89 */ bl TRKAppendBuffer1_ui64 /* 801D7F58 001D3BB8 48 00 00 AC */ b lbl_801D8004 lbl_801D7F5C: /* 801D7F5C 001D3BBC 7F 03 C3 78 */ mr r3, r24 /* 801D7F60 001D3BC0 38 81 00 0C */ addi r4, r1, 0xc /* 801D7F64 001D3BC4 4B FF CF 2D */ bl TRKReadBuffer1_ui64 /* 801D7F68 001D3BC8 3C 60 80 40 */ lis r3, lbl_80400004@ha /* 801D7F6C 001D3BCC 85 83 D6 F0 */ lwzu r12, -0x2910(r3) /* 801D7F70 001D3BD0 2C 1A 00 00 */ cmpwi r26, 0 /* 801D7F74 001D3BD4 67 C0 E0 03 */ oris r0, r30, 0xe003 /* 801D7F78 001D3BD8 81 63 00 04 */ lwz r11, lbl_80400004@l(r3) /* 801D7F7C 001D3BDC 81 43 00 08 */ lwz r10, 8(r3) /* 801D7F80 001D3BE0 81 23 00 0C */ lwz r9, 0xc(r3) /* 801D7F84 001D3BE4 81 03 00 10 */ lwz r8, 0x10(r3) /* 801D7F88 001D3BE8 80 E3 00 14 */ lwz r7, 0x14(r3) /* 801D7F8C 001D3BEC 80 C3 00 18 */ lwz r6, 0x18(r3) /* 801D7F90 001D3BF0 80 A3 00 1C */ lwz r5, 0x1c(r3) /* 801D7F94 001D3BF4 80 83 00 20 */ lwz r4, 0x20(r3) /* 801D7F98 001D3BF8 80 63 00 24 */ lwz r3, 0x24(r3) /* 801D7F9C 001D3BFC 91 81 00 24 */ stw r12, 0x24(r1) /* 801D7FA0 001D3C00 91 61 00 28 */ stw r11, 0x28(r1) /* 801D7FA4 001D3C04 91 41 00 2C */ stw r10, 0x2c(r1) /* 801D7FA8 001D3C08 91 21 00 30 */ stw r9, 0x30(r1) /* 801D7FAC 001D3C0C 91 01 00 34 */ stw r8, 0x34(r1) /* 801D7FB0 001D3C10 90 E1 00 38 */ stw r7, 0x38(r1) /* 801D7FB4 001D3C14 90 C1 00 3C */ stw r6, 0x3c(r1) /* 801D7FB8 001D3C18 90 A1 00 40 */ stw r5, 0x40(r1) /* 801D7FBC 001D3C1C 90 81 00 44 */ stw r4, 0x44(r1) /* 801D7FC0 001D3C20 90 61 00 48 */ stw r3, 0x48(r1) /* 801D7FC4 001D3C24 41 82 00 08 */ beq lbl_801D7FCC /* 801D7FC8 001D3C28 67 C0 F0 03 */ oris r0, r30, 0xf003 lbl_801D7FCC: /* 801D7FCC 001D3C2C 3C 60 4E 80 */ lis r3, 0x4E800020@ha /* 801D7FD0 001D3C30 90 01 00 24 */ stw r0, 0x24(r1) /* 801D7FD4 001D3C34 38 03 00 20 */ addi r0, r3, 0x4E800020@l /* 801D7FD8 001D3C38 7F 83 E3 78 */ mr r3, r28 /* 801D7FDC 001D3C3C 90 01 00 48 */ stw r0, 0x48(r1) /* 801D7FE0 001D3C40 38 80 00 28 */ li r4, 0x28 /* 801D7FE4 001D3C44 4B FF F1 21 */ bl TRK_flush_cache /* 801D7FE8 001D3C48 3C 60 80 49 */ lis r3, lbl_80490D5C@ha /* 801D7FEC 001D3C4C 39 81 00 24 */ addi r12, r1, 0x24 /* 801D7FF0 001D3C50 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l /* 801D7FF4 001D3C54 38 61 00 0C */ addi r3, r1, 0xc /* 801D7FF8 001D3C58 7D 89 03 A6 */ mtctr r12 /* 801D7FFC 001D3C5C 4E 80 04 21 */ bctrl /* 801D8000 001D3C60 38 60 00 00 */ li r3, 0 lbl_801D8004: /* 801D8004 001D3C64 80 99 00 00 */ lwz r4, 0(r25) /* 801D8008 001D3C68 3F DE 00 20 */ addis r30, r30, 0x20 /* 801D800C 001D3C6C 3B 7B 00 01 */ addi r27, r27, 1 /* 801D8010 001D3C70 38 04 00 08 */ addi r0, r4, 8 /* 801D8014 001D3C74 90 19 00 00 */ stw r0, 0(r25) lbl_801D8018: /* 801D8018 001D3C78 7C 1B B8 40 */ cmplw r27, r23 /* 801D801C 001D3C7C 41 81 00 0C */ bgt lbl_801D8028 /* 801D8020 001D3C80 2C 03 00 00 */ cmpwi r3, 0 /* 801D8024 001D3C84 41 82 FE 88 */ beq lbl_801D7EAC lbl_801D8028: /* 801D8028 001D3C88 88 1F 00 0D */ lbz r0, 0xd(r31) /* 801D802C 001D3C8C 28 00 00 00 */ cmplwi r0, 0 /* 801D8030 001D3C90 41 82 00 10 */ beq lbl_801D8040 /* 801D8034 001D3C94 38 00 00 00 */ li r0, 0 /* 801D8038 001D3C98 38 60 07 02 */ li r3, 0x702 /* 801D803C 001D3C9C 90 19 00 00 */ stw r0, 0(r25) lbl_801D8040: /* 801D8040 001D3CA0 3C 80 80 42 */ lis r4, lbl_8042323C@ha /* 801D8044 001D3CA4 80 C1 00 14 */ lwz r6, 0x14(r1) /* 801D8048 001D3CA8 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l /* 801D804C 001D3CAC 80 A1 00 18 */ lwz r5, 0x18(r1) /* 801D8050 001D3CB0 80 81 00 1C */ lwz r4, 0x1c(r1) /* 801D8054 001D3CB4 80 01 00 20 */ lwz r0, 0x20(r1) /* 801D8058 001D3CB8 90 C7 00 00 */ stw r6, 0(r7) /* 801D805C 001D3CBC 90 A7 00 04 */ stw r5, 4(r7) /* 801D8060 001D3CC0 90 87 00 08 */ stw r4, 8(r7) /* 801D8064 001D3CC4 90 07 00 0C */ stw r0, 0xc(r7) lbl_801D8068: /* 801D8068 001D3CC8 BA 61 00 FC */ lmw r19, 0xfc(r1) /* 801D806C 001D3CCC 80 01 01 34 */ lwz r0, 0x134(r1) /* 801D8070 001D3CD0 7C 08 03 A6 */ mtlr r0 /* 801D8074 001D3CD4 38 21 01 30 */ addi r1, r1, 0x130 /* 801D8078 001D3CD8 4E 80 00 20 */ blr .global TRKTargetAccessExtended1 TRKTargetAccessExtended1: /* 801D807C 001D3CDC 94 21 FF E0 */ stwu r1, -0x20(r1) /* 801D8080 001D3CE0 7C 08 02 A6 */ mflr r0 /* 801D8084 001D3CE4 28 04 00 60 */ cmplwi r4, 0x60 /* 801D8088 001D3CE8 90 01 00 24 */ stw r0, 0x24(r1) /* 801D808C 001D3CEC 93 E1 00 1C */ stw r31, 0x1c(r1) /* 801D8090 001D3CF0 93 C1 00 18 */ stw r30, 0x18(r1) /* 801D8094 001D3CF4 7C DE 33 78 */ mr r30, r6 /* 801D8098 001D3CF8 40 81 00 0C */ ble lbl_801D80A4 /* 801D809C 001D3CFC 38 60 07 01 */ li r3, 0x701 /* 801D80A0 001D3D00 48 00 01 34 */ b lbl_801D81D4 lbl_801D80A4: /* 801D80A4 001D3D04 3C C0 80 42 */ lis r6, lbl_8042323C@ha /* 801D80A8 001D3D08 38 00 00 00 */ li r0, 0 /* 801D80AC 001D3D0C 3B E6 32 3C */ addi r31, r6, lbl_8042323C@l /* 801D80B0 001D3D10 7C 03 20 40 */ cmplw r3, r4 /* 801D80B4 001D3D14 80 DF 00 0C */ lwz r6, 0xc(r31) /* 801D80B8 001D3D18 81 5F 00 00 */ lwz r10, 0(r31) /* 801D80BC 001D3D1C 81 3F 00 04 */ lwz r9, 4(r31) /* 801D80C0 001D3D20 81 1F 00 08 */ lwz r8, 8(r31) /* 801D80C4 001D3D24 98 1F 00 0D */ stb r0, 0xd(r31) /* 801D80C8 001D3D28 91 41 00 08 */ stw r10, 8(r1) /* 801D80CC 001D3D2C 91 21 00 0C */ stw r9, 0xc(r1) /* 801D80D0 001D3D30 91 01 00 10 */ stw r8, 0x10(r1) /* 801D80D4 001D3D34 90 C1 00 14 */ stw r6, 0x14(r1) /* 801D80D8 001D3D38 90 1E 00 00 */ stw r0, 0(r30) /* 801D80DC 001D3D3C 41 81 00 B8 */ bgt lbl_801D8194 /* 801D80E0 001D3D40 7C 83 20 50 */ subf r4, r3, r4 /* 801D80E4 001D3D44 3D 00 80 49 */ lis r8, lbl_80490898@ha /* 801D80E8 001D3D48 38 04 00 01 */ addi r0, r4, 1 /* 801D80EC 001D3D4C 80 9E 00 00 */ lwz r4, 0(r30) /* 801D80F0 001D3D50 54 06 10 3A */ slwi r6, r0, 2 /* 801D80F4 001D3D54 2C 07 00 00 */ cmpwi r7, 0 /* 801D80F8 001D3D58 7C 84 32 14 */ add r4, r4, r6 /* 801D80FC 001D3D5C 38 E8 08 98 */ addi r7, r8, lbl_80490898@l /* 801D8100 001D3D60 54 63 10 3A */ slwi r3, r3, 2 /* 801D8104 001D3D64 90 9E 00 00 */ stw r4, 0(r30) /* 801D8108 001D3D68 7C 87 1A 14 */ add r4, r7, r3 /* 801D810C 001D3D6C 38 84 01 A8 */ addi r4, r4, 0x1a8 /* 801D8110 001D3D70 41 82 00 14 */ beq lbl_801D8124 /* 801D8114 001D3D74 7C A3 2B 78 */ mr r3, r5 /* 801D8118 001D3D78 7C 05 03 78 */ mr r5, r0 /* 801D811C 001D3D7C 4B FF CE 5D */ bl TRKAppendBuffer_ui32 /* 801D8120 001D3D80 48 00 00 74 */ b lbl_801D8194 lbl_801D8124: /* 801D8124 001D3D84 38 67 01 EC */ addi r3, r7, 0x1ec /* 801D8128 001D3D88 7C 04 18 40 */ cmplw r4, r3 /* 801D812C 001D3D8C 41 81 00 24 */ bgt lbl_801D8150 /* 801D8130 001D3D90 38 C6 FF FC */ addi r6, r6, -4 /* 801D8134 001D3D94 38 67 01 E8 */ addi r3, r7, 0x1e8 /* 801D8138 001D3D98 7C C4 32 14 */ add r6, r4, r6 /* 801D813C 001D3D9C 7C 06 18 40 */ cmplw r6, r3 /* 801D8140 001D3DA0 41 80 00 10 */ blt lbl_801D8150 /* 801D8144 001D3DA4 3C 60 80 42 */ lis r3, lbl_80423230@ha /* 801D8148 001D3DA8 38 C0 00 01 */ li r6, 1 /* 801D814C 001D3DAC 98 C3 32 30 */ stb r6, lbl_80423230@l(r3) lbl_801D8150: /* 801D8150 001D3DB0 3C 60 80 49 */ lis r3, lbl_80490898@ha /* 801D8154 001D3DB4 38 63 08 98 */ addi r3, r3, lbl_80490898@l /* 801D8158 001D3DB8 38 C3 02 78 */ addi r6, r3, 0x278 /* 801D815C 001D3DBC 7C 04 30 40 */ cmplw r4, r6 /* 801D8160 001D3DC0 41 81 00 28 */ bgt lbl_801D8188 /* 801D8164 001D3DC4 54 03 10 3A */ slwi r3, r0, 2 /* 801D8168 001D3DC8 38 63 FF FC */ addi r3, r3, -4 /* 801D816C 001D3DCC 7C 64 1A 14 */ add r3, r4, r3 /* 801D8170 001D3DD0 7C 03 30 40 */ cmplw r3, r6 /* 801D8174 001D3DD4 41 80 00 14 */ blt lbl_801D8188 /* 801D8178 001D3DD8 3C 60 80 42 */ lis r3, lbl_80423230@ha /* 801D817C 001D3DDC 38 C0 00 01 */ li r6, 1 /* 801D8180 001D3DE0 38 63 32 30 */ addi r3, r3, lbl_80423230@l /* 801D8184 001D3DE4 98 C3 00 01 */ stb r6, 1(r3) lbl_801D8188: /* 801D8188 001D3DE8 7C A3 2B 78 */ mr r3, r5 /* 801D818C 001D3DEC 7C 05 03 78 */ mr r5, r0 /* 801D8190 001D3DF0 4B FF CB 79 */ bl TRKReadBuffer_ui32 lbl_801D8194: /* 801D8194 001D3DF4 88 1F 00 0D */ lbz r0, 0xd(r31) /* 801D8198 001D3DF8 28 00 00 00 */ cmplwi r0, 0 /* 801D819C 001D3DFC 41 82 00 10 */ beq lbl_801D81AC /* 801D81A0 001D3E00 38 00 00 00 */ li r0, 0 /* 801D81A4 001D3E04 38 60 07 02 */ li r3, 0x702 /* 801D81A8 001D3E08 90 1E 00 00 */ stw r0, 0(r30) lbl_801D81AC: /* 801D81AC 001D3E0C 3C 80 80 42 */ lis r4, lbl_8042323C@ha /* 801D81B0 001D3E10 80 C1 00 08 */ lwz r6, 8(r1) /* 801D81B4 001D3E14 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l /* 801D81B8 001D3E18 80 A1 00 0C */ lwz r5, 0xc(r1) /* 801D81BC 001D3E1C 80 81 00 10 */ lwz r4, 0x10(r1) /* 801D81C0 001D3E20 80 01 00 14 */ lwz r0, 0x14(r1) /* 801D81C4 001D3E24 90 C7 00 00 */ stw r6, 0(r7) /* 801D81C8 001D3E28 90 A7 00 04 */ stw r5, 4(r7) /* 801D81CC 001D3E2C 90 87 00 08 */ stw r4, 8(r7) /* 801D81D0 001D3E30 90 07 00 0C */ stw r0, 0xc(r7) lbl_801D81D4: /* 801D81D4 001D3E34 80 01 00 24 */ lwz r0, 0x24(r1) /* 801D81D8 001D3E38 83 E1 00 1C */ lwz r31, 0x1c(r1) /* 801D81DC 001D3E3C 83 C1 00 18 */ lwz r30, 0x18(r1) /* 801D81E0 001D3E40 7C 08 03 A6 */ mtlr r0 /* 801D81E4 001D3E44 38 21 00 20 */ addi r1, r1, 0x20 /* 801D81E8 001D3E48 4E 80 00 20 */ blr .global TRKTargetAccessFP TRKTargetAccessFP: /* 801D81EC 001D3E4C 94 21 FF 10 */ stwu r1, -0xf0(r1) /* 801D81F0 001D3E50 7C 08 02 A6 */ mflr r0 /* 801D81F4 001D3E54 90 01 00 F4 */ stw r0, 0xf4(r1) /* 801D81F8 001D3E58 BE 81 00 C0 */ stmw r20, 0xc0(r1) /* 801D81FC 001D3E5C 7C 9C 23 78 */ mr r28, r4 /* 801D8200 001D3E60 28 1C 00 21 */ cmplwi r28, 0x21 /* 801D8204 001D3E64 7C 74 1B 78 */ mr r20, r3 /* 801D8208 001D3E68 7C BD 2B 78 */ mr r29, r5 /* 801D820C 001D3E6C 7C DE 33 78 */ mr r30, r6 /* 801D8210 001D3E70 7C FF 3B 78 */ mr r31, r7 /* 801D8214 001D3E74 40 81 00 0C */ ble lbl_801D8220 /* 801D8218 001D3E78 38 60 07 01 */ li r3, 0x701 /* 801D821C 001D3E7C 48 00 04 C8 */ b lbl_801D86E4 lbl_801D8220: /* 801D8220 001D3E80 3C 60 80 42 */ lis r3, lbl_8042323C@ha /* 801D8224 001D3E84 38 00 00 00 */ li r0, 0 /* 801D8228 001D3E88 3B 63 32 3C */ addi r27, r3, lbl_8042323C@l /* 801D822C 001D3E8C 80 7B 00 0C */ lwz r3, 0xc(r27) /* 801D8230 001D3E90 80 DB 00 00 */ lwz r6, 0(r27) /* 801D8234 001D3E94 80 BB 00 04 */ lwz r5, 4(r27) /* 801D8238 001D3E98 80 9B 00 08 */ lwz r4, 8(r27) /* 801D823C 001D3E9C 90 C1 00 10 */ stw r6, 0x10(r1) /* 801D8240 001D3EA0 90 A1 00 14 */ stw r5, 0x14(r1) /* 801D8244 001D3EA4 90 81 00 18 */ stw r4, 0x18(r1) /* 801D8248 001D3EA8 90 61 00 1C */ stw r3, 0x1c(r1) /* 801D824C 001D3EAC 98 1B 00 0D */ stb r0, 0xd(r27) /* 801D8250 001D3EB0 4B FF EF C1 */ bl __TRK_get_MSR /* 801D8254 001D3EB4 60 63 20 00 */ ori r3, r3, 0x2000 /* 801D8258 001D3EB8 4B FF EF C1 */ bl __TRK_set_MSR /* 801D825C 001D3EBC 38 00 00 00 */ li r0, 0 /* 801D8260 001D3EC0 7E 95 A3 78 */ mr r21, r20 /* 801D8264 001D3EC4 90 1E 00 00 */ stw r0, 0(r30) /* 801D8268 001D3EC8 56 9A A8 14 */ slwi r26, r20, 0x15 /* 801D826C 001D3ECC 3B 21 00 98 */ addi r25, r1, 0x98 /* 801D8270 001D3ED0 3B 01 00 48 */ addi r24, r1, 0x48 /* 801D8274 001D3ED4 3A E1 00 70 */ addi r23, r1, 0x70 /* 801D8278 001D3ED8 3A C1 00 20 */ addi r22, r1, 0x20 /* 801D827C 001D3EDC 38 60 00 00 */ li r3, 0 /* 801D8280 001D3EE0 48 00 04 14 */ b lbl_801D8694 lbl_801D8284: /* 801D8284 001D3EE4 2C 1F 00 00 */ cmpwi r31, 0 /* 801D8288 001D3EE8 41 82 01 FC */ beq lbl_801D8484 /* 801D828C 001D3EEC 3C 60 80 40 */ lis r3, lbl_803FD718@ha /* 801D8290 001D3EF0 28 15 00 20 */ cmplwi r21, 0x20 /* 801D8294 001D3EF4 39 83 D7 18 */ addi r12, r3, lbl_803FD718@l /* 801D8298 001D3EF8 81 6C 00 00 */ lwz r11, 0(r12) /* 801D829C 001D3EFC 81 4C 00 04 */ lwz r10, 4(r12) /* 801D82A0 001D3F00 81 2C 00 08 */ lwz r9, 8(r12) /* 801D82A4 001D3F04 81 0C 00 0C */ lwz r8, 0xc(r12) /* 801D82A8 001D3F08 80 EC 00 10 */ lwz r7, 0x10(r12) /* 801D82AC 001D3F0C 80 CC 00 14 */ lwz r6, 0x14(r12) /* 801D82B0 001D3F10 80 AC 00 18 */ lwz r5, 0x18(r12) /* 801D82B4 001D3F14 80 8C 00 1C */ lwz r4, 0x1c(r12) /* 801D82B8 001D3F18 80 6C 00 20 */ lwz r3, 0x20(r12) /* 801D82BC 001D3F1C 80 0C 00 24 */ lwz r0, 0x24(r12) /* 801D82C0 001D3F20 91 61 00 98 */ stw r11, 0x98(r1) /* 801D82C4 001D3F24 91 41 00 9C */ stw r10, 0x9c(r1) /* 801D82C8 001D3F28 91 21 00 A0 */ stw r9, 0xa0(r1) /* 801D82CC 001D3F2C 91 01 00 A4 */ stw r8, 0xa4(r1) /* 801D82D0 001D3F30 90 E1 00 A8 */ stw r7, 0xa8(r1) /* 801D82D4 001D3F34 90 C1 00 AC */ stw r6, 0xac(r1) /* 801D82D8 001D3F38 90 A1 00 B0 */ stw r5, 0xb0(r1) /* 801D82DC 001D3F3C 90 81 00 B4 */ stw r4, 0xb4(r1) /* 801D82E0 001D3F40 90 61 00 B8 */ stw r3, 0xb8(r1) /* 801D82E4 001D3F44 90 01 00 BC */ stw r0, 0xbc(r1) /* 801D82E8 001D3F48 40 80 00 4C */ bge lbl_801D8334 /* 801D82EC 001D3F4C 2C 1F 00 00 */ cmpwi r31, 0 /* 801D82F0 001D3F50 67 40 C8 03 */ oris r0, r26, 0xc803 /* 801D82F4 001D3F54 41 82 00 08 */ beq lbl_801D82FC /* 801D82F8 001D3F58 67 40 D8 03 */ oris r0, r26, 0xd803 lbl_801D82FC: /* 801D82FC 001D3F5C 3C 60 4E 80 */ lis r3, 0x4E800020@ha /* 801D8300 001D3F60 90 01 00 98 */ stw r0, 0x98(r1) /* 801D8304 001D3F64 38 03 00 20 */ addi r0, r3, 0x4E800020@l /* 801D8308 001D3F68 7F 23 CB 78 */ mr r3, r25 /* 801D830C 001D3F6C 90 01 00 BC */ stw r0, 0xbc(r1) /* 801D8310 001D3F70 38 80 00 28 */ li r4, 0x28 /* 801D8314 001D3F74 4B FF ED F1 */ bl TRK_flush_cache /* 801D8318 001D3F78 3C 60 80 49 */ lis r3, lbl_80490D5C@ha /* 801D831C 001D3F7C 39 81 00 98 */ addi r12, r1, 0x98 /* 801D8320 001D3F80 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l /* 801D8324 001D3F84 38 61 00 08 */ addi r3, r1, 8 /* 801D8328 001D3F88 7D 89 03 A6 */ mtctr r12 /* 801D832C 001D3F8C 4E 80 04 21 */ bctrl /* 801D8330 001D3F90 48 00 01 40 */ b lbl_801D8470 lbl_801D8334: /* 801D8334 001D3F94 40 82 00 44 */ bne lbl_801D8378 /* 801D8338 001D3F98 2C 1F 00 00 */ cmpwi r31, 0 /* 801D833C 001D3F9C 41 82 00 10 */ beq lbl_801D834C /* 801D8340 001D3FA0 38 61 00 08 */ addi r3, r1, 8 /* 801D8344 001D3FA4 4B FF F2 61 */ bl ReadFPSCR /* 801D8348 001D3FA8 48 00 00 0C */ b lbl_801D8354 lbl_801D834C: /* 801D834C 001D3FAC 38 61 00 08 */ addi r3, r1, 8 /* 801D8350 001D3FB0 4B FF F2 79 */ bl WriteFPSCR lbl_801D8354: /* 801D8354 001D3FB4 80 81 00 08 */ lwz r4, 8(r1) /* 801D8358 001D3FB8 38 00 00 00 */ li r0, 0 /* 801D835C 001D3FBC 80 A1 00 0C */ lwz r5, 0xc(r1) /* 801D8360 001D3FC0 38 60 FF FF */ li r3, -1 /* 801D8364 001D3FC4 7C 80 00 38 */ and r0, r4, r0 /* 801D8368 001D3FC8 7C A3 18 38 */ and r3, r5, r3 /* 801D836C 001D3FCC 90 01 00 08 */ stw r0, 8(r1) /* 801D8370 001D3FD0 90 61 00 0C */ stw r3, 0xc(r1) /* 801D8374 001D3FD4 48 00 00 FC */ b lbl_801D8470 lbl_801D8378: /* 801D8378 001D3FD8 28 15 00 21 */ cmplwi r21, 0x21 /* 801D837C 001D3FDC 40 82 00 F4 */ bne lbl_801D8470 /* 801D8380 001D3FE0 2C 1F 00 00 */ cmpwi r31, 0 /* 801D8384 001D3FE4 40 82 00 0C */ bne lbl_801D8390 /* 801D8388 001D3FE8 80 01 00 0C */ lwz r0, 0xc(r1) /* 801D838C 001D3FEC 90 01 00 08 */ stw r0, 8(r1) lbl_801D8390: /* 801D8390 001D3FF0 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha /* 801D8394 001D3FF4 2C 1F 00 00 */ cmpwi r31, 0 /* 801D8398 001D3FF8 39 83 D6 C8 */ addi r12, r3, lbl_803FD6C8@l /* 801D839C 001D3FFC 81 6C 00 00 */ lwz r11, 0(r12) /* 801D83A0 001D4000 81 4C 00 04 */ lwz r10, 4(r12) /* 801D83A4 001D4004 81 2C 00 08 */ lwz r9, 8(r12) /* 801D83A8 001D4008 81 0C 00 0C */ lwz r8, 0xc(r12) /* 801D83AC 001D400C 80 EC 00 10 */ lwz r7, 0x10(r12) /* 801D83B0 001D4010 80 CC 00 14 */ lwz r6, 0x14(r12) /* 801D83B4 001D4014 80 AC 00 18 */ lwz r5, 0x18(r12) /* 801D83B8 001D4018 80 8C 00 1C */ lwz r4, 0x1c(r12) /* 801D83BC 001D401C 80 6C 00 20 */ lwz r3, 0x20(r12) /* 801D83C0 001D4020 80 0C 00 24 */ lwz r0, 0x24(r12) /* 801D83C4 001D4024 91 61 00 48 */ stw r11, 0x48(r1) /* 801D83C8 001D4028 91 41 00 4C */ stw r10, 0x4c(r1) /* 801D83CC 001D402C 91 21 00 50 */ stw r9, 0x50(r1) /* 801D83D0 001D4030 91 01 00 54 */ stw r8, 0x54(r1) /* 801D83D4 001D4034 90 E1 00 58 */ stw r7, 0x58(r1) /* 801D83D8 001D4038 90 C1 00 5C */ stw r6, 0x5c(r1) /* 801D83DC 001D403C 90 A1 00 60 */ stw r5, 0x60(r1) /* 801D83E0 001D4040 90 81 00 64 */ stw r4, 0x64(r1) /* 801D83E4 001D4044 90 61 00 68 */ stw r3, 0x68(r1) /* 801D83E8 001D4048 90 01 00 6C */ stw r0, 0x6c(r1) /* 801D83EC 001D404C 41 82 00 1C */ beq lbl_801D8408 /* 801D83F0 001D4050 3C 60 7C 9F */ lis r3, 0x7C9EFAA6@ha /* 801D83F4 001D4054 3C 00 90 83 */ lis r0, 0x9083 /* 801D83F8 001D4058 38 63 FA A6 */ addi r3, r3, 0x7C9EFAA6@l /* 801D83FC 001D405C 90 01 00 4C */ stw r0, 0x4c(r1) /* 801D8400 001D4060 90 61 00 48 */ stw r3, 0x48(r1) /* 801D8404 001D4064 48 00 00 18 */ b lbl_801D841C lbl_801D8408: /* 801D8408 001D4068 3C 60 7C 9F */ lis r3, 0x7C9EFBA6@ha /* 801D840C 001D406C 3C 80 80 83 */ lis r4, 0x8083 /* 801D8410 001D4070 38 03 FB A6 */ addi r0, r3, 0x7C9EFBA6@l /* 801D8414 001D4074 90 81 00 48 */ stw r4, 0x48(r1) /* 801D8418 001D4078 90 01 00 4C */ stw r0, 0x4c(r1) lbl_801D841C: /* 801D841C 001D407C 3C 80 4E 80 */ lis r4, 0x4E800020@ha /* 801D8420 001D4080 7F 03 C3 78 */ mr r3, r24 /* 801D8424 001D4084 38 04 00 20 */ addi r0, r4, 0x4E800020@l /* 801D8428 001D4088 38 80 00 28 */ li r4, 0x28 /* 801D842C 001D408C 90 01 00 6C */ stw r0, 0x6c(r1) /* 801D8430 001D4090 4B FF EC D5 */ bl TRK_flush_cache /* 801D8434 001D4094 3C 60 80 49 */ lis r3, lbl_80490D5C@ha /* 801D8438 001D4098 39 81 00 48 */ addi r12, r1, 0x48 /* 801D843C 001D409C 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l /* 801D8440 001D40A0 38 61 00 08 */ addi r3, r1, 8 /* 801D8444 001D40A4 7D 89 03 A6 */ mtctr r12 /* 801D8448 001D40A8 4E 80 04 21 */ bctrl /* 801D844C 001D40AC 2C 1F 00 00 */ cmpwi r31, 0 /* 801D8450 001D40B0 41 82 00 20 */ beq lbl_801D8470 /* 801D8454 001D40B4 80 61 00 08 */ lwz r3, 8(r1) /* 801D8458 001D40B8 38 80 00 00 */ li r4, 0 /* 801D845C 001D40BC 38 00 FF FF */ li r0, -1 /* 801D8460 001D40C0 7C 63 00 38 */ and r3, r3, r0 /* 801D8464 001D40C4 7C 80 20 38 */ and r0, r4, r4 /* 801D8468 001D40C8 90 61 00 0C */ stw r3, 0xc(r1) /* 801D846C 001D40CC 90 01 00 08 */ stw r0, 8(r1) lbl_801D8470: /* 801D8470 001D40D0 80 A1 00 08 */ lwz r5, 8(r1) /* 801D8474 001D40D4 7F A3 EB 78 */ mr r3, r29 /* 801D8478 001D40D8 80 C1 00 0C */ lwz r6, 0xc(r1) /* 801D847C 001D40DC 4B FF CC 61 */ bl TRKAppendBuffer1_ui64 /* 801D8480 001D40E0 48 00 02 00 */ b lbl_801D8680 lbl_801D8484: /* 801D8484 001D40E4 7F A3 EB 78 */ mr r3, r29 /* 801D8488 001D40E8 38 81 00 08 */ addi r4, r1, 8 /* 801D848C 001D40EC 4B FF CA 05 */ bl TRKReadBuffer1_ui64 /* 801D8490 001D40F0 3C 60 80 40 */ lis r3, lbl_803FD718@ha /* 801D8494 001D40F4 28 15 00 20 */ cmplwi r21, 0x20 /* 801D8498 001D40F8 39 83 D7 18 */ addi r12, r3, lbl_803FD718@l /* 801D849C 001D40FC 3A 80 00 00 */ li r20, 0 /* 801D84A0 001D4100 81 6C 00 00 */ lwz r11, 0(r12) /* 801D84A4 001D4104 81 4C 00 04 */ lwz r10, 4(r12) /* 801D84A8 001D4108 81 2C 00 08 */ lwz r9, 8(r12) /* 801D84AC 001D410C 81 0C 00 0C */ lwz r8, 0xc(r12) /* 801D84B0 001D4110 80 EC 00 10 */ lwz r7, 0x10(r12) /* 801D84B4 001D4114 80 CC 00 14 */ lwz r6, 0x14(r12) /* 801D84B8 001D4118 80 AC 00 18 */ lwz r5, 0x18(r12) /* 801D84BC 001D411C 80 8C 00 1C */ lwz r4, 0x1c(r12) /* 801D84C0 001D4120 80 6C 00 20 */ lwz r3, 0x20(r12) /* 801D84C4 001D4124 80 0C 00 24 */ lwz r0, 0x24(r12) /* 801D84C8 001D4128 91 61 00 70 */ stw r11, 0x70(r1) /* 801D84CC 001D412C 91 41 00 74 */ stw r10, 0x74(r1) /* 801D84D0 001D4130 91 21 00 78 */ stw r9, 0x78(r1) /* 801D84D4 001D4134 91 01 00 7C */ stw r8, 0x7c(r1) /* 801D84D8 001D4138 90 E1 00 80 */ stw r7, 0x80(r1) /* 801D84DC 001D413C 90 C1 00 84 */ stw r6, 0x84(r1) /* 801D84E0 001D4140 90 A1 00 88 */ stw r5, 0x88(r1) /* 801D84E4 001D4144 90 81 00 8C */ stw r4, 0x8c(r1) /* 801D84E8 001D4148 90 61 00 90 */ stw r3, 0x90(r1) /* 801D84EC 001D414C 90 01 00 94 */ stw r0, 0x94(r1) /* 801D84F0 001D4150 40 80 00 50 */ bge lbl_801D8540 /* 801D84F4 001D4154 2C 1F 00 00 */ cmpwi r31, 0 /* 801D84F8 001D4158 67 40 C8 03 */ oris r0, r26, 0xc803 /* 801D84FC 001D415C 41 82 00 08 */ beq lbl_801D8504 /* 801D8500 001D4160 67 40 D8 03 */ oris r0, r26, 0xd803 lbl_801D8504: /* 801D8504 001D4164 3C 60 4E 80 */ lis r3, 0x4E800020@ha /* 801D8508 001D4168 90 01 00 70 */ stw r0, 0x70(r1) /* 801D850C 001D416C 38 03 00 20 */ addi r0, r3, 0x4E800020@l /* 801D8510 001D4170 7E E3 BB 78 */ mr r3, r23 /* 801D8514 001D4174 90 01 00 94 */ stw r0, 0x94(r1) /* 801D8518 001D4178 38 80 00 28 */ li r4, 0x28 /* 801D851C 001D417C 4B FF EB E9 */ bl TRK_flush_cache /* 801D8520 001D4180 3C 60 80 49 */ lis r3, lbl_80490D5C@ha /* 801D8524 001D4184 39 81 00 70 */ addi r12, r1, 0x70 /* 801D8528 001D4188 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l /* 801D852C 001D418C 38 61 00 08 */ addi r3, r1, 8 /* 801D8530 001D4190 7D 89 03 A6 */ mtctr r12 /* 801D8534 001D4194 4E 80 04 21 */ bctrl /* 801D8538 001D4198 3A 80 00 00 */ li r20, 0 /* 801D853C 001D419C 48 00 01 40 */ b lbl_801D867C lbl_801D8540: /* 801D8540 001D41A0 40 82 00 44 */ bne lbl_801D8584 /* 801D8544 001D41A4 2C 1F 00 00 */ cmpwi r31, 0 /* 801D8548 001D41A8 41 82 00 10 */ beq lbl_801D8558 /* 801D854C 001D41AC 38 61 00 08 */ addi r3, r1, 8 /* 801D8550 001D41B0 4B FF F0 55 */ bl ReadFPSCR /* 801D8554 001D41B4 48 00 00 0C */ b lbl_801D8560 lbl_801D8558: /* 801D8558 001D41B8 38 61 00 08 */ addi r3, r1, 8 /* 801D855C 001D41BC 4B FF F0 6D */ bl WriteFPSCR lbl_801D8560: /* 801D8560 001D41C0 80 81 00 08 */ lwz r4, 8(r1) /* 801D8564 001D41C4 38 00 00 00 */ li r0, 0 /* 801D8568 001D41C8 80 A1 00 0C */ lwz r5, 0xc(r1) /* 801D856C 001D41CC 38 60 FF FF */ li r3, -1 /* 801D8570 001D41D0 7C 80 00 38 */ and r0, r4, r0 /* 801D8574 001D41D4 7C A3 18 38 */ and r3, r5, r3 /* 801D8578 001D41D8 90 01 00 08 */ stw r0, 8(r1) /* 801D857C 001D41DC 90 61 00 0C */ stw r3, 0xc(r1) /* 801D8580 001D41E0 48 00 00 FC */ b lbl_801D867C lbl_801D8584: /* 801D8584 001D41E4 28 15 00 21 */ cmplwi r21, 0x21 /* 801D8588 001D41E8 40 82 00 F4 */ bne lbl_801D867C /* 801D858C 001D41EC 2C 1F 00 00 */ cmpwi r31, 0 /* 801D8590 001D41F0 40 82 00 0C */ bne lbl_801D859C /* 801D8594 001D41F4 80 01 00 0C */ lwz r0, 0xc(r1) /* 801D8598 001D41F8 90 01 00 08 */ stw r0, 8(r1) lbl_801D859C: /* 801D859C 001D41FC 3C 60 80 40 */ lis r3, lbl_803FD6C8@ha /* 801D85A0 001D4200 2C 1F 00 00 */ cmpwi r31, 0 /* 801D85A4 001D4204 39 83 D6 C8 */ addi r12, r3, lbl_803FD6C8@l /* 801D85A8 001D4208 81 6C 00 00 */ lwz r11, 0(r12) /* 801D85AC 001D420C 81 4C 00 04 */ lwz r10, 4(r12) /* 801D85B0 001D4210 81 2C 00 08 */ lwz r9, 8(r12) /* 801D85B4 001D4214 81 0C 00 0C */ lwz r8, 0xc(r12) /* 801D85B8 001D4218 80 EC 00 10 */ lwz r7, 0x10(r12) /* 801D85BC 001D421C 80 CC 00 14 */ lwz r6, 0x14(r12) /* 801D85C0 001D4220 80 AC 00 18 */ lwz r5, 0x18(r12) /* 801D85C4 001D4224 80 8C 00 1C */ lwz r4, 0x1c(r12) /* 801D85C8 001D4228 80 6C 00 20 */ lwz r3, 0x20(r12) /* 801D85CC 001D422C 80 0C 00 24 */ lwz r0, 0x24(r12) /* 801D85D0 001D4230 91 61 00 20 */ stw r11, 0x20(r1) /* 801D85D4 001D4234 91 41 00 24 */ stw r10, 0x24(r1) /* 801D85D8 001D4238 91 21 00 28 */ stw r9, 0x28(r1) /* 801D85DC 001D423C 91 01 00 2C */ stw r8, 0x2c(r1) /* 801D85E0 001D4240 90 E1 00 30 */ stw r7, 0x30(r1) /* 801D85E4 001D4244 90 C1 00 34 */ stw r6, 0x34(r1) /* 801D85E8 001D4248 90 A1 00 38 */ stw r5, 0x38(r1) /* 801D85EC 001D424C 90 81 00 3C */ stw r4, 0x3c(r1) /* 801D85F0 001D4250 90 61 00 40 */ stw r3, 0x40(r1) /* 801D85F4 001D4254 90 01 00 44 */ stw r0, 0x44(r1) /* 801D85F8 001D4258 41 82 00 1C */ beq lbl_801D8614 /* 801D85FC 001D425C 3C 60 7C 9F */ lis r3, 0x7C9EFAA6@ha /* 801D8600 001D4260 3C 00 90 83 */ lis r0, 0x9083 /* 801D8604 001D4264 38 63 FA A6 */ addi r3, r3, 0x7C9EFAA6@l /* 801D8608 001D4268 90 01 00 24 */ stw r0, 0x24(r1) /* 801D860C 001D426C 90 61 00 20 */ stw r3, 0x20(r1) /* 801D8610 001D4270 48 00 00 18 */ b lbl_801D8628 lbl_801D8614: /* 801D8614 001D4274 3C 60 7C 9F */ lis r3, 0x7C9EFBA6@ha /* 801D8618 001D4278 3C 80 80 83 */ lis r4, 0x8083 /* 801D861C 001D427C 38 03 FB A6 */ addi r0, r3, 0x7C9EFBA6@l /* 801D8620 001D4280 90 81 00 20 */ stw r4, 0x20(r1) /* 801D8624 001D4284 90 01 00 24 */ stw r0, 0x24(r1) lbl_801D8628: /* 801D8628 001D4288 3C 80 4E 80 */ lis r4, 0x4E800020@ha /* 801D862C 001D428C 7E C3 B3 78 */ mr r3, r22 /* 801D8630 001D4290 38 04 00 20 */ addi r0, r4, 0x4E800020@l /* 801D8634 001D4294 38 80 00 28 */ li r4, 0x28 /* 801D8638 001D4298 90 01 00 44 */ stw r0, 0x44(r1) /* 801D863C 001D429C 4B FF EA C9 */ bl TRK_flush_cache /* 801D8640 001D42A0 3C 60 80 49 */ lis r3, lbl_80490D5C@ha /* 801D8644 001D42A4 39 81 00 20 */ addi r12, r1, 0x20 /* 801D8648 001D42A8 38 83 0D 5C */ addi r4, r3, lbl_80490D5C@l /* 801D864C 001D42AC 38 61 00 08 */ addi r3, r1, 8 /* 801D8650 001D42B0 7D 89 03 A6 */ mtctr r12 /* 801D8654 001D42B4 4E 80 04 21 */ bctrl /* 801D8658 001D42B8 2C 1F 00 00 */ cmpwi r31, 0 /* 801D865C 001D42BC 3A 80 00 00 */ li r20, 0 /* 801D8660 001D42C0 41 82 00 1C */ beq lbl_801D867C /* 801D8664 001D42C4 80 81 00 08 */ lwz r4, 8(r1) /* 801D8668 001D42C8 38 60 FF FF */ li r3, -1 /* 801D866C 001D42CC 7E 80 A0 38 */ and r0, r20, r20 /* 801D8670 001D42D0 7C 83 18 38 */ and r3, r4, r3 /* 801D8674 001D42D4 90 01 00 08 */ stw r0, 8(r1) /* 801D8678 001D42D8 90 61 00 0C */ stw r3, 0xc(r1) lbl_801D867C: /* 801D867C 001D42DC 7E 83 A3 78 */ mr r3, r20 lbl_801D8680: /* 801D8680 001D42E0 80 9E 00 00 */ lwz r4, 0(r30) /* 801D8684 001D42E4 3F 5A 00 20 */ addis r26, r26, 0x20 /* 801D8688 001D42E8 3A B5 00 01 */ addi r21, r21, 1 /* 801D868C 001D42EC 38 04 00 08 */ addi r0, r4, 8 /* 801D8690 001D42F0 90 1E 00 00 */ stw r0, 0(r30) lbl_801D8694: /* 801D8694 001D42F4 7C 15 E0 40 */ cmplw r21, r28 /* 801D8698 001D42F8 41 81 00 0C */ bgt lbl_801D86A4 /* 801D869C 001D42FC 2C 03 00 00 */ cmpwi r3, 0 /* 801D86A0 001D4300 41 82 FB E4 */ beq lbl_801D8284 lbl_801D86A4: /* 801D86A4 001D4304 88 1B 00 0D */ lbz r0, 0xd(r27) /* 801D86A8 001D4308 28 00 00 00 */ cmplwi r0, 0 /* 801D86AC 001D430C 41 82 00 10 */ beq lbl_801D86BC /* 801D86B0 001D4310 38 00 00 00 */ li r0, 0 /* 801D86B4 001D4314 38 60 07 02 */ li r3, 0x702 /* 801D86B8 001D4318 90 1E 00 00 */ stw r0, 0(r30) lbl_801D86BC: /* 801D86BC 001D431C 3C 80 80 42 */ lis r4, lbl_8042323C@ha /* 801D86C0 001D4320 80 C1 00 10 */ lwz r6, 0x10(r1) /* 801D86C4 001D4324 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l /* 801D86C8 001D4328 80 A1 00 14 */ lwz r5, 0x14(r1) /* 801D86CC 001D432C 80 81 00 18 */ lwz r4, 0x18(r1) /* 801D86D0 001D4330 80 01 00 1C */ lwz r0, 0x1c(r1) /* 801D86D4 001D4334 90 C7 00 00 */ stw r6, 0(r7) /* 801D86D8 001D4338 90 A7 00 04 */ stw r5, 4(r7) /* 801D86DC 001D433C 90 87 00 08 */ stw r4, 8(r7) /* 801D86E0 001D4340 90 07 00 0C */ stw r0, 0xc(r7) lbl_801D86E4: /* 801D86E4 001D4344 BA 81 00 C0 */ lmw r20, 0xc0(r1) /* 801D86E8 001D4348 80 01 00 F4 */ lwz r0, 0xf4(r1) /* 801D86EC 001D434C 7C 08 03 A6 */ mtlr r0 /* 801D86F0 001D4350 38 21 00 F0 */ addi r1, r1, 0xf0 /* 801D86F4 001D4354 4E 80 00 20 */ blr .global TRKTargetAccessDefault TRKTargetAccessDefault: /* 801D86F8 001D4358 94 21 FF E0 */ stwu r1, -0x20(r1) /* 801D86FC 001D435C 7C 08 02 A6 */ mflr r0 /* 801D8700 001D4360 28 04 00 24 */ cmplwi r4, 0x24 /* 801D8704 001D4364 90 01 00 24 */ stw r0, 0x24(r1) /* 801D8708 001D4368 93 E1 00 1C */ stw r31, 0x1c(r1) /* 801D870C 001D436C 7C DF 33 78 */ mr r31, r6 /* 801D8710 001D4370 93 C1 00 18 */ stw r30, 0x18(r1) /* 801D8714 001D4374 40 81 00 0C */ ble lbl_801D8720 /* 801D8718 001D4378 38 60 07 01 */ li r3, 0x701 /* 801D871C 001D437C 48 00 00 B8 */ b lbl_801D87D4 lbl_801D8720: /* 801D8720 001D4380 3C C0 80 42 */ lis r6, lbl_8042323C@ha /* 801D8724 001D4384 7C 83 20 50 */ subf r4, r3, r4 /* 801D8728 001D4388 3B C6 32 3C */ addi r30, r6, lbl_8042323C@l /* 801D872C 001D438C 3C C0 80 49 */ lis r6, lbl_80490898@ha /* 801D8730 001D4390 81 3E 00 0C */ lwz r9, 0xc(r30) /* 801D8734 001D4394 39 00 00 00 */ li r8, 0 /* 801D8738 001D4398 39 84 00 01 */ addi r12, r4, 1 /* 801D873C 001D439C 81 7E 00 00 */ lwz r11, 0(r30) /* 801D8740 001D43A0 81 5E 00 04 */ lwz r10, 4(r30) /* 801D8744 001D43A4 2C 07 00 00 */ cmpwi r7, 0 /* 801D8748 001D43A8 80 FE 00 08 */ lwz r7, 8(r30) /* 801D874C 001D43AC 55 80 10 3A */ slwi r0, r12, 2 /* 801D8750 001D43B0 99 1E 00 0D */ stb r8, 0xd(r30) /* 801D8754 001D43B4 54 64 10 3A */ slwi r4, r3, 2 /* 801D8758 001D43B8 38 66 08 98 */ addi r3, r6, lbl_80490898@l /* 801D875C 001D43BC 91 61 00 08 */ stw r11, 8(r1) /* 801D8760 001D43C0 7C 83 22 14 */ add r4, r3, r4 /* 801D8764 001D43C4 91 41 00 0C */ stw r10, 0xc(r1) /* 801D8768 001D43C8 90 E1 00 10 */ stw r7, 0x10(r1) /* 801D876C 001D43CC 91 21 00 14 */ stw r9, 0x14(r1) /* 801D8770 001D43D0 90 1F 00 00 */ stw r0, 0(r31) /* 801D8774 001D43D4 41 82 00 14 */ beq lbl_801D8788 /* 801D8778 001D43D8 7C A3 2B 78 */ mr r3, r5 /* 801D877C 001D43DC 7D 85 63 78 */ mr r5, r12 /* 801D8780 001D43E0 4B FF C7 F9 */ bl TRKAppendBuffer_ui32 /* 801D8784 001D43E4 48 00 00 10 */ b lbl_801D8794 lbl_801D8788: /* 801D8788 001D43E8 7C A3 2B 78 */ mr r3, r5 /* 801D878C 001D43EC 7D 85 63 78 */ mr r5, r12 /* 801D8790 001D43F0 4B FF C5 79 */ bl TRKReadBuffer_ui32 lbl_801D8794: /* 801D8794 001D43F4 88 1E 00 0D */ lbz r0, 0xd(r30) /* 801D8798 001D43F8 28 00 00 00 */ cmplwi r0, 0 /* 801D879C 001D43FC 41 82 00 10 */ beq lbl_801D87AC /* 801D87A0 001D4400 38 00 00 00 */ li r0, 0 /* 801D87A4 001D4404 38 60 07 02 */ li r3, 0x702 /* 801D87A8 001D4408 90 1F 00 00 */ stw r0, 0(r31) lbl_801D87AC: /* 801D87AC 001D440C 3C 80 80 42 */ lis r4, lbl_8042323C@ha /* 801D87B0 001D4410 80 C1 00 08 */ lwz r6, 8(r1) /* 801D87B4 001D4414 38 E4 32 3C */ addi r7, r4, lbl_8042323C@l /* 801D87B8 001D4418 80 A1 00 0C */ lwz r5, 0xc(r1) /* 801D87BC 001D441C 80 81 00 10 */ lwz r4, 0x10(r1) /* 801D87C0 001D4420 80 01 00 14 */ lwz r0, 0x14(r1) /* 801D87C4 001D4424 90 C7 00 00 */ stw r6, 0(r7) /* 801D87C8 001D4428 90 A7 00 04 */ stw r5, 4(r7) /* 801D87CC 001D442C 90 87 00 08 */ stw r4, 8(r7) /* 801D87D0 001D4430 90 07 00 0C */ stw r0, 0xc(r7) lbl_801D87D4: /* 801D87D4 001D4434 80 01 00 24 */ lwz r0, 0x24(r1) /* 801D87D8 001D4438 83 E1 00 1C */ lwz r31, 0x1c(r1) /* 801D87DC 001D443C 83 C1 00 18 */ lwz r30, 0x18(r1) /* 801D87E0 001D4440 7C 08 03 A6 */ mtlr r0 /* 801D87E4 001D4444 38 21 00 20 */ addi r1, r1, 0x20 /* 801D87E8 001D4448 4E 80 00 20 */ blr .global TRKTargetReadInstruction TRKTargetReadInstruction: /* 801D87EC 001D444C 94 21 FF F0 */ stwu r1, -0x10(r1) /* 801D87F0 001D4450 7C 08 02 A6 */ mflr r0 /* 801D87F4 001D4454 38 C0 00 00 */ li r6, 0 /* 801D87F8 001D4458 38 E0 00 01 */ li r7, 1 /* 801D87FC 001D445C 90 01 00 14 */ stw r0, 0x14(r1) /* 801D8800 001D4460 38 00 00 04 */ li r0, 4 /* 801D8804 001D4464 38 A1 00 08 */ addi r5, r1, 8 /* 801D8808 001D4468 90 01 00 08 */ stw r0, 8(r1) /* 801D880C 001D446C 48 00 00 2D */ bl TRKTargetAccessMemory /* 801D8810 001D4470 2C 03 00 00 */ cmpwi r3, 0 /* 801D8814 001D4474 40 82 00 14 */ bne lbl_801D8828 /* 801D8818 001D4478 80 01 00 08 */ lwz r0, 8(r1) /* 801D881C 001D447C 28 00 00 04 */ cmplwi r0, 4 /* 801D8820 001D4480 41 82 00 08 */ beq lbl_801D8828 /* 801D8824 001D4484 38 60 07 00 */ li r3, 0x700 lbl_801D8828: /* 801D8828 001D4488 80 01 00 14 */ lwz r0, 0x14(r1) /* 801D882C 001D448C 7C 08 03 A6 */ mtlr r0 /* 801D8830 001D4490 38 21 00 10 */ addi r1, r1, 0x10 /* 801D8834 001D4494 4E 80 00 20 */ blr .global TRKTargetAccessMemory TRKTargetAccessMemory: /* 801D8838 001D4498 94 21 FF C0 */ stwu r1, -0x40(r1) /* 801D883C 001D449C 7C 08 02 A6 */ mflr r0 /* 801D8840 001D44A0 3C C0 80 42 */ lis r6, lbl_8042323C@ha /* 801D8844 001D44A4 90 01 00 44 */ stw r0, 0x44(r1) /* 801D8848 001D44A8 38 00 00 00 */ li r0, 0 /* 801D884C 001D44AC BF 21 00 24 */ stmw r25, 0x24(r1) /* 801D8850 001D44B0 3B E6 32 3C */ addi r31, r6, lbl_8042323C@l /* 801D8854 001D44B4 7C 9B 23 78 */ mr r27, r4 /* 801D8858 001D44B8 7C BC 2B 78 */ mr r28, r5 /* 801D885C 001D44BC 7C 7A 1B 78 */ mr r26, r3 /* 801D8860 001D44C0 7C FD 3B 78 */ mr r29, r7 /* 801D8864 001D44C4 7F 63 DB 78 */ mr r3, r27 /* 801D8868 001D44C8 80 9F 00 0C */ lwz r4, 0xc(r31) /* 801D886C 001D44CC 81 1F 00 00 */ lwz r8, 0(r31) /* 801D8870 001D44D0 80 DF 00 04 */ lwz r6, 4(r31) /* 801D8874 001D44D4 80 BF 00 08 */ lwz r5, 8(r31) /* 801D8878 001D44D8 91 01 00 08 */ stw r8, 8(r1) /* 801D887C 001D44DC 90 C1 00 0C */ stw r6, 0xc(r1) /* 801D8880 001D44E0 90 A1 00 10 */ stw r5, 0x10(r1) /* 801D8884 001D44E4 90 81 00 14 */ stw r4, 0x14(r1) /* 801D8888 001D44E8 98 1F 00 0D */ stb r0, 0xd(r31) /* 801D888C 001D44EC 48 00 0B 51 */ bl TRKTargetTranslate /* 801D8890 001D44F0 7F A0 00 34 */ cntlzw r0, r29 /* 801D8894 001D44F4 80 9C 00 00 */ lwz r4, 0(r28) /* 801D8898 001D44F8 7C 79 1B 78 */ mr r25, r3 /* 801D889C 001D44FC 54 05 D9 7E */ srwi r5, r0, 5 /* 801D88A0 001D4500 48 00 00 E5 */ bl TRKValidMemory32 /* 801D88A4 001D4504 7C 7E 1B 79 */ or. r30, r3, r3 /* 801D88A8 001D4508 41 82 00 10 */ beq lbl_801D88B8 /* 801D88AC 001D450C 38 00 00 00 */ li r0, 0 /* 801D88B0 001D4510 90 1C 00 00 */ stw r0, 0(r28) /* 801D88B4 001D4514 48 00 00 78 */ b lbl_801D892C lbl_801D88B8: /* 801D88B8 001D4518 4B FF E9 59 */ bl __TRK_get_MSR /* 801D88BC 001D451C 3C 80 80 49 */ lis r4, lbl_80490898@ha /* 801D88C0 001D4520 2C 1D 00 00 */ cmpwi r29, 0 /* 801D88C4 001D4524 38 84 08 98 */ addi r4, r4, lbl_80490898@l /* 801D88C8 001D4528 7C 68 1B 78 */ mr r8, r3 /* 801D88CC 001D452C 80 04 01 F8 */ lwz r0, 0x1f8(r4) /* 801D88D0 001D4530 54 00 06 F6 */ rlwinm r0, r0, 0, 0x1b, 0x1b /* 801D88D4 001D4534 7D 07 03 78 */ or r7, r8, r0 /* 801D88D8 001D4538 41 82 00 1C */ beq lbl_801D88F4 /* 801D88DC 001D453C 80 BC 00 00 */ lwz r5, 0(r28) /* 801D88E0 001D4540 7F 43 D3 78 */ mr r3, r26 /* 801D88E4 001D4544 7F 24 CB 78 */ mr r4, r25 /* 801D88E8 001D4548 7D 06 43 78 */ mr r6, r8 /* 801D88EC 001D454C 4B FF E9 35 */ bl TRK_ppc_memcpy /* 801D88F0 001D4550 48 00 00 3C */ b lbl_801D892C lbl_801D88F4: /* 801D88F4 001D4554 80 BC 00 00 */ lwz r5, 0(r28) /* 801D88F8 001D4558 7F 23 CB 78 */ mr r3, r25 /* 801D88FC 001D455C 7F 44 D3 78 */ mr r4, r26 /* 801D8900 001D4560 7C E6 3B 78 */ mr r6, r7 /* 801D8904 001D4564 7D 07 43 78 */ mr r7, r8 /* 801D8908 001D4568 4B FF E9 19 */ bl TRK_ppc_memcpy /* 801D890C 001D456C 80 9C 00 00 */ lwz r4, 0(r28) /* 801D8910 001D4570 7F 23 CB 78 */ mr r3, r25 /* 801D8914 001D4574 4B FF E7 F1 */ bl TRK_flush_cache /* 801D8918 001D4578 7C 1B C8 40 */ cmplw r27, r25 /* 801D891C 001D457C 41 82 00 10 */ beq lbl_801D892C /* 801D8920 001D4580 80 9C 00 00 */ lwz r4, 0(r28) /* 801D8924 001D4584 7F 63 DB 78 */ mr r3, r27 /* 801D8928 001D4588 4B FF E7 DD */ bl TRK_flush_cache lbl_801D892C: /* 801D892C 001D458C 88 1F 00 0D */ lbz r0, 0xd(r31) /* 801D8930 001D4590 28 00 00 00 */ cmplwi r0, 0 /* 801D8934 001D4594 41 82 00 10 */ beq lbl_801D8944 /* 801D8938 001D4598 38 00 00 00 */ li r0, 0 /* 801D893C 001D459C 3B C0 07 02 */ li r30, 0x702 /* 801D8940 001D45A0 90 1C 00 00 */ stw r0, 0(r28) lbl_801D8944: /* 801D8944 001D45A4 3C 60 80 42 */ lis r3, lbl_8042323C@ha /* 801D8948 001D45A8 80 C1 00 08 */ lwz r6, 8(r1) /* 801D894C 001D45AC 38 E3 32 3C */ addi r7, r3, lbl_8042323C@l /* 801D8950 001D45B0 80 A1 00 0C */ lwz r5, 0xc(r1) /* 801D8954 001D45B4 80 81 00 10 */ lwz r4, 0x10(r1) /* 801D8958 001D45B8 7F C3 F3 78 */ mr r3, r30 /* 801D895C 001D45BC 80 01 00 14 */ lwz r0, 0x14(r1) /* 801D8960 001D45C0 90 C7 00 00 */ stw r6, 0(r7) /* 801D8964 001D45C4 90 A7 00 04 */ stw r5, 4(r7) /* 801D8968 001D45C8 90 87 00 08 */ stw r4, 8(r7) /* 801D896C 001D45CC 90 07 00 0C */ stw r0, 0xc(r7) /* 801D8970 001D45D0 BB 21 00 24 */ lmw r25, 0x24(r1) /* 801D8974 001D45D4 80 01 00 44 */ lwz r0, 0x44(r1) /* 801D8978 001D45D8 7C 08 03 A6 */ mtlr r0 /* 801D897C 001D45DC 38 21 00 40 */ addi r1, r1, 0x40 /* 801D8980 001D45E0 4E 80 00 20 */ blr .global TRKValidMemory32 TRKValidMemory32: /* 801D8984 001D45E4 94 21 FF E0 */ stwu r1, -0x20(r1) /* 801D8988 001D45E8 7C 08 02 A6 */ mflr r0 /* 801D898C 001D45EC 90 01 00 24 */ stw r0, 0x24(r1) /* 801D8990 001D45F0 BF 41 00 08 */ stmw r26, 8(r1) /* 801D8994 001D45F4 7F 64 1A 14 */ add r27, r4, r3 /* 801D8998 001D45F8 3B 7B FF FF */ addi r27, r27, -1 /* 801D899C 001D45FC 7C BA 2B 78 */ mr r26, r5 /* 801D89A0 001D4600 7C 1B 18 40 */ cmplw r27, r3 /* 801D89A4 001D4604 38 A0 07 00 */ li r5, 0x700 /* 801D89A8 001D4608 40 80 00 0C */ bge lbl_801D89B4 /* 801D89AC 001D460C 38 60 07 00 */ li r3, 0x700 /* 801D89B0 001D4610 48 00 02 64 */ b lbl_801D8C14 lbl_801D89B4: /* 801D89B4 001D4614 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha /* 801D89B8 001D4618 38 C0 00 00 */ li r6, 0 /* 801D89BC 001D461C 3B E4 D6 B8 */ addi r31, r4, lbl_803FD6B8@l /* 801D89C0 001D4620 80 1F 00 04 */ lwz r0, 4(r31) /* 801D89C4 001D4624 7C 03 00 40 */ cmplw r3, r0 /* 801D89C8 001D4628 41 81 02 48 */ bgt lbl_801D8C10 /* 801D89CC 001D462C 80 1F 00 00 */ lwz r0, 0(r31) /* 801D89D0 001D4630 7C 1B 00 40 */ cmplw r27, r0 /* 801D89D4 001D4634 41 80 02 3C */ blt lbl_801D8C10 /* 801D89D8 001D4638 2C 1A 00 00 */ cmpwi r26, 0 /* 801D89DC 001D463C 40 82 00 18 */ bne lbl_801D89F4 /* 801D89E0 001D4640 54 C0 20 36 */ slwi r0, r6, 4 /* 801D89E4 001D4644 7C 9F 02 14 */ add r4, r31, r0 /* 801D89E8 001D4648 80 04 00 08 */ lwz r0, 8(r4) /* 801D89EC 001D464C 2C 00 00 00 */ cmpwi r0, 0 /* 801D89F0 001D4650 41 82 00 28 */ beq lbl_801D8A18 lbl_801D89F4: /* 801D89F4 001D4654 2C 1A 00 01 */ cmpwi r26, 1 /* 801D89F8 001D4658 40 82 00 28 */ bne lbl_801D8A20 /* 801D89FC 001D465C 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha /* 801D8A00 001D4660 54 C0 20 36 */ slwi r0, r6, 4 /* 801D8A04 001D4664 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l /* 801D8A08 001D4668 7C 84 02 14 */ add r4, r4, r0 /* 801D8A0C 001D466C 80 04 00 0C */ lwz r0, 0xc(r4) /* 801D8A10 001D4670 2C 00 00 00 */ cmpwi r0, 0 /* 801D8A14 001D4674 40 82 00 0C */ bne lbl_801D8A20 lbl_801D8A18: /* 801D8A18 001D4678 38 A0 07 00 */ li r5, 0x700 /* 801D8A1C 001D467C 48 00 01 F4 */ b lbl_801D8C10 lbl_801D8A20: /* 801D8A20 001D4680 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha /* 801D8A24 001D4684 54 DD 20 36 */ slwi r29, r6, 4 /* 801D8A28 001D4688 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l /* 801D8A2C 001D468C 38 A0 00 00 */ li r5, 0 /* 801D8A30 001D4690 7C 04 E8 2E */ lwzx r0, r4, r29 /* 801D8A34 001D4694 7C 03 00 40 */ cmplw r3, r0 /* 801D8A38 001D4698 40 80 00 E4 */ bge lbl_801D8B1C /* 801D8A3C 001D469C 7C 03 00 50 */ subf r0, r3, r0 /* 801D8A40 001D46A0 38 C0 07 00 */ li r6, 0x700 /* 801D8A44 001D46A4 7F C0 1A 14 */ add r30, r0, r3 /* 801D8A48 001D46A8 3B DE FF FF */ addi r30, r30, -1 /* 801D8A4C 001D46AC 7C 1E 18 40 */ cmplw r30, r3 /* 801D8A50 001D46B0 40 80 00 08 */ bge lbl_801D8A58 /* 801D8A54 001D46B4 48 00 00 C4 */ b lbl_801D8B18 lbl_801D8A58: /* 801D8A58 001D46B8 80 1F 00 04 */ lwz r0, 4(r31) /* 801D8A5C 001D46BC 38 A0 00 00 */ li r5, 0 /* 801D8A60 001D46C0 7C 03 00 40 */ cmplw r3, r0 /* 801D8A64 001D46C4 41 81 00 B4 */ bgt lbl_801D8B18 /* 801D8A68 001D46C8 80 1F 00 00 */ lwz r0, 0(r31) /* 801D8A6C 001D46CC 7C 1E 00 40 */ cmplw r30, r0 /* 801D8A70 001D46D0 41 80 00 A8 */ blt lbl_801D8B18 /* 801D8A74 001D46D4 2C 1A 00 00 */ cmpwi r26, 0 /* 801D8A78 001D46D8 40 82 00 18 */ bne lbl_801D8A90 /* 801D8A7C 001D46DC 54 A0 20 36 */ slwi r0, r5, 4 /* 801D8A80 001D46E0 7C 84 02 14 */ add r4, r4, r0 /* 801D8A84 001D46E4 80 04 00 08 */ lwz r0, 8(r4) /* 801D8A88 001D46E8 2C 00 00 00 */ cmpwi r0, 0 /* 801D8A8C 001D46EC 41 82 00 28 */ beq lbl_801D8AB4 lbl_801D8A90: /* 801D8A90 001D46F0 2C 1A 00 01 */ cmpwi r26, 1 /* 801D8A94 001D46F4 40 82 00 28 */ bne lbl_801D8ABC /* 801D8A98 001D46F8 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha /* 801D8A9C 001D46FC 54 A0 20 36 */ slwi r0, r5, 4 /* 801D8AA0 001D4700 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l /* 801D8AA4 001D4704 7C 84 02 14 */ add r4, r4, r0 /* 801D8AA8 001D4708 80 04 00 0C */ lwz r0, 0xc(r4) /* 801D8AAC 001D470C 2C 00 00 00 */ cmpwi r0, 0 /* 801D8AB0 001D4710 40 82 00 0C */ bne lbl_801D8ABC lbl_801D8AB4: /* 801D8AB4 001D4714 38 C0 07 00 */ li r6, 0x700 /* 801D8AB8 001D4718 48 00 00 60 */ b lbl_801D8B18 lbl_801D8ABC: /* 801D8ABC 001D471C 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha /* 801D8AC0 001D4720 54 BC 20 36 */ slwi r28, r5, 4 /* 801D8AC4 001D4724 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l /* 801D8AC8 001D4728 38 C0 00 00 */ li r6, 0 /* 801D8ACC 001D472C 7C 04 E0 2E */ lwzx r0, r4, r28 /* 801D8AD0 001D4730 7C 03 00 40 */ cmplw r3, r0 /* 801D8AD4 001D4734 40 80 00 14 */ bge lbl_801D8AE8 /* 801D8AD8 001D4738 7F 45 D3 78 */ mr r5, r26 /* 801D8ADC 001D473C 7C 83 00 50 */ subf r4, r3, r0 /* 801D8AE0 001D4740 4B FF FE A5 */ bl TRKValidMemory32 /* 801D8AE4 001D4744 7C 66 1B 78 */ mr r6, r3 lbl_801D8AE8: /* 801D8AE8 001D4748 2C 06 00 00 */ cmpwi r6, 0 /* 801D8AEC 001D474C 40 82 00 2C */ bne lbl_801D8B18 /* 801D8AF0 001D4750 3C 60 80 40 */ lis r3, lbl_803FD6B8@ha /* 801D8AF4 001D4754 38 03 D6 B8 */ addi r0, r3, lbl_803FD6B8@l /* 801D8AF8 001D4758 7C 60 E2 14 */ add r3, r0, r28 /* 801D8AFC 001D475C 80 63 00 04 */ lwz r3, 4(r3) /* 801D8B00 001D4760 7C 1E 18 40 */ cmplw r30, r3 /* 801D8B04 001D4764 40 81 00 14 */ ble lbl_801D8B18 /* 801D8B08 001D4768 7F 45 D3 78 */ mr r5, r26 /* 801D8B0C 001D476C 7C 83 F0 50 */ subf r4, r3, r30 /* 801D8B10 001D4770 4B FF FE 75 */ bl TRKValidMemory32 /* 801D8B14 001D4774 7C 66 1B 78 */ mr r6, r3 lbl_801D8B18: /* 801D8B18 001D4778 7C C5 33 78 */ mr r5, r6 lbl_801D8B1C: /* 801D8B1C 001D477C 2C 05 00 00 */ cmpwi r5, 0 /* 801D8B20 001D4780 40 82 00 F0 */ bne lbl_801D8C10 /* 801D8B24 001D4784 3C 60 80 40 */ lis r3, lbl_803FD6B8@ha /* 801D8B28 001D4788 38 83 D6 B8 */ addi r4, r3, lbl_803FD6B8@l /* 801D8B2C 001D478C 3B 84 00 04 */ addi r28, r4, 4 /* 801D8B30 001D4790 7C 7C E8 2E */ lwzx r3, r28, r29 /* 801D8B34 001D4794 7C 1B 18 40 */ cmplw r27, r3 /* 801D8B38 001D4798 40 81 00 D8 */ ble lbl_801D8C10 /* 801D8B3C 001D479C 7C 03 D8 50 */ subf r0, r3, r27 /* 801D8B40 001D47A0 38 C0 07 00 */ li r6, 0x700 /* 801D8B44 001D47A4 7F C0 1A 14 */ add r30, r0, r3 /* 801D8B48 001D47A8 3B DE FF FF */ addi r30, r30, -1 /* 801D8B4C 001D47AC 7C 1E 18 40 */ cmplw r30, r3 /* 801D8B50 001D47B0 40 80 00 08 */ bge lbl_801D8B58 /* 801D8B54 001D47B4 48 00 00 B8 */ b lbl_801D8C0C lbl_801D8B58: /* 801D8B58 001D47B8 80 1F 00 04 */ lwz r0, 4(r31) /* 801D8B5C 001D47BC 38 A0 00 00 */ li r5, 0 /* 801D8B60 001D47C0 7C 03 00 40 */ cmplw r3, r0 /* 801D8B64 001D47C4 41 81 00 A8 */ bgt lbl_801D8C0C /* 801D8B68 001D47C8 80 1F 00 00 */ lwz r0, 0(r31) /* 801D8B6C 001D47CC 7C 1E 00 40 */ cmplw r30, r0 /* 801D8B70 001D47D0 41 80 00 9C */ blt lbl_801D8C0C /* 801D8B74 001D47D4 2C 1A 00 00 */ cmpwi r26, 0 /* 801D8B78 001D47D8 40 82 00 18 */ bne lbl_801D8B90 /* 801D8B7C 001D47DC 54 A0 20 36 */ slwi r0, r5, 4 /* 801D8B80 001D47E0 7C 84 02 14 */ add r4, r4, r0 /* 801D8B84 001D47E4 80 04 00 08 */ lwz r0, 8(r4) /* 801D8B88 001D47E8 2C 00 00 00 */ cmpwi r0, 0 /* 801D8B8C 001D47EC 41 82 00 28 */ beq lbl_801D8BB4 lbl_801D8B90: /* 801D8B90 001D47F0 2C 1A 00 01 */ cmpwi r26, 1 /* 801D8B94 001D47F4 40 82 00 28 */ bne lbl_801D8BBC /* 801D8B98 001D47F8 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha /* 801D8B9C 001D47FC 54 A0 20 36 */ slwi r0, r5, 4 /* 801D8BA0 001D4800 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l /* 801D8BA4 001D4804 7C 84 02 14 */ add r4, r4, r0 /* 801D8BA8 001D4808 80 04 00 0C */ lwz r0, 0xc(r4) /* 801D8BAC 001D480C 2C 00 00 00 */ cmpwi r0, 0 /* 801D8BB0 001D4810 40 82 00 0C */ bne lbl_801D8BBC lbl_801D8BB4: /* 801D8BB4 001D4814 38 C0 07 00 */ li r6, 0x700 /* 801D8BB8 001D4818 48 00 00 54 */ b lbl_801D8C0C lbl_801D8BBC: /* 801D8BBC 001D481C 3C 80 80 40 */ lis r4, lbl_803FD6B8@ha /* 801D8BC0 001D4820 54 BB 20 36 */ slwi r27, r5, 4 /* 801D8BC4 001D4824 38 84 D6 B8 */ addi r4, r4, lbl_803FD6B8@l /* 801D8BC8 001D4828 38 C0 00 00 */ li r6, 0 /* 801D8BCC 001D482C 7C 04 D8 2E */ lwzx r0, r4, r27 /* 801D8BD0 001D4830 7C 03 00 40 */ cmplw r3, r0 /* 801D8BD4 001D4834 40 80 00 14 */ bge lbl_801D8BE8 /* 801D8BD8 001D4838 7F 45 D3 78 */ mr r5, r26 /* 801D8BDC 001D483C 7C 83 00 50 */ subf r4, r3, r0 /* 801D8BE0 001D4840 4B FF FD A5 */ bl TRKValidMemory32 /* 801D8BE4 001D4844 7C 66 1B 78 */ mr r6, r3 lbl_801D8BE8: /* 801D8BE8 001D4848 2C 06 00 00 */ cmpwi r6, 0 /* 801D8BEC 001D484C 40 82 00 20 */ bne lbl_801D8C0C /* 801D8BF0 001D4850 7C 7C D8 2E */ lwzx r3, r28, r27 /* 801D8BF4 001D4854 7C 1E 18 40 */ cmplw r30, r3 /* 801D8BF8 001D4858 40 81 00 14 */ ble lbl_801D8C0C /* 801D8BFC 001D485C 7F 45 D3 78 */ mr r5, r26 /* 801D8C00 001D4860 7C 83 F0 50 */ subf r4, r3, r30 /* 801D8C04 001D4864 4B FF FD 81 */ bl TRKValidMemory32 /* 801D8C08 001D4868 7C 66 1B 78 */ mr r6, r3 lbl_801D8C0C: /* 801D8C0C 001D486C 7C C5 33 78 */ mr r5, r6 lbl_801D8C10: /* 801D8C10 001D4870 7C A3 2B 78 */ mr r3, r5 lbl_801D8C14: /* 801D8C14 001D4874 BB 41 00 08 */ lmw r26, 8(r1) /* 801D8C18 001D4878 80 01 00 24 */ lwz r0, 0x24(r1) /* 801D8C1C 001D487C 7C 08 03 A6 */ mtlr r0 /* 801D8C20 001D4880 38 21 00 20 */ addi r1, r1, 0x20 /* 801D8C24 001D4884 4E 80 00 20 */ blr /* 801D8C28 001D4888 00 00 00 00 */ .4byte 0x00000000 /* unknown instruction */ /* 801D8C2C 001D488C 00 00 00 00 */ .4byte 0x00000000 /* unknown instruction */ .global $6fill$6 $6fill$6: /* 801D8C30 001D4890 0F E0 00 00 */ twui r0, 0 /* 801D8C34 001D4894 4E 80 00 20 */ blr /* 801D8C38 001D4898 0F E0 00 00 */ twui r0, 0 /* 801D8C3C 001D489C 4E 80 00 20 */ blr /* 801D8C40 001D48A0 0F E0 00 00 */ twui r0, 0 /* 801D8C44 001D48A4 4E 80 00 20 */ blr /* 801D8C48 001D48A8 0F E0 00 00 */ twui r0, 0 /* 801D8C4C 001D48AC 4E 80 00 20 */ blr