initial commit

12 files changed, 6444 insertions, 0 deletions

diff --git a/gcc/config/a29k/a29k.c b/gcc/config/a29k/a29k.c
new file mode 100755
index 0000000..395a6ff
--- /dev/null
+++ b/gcc/config/a29k/a29k.c
@@ -0,0 +1,1538 @@
+/* Subroutines used for code generation on AMD Am29000.
+   Copyright (C) 1987, 88, 90-94, 1995, 1997 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (kenner@nyu.edu)
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#include "config.h"
+#include <stdio.h>
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "recog.h"
+#include "expr.h"
+#include "obstack.h"
+#include "tree.h"
+#include "reload.h"
+
+#define min(A,B)	((A) < (B) ? (A) : (B))
+
+/* This gives the size in words of the register stack for the current
+   procedure.  */
+
+static int a29k_regstack_size;
+
+/* True if the current procedure has a call instruction.  */
+
+static int a29k_makes_calls;
+
+/* This points to the last insn of the insn prologue.  It is set when
+   an insn without a filled delay slot is found near the start of the
+   function.  */
+
+static char *a29k_last_prologue_insn;
+
+/* This points to the first insn that will be in the epilogue.  It is null if
+   no epilogue is required.  */
+
+static char *a29k_first_epilogue_insn;
+
+/* This is nonzero if a a29k_first_epilogue_insn was put in a delay slot.  It
+   indicates that an intermediate label needs to be written.  */
+
+static int a29k_first_epilogue_insn_used;
+
+/* Location to hold the name of the current function.  We need this prolog to
+   contain the tag words prior to the declaration.  So the name must be stored
+   away.  */
+
+char *a29k_function_name;
+
+/* Mapping of registers to debug register numbers.  The only change is
+   for the frame pointer and the register numbers used for the incoming
+   arguments.  */
+
+int a29k_debug_reg_map[FIRST_PSEUDO_REGISTER];
+
+/* Save information from a "cmpxx" operation until the branch or scc is
+   emitted.  */
+
+rtx a29k_compare_op0, a29k_compare_op1;
+int a29k_compare_fp_p;
+
+/* Gives names for registers.  */
+extern char *reg_names[];
+
+/* Returns 1 if OP is a 8-bit constant. */
+
+int
+cint_8_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  return GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffffff00) == 0;
+}
+
+/* Returns 1 if OP is a 16-bit constant.  */
+
+int
+cint_16_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return GET_CODE (op) == CONST_INT && (INTVAL (op) & 0xffff0000) == 0;
+}
+
+/* Returns 1 if OP is a constant that cannot be moved in a single insn.  */
+
+int
+long_const_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  if (! CONSTANT_P (op))
+    return 0;
+
+  if (TARGET_29050 && GET_CODE (op) == CONST_INT
+      && (INTVAL (op) & 0xffff) == 0)
+    return 0;
+
+  return (GET_CODE (op) != CONST_INT
+	  || ((INTVAL (op) & 0xffff0000) != 0
+	      && (INTVAL (op) & 0xffff0000) != 0xffff0000
+	      && INTVAL (op) != 0x80000000));
+}
+
+/* The following four functions detect constants of 0, 8, 16, and 24 used as
+   a position in ZERO_EXTRACT operations.  They can either be the appropriate
+   constant integer or a shift (which will be produced by combine).  */
+
+static int
+shift_constant_operand (op, mode, val)
+     rtx op;
+     enum machine_mode mode;
+     int val;
+{
+  return ((GET_CODE (op) == CONST_INT && INTVAL (op) == val)
+	  || (GET_CODE (op) == ASHIFT
+	      && GET_CODE (XEXP (op, 0)) == CONST_INT
+	      && INTVAL (XEXP (op, 0)) == val / 8
+	      && GET_CODE (XEXP (op, 1)) == CONST_INT
+	      && INTVAL (XEXP (op, 1)) == 3));
+}
+
+int
+const_0_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return shift_constant_operand (op, mode, 0);
+}
+
+int
+const_8_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return shift_constant_operand (op, mode, 8);
+}
+
+int
+const_16_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return shift_constant_operand (op, mode, 16);
+}
+
+int
+const_24_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return shift_constant_operand (op, mode, 24);
+}
+
+/* Returns 1 if OP is a floating-point constant of the proper mode.  */
+
+int
+float_const_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == mode;
+}
+
+/* Returns 1 if OP is a floating-point constant of the proper mode or a
+   general-purpose register.  */
+
+int
+gpc_reg_or_float_constant_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return float_const_operand (op, mode) || gpc_reg_operand (op, mode);
+}
+
+/* Returns 1 if OP is an integer constant of the proper mode or a
+   general-purpose register.  */
+
+int
+gpc_reg_or_integer_constant_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return ((GET_MODE (op) == VOIDmode
+	   && (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE))
+	  || gpc_reg_operand (op, mode));
+}
+     
+/* Returns 1 if OP is a special machine register.  */
+
+int
+spec_reg_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) != REG || GET_MODE (op) != mode)
+    return 0;
+
+  switch (GET_MODE_CLASS (mode))
+    {
+    case MODE_PARTIAL_INT:
+      return REGNO (op) >= R_BP && REGNO (op) <= R_CR;
+    case MODE_INT:
+      return REGNO (op) >= R_Q && REGNO (op) <= R_EXO;
+    default:
+      return 0;
+    }
+}
+
+/* Returns 1 if OP is an accumulator register.  */
+
+int
+accum_reg_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return (GET_CODE (op) == REG
+	  && REGNO (op) >= R_ACU (0) && REGNO (op) <= R_ACU (3));
+}
+
+/* Returns 1 if OP is a normal data register.  */
+
+int
+gpc_reg_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  int regno;
+
+  if (GET_MODE (op) != mode && mode != VOIDmode)
+    return 0;
+
+  if (GET_CODE (op) == REG)
+    regno = REGNO (op);
+  else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
+    {
+      regno = REGNO (SUBREG_REG (op));
+      if (regno < FIRST_PSEUDO_REGISTER)
+	regno += SUBREG_WORD (op);
+    }
+  else
+    return 0;
+
+  return (regno >= FIRST_PSEUDO_REGISTER || regno < R_BP
+	  || (regno >= R_KR (0) && regno <= R_KR (31)));
+}
+
+/* Returns 1 if OP is either an 8-bit constant integer or a general register.
+   If a register, it must be in the proper mode unless MODE is VOIDmode.  */
+
+int
+srcb_operand (op, mode)
+      register rtx op;
+      enum machine_mode mode;
+{
+  if (GET_CODE (op) == CONST_INT
+      && (mode == QImode
+	  || (INTVAL (op) & 0xffffff00) == 0))
+    return 1;
+
+  if (GET_MODE (op) != mode && mode != VOIDmode)
+    return 0;
+
+  return gpc_reg_operand (op, mode);
+}
+
+int
+cmplsrcb_operand (op, mode)
+      register rtx op;
+      enum machine_mode mode;
+{
+  if (GET_CODE (op) == CONST_INT
+      && (mode == QImode
+	  || (INTVAL (op) & 0xffffff00) == 0xffffff00))
+    return 1;
+
+  if (GET_MODE (op) != mode && mode != VOIDmode)
+    return 0;
+
+  return gpc_reg_operand (op, mode);
+}
+
+/* Return 1 if OP is either an immediate or a general register.  This is used
+   for the input operand of mtsr/mtrsim.  */
+
+int
+gpc_reg_or_immediate_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return gpc_reg_operand (op, mode) || immediate_operand (op, mode);
+}
+
+/* Return 1 if OP can be used as the second operand of and AND insn.  This
+   includes srcb_operand and a constant whose complement fits in 8 bits.  */
+
+int
+and_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return (srcb_operand (op, mode)
+	  || (GET_CODE (op) == CONST_INT
+	      && ((unsigned) ((~ INTVAL (op)) & GET_MODE_MASK (mode)) < 256)));
+}
+
+/* Return 1 if OP can be used as the second operand of an ADD insn.
+   This is the same as above, except we use negative, rather than
+   complement.   */
+
+int
+add_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return (srcb_operand (op, mode)
+	  || (GET_CODE (op) == CONST_INT
+	      && ((unsigned) ((- INTVAL (op)) & GET_MODE_MASK (mode)) < 256)));
+}
+
+/* Return 1 if OP is a valid address in a CALL_INSN.  These are a SYMBOL_REF
+   to the current function, all SYMBOL_REFs if TARGET_SMALL_MEMORY, or
+   a sufficiently-small constant.  */
+
+int
+call_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  switch (GET_CODE (op))
+    {
+    case SYMBOL_REF:
+      return (TARGET_SMALL_MEMORY
+	      || (! TARGET_LARGE_MEMORY
+		  && ((GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FLAG (op))
+		      || ! strcmp (XSTR (op, 0), current_function_name))));
+
+    case CONST_INT:
+      return (unsigned HOST_WIDE_INT) INTVAL (op) < 0x40000;
+
+    default:
+      return 0;
+    }
+}
+
+/* Return 1 if OP can be used as the input operand for a move insn.  */
+
+int
+in_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  rtx orig_op = op;
+
+  if (! general_operand (op, mode))
+    return 0;
+
+  while (GET_CODE (op) == SUBREG)
+    op = SUBREG_REG (op);
+
+  switch (GET_CODE (op))
+    {
+    case REG:
+      return 1;
+
+    case MEM:
+      return (GET_MODE_SIZE (mode) >= UNITS_PER_WORD || TARGET_DW_ENABLE);
+
+    case CONST_INT:
+      if (GET_MODE_CLASS (mode) != MODE_INT
+	  && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
+	return 0;
+
+      return 1;
+
+    case CONST:
+    case SYMBOL_REF:
+    case LABEL_REF:
+      return (GET_MODE (op) == mode
+	      || mode == SImode || mode == HImode || mode == QImode);
+
+    case CONST_DOUBLE:
+      return ((GET_MODE_CLASS (mode) == MODE_FLOAT
+	       && mode == GET_MODE (op))
+	      || (GET_MODE (op) == VOIDmode
+		  && GET_MODE_CLASS (mode) == MODE_INT));
+
+    default:
+      return 0;
+    }
+}
+
+/* Return 1 if OP can be used as the output operand for a move insn.  */
+
+int
+out_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  rtx orig_op = op;
+
+  if (! general_operand (op, mode))
+    return 0;
+
+  while (GET_CODE (op) == SUBREG)
+    op = SUBREG_REG (op);
+
+  if (GET_CODE (op) == REG)
+    return (gpc_reg_operand (orig_op, mode)
+	    || spec_reg_operand (orig_op, mode)
+	    || (GET_MODE_CLASS (mode) == MODE_FLOAT
+		&& accum_reg_operand (orig_op, mode)));
+
+  else if (GET_CODE (op) == MEM)
+    return (GET_MODE_SIZE (mode) >= UNITS_PER_WORD || TARGET_DW_ENABLE);
+  else
+    return 0;
+}
+
+/* Return 1 if OP is an item in memory, given that we are in reload.  */
+
+int
+reload_memory_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  int regno = true_regnum (op);
+
+  return (! CONSTANT_P (op)
+	  && (regno == -1
+	      || (GET_CODE (op) == REG
+		  && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
+}
+
+/* Given an object for which reload_memory_operand is true, return the address
+   of the operand, taking into account anything that reload may do.  */
+
+rtx
+a29k_get_reloaded_address (op)
+     rtx op;
+{
+  if (GET_CODE (op) == SUBREG)
+    {
+      if (SUBREG_WORD (op) != 0)
+	abort ();
+
+      op = SUBREG_REG (op);
+    }
+
+  if (GET_CODE (op) == REG)
+    op = reg_equiv_mem[REGNO (op)];
+
+  return find_replacement (&XEXP (op, 0));
+}
+
+/* Subfunction of the following function.  Update the flags of any MEM
+   found in part of X.  */
+
+static void
+a29k_set_memflags_1 (x, in_struct_p, scalar_p, volatile_p, unchanging_p)
+     rtx x;
+     int in_struct_p, scalar_p, volatile_p, unchanging_p;
+{
+  int i;
+
+  switch (GET_CODE (x))
+    {
+    case SEQUENCE:
+    case PARALLEL:
+      for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
+	a29k_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
+			     unchanging_p);
+      break;
+
+    case INSN:
+      a29k_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
+			   unchanging_p);
+      break;
+
+    case SET:
+      a29k_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
+			   unchanging_p);
+      a29k_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p, unchanging_p);
+      break;
+
+    case MEM:
+      MEM_IN_STRUCT_P (x) = in_struct_p;
+      MEM_SCALAR_P (x) = scalar_p;
+      MEM_VOLATILE_P (x) = volatile_p;
+      RTX_UNCHANGING_P (x) = unchanging_p;
+      break;
+    }
+}
+
+/* Given INSN, which is either an INSN or a SEQUENCE generated to
+   perform a memory operation, look for any MEMs in either a SET_DEST or
+   a SET_SRC and copy the in-struct, unchanging, and volatile flags from
+   REF into each of the MEMs found.  If REF is not a MEM, don't do
+   anything.  */
+
+void
+a29k_set_memflags (insn, ref)
+     rtx insn;
+     rtx ref;
+{
+  /* Note that it is always safe to get these flags, though they won't
+     be what we think if REF is not a MEM.  */
+  int in_struct_p = MEM_IN_STRUCT_P (ref);
+  int scalar_p = MEM_IN_SCALAR_P (ref);
+  int volatile_p = MEM_VOLATILE_P (ref);
+  int unchanging_p = RTX_UNCHANGING_P (ref);
+
+  if (GET_CODE (ref) != MEM
+      || (! in_struct_p && ! volatile_p && ! unchanging_p))
+    return;
+
+  a29k_set_memflags_1 (insn, in_struct_p, scalar_p, volatile_p, unchanging_p);
+}
+
+/* Return 1 if OP is a comparison operator that we have in floating-point.  */
+
+int
+fp_comparison_operator (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return ((mode == VOIDmode || mode == GET_MODE (op))
+	  && (GET_CODE (op) == EQ || GET_CODE (op) == GT ||
+	      GET_CODE (op) == GE));
+}
+
+/* Return 1 if OP is a valid branch comparison.  */
+
+int
+branch_operator (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return ((mode == VOIDmode || mode == GET_MODE (op))
+	  && (GET_CODE (op) == GE || GET_CODE (op) == LT));
+}
+
+/* Return 1 if OP is a load multiple operation.  It is known to be a
+   PARALLEL and the first three sections will be tested.  */
+
+int
+load_multiple_operation (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  int count = XVECLEN (op, 0) - 2;
+  int dest_regno;
+  rtx src_addr;
+  int i;
+
+  /* Perform a quick check so we don't blow up below.  */
+  if (count <= 1
+      || GET_CODE (XVECEXP (op, 0, 0)) != SET
+      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
+      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
+    return 0;
+
+  dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
+  src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
+
+  for (i = 1; i < count; i++)
+    {
+      rtx elt = XVECEXP (op, 0, i + 2);
+
+      if (GET_CODE (elt) != SET
+	  || GET_CODE (SET_DEST (elt)) != REG
+	  || GET_MODE (SET_DEST (elt)) != SImode
+	  || REGNO (SET_DEST (elt)) != dest_regno + i
+	  || GET_CODE (SET_SRC (elt)) != MEM
+	  || GET_MODE (SET_SRC (elt)) != SImode
+	  || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
+	  || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
+	  || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
+	  || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
+	return 0;
+    }
+
+  return 1;
+}
+
+/* Similar, but tests for store multiple.  */
+
+int
+store_multiple_operation (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  int num_special = TARGET_NO_STOREM_BUG ? 2 : 1;
+  int count = XVECLEN (op, 0) - num_special;
+  int src_regno;
+  rtx dest_addr;
+  int i;
+
+  /* Perform a quick check so we don't blow up below.  */
+  if (count <= 1
+      || GET_CODE (XVECEXP (op, 0, 0)) != SET
+      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
+      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+    return 0;
+
+  src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
+  dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
+
+  for (i = 1; i < count; i++)
+    {
+      rtx elt = XVECEXP (op, 0, i + num_special);
+
+      if (GET_CODE (elt) != SET
+	  || GET_CODE (SET_SRC (elt)) != REG
+	  || GET_MODE (SET_SRC (elt)) != SImode
+	  || REGNO (SET_SRC (elt)) != src_regno + i
+	  || GET_CODE (SET_DEST (elt)) != MEM
+	  || GET_MODE (SET_DEST (elt)) != SImode
+	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
+	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
+	  || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
+	  || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
+	return 0;
+    }
+
+  return 1;
+}
+
+/* Given a special register REG and MASK, a value being masked against a
+   quantity to which the special register is set, return 1 if the masking
+   operation is built-in to the setting of that special register.  */
+
+int
+masks_bits_for_special (reg, mask)
+     rtx reg;
+     rtx mask;
+{
+   int needed_mask_value;
+
+  if (GET_CODE (reg) != REG || GET_CODE (mask) != CONST_INT)
+    abort ();
+
+  switch (REGNO (reg))
+    {
+    case R_BP:
+    case R_INT:
+      needed_mask_value = 3;
+      break;
+
+    case R_FC:
+      needed_mask_value = 31;
+      break;
+
+    case R_CR:
+    case R_LRU:
+      needed_mask_value = 255;
+      break;
+
+    case R_FPE:
+      needed_mask_value = 511;
+      break;
+
+    case R_MMU:
+      needed_mask_value = 0x3ff;
+      break;
+
+    case R_OPS:
+    case R_CPS:
+    case R_RBP:
+    case R_FPS:
+      needed_mask_value = 0xffff;
+      break;
+
+    case R_VAB:
+      needed_mask_value = 0xffff0000;
+      break;
+
+    case R_Q:
+    case R_CFG:
+    case R_CHA:
+    case R_CHD:
+    case R_CHC:
+    case R_TMC:
+    case R_TMR:
+    case R_PC0:
+    case R_PC1:
+    case R_PC2:
+      return 0;
+
+    default:
+      abort ();
+    }
+
+   return (INTVAL (mask) & ~ needed_mask_value) == 0;
+}
+
+/* Return nonzero if this label is that of the return point, but there is
+   a non-null epilogue.  */
+
+int
+epilogue_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return next_active_insn (op) == 0 && a29k_first_epilogue_insn != 0;
+}
+
+/* Return the register class of a scratch register needed to copy IN into
+   or out of a register in CLASS in MODE.  If it can be done directly,
+   NO_REGS is returned.  */
+
+enum reg_class
+secondary_reload_class (class, mode, in)
+     enum reg_class class;
+     enum machine_mode mode;
+     rtx in;
+{
+  int regno = -1;
+  enum rtx_code code = GET_CODE (in);
+
+  if (! CONSTANT_P (in))
+    {
+      regno = true_regnum (in);
+
+      /* A pseudo is the same as memory.  */
+      if (regno == -1 || regno >= FIRST_PSEUDO_REGISTER)
+	code = MEM;
+    }
+
+  /* If we are transferring between memory and a multi-word mode, we need
+     CR.  */
+
+  if (code == MEM && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+    return CR_REGS;
+
+  /* If between memory and a mode smaller than a word without DW being
+     enabled, we need BP.  */
+
+  if (code == MEM && ! TARGET_DW_ENABLE
+      && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
+    return BP_REGS;
+
+  /* Otherwise, we can place anything into GENERAL_REGS and can put
+     GENERAL_REGS into anything.  */
+  if (class == GENERAL_REGS
+      || (regno != -1
+	  && (regno < R_BP
+	      || (regno >= R_KR (0) && regno <= R_KR (31)))))
+    return NO_REGS;
+
+  /* We can place 16-bit constants into a special register.  */
+  if (code == CONST_INT
+      && (GET_MODE_BITSIZE (mode) <= 16 || (unsigned) INTVAL (in) <= 65535)
+      && (class == BP_REGS || class == Q_REGS || class == SPECIAL_REGS))
+    return NO_REGS;
+
+  /* Otherwise, we need GENERAL_REGS.  */
+  return GENERAL_REGS;
+}
+
+/* START is the zero-based incoming argument register index used (0 is 160,
+   i.e., the first incoming argument register) and COUNT is the number used.
+
+   Mark the corresponding incoming registers as neither fixed nor call used.
+   For each register used for incoming arguments, we have one less local
+   register that can be used.  So also mark some high-numbered registers as
+   fixed.
+
+   Return the first register number to use for the argument.  */
+
+int
+incoming_reg (start, count)
+     int start;
+     int count;
+{
+  int i;
+
+  /* We only use 16 argument registers, so truncate at the end of the
+     area.  */
+  if (start + count > 16)
+    count = 16 - start;
+
+  if (! TARGET_NO_REUSE_ARGS)
+    /* Mark all the used registers as not fixed and saved over calls.  */
+    for (i = R_AR (start); i < R_AR (start + count); i++)
+      {
+	fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 0;
+	CLEAR_HARD_REG_BIT (fixed_reg_set, i);
+	CLEAR_HARD_REG_BIT (call_used_reg_set, i);
+	CLEAR_HARD_REG_BIT (call_fixed_reg_set, i);
+      }
+
+  /* Shorten the maximum size of the frame.
+     Remember that R_AR(-1,-2) are place holders for the caller's lr0,lr1.
+     Make sure to keep the frame rounded to an even boundary.  Rounding up
+     to an 8 byte boundary will use a slot.  Otherwise a frame with 121 local
+     regs and 5 arguments will overrun the stack (121+1 + 5 + 2 > 128).  */
+  /* ??? An alternative would be to never allocate one reg.  */
+  for (i = (R_AR (0) - 2 - start - count) & ~1; i < R_AR (0) - 2 - start; i++)
+    {
+      fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
+      SET_HARD_REG_BIT (fixed_reg_set, i);
+      SET_HARD_REG_BIT (call_used_reg_set, i);
+      SET_HARD_REG_BIT (call_fixed_reg_set, i);
+    }
+
+  return R_AR (start);
+}
+
+/* Add CLOBBERs to CALL_INSN_FUNCTION_USAGE chain of INSN indicating
+   that LR2 up to, but not including, OP are clobbered.  If OP is
+   zero, indicate all parameter registers are clobbered.  */
+
+void
+a29k_clobbers_to (insn, op)
+     rtx insn;
+     rtx op;
+{
+  int i;
+  int high_regno;
+
+  if (op == 0)
+    high_regno = R_LR (18);
+  else if (GET_CODE (op) != REG || REGNO (op) < R_LR (0)
+	   || REGNO (op) > R_LR (18))
+    abort ();
+  else
+    high_regno = REGNO (op);
+
+  for (i = R_LR (2); i < high_regno; i++)
+    CALL_INSN_FUNCTION_USAGE (insn)
+      = gen_rtx (EXPR_LIST, VOIDmode,
+		 gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, i)),
+		 CALL_INSN_FUNCTION_USAGE (insn));
+}
+
+/* These routines are used in finding insns to fill delay slots in the
+   epilogue.  */
+
+/* Return 1 if the current function will adjust the register stack.  */
+
+int
+needs_regstack_p ()
+{
+  int i;
+  rtx insn;
+
+  if (frame_pointer_needed)
+    return 1;
+
+  /* If any local register is used, we need to adjust the regstack.  */
+  for (i = R_LR (127); i >= R_LR (0); i --)
+    if (regs_ever_live[i])
+      return 1;
+
+  /* We need a register stack if we make any calls.  */
+  for (insn = get_insns (); insn; insn = next_insn (insn))
+    if (GET_CODE (insn) == CALL_INSN
+	|| (GET_CODE (insn) == INSN
+	    && GET_CODE (PATTERN (insn)) == SEQUENCE
+	    && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN))
+      return 1;
+
+  /* Otherwise, we don't.  */
+  return 0;
+}
+
+/* Return 1 if X uses a local register.  */
+
+int
+uses_local_reg_p (x)
+     rtx x;
+{
+  char *fmt;
+  int i, j;
+
+  switch (GET_CODE (x))
+    {
+    case REG:
+      return REGNO (x) >= R_LR (0) && REGNO (x) <= R_FP;
+
+    case CONST_INT:
+    case CONST:
+    case PC:
+    case CC0:
+    case LABEL_REF:
+    case SYMBOL_REF:
+      return 0;
+    }
+
+  fmt = GET_RTX_FORMAT (GET_CODE (x));
+  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'e')
+	{
+	  if (uses_local_reg_p (XEXP (x, i)))
+	    return 1;
+	}
+      else if (fmt[i] == 'E')
+	{
+	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
+	    if (uses_local_reg_p (XVECEXP (x, i, j)))
+	      return 1;
+	}
+    }
+
+  return 0;
+}
+
+/* Returns 1 if this function is known to have a null epilogue.  */
+
+int
+null_epilogue ()
+{
+  return (reload_completed && ! needs_regstack_p ()
+	  && get_frame_size () == 0
+	  && current_function_pretend_args_size == 0);
+}
+
+/* Write out the assembler form of an operand.  Recognize the following
+   special options:
+
+	%N means write the low-order 8 bits of the negative of the constant
+	%Q means write a QImode operand (truncate constants to 8 bits)
+	%M means write the low-order 16 bits of the constant
+	%m means write the low-order 16 bits shifted left 16 bits
+	%C means write the low-order 8 bits of the complement of the constant
+	%b means write `f' is this is a reversed condition, `t' otherwise
+	%B means write `t' is this is a reversed condition, `f' otherwise
+	%J means write the 29k opcode part for a comparison operation
+	%e means write the label with an extra `X' is this is the epilogue
+	               otherwise the normal label name
+	%E means write nothing if this insn has a delay slot,
+		       a nop unless this is the epilogue label, in which case
+		       write the first epilogue insn
+	%F means write just the normal operand if the insn has a delay slot;
+		       otherwise, this is a recursive call so output the
+		       symbol + 4 and write the first prologue insn in the
+		       delay slot.
+	%L means write the register number plus one ("low order" register)
+		       or the low-order part of a multi-word constant
+	%O means write the register number plus two
+	%P means write the register number plus three ("low order" of TImode)
+	%S means write the number of words in the mode of the operand,
+		       minus one (for CR)
+        %V means write the number of elements in a PARALLEL minus 1
+	%# means write nothing if we have a delay slot, "\n\tnop" otherwise
+	%* means write the register name for TPC.  */
+
+void
+print_operand (file, x, code)
+     FILE *file;
+     rtx x;
+     char code;
+{
+  char buf[100];
+
+  /* These macros test for integers and extract the low-order bits.  */
+#define INT_P(X)  \
+((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE)	\
+ && GET_MODE (X) == VOIDmode)
+
+#define INT_LOWPART(X) \
+  (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
+
+  switch (code)
+    {
+    case 'Q':
+      if (GET_CODE (x) == REG)
+	break;
+      else if (! INT_P (x))
+	output_operand_lossage ("invalid %%Q value");
+      fprintf (file, "%d", INT_LOWPART (x) & 0xff);
+      return;
+
+    case 'C':
+      if (! INT_P (x))
+	output_operand_lossage ("invalid %%C value");
+      fprintf (file, "%d", (~ INT_LOWPART (x)) & 0xff);
+      return;
+
+    case 'N':
+      if (! INT_P (x))
+	output_operand_lossage ("invalid %%N value");
+      fprintf (file, "%d", (- INT_LOWPART (x)) & 0xff);
+      return;
+
+    case 'M':
+      if (! INT_P (x))
+	output_operand_lossage ("invalid %%M value");
+      fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
+      return;
+
+    case 'm':
+      if (! INT_P (x))
+	output_operand_lossage ("invalid %%m value");
+      fprintf (file, "%d", (INT_LOWPART (x) & 0xffff) << 16);
+      return;
+
+    case 'b':
+      if (GET_CODE (x) == GE)
+	fprintf (file, "f");
+      else
+	fprintf (file, "t");
+      return;
+
+    case 'B':
+      if (GET_CODE (x) == GE)
+	fprintf (file, "t");
+      else
+	fprintf (file, "f");
+      return;
+
+    case 'J':
+      /* It so happens that the RTX names for the conditions are the same as
+	 the 29k's insns except for "ne", which requires "neq".  */
+      fprintf (file, GET_RTX_NAME (GET_CODE (x)));
+      if (GET_CODE (x) == NE)
+	fprintf (file, "q");
+      return;
+
+    case 'e':
+      if (optimize && flag_delayed_branch
+	  && a29k_last_prologue_insn == 0 && epilogue_operand (x, VOIDmode)
+	  && dbr_sequence_length () == 0)
+	{
+	  /* We need to output the label number of the last label in the
+	     function, which is not necessarily X since there might be
+	     a USE insn in between.  First go forward to the last insn, then
+	     back up to a label.  */
+	  while (NEXT_INSN (x) != 0)
+	    x = NEXT_INSN (x);
+
+	  while (GET_CODE (x) != CODE_LABEL)
+	    x = PREV_INSN (x);
+
+	  ASM_GENERATE_INTERNAL_LABEL (buf, "LX", CODE_LABEL_NUMBER (x));
+	  assemble_name (file, buf);
+	}
+      else
+	output_asm_label (x);
+      return;
+
+    case 'E':
+      if (dbr_sequence_length ())
+	;
+      else if (a29k_last_prologue_insn)
+	{
+	  fprintf (file, "\n\t%s", a29k_last_prologue_insn);
+	  a29k_last_prologue_insn = 0;
+	}
+      else if (optimize && flag_delayed_branch
+	       && epilogue_operand (x, VOIDmode))
+	{
+	  fprintf (file, "\n\t%s", a29k_first_epilogue_insn);
+	  a29k_first_epilogue_insn_used = 1;
+	}
+      else
+	fprintf (file, "\n\tnop");
+      return;
+      
+    case 'F':
+      output_addr_const (file, x);
+      if (dbr_sequence_length () == 0)
+	{
+	  /* If this doesn't have its delay slot filled, see if we need to
+	     put the last insn of the prolog in it.  If not, see if this is
+	     a recursive call.  If so, we can put the first insn of its
+	     prolog in the delay slot.  Otherwise, write a nop.  */
+	  if (a29k_last_prologue_insn)
+	    {
+	      fprintf (file, "\n\t%s", a29k_last_prologue_insn);
+	      a29k_last_prologue_insn = 0;
+	    }
+	  else if (GET_CODE (x) == SYMBOL_REF
+	      && ! strcmp (XSTR (x, 0), current_function_name))
+	    fprintf (file, "+4\n\t%s,%d",
+		     a29k_regstack_size >= 64 ? "const gr121" : "sub gr1,gr1",
+		     a29k_regstack_size * 4);
+	  else
+	    fprintf (file, "\n\tnop");
+	}
+      return;
+
+    case 'L':
+      if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
+	{
+	  union real_extract u;
+
+	  bcopy ((char *) &CONST_DOUBLE_LOW (x), (char *) &u, sizeof u);
+	  fprintf (file, "$double1(%.20e)", u.d);
+	}
+      else if (GET_CODE (x) == REG)
+	fprintf (file, "%s", reg_names[REGNO (x) + 1]);
+      else
+	output_operand_lossage ("invalid %%L value");
+      return;
+
+    case 'O':
+      if (GET_CODE (x) != REG)
+	output_operand_lossage ("invalid %%O value");
+      fprintf (file, "%s", reg_names[REGNO (x) + 2]);
+      return;
+
+    case 'P':
+      if (GET_CODE (x) != REG)
+	output_operand_lossage ("invalid %%P value");
+      fprintf (file, "%s", reg_names[REGNO (x) + 3]);
+      return;
+
+    case 'S':
+      fprintf (file, "%d", (GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD)-1);
+      return;
+
+    case 'V':
+      if (GET_CODE (x) != PARALLEL)
+	output_operand_lossage ("invalid %%V value");
+      fprintf (file, "%d", XVECLEN (x, 0) - 2);
+      return;
+
+    case '#':
+      if (dbr_sequence_length () == 0)
+	{
+	  if (a29k_last_prologue_insn)
+	    {
+	      fprintf (file, "\n\t%s", a29k_last_prologue_insn);
+	      a29k_last_prologue_insn = 0;
+	    }
+	  else
+	    fprintf (file, "\n\tnop");
+	}
+      return;
+
+    case '*':
+      fprintf (file, "%s", reg_names [R_TPC]);
+      return;
+    }
+
+  if (GET_CODE (x) == REG)
+    fprintf (file, "%s", reg_names [REGNO (x)]);
+
+  else if (GET_CODE (x) == MEM)
+    output_address (XEXP (x, 0));
+
+  else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == SUBREG
+	   && GET_CODE (SUBREG_REG (XEXP (x, 0))) == CONST_DOUBLE)
+    {
+      union real_extract u;
+
+      if (GET_MODE (SUBREG_REG (XEXP (x, 0))) == SFmode)
+	fprintf (file, "$float");
+      else
+	fprintf (file, "$double%d", SUBREG_WORD (XEXP (x, 0)));
+      bcopy ((char *) &CONST_DOUBLE_LOW (SUBREG_REG (XEXP (x, 0))),
+	     (char *) &u, sizeof u);
+      fprintf (file, "(%.20e)", u.d);
+    }
+
+  else if (GET_CODE (x) == CONST_DOUBLE
+	   && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
+    {
+      union real_extract u;
+
+      bcopy ((char *) &CONST_DOUBLE_LOW (x), (char *) &u, sizeof u);
+      fprintf (file, "$%s(%.20e)",
+	       GET_MODE (x) == SFmode ? "float" : "double0", u.d);
+    }
+
+  else
+    output_addr_const (file, x);
+}
+
+/* This page contains routines to output function prolog and epilog code. */
+
+/* Compute the size of the register stack, and determine if there are any
+   call instructions.  */
+
+static void
+compute_regstack_size ()
+{
+  int i;
+  rtx insn;
+
+  /* See if we make any calls.  We need to set lr1 if so.  */
+  a29k_makes_calls = 0;
+  for (insn = get_insns (); insn; insn = next_insn (insn))
+    if (GET_CODE (insn) == CALL_INSN
+	|| (GET_CODE (insn) == INSN
+	    && GET_CODE (PATTERN (insn)) == SEQUENCE
+	    && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == CALL_INSN))
+      {
+	a29k_makes_calls = 1;
+	break;
+      }
+
+  /* Find the highest local register used.  */
+  for (i = R_LR (127); i >= R_LR (0); i--)
+    if (regs_ever_live[i])
+      break;
+
+  a29k_regstack_size = i - (R_LR (0) - 1);
+
+  /* If calling routines, ensure we count lr0 & lr1.  */
+  if (a29k_makes_calls && a29k_regstack_size < 2)
+    a29k_regstack_size = 2;
+
+  /* Count frame pointer and align to 8 byte boundary (even number of
+     registers).  */
+  a29k_regstack_size += frame_pointer_needed;
+  if (a29k_regstack_size & 1) a29k_regstack_size++;
+}
+
+/*  Sets register names for incoming arguments and frame pointer.
+    This can't be computed until after register allocation.  */
+
+void
+a29k_compute_reg_names ()
+{
+  int i;
+
+  compute_regstack_size ();
+
+  /* Set the names and numbers of the frame pointer and incoming argument
+     registers.  */
+
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    a29k_debug_reg_map[i] = i;
+
+  reg_names[FRAME_POINTER_REGNUM] = reg_names[R_LR (a29k_regstack_size - 1)];
+  a29k_debug_reg_map[FRAME_POINTER_REGNUM] = R_LR (a29k_regstack_size - 1);
+
+  for (i = 0; i < 16; i++)
+    {
+      reg_names[R_AR (i)] = reg_names[R_LR (a29k_regstack_size + i + 2)];
+      a29k_debug_reg_map[R_AR (i)] = R_LR (a29k_regstack_size + i + 2);
+    }
+
+  /* If using kernel register map, swap numbers for kernel and user
+     registers.  */
+  if (TARGET_KERNEL_REGISTERS)
+    for (i = 0; i < 32; i++)
+      {
+	int tem = a29k_debug_reg_map[i];
+	a29k_debug_reg_map[i] = a29k_debug_reg_map[R_KR (i)];
+	a29k_debug_reg_map[R_KR (i)] = tem;
+      }
+}
+
+/* Output function prolog code to file FILE.  Memory stack size is SIZE.  */
+
+void
+output_prolog (file, size)
+     FILE *file;
+     int size;
+{
+  int i;
+  int arg_count = 0;
+  rtx insn;
+  unsigned int tag_word;
+
+  /* See how many incoming arguments we have in registers.  */
+  for (i = R_AR (0); i < R_AR (16); i++)
+    if (! fixed_regs[i])
+      arg_count++;
+
+  /* The argument count includes the caller's lr0 and lr1.  */
+  arg_count += 2;
+
+  /* Compute memory stack size.  Add in number of bytes that the we should
+     push and pretend the caller did and the size of outgoing arguments.
+     Then round to a doubleword boundary.  */
+  size += (current_function_pretend_args_size
+	   + current_function_outgoing_args_size);
+  size = (size + 7) & ~7;
+
+  /* Write header words.  See if one or two word form.  */
+  tag_word = (frame_pointer_needed ? 0x400000 : 0) + (arg_count << 16);
+
+  if (size / 8 > 0xff)
+    fprintf (file, "\t.word %d, 0x%0x\n", (size / 8) << 2,
+	     0x800000 + tag_word);
+  else
+    fprintf (file, "\t.word 0x%0x\n", tag_word + ((size / 8) << 3));
+
+  /* Define the function name.  */
+  assemble_name (file, a29k_function_name);
+  fprintf (file, ":\n");
+
+  /* Push the register stack by the proper amount.  There are two possible
+     ways to do this.  */
+  if (a29k_regstack_size >= 256/4)
+    fprintf (file, "\tconst %s,%d\n\tsub gr1,gr1,%s\n",
+	     reg_names[R_TAV], a29k_regstack_size * 4, reg_names[R_TAV]);
+  else if (a29k_regstack_size)
+    fprintf (file, "\tsub gr1,gr1,%d\n", a29k_regstack_size * 4);
+
+  /* Test that the registers are available.  */
+  if (a29k_regstack_size)
+    fprintf (file, "\tasgeu V_%sSPILL,gr1,%s\n",
+	     TARGET_KERNEL_REGISTERS ? "K" : "", reg_names[R_RAB]);
+
+  /* Set up frame pointer, if one is needed.  */
+  if (frame_pointer_needed)
+    fprintf (file, "\tsll %s,%s,0\n", reg_names[FRAME_POINTER_REGNUM],
+	     reg_names[R_MSP]);
+
+  /* Make room for any frame space.  There are three ways to do this.  */
+  if (size >= 256)
+    {
+      fprintf (file, "\tconst %s,%d\n", reg_names[R_TAV], size);
+      if (size >= 65536)
+	fprintf (file, "\tconsth %s,%d\n", reg_names[R_TAV], size);
+      if (TARGET_STACK_CHECK)
+	fprintf (file, "\tcall %s,__msp_check\n", reg_names[R_TPC]);
+      fprintf (file, "\tsub %s,%s,%s\n",
+	       reg_names[R_MSP], reg_names[R_MSP], reg_names[R_TAV]);
+    }
+  else if (size)
+    {
+      if (TARGET_STACK_CHECK)
+	fprintf (file, "\tcall %s,__msp_check\n", reg_names[R_TPC]);
+      fprintf (file, "\tsub %s,%s,%d\n",
+	       reg_names[R_MSP], reg_names[R_MSP], size);
+    }
+
+  /* If this routine will make calls, set lr1.  If we see an insn that
+     can use a delay slot before a call or jump, save this insn for that
+     slot (this condition is equivalent to seeing if we have an insn that
+     needs delay slots before an insn that has a filled delay slot).  */
+  a29k_last_prologue_insn = 0;
+  if (a29k_makes_calls)
+    {
+      i = (a29k_regstack_size + arg_count) * 4;
+      if (i >= 256)
+	fprintf (file, "\tconst %s,%d\n\tadd lr1,gr1,%s\n",
+		 reg_names[R_TAV], i, reg_names[R_TAV]);
+      else
+	{
+	  if (optimize && flag_delayed_branch)
+	    for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+	      {
+		if (GET_CODE (insn) == CODE_LABEL
+		    || (GET_CODE (insn) == INSN
+			&& GET_CODE (PATTERN (insn)) == SEQUENCE))
+		  break;
+
+		if (GET_CODE (insn) == NOTE
+		    || (GET_CODE (insn) == INSN
+			&& (GET_CODE (PATTERN (insn)) == USE
+			    || GET_CODE (PATTERN (insn)) == CLOBBER)))
+		  continue;
+
+		if (num_delay_slots (insn) > 0)
+		  {
+		    a29k_last_prologue_insn = (char *) oballoc (100);
+		    sprintf (a29k_last_prologue_insn, "add lr1,gr1,%d", i);
+		    break;
+		  }
+	      }
+
+	  if (a29k_last_prologue_insn == 0)
+	    fprintf (file, "\tadd lr1,gr1,%d\n", i);
+	}
+    }
+
+  /* Compute the first insn of the epilogue.  */
+  a29k_first_epilogue_insn_used = 0;
+
+  if (size == 0 && a29k_regstack_size == 0 && ! frame_pointer_needed)
+    a29k_first_epilogue_insn = 0;
+  else
+    a29k_first_epilogue_insn = (char *) oballoc (100);
+
+  if (frame_pointer_needed)
+    sprintf (a29k_first_epilogue_insn, "sll %s,%s,0",
+	     reg_names[R_MSP], reg_names[FRAME_POINTER_REGNUM]);
+  else if (a29k_regstack_size)
+    {
+      if (a29k_regstack_size >= 256 / 4)
+	sprintf (a29k_first_epilogue_insn, "const %s,%d",
+		 reg_names[R_TAV], a29k_regstack_size * 4);
+      else
+	sprintf (a29k_first_epilogue_insn, "add gr1,gr1,%d",
+		 a29k_regstack_size * 4);
+    }
+  else if (size)
+    {
+      if (size >= 256)
+	sprintf (a29k_first_epilogue_insn, "const %s,%d",
+		 reg_names[R_TAV], size);
+      else
+	sprintf (a29k_first_epilogue_insn, "add %s,%s,%d",
+		 reg_names[R_MSP], reg_names[R_MSP], size);
+    }
+}
+
+/* Call this after writing what might be the first instruction of the
+   epilogue.  If that first insn was used in a delay slot, an intermediate
+   label is written.  */
+
+static void
+check_epilogue_internal_label (file)
+     FILE *file;
+{
+  rtx insn;
+
+  if (! a29k_first_epilogue_insn_used)
+    return;
+
+  for (insn = get_last_insn ();
+       GET_CODE (insn) != CODE_LABEL;
+       insn = PREV_INSN (insn))
+    ;
+
+  ASM_OUTPUT_INTERNAL_LABEL (file, "LX", CODE_LABEL_NUMBER (insn));
+  a29k_first_epilogue_insn_used = 0;
+}
+
+/* Output the epilog of the last procedure to file FILE.  SIZE is the memory
+   stack size.  The register stack size is in the variable
+   A29K_REGSTACK_SIZE.  */
+
+void
+output_epilog (file, size)
+     FILE *file;
+     int size;
+{
+  rtx insn;
+  int locals_unavailable = 0;	/* True until after first insn
+				   after gr1 update. */
+
+  /* If we hit a BARRIER before a real insn or CODE_LABEL, we don't
+     need to do anything because we are never jumped to.  */
+  insn = get_last_insn ();
+  if (GET_CODE (insn) == NOTE)
+    insn = prev_nonnote_insn (insn);
+
+  if (insn && GET_CODE (insn) == BARRIER)
+    return;
+
+  /* If a frame pointer was needed we must restore the memory stack pointer
+     before adjusting the register stack.  */
+  if (frame_pointer_needed)
+    {
+      fprintf (file, "\tsll %s,%s,0\n",
+	       reg_names[R_MSP], reg_names[FRAME_POINTER_REGNUM]);
+      check_epilogue_internal_label (file);
+    }
+
+  /* Restore the register stack.  There are two ways to do this.  */
+  if (a29k_regstack_size)
+    {
+      if (a29k_regstack_size >= 256/4)
+	{
+	  fprintf (file, "\tconst %s,%d\n",
+		   reg_names[R_TAV], a29k_regstack_size * 4);
+	  check_epilogue_internal_label (file);
+	  fprintf (file, "\tadd gr1,gr1,%s\n", reg_names[R_TAV]);
+	}
+      else
+	{
+	  fprintf (file, "\tadd gr1,gr1,%d\n", a29k_regstack_size * 4);
+	  check_epilogue_internal_label (file);
+	}
+      locals_unavailable = 1;
+    }
+
+  /* Restore the memory stack pointer if there is no frame pointer.
+     Adjust the size to include any pretend arguments and pushed
+     arguments and round to doubleword boundary.  */
+  size += (current_function_pretend_args_size
+	   + current_function_outgoing_args_size);
+  size = (size + 7) & ~7;
+
+  if (size && ! frame_pointer_needed)
+    {
+      if (size >= 256)
+	{
+	  fprintf (file, "\tconst %s,%d\n", reg_names[R_TAV], size);
+	  check_epilogue_internal_label (file);
+	  locals_unavailable = 0;
+	  if (size >= 65536)
+	    fprintf (file, "\tconsth %s,%d\n", reg_names[R_TAV], size);
+	  fprintf (file, "\tadd %s,%s,%s\n",
+		   reg_names[R_MSP], reg_names[R_MSP], reg_names[R_TAV]);
+	}
+      else
+	{
+	  fprintf (file, "\tadd %s,%s,%d\n",
+		   reg_names[R_MSP], reg_names[R_MSP], size);
+	  check_epilogue_internal_label (file);
+	  locals_unavailable = 0;
+	}
+    }
+
+  if (locals_unavailable)
+    {
+      /* If we have an insn for this delay slot, write it.  */
+      if (current_function_epilogue_delay_list)
+	final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
+			 file, 1, -2, 1);
+      else
+	fprintf (file, "\tnop\n");
+    }
+
+  fprintf (file, "\tjmpi lr0\n");
+  if (a29k_regstack_size)
+    fprintf (file, "\tasleu V_%sFILL,lr1,%s\n",
+	     TARGET_KERNEL_REGISTERS ? "K" : "", reg_names[R_RFB]);
+  else if (current_function_epilogue_delay_list)
+    final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
+		     file, 1, -2, 1);
+  else
+    fprintf (file, "\tnop\n");
+}
diff --git a/gcc/config/a29k/a29k.h b/gcc/config/a29k/a29k.h
new file mode 100755
index 0000000..acff143
--- /dev/null
+++ b/gcc/config/a29k/a29k.h
@@ -0,0 +1,1673 @@
+/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU.
+   Copyright (C) 1988, 90-97, 1998 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (kenner@nyu.edu)
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#define CPP_PREDEFINES "-D_AM29K -D_AM29000 -D_EPI -Acpu(a29k) -Amachine(a29k)"
+
+/* Print subsidiary information on the compiler version in use.  */
+#define TARGET_VERSION
+
+/* Pass -w to assembler.  */
+#define ASM_SPEC "-w"
+
+/* Run-time compilation parameters selecting different hardware subsets.  */
+
+extern int target_flags;
+
+/* Macro to define tables used to set the flags.
+   This is a list in braces of pairs in braces,
+   each pair being { "NAME", VALUE }
+   where VALUE is the bits to set or minus the bits to clear.
+   An empty string NAME is used to identify the default VALUE.  */
+
+/* This means that the DW bit will be enabled, to allow direct loads
+   of bytes.  */
+
+#define TARGET_DW_ENABLE	(target_flags & 1)
+
+/* This means that the external hardware does supports byte writes.  */
+
+#define TARGET_BYTE_WRITES	(target_flags & 2)
+
+/* This means that a "small memory model" has been selected where all
+   function addresses are known to be within 256K.  This allows CALL to be
+   used.  */
+
+#define TARGET_SMALL_MEMORY	(target_flags & 4)
+
+/* This means that we must always used on indirect call, even when
+   calling a function in the same file, since the file might be > 256KB.  */
+
+#define TARGET_LARGE_MEMORY	(target_flags & 8)
+
+/* This means that we are compiling for a 29050.  */
+
+#define TARGET_29050		(target_flags & 16)
+
+/* This means that we are compiling for the kernel which means that we use
+   gr64-gr95 instead of gr96-126.  */
+
+#define TARGET_KERNEL_REGISTERS	(target_flags & 32)
+
+/* This means that a call to "__msp_check" should be inserted after each stack
+   adjustment to check for stack overflow.  */
+
+#define TARGET_STACK_CHECK	(target_flags & 64)
+
+/* This handles 29k processors which cannot handle the separation
+   of a mtsrim insns and a storem insn (most 29000 chips to date, but
+   not the 29050.  */
+
+#define TARGET_NO_STOREM_BUG	(target_flags & 128)
+
+/* This forces the compiler not to use incoming argument registers except
+   for copying out arguments.  It helps detect problems when a function is
+   called with fewer arguments than it is declared with.  */
+
+#define TARGET_NO_REUSE_ARGS	(target_flags & 256)
+
+/* This means that neither builtin nor emulated float operations are
+   available, and that GCC should generate libcalls instead. */
+
+#define TARGET_SOFT_FLOAT	(target_flags & 512)
+
+/* This means that we should not emit the multm or mutmu instructions
+   that some embedded systems' trap handlers don't support.  */
+
+#define TARGET_MULTM		((target_flags & 1024) == 0)
+
+#define TARGET_SWITCHES			\
+  { {"dw", 1},				\
+    {"ndw", -1},			\
+    {"bw", 2},				\
+    {"nbw", - (1|2)},			\
+    {"small", 4},			\
+    {"normal", - (4|8)},		\
+    {"large", 8},			\
+    {"29050", 16+128},			\
+    {"29000", -16},			\
+    {"kernel-registers", 32},		\
+    {"user-registers", -32},		\
+    {"stack-check", 64},		\
+    {"no-stack-check", - 74},		\
+    {"storem-bug", -128},		\
+    {"no-storem-bug", 128},		\
+    {"reuse-arg-regs", -256},		\
+    {"no-reuse-arg-regs", 256},		\
+    {"soft-float", 512},		\
+    {"no-multm", 1024},			\
+    {"", TARGET_DEFAULT}}
+
+/* CYGNUS LOCAL: reuse-arg-regs bug, see PR 8144 */
+#define TARGET_DEFAULT (3 + 256)
+
+/* Show we can debug even without a frame pointer.  */
+#define CAN_DEBUG_WITHOUT_FP
+
+/* target machine storage layout */
+
+/* Define the types for size_t, ptrdiff_t, and wchar_t.  These are the
+   same as those used by EPI.  The type for wchar_t does not make much
+   sense, but is what is used.  */
+
+#define SIZE_TYPE "unsigned int"
+#define PTRDIFF_TYPE "int"
+#define WCHAR_TYPE "char"
+#define WCHAR_TYPE_SIZE BITS_PER_UNIT
+
+/* Define this macro if it is advisable to hold scalars in registers
+   in a wider mode than that declared by the program.  In such cases, 
+   the value is constrained to be within the bounds of the declared
+   type, but kept valid in the wider mode.  The signedness of the
+   extension may differ from that of the type.  */
+
+#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)  \
+  if (GET_MODE_CLASS (MODE) == MODE_INT	\
+      && GET_MODE_SIZE (MODE) < 4)  	\
+    (MODE) = SImode;
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.
+   This is arbitrary on the 29k since it has no actual bit-field insns.
+   It is better to define this as TRUE because BYTES_BIG_ENDIAN is TRUE
+   and we want to be able to convert BP position to bit position with
+   just a shift.  */
+#define BITS_BIG_ENDIAN 1
+
+/* Define this if most significant byte of a word is the lowest numbered.
+   This is true on 29k.  */
+#define BYTES_BIG_ENDIAN 1
+
+/* Define this if most significant word of a multiword number is lowest
+   numbered. 
+
+   For 29k we can decide arbitrarily since there are no machine instructions
+   for them.  Might as well be consistent with bytes. */
+#define WORDS_BIG_ENDIAN 1
+
+/* number of bits in an addressable storage unit */
+#define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+   Note that this is not necessarily the width of data type `int';
+   if using 16-bit ints on a 68000, this would still be 32.
+   But on a machine with 16-bit registers, this would be 16.  */
+#define BITS_PER_WORD 32
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD 4
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#define POINTER_SIZE 32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY 32
+
+/* Boundary (in *bits*) on which stack pointer should be aligned.  */
+#define STACK_BOUNDARY 64
+
+/* Allocation boundary (in *bits*) for the code of a function.  */
+#define FUNCTION_BOUNDARY 32
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY 32
+
+/* Every structure's size must be a multiple of this.  */
+#define STRUCTURE_SIZE_BOUNDARY 8
+
+/* A bitfield declared as `int' forces `int' alignment for the struct.  */
+#define PCC_BITFIELD_TYPE_MATTERS 1
+
+/* No data type wants to be aligned rounder than this.  */
+#define BIGGEST_ALIGNMENT 32
+
+/* Make strings word-aligned so strcpy from constants will be faster.  */
+#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
+  (TREE_CODE (EXP) == STRING_CST	\
+   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+
+/* Make arrays of chars word-aligned for the same reasons.  */
+#define DATA_ALIGNMENT(TYPE, ALIGN)		\
+  (TREE_CODE (TYPE) == ARRAY_TYPE		\
+   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
+   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+
+/* Set this non-zero if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT 0
+
+/* Set this non-zero if unaligned move instructions are extremely slow.
+
+   On the 29k, they trap.  */
+#define SLOW_UNALIGNED_ACCESS 1
+
+/* Standard register usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.
+
+   29k has 256 registers, of which 62 are not defined.  gr0 and gr1 are
+   not produced in generated RTL so we can start at gr96, and call it
+   register zero.
+
+   So 0-31 are gr96-gr127, lr0-lr127 are 32-159.  To represent the input
+   arguments, whose register numbers we won't know until we are done,
+   use register 160-175.  They cannot be modified.  Similarly, 176 is used
+   for the frame pointer.  It is assigned the last local register number
+   once the number of registers used is known.
+
+   We use 177, 178, 179, and 180 for the special registers BP, FC, CR, and Q,
+   respectively.  Registers 181 through 199 are used for the other special
+   registers that may be used by the programmer, but are never used by the
+   compiler.
+
+   Registers 200-203 are the four floating-point accumulator register in
+   the 29050.
+
+   Registers 204-235 are the 32 global registers for kernel mode when
+   -mkernel-registers is not specified, and the 32 global user registers
+   when it is.
+
+   When -mkernel-registers is specified, we still use the same register
+   map but change the names so 0-31 print as gr64-gr95.  */
+
+#define FIRST_PSEUDO_REGISTER 236
+
+/* Because of the large number of registers on the 29k, we define macros
+   to refer to each group of registers and then define the number for some
+   registers used in the calling sequence.  */
+
+#define R_GR(N)		((N) - 96)	/* gr96 is register number 0 */
+#define R_LR(N)		((N) + 32)	/* lr0 is register number 32 */
+#define R_FP		176		/* frame pointer is register 176 */
+#define R_AR(N)		((N) + 160)	/* first incoming arg reg is 160 */
+#define R_KR(N)		((N) + 204)	/* kernel registers (gr64 to gr95) */
+
+/* Define the numbers of the special registers.  */
+#define R_BP	177
+#define R_FC	178
+#define R_CR	179
+#define R_Q	180
+
+/* These special registers are not used by the compiler, but may be referenced
+   by the programmer via asm declarations.  */
+
+#define R_VAB	181
+#define R_OPS	182
+#define R_CPS	183
+#define R_CFG	184
+#define R_CHA	185
+#define R_CHD	186
+#define R_CHC	187
+#define R_RBP	188
+#define R_TMC	189
+#define R_TMR	190
+#define R_PC0	191
+#define R_PC1	192
+#define R_PC2	193
+#define R_MMU	194
+#define R_LRU	195
+#define R_FPE	196
+#define R_INT	197
+#define R_FPS	198
+#define R_EXO	199
+
+/* Define the number for floating-point accumulator N.  */
+#define R_ACU(N)	((N) + 200)
+
+/* Now define the registers used in the calling sequence.  */
+#define R_TAV	R_GR (121)
+#define R_TPC	R_GR (122)
+#define R_LRP	R_GR (123)
+#define R_SLP	R_GR (124)
+#define R_MSP	R_GR (125)
+#define R_RAB	R_GR (126)
+#define R_RFB	R_GR (127)
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.  */
+
+#define FIXED_REGISTERS  \
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
+  0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 1, 1, 1, 1, 1, 1, 1,			  \
+  0, 0, 0, 0,					  \
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.  */
+#define CALL_USED_REGISTERS  \
+ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 1, 1, 1, 1, 1, 1, 1,			  \
+  1, 1, 1, 1,					  \
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
+
+/* List the order in which to allocate registers.  Each register must be
+   listed once, even those in FIXED_REGISTERS.
+
+   We allocate in the following order:
+	gr116-gr120	(not used for anything but temps)
+	gr96-gr111	(function return values, reverse order)
+	argument registers (160-175)
+	lr0-lr127	(locals, saved)
+        acc3-0		(acc0 special)
+	everything else  */
+
+#define REG_ALLOC_ORDER		\
+  {R_GR (116), R_GR (117), R_GR (118), R_GR (119), R_GR (120),		\
+   R_GR (111), R_GR (110), R_GR (109), R_GR (108), R_GR (107),		\
+   R_GR (106), R_GR (105), R_GR (104), R_GR (103), R_GR (102),		\
+   R_GR (101), R_GR (100), R_GR (99), R_GR (98), R_GR (97), R_GR (96),	\
+   R_AR (0), R_AR (1), R_AR (2), R_AR (3), R_AR (4), R_AR (5),		\
+   R_AR (6), R_AR (7), R_AR (8), R_AR (9), R_AR (10), R_AR (11),	\
+   R_AR (12), R_AR (13), R_AR (14), R_AR (15),				\
+   R_LR (0), R_LR (1), R_LR (2), R_LR (3), R_LR (4), R_LR (5),		\
+   R_LR (6), R_LR (7), R_LR (8), R_LR (9), R_LR (10), R_LR (11),	\
+   R_LR (12), R_LR (13), R_LR (14), R_LR (15), R_LR (16), R_LR (17),	\
+   R_LR (18), R_LR (19), R_LR (20), R_LR (21), R_LR (22), R_LR (23),	\
+   R_LR (24), R_LR (25), R_LR (26), R_LR (27), R_LR (28), R_LR (29),	\
+   R_LR (30), R_LR (31), R_LR (32), R_LR (33), R_LR (34), R_LR (35),	\
+   R_LR (36), R_LR (37), R_LR (38), R_LR (39), R_LR (40), R_LR (41),	\
+   R_LR (42), R_LR (43), R_LR (44), R_LR (45), R_LR (46), R_LR (47), 	\
+   R_LR (48), R_LR (49), R_LR (50), R_LR (51), R_LR (52), R_LR (53),	\
+   R_LR (54), R_LR (55), R_LR (56), R_LR (57), R_LR (58), R_LR (59),	\
+   R_LR (60), R_LR (61), R_LR (62), R_LR (63), R_LR (64), R_LR (65),	\
+   R_LR (66), R_LR (67), R_LR (68), R_LR (69), R_LR (70), R_LR (71),	\
+   R_LR (72), R_LR (73), R_LR (74), R_LR (75), R_LR (76), R_LR (77),	\
+   R_LR (78), R_LR (79), R_LR (80), R_LR (81), R_LR (82), R_LR (83),	\
+   R_LR (84), R_LR (85), R_LR (86), R_LR (87), R_LR (88), R_LR (89),	\
+   R_LR (90), R_LR (91), R_LR (92), R_LR (93), R_LR (94), R_LR (95),	\
+   R_LR (96), R_LR (97), R_LR (98), R_LR (99), R_LR (100), R_LR (101),	\
+   R_LR (102), R_LR (103), R_LR (104), R_LR (105), R_LR (106),		\
+   R_LR (107), R_LR (108), R_LR (109), R_LR (110), R_LR (111),		\
+   R_LR (112), R_LR (113), R_LR (114), R_LR (115), R_LR (116),		\
+   R_LR (117), R_LR (118), R_LR (119), R_LR (120), R_LR (121),		\
+   R_LR (122), R_LR (123), R_LR (124), R_LR (124), R_LR (126),		\
+   R_LR (127),								\
+   R_ACU (3), R_ACU (2), R_ACU (1), R_ACU (0),				\
+   R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (121),		\
+   R_GR (122), R_GR (123), R_GR (124), R_GR (125), R_GR (126),		\
+   R_GR (127),								\
+   R_FP, R_BP, R_FC, R_CR, R_Q,						\
+   R_VAB, R_OPS, R_CPS, R_CFG, R_CHA, R_CHD, R_CHC, R_RBP, R_TMC,	\
+   R_TMR, R_PC0, R_PC1, R_PC2, R_MMU, R_LRU, R_FPE, R_INT, R_FPS,	\
+   R_EXO,								\
+   R_KR (0), R_KR (1), R_KR (2), R_KR (3), R_KR (4), R_KR (5), 		\
+   R_KR (6), R_KR (7), R_KR (8), R_KR (9), R_KR (10), R_KR (11),	\
+   R_KR (12), R_KR (13), R_KR (14), R_KR (15), R_KR (16), R_KR (17),	\
+   R_KR (18), R_KR (19), R_KR (20), R_KR (21), R_KR (22), R_KR (23),	\
+   R_KR (24), R_KR (25), R_KR (26), R_KR (27), R_KR (28), R_KR (29),	\
+   R_KR (30), R_KR (31) }
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.  */
+
+#define HARD_REGNO_NREGS(REGNO, MODE)   \
+  ((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3)? 1		\
+   : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
+   On 29k, the cpu registers can hold any mode.  But a double-precision
+   floating-point value should start at an even register.  The special
+   registers cannot hold floating-point values, BP, CR, and FC cannot
+   hold integer or floating-point values,  and the accumulators cannot
+   hold integer values.
+
+   DImode and larger values should start at an even register just like
+   DFmode values, even though the instruction set doesn't require it, in order
+   to prevent reload from aborting due to a modes_equiv_for_class_p failure.
+
+   (I'd like to use the "?:" syntax to make this more readable, but Sun's
+   compiler doesn't seem to accept it.)  */
+#define HARD_REGNO_MODE_OK(REGNO, MODE)  				\
+(((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3)				\
+    && (GET_MODE_CLASS (MODE) == MODE_FLOAT				\
+	|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT))		\
+   || ((REGNO) >= R_BP && (REGNO) <= R_CR				\
+       && GET_MODE_CLASS (MODE) == MODE_PARTIAL_INT)			\
+   || ((REGNO) >= R_Q && (REGNO) < R_ACU (0)				\
+       && GET_MODE_CLASS (MODE) != MODE_FLOAT				\
+       && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT)			\
+   || (((REGNO) < R_BP || (REGNO) >= R_KR (0))				 \
+       && ((((REGNO) & 1) == 0)						\
+	   || GET_MODE_UNIT_SIZE (MODE) <= UNITS_PER_WORD)))
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+   when one has mode MODE1 and one has mode MODE2.
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+   for any hard reg, then this must be 0 for correct output.
+
+   On the 29k, normally we'd just have problems with DFmode because of the
+   even alignment.  However, we also have to be a bit concerned about
+   the special register's restriction to non-floating and the floating-point
+   accumulator's restriction to only floating.  This probably won't
+   cause any great inefficiencies in practice.  */
+
+#define MODES_TIEABLE_P(MODE1, MODE2)			\
+  ((MODE1) == (MODE2)					\
+   || (GET_MODE_CLASS (MODE1) == MODE_INT		\
+       && GET_MODE_CLASS (MODE2) == MODE_INT))
+
+/* Specify the registers used for certain standard purposes.
+   The values of these macros are register numbers.  */
+
+/* 29k pc isn't overloaded on a register that the compiler knows about.  */
+/* #define PC_REGNUM  */
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM R_GR (125)
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM R_FP
+
+/* Value should be nonzero if functions must have frame pointers.
+   Zero means the frame pointer need not be set up (and parms
+   may be accessed via the stack pointer) in functions that seem suitable.
+   This is computed in `reload', in reload1.c.  */
+#define FRAME_POINTER_REQUIRED 0
+
+/* Base register for access to arguments of the function.  */
+#define ARG_POINTER_REGNUM R_FP
+
+/* Register in which static-chain is passed to a function.  */
+#define STATIC_CHAIN_REGNUM R_SLP
+
+/* Register in which address to store a structure value
+   is passed to a function.  */
+#define STRUCT_VALUE_REGNUM R_LRP
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.
+   
+   The 29k has nine registers classes: LR0_REGS, GENERAL_REGS, SPECIAL_REGS,
+   BP_REGS, FC_REGS, CR_REGS, Q_REGS, ACCUM_REGS, and ACCUM0_REGS.
+   LR0_REGS, BP_REGS, FC_REGS, CR_REGS, and Q_REGS contain just the single
+   register.  The latter two classes are used to represent the floating-point
+   accumulator registers in the 29050.  We also define the union class
+   FLOAT_REGS to represent any register that can be used to hold a
+   floating-point value.  The union of SPECIAL_REGS and ACCUM_REGS isn't
+   useful as the former cannot contain floating-point and the latter can only
+   contain floating-point.  */
+
+enum reg_class { NO_REGS, LR0_REGS, GENERAL_REGS, BP_REGS, FC_REGS, CR_REGS,
+		 Q_REGS, SPECIAL_REGS, ACCUM0_REGS, ACCUM_REGS, FLOAT_REGS,
+		 ALL_REGS, LIM_REG_CLASSES };
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.   */
+
+#define REG_CLASS_NAMES				\
+ {"NO_REGS", "LR0_REGS", "GENERAL_REGS", "BP_REGS", "FC_REGS", "CR_REGS", \
+  "Q_REGS", "SPECIAL_REGS", "ACCUM0_REGS", "ACCUM_REGS", "FLOAT_REGS",    \
+  "ALL_REGS" }
+
+/* Define which registers fit in which classes.
+   This is an initializer for a vector of HARD_REG_SET
+   of length N_REG_CLASSES.  */
+
+#define REG_CLASS_CONTENTS	\
+  { {0, 0, 0, 0, 0, 0, 0, 0}, 				   \
+    {0, 1, 0, 0, 0, 0, 0, 0},				   \
+    {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xfff, 0xfff},	   \
+    {0, 0, 0, 0, 0, 0x20000, 0, 0}, 			   \
+    {0, 0, 0, 0, 0, 0x40000, 0, 0}, 			   \
+    {0, 0, 0, 0, 0, 0x80000, 0, 0}, 			   \
+    {0, 0, 0, 0, 0, 0x100000, 0, 0}, 			   \
+    {0, 0, 0, 0, 0, 0xfffe0000, 0xff, 0},		   \
+    {0, 0, 0, 0, 0, 0, 0x100, 0},			   \
+    {0, 0, 0, 0, 0, 0, 0xf00, 0},			   \
+    {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xff, 0xfff}, 	   \
+    {~0, ~0, ~0, ~0, ~0, ~0, ~0, 0xfff} }
+
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+
+#define REGNO_REG_CLASS(REGNO)		\
+  ((REGNO) == R_BP ? BP_REGS		\
+   : (REGNO) == R_FC ? FC_REGS		\
+   : (REGNO) == R_CR ? CR_REGS		\
+   : (REGNO) == R_Q ? Q_REGS		\
+   : (REGNO) > R_BP && (REGNO) <= R_EXO ? SPECIAL_REGS	\
+   : (REGNO) == R_ACU (0) ? ACCUM0_REGS	\
+   : (REGNO) >= R_KR (0) ? GENERAL_REGS \
+   : (REGNO) > R_ACU (0) ? ACCUM_REGS	\
+   : (REGNO) == R_LR (0) ? LR0_REGS	\
+   : GENERAL_REGS)
+
+/* The class value for index registers, and the one for base regs.  */
+#define INDEX_REG_CLASS NO_REGS
+#define BASE_REG_CLASS GENERAL_REGS
+
+/* Get reg_class from a letter such as appears in the machine description.  */
+
+#define REG_CLASS_FROM_LETTER(C)	\
+ ((C) == 'r' ? GENERAL_REGS		\
+  : (C) == 'l' ? LR0_REGS		\
+  : (C) == 'b' ? BP_REGS		\
+  : (C) == 'f' ? FC_REGS		\
+  : (C) == 'c' ? CR_REGS		\
+  : (C) == 'q' ? Q_REGS			\
+  : (C) == 'h' ? SPECIAL_REGS		\
+  : (C) == 'a' ? ACCUM_REGS		\
+  : (C) == 'A' ? ACCUM0_REGS		\
+  : (C) == 'f' ? FLOAT_REGS		\
+  : NO_REGS)
+
+/* Define this macro to change register usage conditional on target flags.
+
+   On the 29k, we use this to change the register names for kernel mapping.  */
+
+#define CONDITIONAL_REGISTER_USAGE		\
+  {						\
+    char *p;					\
+    int i;					\
+						\
+    if (TARGET_KERNEL_REGISTERS)		\
+      for (i = 0; i < 32; i++)			\
+	{					\
+	  p = reg_names[i];			\
+	  reg_names[i] = reg_names[R_KR (i)];	\
+	  reg_names[R_KR (i)] = p;		\
+	}					\
+  }
+
+/* The letters I, J, K, L, M, N, O, and P in a register constraint string
+   can be used to stand for particular ranges of immediate operands.
+   This macro defines what the ranges are.
+   C is the letter, and VALUE is a constant value.
+   Return 1 if VALUE is in the range specified by C.
+
+   For 29k:
+   `I' is used for the range of constants most insns can contain.
+   `J' is for the few 16-bit insns.
+   `K' is a constant whose high-order 24 bits are all one
+   `L' is a HImode constant whose high-order 8 bits are all one
+   `M' is a 32-bit constant whose high-order 16 bits are all one (for CONSTN)
+   `N' is a 32-bit constant whose negative is 8 bits
+   `O' is the 32-bit constant 0x80000000, any constant with low-order
+          16 bits zero for 29050.
+   `P' is a HImode constant whose negative is 8 bits  */
+
+#define CONST_OK_FOR_LETTER_P(VALUE, C)				\
+  ((C) == 'I' ? (unsigned) (VALUE) < 0x100			\
+   : (C) == 'J' ? (unsigned) (VALUE) < 0x10000			\
+   : (C) == 'K' ? ((VALUE) & 0xffffff00) == 0xffffff00		\
+   : (C) == 'L' ? ((VALUE) & 0xff00) == 0xff00			\
+   : (C) == 'M' ? ((VALUE) & 0xffff0000) == 0xffff0000		\
+   : (C) == 'N' ? ((VALUE) < 0 && (VALUE) > -256)		\
+   : (C) == 'O' ? ((VALUE) == 0x80000000			\
+		   || (TARGET_29050 && ((VALUE) & 0xffff) == 0)) \
+   : (C) == 'P' ? (((VALUE) | 0xffff0000) < 0			\
+		   && ((VALUE) | 0xffff0000) > -256)		\
+   : 0)
+
+/* Similar, but for floating constants, and defining letters G and H.
+   Here VALUE is the CONST_DOUBLE rtx itself.
+   All floating-point constants are valid on 29k.  */
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  1
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class.  */
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS)	CLASS
+
+/* Return the register class of a scratch register needed to copy IN into
+   or out of a register in CLASS in MODE.  If it can be done directly,
+   NO_REGS is returned.  */
+
+#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
+  secondary_reload_class (CLASS, MODE, IN)
+
+/* This function is used to get the address of an object.  */
+
+extern struct rtx_def *a29k_get_reloaded_address ();
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.
+
+   On 29k, this is the size of MODE in words except that the floating-point
+   accumulators only require one word for anything they can hold.  */
+
+#define CLASS_MAX_NREGS(CLASS, MODE)				\
+ (((CLASS) == ACCUM_REGS || (CLASS) == ACCUM0_REGS) ? 1		\
+  : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Define the cost of moving between registers of various classes.  Everything
+   involving a general register is cheap, but moving between the other types
+   (even within a class) is two insns.  */
+
+#define REGISTER_MOVE_COST(CLASS1, CLASS2)	\
+  ((CLASS1) == GENERAL_REGS || (CLASS2) == GENERAL_REGS ? 2 : 4)
+
+/* A C expressions returning the cost of moving data of MODE from a register to
+   or from memory.
+
+   It takes extra insns on the 29k to form addresses, so we want to make
+   this higher.  In addition, we need to keep it more expensive than the
+   most expensive register-register copy.  */
+
+#define MEMORY_MOVE_COST(MODE,CLASS,IN) 6
+
+/* A C statement (sans semicolon) to update the integer variable COST
+   based on the relationship between INSN that is dependent on
+   DEP_INSN through the dependence LINK.  The default is to make no
+   adjustment to COST.  On the a29k, ignore the cost of anti- and
+   output-dependencies.  */
+#define ADJUST_COST(INSN,LINK,DEP_INSN,COST)				\
+  if (REG_NOTE_KIND (LINK) != 0)					\
+    (COST) = 0; /* Anti or output dependence.  */
+
+/* Stack layout; function entry, exit and calling.  */
+
+/* Define this if pushing a word on the stack
+   makes the stack pointer a smaller address.  */
+#define STACK_GROWS_DOWNWARD
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset in the frame.  */
+#define FRAME_GROWS_DOWNWARD
+
+/* Offset within stack frame to start allocating local variables at.
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
+   of the first local allocated.  */
+
+#define STARTING_FRAME_OFFSET (- current_function_pretend_args_size)
+
+/* If we generate an insn to push BYTES bytes,
+   this says how many the stack pointer really advances by.
+   On 29k, don't define this because there are no push insns.  */
+/*  #define PUSH_ROUNDING(BYTES) */
+
+/* Define this if the maximum size of all the outgoing args is to be
+   accumulated and pushed during the prologue.  The amount can be
+   found in the variable current_function_outgoing_args_size.  */
+#define ACCUMULATE_OUTGOING_ARGS
+
+/* Offset of first parameter from the argument pointer register value.  */
+
+#define FIRST_PARM_OFFSET(FNDECL) (- current_function_pretend_args_size)
+
+/* Define this if stack space is still allocated for a parameter passed
+   in a register.  */
+/* #define REG_PARM_STACK_SPACE */
+
+/* Value is the number of bytes of arguments automatically
+   popped when returning from a subroutine call.
+   FUNDECL is the declaration node of the function (as a tree),
+   FUNTYPE is the data type of the function (as a tree),
+   or for a library call it is an identifier node for the subroutine name.
+   SIZE is the number of bytes of arguments passed on the stack.  */
+
+#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.
+
+   On 29k the value is found in gr96.  */
+
+#define FUNCTION_VALUE(VALTYPE, FUNC)  \
+  gen_rtx (REG, TYPE_MODE (VALTYPE), R_GR (96))
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+
+#define LIBCALL_VALUE(MODE)  gen_rtx (REG, MODE, R_GR (96))
+
+/* 1 if N is a possible register number for a function value
+   as seen by the caller.
+   On 29k, gr96-gr111 are used.  */
+
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == R_GR (96))
+
+/* 1 if N is a possible register number for function argument passing.
+   On 29k, these are lr2-lr17.  */
+
+#define FUNCTION_ARG_REGNO_P(N) ((N) <= R_LR (17) && (N) >= R_LR (2))
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On 29k, this is a single integer, which is a number of words
+   of arguments scanned so far.
+   Thus 16 or more means all following args should go on the stack.  */
+
+#define CUMULATIVE_ARGS int
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.  */
+
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)  (CUM) = 0
+
+/* Same, but called for incoming args.
+
+   On the 29k, we use this to set all argument registers to fixed and
+   set the last 16 local regs, less two, (lr110-lr125) to available.  Some
+   will later be changed to call-saved by FUNCTION_INCOMING_ARG.
+   lr126,lr127 are always fixed, they are place holders for the caller's
+   lr0,lr1.  */
+
+#define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE)	\
+{ int i;							\
+  for (i = R_AR (0) - 2; i < R_AR (16); i++)			\
+    {								\
+      fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; \
+      SET_HARD_REG_BIT (fixed_reg_set, i);			\
+      SET_HARD_REG_BIT (call_used_reg_set, i);			\
+      SET_HARD_REG_BIT (call_fixed_reg_set, i);			\
+    }								\
+  for (i = R_LR (110); i < R_LR (126); i++)					\
+    {								\
+      fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 0; \
+      CLEAR_HARD_REG_BIT (fixed_reg_set, i);			\
+      CLEAR_HARD_REG_BIT (call_used_reg_set, i);		\
+      CLEAR_HARD_REG_BIT (call_fixed_reg_set, i);		\
+    }								\
+  (CUM) = 0;							\
+ }
+
+/* Define intermediate macro to compute the size (in registers) of an argument
+   for the 29k.  */
+
+#define A29K_ARG_SIZE(MODE, TYPE, NAMED)				\
+(! (NAMED) ? 0								\
+ : (MODE) != BLKmode							\
+ ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD 	\
+ : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
+  if (MUST_PASS_IN_STACK (MODE, TYPE))					\
+    (CUM) = 16;								\
+  else									\
+    (CUM) += A29K_ARG_SIZE (MODE, TYPE, NAMED)
+
+/* Determine where to put an argument to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).
+
+   On 29k the first 16 words of args are normally in registers
+   and the rest are pushed.  */
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)			\
+((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE)	\
+ ? gen_rtx(REG, (MODE), R_LR (2) + (CUM)) : 0)
+
+/* Define where a function finds its arguments.
+   This is different from FUNCTION_ARG because of register windows.
+
+   On the 29k, we hack this to call a function that sets the used registers
+   as non-fixed and not used by calls.  */
+
+#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED)			\
+((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE)		\
+ ? gen_rtx (REG, MODE,							\
+	    incoming_reg (CUM, A29K_ARG_SIZE (MODE, TYPE, NAMED)))	\
+ : 0)
+
+/* This indicates that an argument is to be passed with an invisible reference
+   (i.e., a pointer to the object is passed).
+
+   On the 29k, we do this if it must be passed on the stack.  */
+
+#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)	\
+  (MUST_PASS_IN_STACK (MODE, TYPE))
+
+/* Specify the padding direction of arguments.
+
+   On the 29k, we must pad upwards in order to be able to pass args in
+   registers.  */
+
+#define FUNCTION_ARG_PADDING(MODE, TYPE)	upward
+
+/* For an arg passed partly in registers and partly in memory,
+   this is the number of registers used.
+   For args passed entirely in registers or entirely in memory, zero.  */
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)		\
+((CUM) < 16 && 16 < (CUM) + A29K_ARG_SIZE (MODE, TYPE, NAMED) && (NAMED) \
+ ? 16 - (CUM) : 0)
+
+/* Perform any needed actions needed for a function that is receiving a
+   variable number of arguments. 
+
+   CUM is as above.
+
+   MODE and TYPE are the mode and type of the current parameter.
+
+   PRETEND_SIZE is a variable that should be set to the amount of stack
+   that must be pushed by the prolog to pretend that our caller pushed
+   it.
+
+   Normally, this macro will push all remaining incoming registers on the
+   stack and set PRETEND_SIZE to the length of the registers pushed.  */
+
+#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
+{ if ((CUM) < 16)							\
+    {									\
+      int first_reg_offset = (CUM);					\
+									\
+      if (MUST_PASS_IN_STACK (MODE, TYPE))				\
+	first_reg_offset += A29K_ARG_SIZE (TYPE_MODE (TYPE), TYPE, 1);	\
+									\
+      if (first_reg_offset > 16)					\
+	first_reg_offset = 16;						\
+									\
+      if (! (NO_RTL) && first_reg_offset != 16)				\
+	move_block_from_reg						\
+	  (R_AR (0) + first_reg_offset,					\
+	   gen_rtx (MEM, BLKmode, virtual_incoming_args_rtx),		\
+	   16 - first_reg_offset, (16 - first_reg_offset) * UNITS_PER_WORD); \
+      PRETEND_SIZE = (16 - first_reg_offset) * UNITS_PER_WORD;		\
+    }									\
+}
+
+/* Define the information needed to generate branch and scc insns.  This is
+   stored from the compare operation.  Note that we can't use "rtx" here
+   since it hasn't been defined!  */
+
+extern struct rtx_def *a29k_compare_op0, *a29k_compare_op1;
+extern int a29k_compare_fp_p;
+
+/* This macro produces the initial definition of a function name.
+
+   For the 29k, we need the prolog to contain one or two words prior to
+   the declaration of the function name.  So just store away the name and
+   write it as part of the prolog.  This also computes the register names,
+   which can't be done until after register allocation, but must be done
+   before final_start_function is called.  */
+
+extern char *a29k_function_name;
+
+#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL)	\
+  a29k_function_name = NAME; \
+  a29k_compute_reg_names ();
+
+/* This macro generates the assembly code for function entry.
+   FILE is a stdio stream to output the code to.
+   SIZE is an int: how many units of temporary storage to allocate.
+   Refer to the array `regs_ever_live' to determine which registers
+   to save; `regs_ever_live[I]' is nonzero if register number I
+   is ever used in the function.  This macro is responsible for
+   knowing which registers should not be saved even if used.  */
+
+#define FUNCTION_PROLOGUE(FILE, SIZE)  output_prolog (FILE, SIZE)
+
+/* Output assembler code to FILE to increment profiler label # LABELNO
+   for profiling a function entry.  */
+
+#define FUNCTION_PROFILER(FILE, LABELNO)
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+
+#define EXIT_IGNORE_STACK 1
+
+/* This macro generates the assembly code for function exit,
+   on machines that need it.  If FUNCTION_EPILOGUE is not defined
+   then individual return instructions are generated for each
+   return statement.  Args are same as for FUNCTION_PROLOGUE.
+
+   The function epilogue should not depend on the current stack pointer!
+   It should use the frame pointer only.  This is mandatory because
+   of alloca; we also take advantage of it to omit stack adjustments
+   before returning.  */
+
+#define FUNCTION_EPILOGUE(FILE, SIZE)	output_epilog (FILE, SIZE)
+
+/* Define the number of delay slots needed for the function epilogue.
+
+   On the 29k, we need a slot except when we have a register stack adjustment,
+   have a memory stack adjustment, and have no frame pointer.  */
+
+#define DELAY_SLOTS_FOR_EPILOGUE 					\
+  (! (needs_regstack_p ()						\
+      && (get_frame_size () + current_function_pretend_args_size	\
+	   + current_function_outgoing_args_size) != 0			\
+      && ! frame_pointer_needed))
+
+/* Define whether INSN can be placed in delay slot N for the epilogue.
+
+   On the 29k, we must be able to place it in a delay slot, it must
+   not use sp if the frame pointer cannot be eliminated, and it cannot
+   use local regs if we need to push the register stack.
+   If this is a SET with a memory as source, it might load from
+   a stack slot, unless the address is constant.  */
+
+#define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N)				\
+  (get_attr_in_delay_slot (INSN) == IN_DELAY_SLOT_YES			\
+   && ! (frame_pointer_needed						\
+	 && reg_mentioned_p (stack_pointer_rtx, PATTERN (INSN)))	\
+   && ! (needs_regstack_p () && uses_local_reg_p (PATTERN (INSN)))	\
+   && (GET_CODE (PATTERN (INSN)) != SET					\
+       || GET_CODE (SET_SRC (PATTERN (INSN))) != MEM			\
+       || ! rtx_varies_p (XEXP (SET_SRC (PATTERN (INSN)), 0))))
+
+/* Output assembler code for a block containing the constant parts
+   of a trampoline, leaving space for the variable parts.
+
+   The trampoline should set the static chain pointer to value placed
+   into the trampoline and should branch to the specified routine.  We
+   use gr121 (tav) as a temporary.  */
+
+#define TRAMPOLINE_TEMPLATE(FILE)			\
+{							\
+  fprintf (FILE, "\tconst %s,0\n", reg_names[R_TAV]);	\
+  fprintf (FILE, "\tconsth %s,0\n", reg_names[R_TAV]);	\
+  fprintf (FILE, "\tconst %s,0\n", reg_names[R_SLP]);	\
+  fprintf (FILE, "\tjmpi %s\n", reg_names[R_TAV]);	\
+  fprintf (FILE, "\tconsth %s,0\n", reg_names[R_SLP]);	\
+}
+
+/* Length in units of the trampoline for entering a nested function.  */
+
+#define TRAMPOLINE_SIZE    20
+
+/* Emit RTL insns to initialize the variable parts of a trampoline.
+   FNADDR is an RTX for the address of the function's pure code.
+   CXT is an RTX for the static chain value for the function.
+
+   We do this on the 29k by writing the bytes of the addresses into the
+   trampoline one byte at a time.  */
+
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
+{									\
+  INITIALIZE_TRAMPOLINE_VALUE (TRAMP, FNADDR, 0, 4);			\
+  INITIALIZE_TRAMPOLINE_VALUE (TRAMP, CXT, 8, 16);			\
+}
+
+/* Define a sub-macro to initialize one value into the trampoline.
+   We specify the offsets of the CONST and CONSTH instructions, respectively
+   and copy the value a byte at a time into these instructions.  */
+
+#define INITIALIZE_TRAMPOLINE_VALUE(TRAMP, VALUE, CONST, CONSTH)	\
+{									\
+  rtx _addr, _temp;							\
+  rtx _val = force_reg (SImode, VALUE);					\
+									\
+  _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 3));	\
+  emit_move_insn (gen_rtx (MEM, QImode, _addr),				\
+		  gen_lowpart (QImode, _val));				\
+									\
+  _temp = expand_shift (RSHIFT_EXPR, SImode, _val,			\
+		       build_int_2 (8, 0), 0, 1);			\
+  _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 1));	\
+  emit_move_insn (gen_rtx (MEM, QImode, _addr),				\
+		  gen_lowpart (QImode, _temp));				\
+									\
+  _temp = expand_shift (RSHIFT_EXPR, SImode, _temp,			\
+		       build_int_2 (8, 0), _temp, 1);			\
+  _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 3));	\
+  emit_move_insn (gen_rtx (MEM, QImode, _addr),				\
+		  gen_lowpart (QImode, _temp));				\
+									\
+  _temp = expand_shift (RSHIFT_EXPR, SImode, _temp,			\
+		       build_int_2 (8, 0), _temp, 1);			\
+  _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 1));	\
+  emit_move_insn (gen_rtx (MEM, QImode, _addr),				\
+		  gen_lowpart (QImode, _temp));				\
+}
+
+/* Addressing modes, and classification of registers for them.  */
+
+/* #define HAVE_POST_INCREMENT 0 */
+/* #define HAVE_POST_DECREMENT 0 */
+
+/* #define HAVE_PRE_DECREMENT 0 */
+/* #define HAVE_PRE_INCREMENT 0 */
+
+/* Macros to check register numbers against specific register classes.  */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   Since they use reg_renumber, they are safe only once reg_renumber
+   has been allocated, which happens in local-alloc.c.  */
+
+#define REGNO_OK_FOR_INDEX_P(REGNO) 0
+#define REGNO_OK_FOR_BASE_P(REGNO) 1
+
+/* Given the value returned from get_frame_size, compute the actual size
+   of the frame we will allocate.   We include the pretend and outgoing
+   arg sizes and round to a doubleword.  */
+
+#define ACTUAL_FRAME_SIZE(SIZE)				\
+  (((SIZE) + current_function_pretend_args_size		\
+    + current_function_outgoing_args_size + 7) & ~7)
+
+/* Define the initial offset between the frame and stack pointer.  */
+
+#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)	\
+  (DEPTH) = ACTUAL_FRAME_SIZE (get_frame_size ())
+
+/* Maximum number of registers that can appear in a valid memory address.  */
+#define MAX_REGS_PER_ADDRESS 1
+
+/* Recognize any constant value that is a valid address.  */
+
+#define CONSTANT_ADDRESS_P(X)  \
+(GET_CODE (X) == CONST_INT && (unsigned) INTVAL (X) < 0x100)
+
+/* Include all constant integers and constant doubles */
+#define LEGITIMATE_CONSTANT_P(X)	1
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects
+   them unless they have been allocated suitable hard regs.
+   The symbol REG_OK_STRICT causes the latter definition to be used.
+
+   Most source files want to accept pseudo regs in the hope that
+   they will get allocated to the class that the insn wants them to be in.
+   Source files for reload pass need to be strict.
+   After reload, it makes no difference, since pseudo regs have
+   been eliminated by then.  */
+
+#ifndef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_INDEX_P(X) 0
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_BASE_P(X)  1
+
+#else
+
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+
+#endif
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.
+
+   On the 29k, a legitimate address is a register and so is a
+   constant of less than 256.  */
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
+{ if (REG_P (X) && REG_OK_FOR_BASE_P (X))	\
+    goto ADDR;					\
+  if (GET_CODE (X) == CONST_INT			\
+      && (unsigned) INTVAL (X) < 0x100)		\
+    goto ADDR;					\
+}
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.
+
+   For the 29k, we need not do anything.  However, if we don't,
+   `memory_address' will try lots of things to get a valid address, most of
+   which will result in dead code and extra pseudos.  So we make the address
+   valid here.
+
+   This is easy:  The only valid addresses are an offset from a register
+   and we know the address isn't valid.  So just call either `force_operand'
+   or `force_reg' unless this is a (plus (reg ...) (const_int 0)).  */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)			\
+{ if (GET_CODE (X) == PLUS && XEXP (X, 1) == const0_rtx)	\
+    X = XEXP (x, 0);						\
+  if (GET_CODE (X) == MULT || GET_CODE (X) == PLUS)		\
+    X = force_operand (X, 0);					\
+  else								\
+    X = force_reg (Pmode, X);					\
+  goto WIN;							\
+}
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for.
+   On the 29k this is never true.  */
+
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
+
+/* Compute the cost of an address.  For the 29k, all valid addresses are
+   the same cost.  */
+
+#define ADDRESS_COST(X)  0
+
+/* Define this if some processing needs to be done immediately before
+   emitting code for an insn.  */
+
+/* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.  */
+#define CASE_VECTOR_MODE SImode
+
+/* Define as C expression which evaluates to nonzero if the tablejump
+   instruction expects the table to contain offsets from the address of the
+   table.
+   Do not define this if the table should contain absolute addresses. */
+/* #define CASE_VECTOR_PC_RELATIVE 1 */
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+
+/* Define this as 1 if `char' should by default be signed; else as 0.  */
+#define DEFAULT_SIGNED_CHAR 0
+
+/* This flag, if defined, says the same insns that convert to a signed fixnum
+   also convert validly to an unsigned one.
+
+   We actually lie a bit here as overflow conditions are different.  But
+   they aren't being checked anyway.  */
+
+#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
+
+/* Max number of bytes we can move to of from memory
+   in one reasonably fast instruction.
+
+   For the 29k, we will define movti, so put this at 4 words.  */
+#define MOVE_MAX 16
+
+/* Largest number of bytes of an object that can be placed in a register.
+   On the 29k we have plenty of registers, so use TImode.  */
+#define MAX_FIXED_MODE_SIZE	GET_MODE_BITSIZE (TImode)
+
+/* Nonzero if access to memory by bytes is no faster than for words.
+   Also non-zero if doing byte operations (specifically shifts) in registers
+   is undesirable. 
+
+   On the 29k, large masks are expensive, so we want to use bytes to
+   manipulate fields.  */
+#define SLOW_BYTE_ACCESS	0
+
+/* Define if operations between registers always perform the operation
+   on the full register even if a narrower mode is specified.  */
+#define WORD_REGISTER_OPERATIONS
+
+/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
+   will either zero-extend or sign-extend.  The value of this macro should
+   be the code that says which one of the two operations is implicitly
+   done, NIL if none.  */
+#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
+
+/* Define if the object format being used is COFF or a superset.  */
+#define OBJECT_FORMAT_COFF
+
+/* This uses COFF, so it wants SDB format.  */
+#define SDB_DEBUGGING_INFO
+
+/* Define this to be the delimiter between SDB sub-sections.  The default
+   is ";".  */
+#define SDB_DELIM	"\n"
+
+/* Do not break .stabs pseudos into continuations.  */
+#define DBX_CONTIN_LENGTH 0
+
+/* Don't try to use the `x' type-cross-reference character in DBX data.
+   Also has the consequence of putting each struct, union or enum
+   into a separate .stabs, containing only cross-refs to the others.  */
+#define DBX_NO_XREFS
+
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+   is done just by pretending it is already truncated.  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+
+/* We assume that the store-condition-codes instructions store 0 for false
+   and some other value for true.  This is the value stored for true, which
+   is just the sign bit.  */
+
+#define STORE_FLAG_VALUE (-2147483647 - 1)
+
+/* Specify the machine mode that pointers have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
+#define Pmode SImode
+
+/* Mode of a function address in a call instruction (for indexing purposes).
+
+   Doesn't matter on 29k.  */
+#define FUNCTION_MODE SImode
+
+/* Define this if addresses of constant functions
+   shouldn't be put through pseudo regs where they can be cse'd.
+   Desirable on machines where ordinary constants are expensive
+   but a CALL with constant address is cheap.  */
+#define NO_FUNCTION_CSE
+
+/* Define this to be nonzero if shift instructions ignore all but the low-order
+   few bits. */
+#define SHIFT_COUNT_TRUNCATED 1
+
+/* Compute the cost of computing a constant rtl expression RTX
+   whose rtx-code is CODE.  The body of this macro is a portion
+   of a switch statement.  If the code is computed here,
+   return it with a return statement.  Otherwise, break from the switch.
+
+   We only care about the cost if it is valid in an insn.  The only
+   constants that cause an insn to generate more than one machine
+   instruction are those involving floating-point or address.  So 
+   only these need be expensive.  */
+
+#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
+  case CONST_INT:						\
+    return 0;							\
+  case CONST:							\
+  case LABEL_REF:						\
+  case SYMBOL_REF:						\
+    return 6;							\
+  case CONST_DOUBLE:						\
+    return GET_MODE (RTX) == SFmode ? 6 : 8;
+    
+/* Provide the costs of a rtl expression.  This is in the body of a
+   switch on CODE.
+
+   All MEMs cost the same if they are valid.  This is used to ensure
+   that (mem (symbol_ref ...)) is placed into a CALL when valid.
+
+   The multiply cost depends on whether this is a 29050 or not.  */
+
+#define RTX_COSTS(X,CODE,OUTER_CODE)			\
+  case MULT:						\
+    return TARGET_29050 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (40);  \
+  case DIV:						\
+  case UDIV:						\
+  case MOD:						\
+  case UMOD:						\
+    return COSTS_N_INSNS (50);				\
+  case MEM:						\
+    return COSTS_N_INSNS (2);
+
+/* Control the assembler format that we output.  */
+
+/* Output at beginning of assembler file.  */
+
+#define ASM_FILE_START(FILE)					\
+{ char *p, *after_dir = main_input_filename;			\
+  if (TARGET_29050)						\
+    fprintf (FILE, "\t.cputype 29050\n");			\
+  for (p = main_input_filename; *p; p++)			\
+    if (*p == '/')						\
+      after_dir = p + 1;					\
+  fprintf (FILE, "\t.file ");					\
+  output_quoted_string (FILE, after_dir);			\
+  fprintf (FILE, "\n");						\
+  fprintf (FILE, "\t.sect .lit,lit\n"); }
+
+/* Output to assembler file text saying following lines
+   may contain character constants, extra white space, comments, etc.  */
+
+#define ASM_APP_ON ""
+
+/* Output to assembler file text saying following lines
+   no longer contain unusual constructs.  */
+
+#define ASM_APP_OFF ""
+
+/* The next few macros don't have tabs on most machines, but
+   at least one 29K assembler wants them.  */
+
+/* Output before instructions.  */
+
+#define TEXT_SECTION_ASM_OP "\t.text"
+
+/* Output before read-only data.  */
+
+#define READONLY_DATA_SECTION_ASM_OP "\t.use .lit"
+
+/* Output before writable data.  */
+
+#define DATA_SECTION_ASM_OP "\t.data"
+
+/* Define an extra section for read-only data, a routine to enter it, and
+   indicate that it is for read-only data.  */
+
+#define EXTRA_SECTIONS	readonly_data
+
+#define EXTRA_SECTION_FUNCTIONS					\
+void								\
+literal_section ()						\
+{								\
+  if (in_section != readonly_data)				\
+    {								\
+      fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
+      in_section = readonly_data;				\
+    }								\
+}								\
+
+#define READONLY_DATA_SECTION	literal_section
+
+/* If we are referencing a function that is static or is known to be
+   in this file, make the SYMBOL_REF special.  We can use this to indicate
+   that we can branch to this function without emitting a no-op after the
+   call.  */
+
+#define ENCODE_SECTION_INFO(DECL)  \
+  if (TREE_CODE (DECL) == FUNCTION_DECL			\
+      && (TREE_ASM_WRITTEN (DECL) || ! TREE_PUBLIC (DECL))) \
+    SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
+
+/* How to refer to registers in assembler output.
+   This sequence is indexed by compiler's hard-register-number (see above).  */
+
+#define REGISTER_NAMES \
+{"gr96", "gr97", "gr98", "gr99", "gr100", "gr101", "gr102", "gr103", "gr104", \
+ "gr105", "gr106", "gr107", "gr108", "gr109", "gr110", "gr111", "gr112", \
+ "gr113", "gr114", "gr115", "gr116", "gr117", "gr118", "gr119", "gr120", \
+ "gr121", "gr122", "gr123", "gr124", "gr125", "gr126", "gr127",		 \
+ "lr0", "lr1", "lr2", "lr3", "lr4", "lr5", "lr6", "lr7", "lr8", "lr9",   \
+ "lr10", "lr11", "lr12", "lr13", "lr14", "lr15", "lr16", "lr17", "lr18", \
+ "lr19", "lr20", "lr21", "lr22", "lr23", "lr24", "lr25", "lr26", "lr27", \
+ "lr28", "lr29", "lr30", "lr31", "lr32", "lr33", "lr34", "lr35", "lr36", \
+ "lr37", "lr38", "lr39", "lr40", "lr41", "lr42", "lr43", "lr44", "lr45", \
+ "lr46", "lr47", "lr48", "lr49", "lr50", "lr51", "lr52", "lr53", "lr54", \
+ "lr55", "lr56", "lr57", "lr58", "lr59", "lr60", "lr61", "lr62", "lr63", \
+ "lr64", "lr65", "lr66", "lr67", "lr68", "lr69", "lr70", "lr71", "lr72", \
+ "lr73", "lr74", "lr75", "lr76", "lr77", "lr78", "lr79", "lr80", "lr81", \
+ "lr82", "lr83", "lr84", "lr85", "lr86", "lr87", "lr88", "lr89", "lr90", \
+ "lr91", "lr92", "lr93", "lr94", "lr95", "lr96", "lr97", "lr98", "lr99", \
+ "lr100", "lr101", "lr102", "lr103", "lr104", "lr105", "lr106", "lr107", \
+ "lr108", "lr109", "lr110", "lr111", "lr112", "lr113", "lr114", "lr115", \
+ "lr116", "lr117", "lr118", "lr119", "lr120", "lr121", "lr122", "lr123", \
+ "lr124", "lr125", "lr126", "lr127",					 \
+  "AI0", "AI1", "AI2", "AI3", "AI4", "AI5", "AI6", "AI7", "AI8", "AI9",  \
+  "AI10", "AI11", "AI12", "AI13", "AI14", "AI15", "FP",			 \
+  "bp", "fc", "cr", "q",						 \
+  "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr",	 \
+  "pc0", "pc1", "pc2", "mmu", "lru", "fpe", "int", "fps", "exo",	 \
+  "0", "1", "2", "3",							 \
+  "gr64", "gr65", "gr66", "gr67", "gr68", "gr69", "gr70", "gr71",	 \
+  "gr72", "gr73", "gr74", "gr75", "gr76", "gr77", "gr78", "gr79",	 \
+  "gr80", "gr81", "gr82", "gr83", "gr84", "gr85", "gr86", "gr87",	 \
+  "gr88", "gr89", "gr90", "gr91", "gr92", "gr93", "gr94", "gr95" }
+
+/* How to renumber registers for dbx and gdb.  */
+
+extern int a29k_debug_reg_map[];
+#define DBX_REGISTER_NUMBER(REGNO) a29k_debug_reg_map[REGNO]
+
+/* This how to write an assembler directive to FILE to switch to
+   section NAME for DECL.  */
+
+#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
+  fprintf (FILE, "\t.sect %s, bss\n\t.use %s\n", NAME, NAME)
+
+/* This is how to output the definition of a user-level label named NAME,
+   such as the label on a static function or variable NAME.  */
+
+#define ASM_OUTPUT_LABEL(FILE,NAME)	\
+  do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
+
+/* This is how to output a command to make the user-level label named NAME
+   defined for reference from other files.  */
+
+#define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
+  do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
+
+/* The prefix to add to user-visible assembler symbols. */
+
+#undef USER_LABEL_PREFIX
+#define USER_LABEL_PREFIX "_"
+
+/* This is how to output an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.  */
+
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
+  fprintf (FILE, "%s%d:\n", PREFIX, NUM)
+
+/* This is how to output a label for a jump table.  Arguments are the same as
+   for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
+   passed. */
+
+#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN)	\
+{ ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
+
+/* This is how to store into the string LABEL
+   the symbol_ref name of an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.
+   This is suitable for output with `assemble_name'.  */
+
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
+  sprintf (LABEL, "*%s%d", PREFIX, NUM)
+
+/* This is how to output an assembler line defining a `double' constant.  */
+
+#define ASM_OUTPUT_DOUBLE(FILE,VALUE)		\
+  fprintf (FILE, "\t.double %.20e\n", (VALUE))
+
+/* This is how to output an assembler line defining a `float' constant.  */
+
+#define ASM_OUTPUT_FLOAT(FILE,VALUE)		\
+  fprintf (FILE, "\t.float %.20e\n", (VALUE))
+
+/* This is how to output an assembler line defining an `int' constant.  */
+
+#define ASM_OUTPUT_INT(FILE,VALUE)  \
+( fprintf (FILE, "\t.word "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* Likewise for `char' and `short' constants.  */
+
+#define ASM_OUTPUT_SHORT(FILE,VALUE)  \
+( fprintf (FILE, "\t.hword "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+#define ASM_OUTPUT_CHAR(FILE,VALUE)  \
+( fprintf (FILE, "\t.byte "),			\
+  output_addr_const (FILE, (VALUE)),		\
+  fprintf (FILE, "\n"))
+
+/* This is how to output an insn to push a register on the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)					\
+  fprintf (FILE, "\tsub %s,%s,4\n\tstore 0,0,%s,%s\n",			\
+           reg_names[R_MSP], reg_names[R_MSP], reg_names[REGNO],	\
+	   reg_names[R_MSP]);
+
+/* This is how to output an insn to pop a register from the stack.
+   It need not be very fast code.  */
+
+#define ASM_OUTPUT_REG_POP(FILE,REGNO)					\
+  fprintf (FILE, "\tload 0,0,%s,%s\n\tadd %s,%s,4\n",			\
+           reg_names[REGNO], reg_names[R_MSP], reg_names[R_MSP],	\
+	   reg_names[R_MSP]);
+
+/* This is how to output an assembler line for a numeric constant byte.  */
+
+#define ASM_OUTPUT_BYTE(FILE,VALUE)  \
+  fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
+
+/* This is how to output an element of a case-vector that is absolute.  */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
+  fprintf (FILE, "\t.word L%d\n", VALUE)
+
+/* This is how to output an element of a case-vector that is relative.
+   Don't define this if it is not supported. */
+
+/* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+
+#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
+  if ((LOG) != 0)			\
+    fprintf (FILE, "\t.align %d\n", 1 << (LOG))
+
+#define ASM_OUTPUT_SKIP(FILE,SIZE)  \
+  fprintf (FILE, "\t.block %d\n", (SIZE))
+
+/* This says how to output an assembler line
+   to define a global common symbol.  */
+
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)  \
+( fputs ("\t.comm ", (FILE)),			\
+  assemble_name ((FILE), (NAME)),		\
+  fprintf ((FILE), ",%d\n", (SIZE)))
+
+/* This says how to output an assembler line
+   to define a local common symbol.  */
+
+#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED)	\
+( fputs ("\t.lcomm ", (FILE)),				\
+  assemble_name ((FILE), (NAME)),			\
+  fprintf ((FILE), ",%d\n", (SIZE)))
+
+/* Store in OUTPUT a string (made with alloca) containing
+   an assembler-name for a local static variable named NAME.
+   LABELNO is an integer which is different for each call.  */
+
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),	\
+  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
+
+/* Define the parentheses used to group arithmetic operations
+   in assembler code.  */
+
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* Define results of standard character escape sequences.  */
+#define TARGET_BELL 007
+#define TARGET_BS 010
+#define TARGET_TAB 011
+#define TARGET_NEWLINE 012
+#define TARGET_VT 013
+#define TARGET_FF 014
+#define TARGET_CR 015
+
+/* Print operand X (an rtx) in assembler syntax to file FILE.
+   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
+   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
+
+#define PRINT_OPERAND(FILE, X, CODE)  print_operand (FILE, X, CODE)
+
+/* Determine which codes are valid without a following integer.  These must
+   not be alphabetic.
+
+   We support `#' which is null if a delay slot exists, otherwise
+   "\n\tnop" and `*' which prints the register name for TPC (gr122).  */
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#' || (CODE) == '*')
+
+/* Print a memory address as an operand to reference that memory location.  */
+
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR)  \
+{ register rtx addr = ADDR;					\
+  if (!REG_P (addr)						\
+      && ! (GET_CODE (addr) == CONST_INT			\
+	    && INTVAL (addr) >= 0 && INTVAL (addr) < 256))	\
+    abort ();							\
+  output_operand (addr, 0);					\
+}
+/* Define the codes that are matched by predicates in a29k.c.  */
+
+#define PREDICATE_CODES \
+  {"cint_8_operand", {CONST_INT}},				\
+  {"cint_16_operand", {CONST_INT}},				\
+  {"long_const_operand", {CONST_INT, CONST, CONST_DOUBLE,	\
+			  LABEL_REF, SYMBOL_REF}},		\
+  {"shift_constant_operand", {CONST_INT, ASHIFT}},		\
+  {"const_0_operand", {CONST_INT, ASHIFT}},			\
+  {"const_8_operand", {CONST_INT, ASHIFT}},			\
+  {"const_16_operand", {CONST_INT, ASHIFT}},			\
+  {"const_24_operand", {CONST_INT, ASHIFT}},			\
+  {"float_const_operand", {CONST_DOUBLE}},			\
+  {"gpc_reg_operand", {SUBREG, REG}},				\
+  {"gpc_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \
+  {"gpc_reg_or_integer_constant_operand", {SUBREG, REG,		\
+					   CONST_INT, CONST_DOUBLE}}, \
+  {"gpc_reg_or_immediate_operand", {SUBREG, REG, CONST_INT,	\
+				    CONST_DOUBLE, CONST,	\
+				    SYMBOL_REF, LABEL_REF}},	\
+  {"spec_reg_operand", {REG}},					\
+  {"accum_reg_operand", {REG}},					\
+  {"srcb_operand", {SUBREG, REG, CONST_INT}},			\
+  {"cmplsrcb_operand", {SUBREG, REG, CONST_INT}},		\
+  {"reg_or_immediate_operand", {SUBREG, REG, CONST_INT, CONST,	\
+				CONST_DOUBLE, CONST, SYMBOL_REF, LABEL_REF}}, \
+  {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}},		\
+  {"and_operand", {SUBREG, REG, CONST_INT}},			\
+  {"add_operand", {SUBREG, REG, CONST_INT}},			\
+  {"call_operand", {SYMBOL_REF, CONST_INT}},			\
+  {"in_operand", {SUBREG, MEM, REG, CONST_INT, CONST, SYMBOL_REF, \
+		  LABEL_REF, CONST_DOUBLE}},			\
+  {"out_operand", {SUBREG, REG, MEM}},				\
+  {"reload_memory_operand", {SUBREG, REG, MEM}},		\
+  {"fp_comparison_operator", {EQ, GT, GE}},			\
+  {"branch_operator", {GE, LT}},				\
+  {"load_multiple_operation", {PARALLEL}},			\
+  {"store_multiple_operation", {PARALLEL}},			\
+  {"epilogue_operand", {CODE_LABEL}},
diff --git a/gcc/config/a29k/a29k.md b/gcc/config/a29k/a29k.md
new file mode 100755
index 0000000..cc4f422
--- /dev/null
+++ b/gcc/config/a29k/a29k.md
@@ -0,0 +1,2874 @@
+;;- Machine description for AMD Am29000 for GNU C compiler
+;;   Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc.
+;;   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;; The insns in this file are presented in the same order as the AMD 29000
+;; User's Manual (i.e., alphabetical by machine op-code).
+;;
+;; DEFINE_EXPAND's are located near the first occurrence of the major insn
+;; that they generate.
+
+;; The only attribute we have is the type.  We only care about calls, branches,
+;; loads, stores, floating-point operations, and multi-word insns.
+;; Everything else is miscellaneous.
+
+(define_attr "type"
+  "call,branch,load,store,fadd,fmul,fam,fdiv,fsqrt,dmul,dam,ddiv,dsqrt,multi,misc"
+  (const_string "misc"))
+
+;; ASM insns cannot go into a delay slot, so call them "multi".
+(define_asm_attributes [(set_attr "type" "multi")])
+
+(define_attr "in_delay_slot" "yes,no"
+  (if_then_else (eq_attr "type" "call,branch,multi")  (const_string "no")
+		(const_string "yes")))
+
+;; Branch and call insns require a single delay slot.  Annulling is not
+;; supported.
+(define_delay (eq_attr "type" "call,branch")
+  [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
+
+;; Define the function unit usages.  We first define memory as a unit.
+(define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 5
+  [(eq_attr "type" "load")])
+(define_function_unit "memory" 1 0 (eq_attr "type" "load") 6 6
+  [(eq_attr "type" "store")])
+(define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
+
+;; Now define the function units for the floating-point support.  Most
+;; units are pipelined and can accept an input every cycle.
+;;
+;; Note that we have an inaccuracy here.  If a fmac insn is issued, followed
+;; 2 cycles later by a fadd, there will be a conflict for the floating
+;; adder that we can't represent.  Also, all insns will conflict for the
+;; floating-point rounder.  It isn't clear how to represent this.
+
+(define_function_unit "multiplier" 1 0 (eq_attr "type" "fmul") 3 0)
+(define_function_unit "multiplier" 1 0 (eq_attr "type" "dmul") 6 4)
+(define_function_unit "multiplier" 1 0 (eq_attr "type" "fam") 6 0)
+(define_function_unit "multiplier" 1 0 (eq_attr "type" "dam") 9 4)
+
+(define_function_unit "adder" 1 0 (eq_attr "type" "fadd,fam,dam") 3 0)
+
+(define_function_unit "divider" 1 0 (eq_attr "type" "fdiv") 11 10)
+(define_function_unit "divider" 1 0 (eq_attr "type" "fsqrt") 28 27)
+(define_function_unit "divider" 1 0 (eq_attr "type" "ddiv") 18 17)
+(define_function_unit "divider" 1 0 (eq_attr "type" "dsqrt") 57 56)
+
+;; ADD
+(define_insn "addsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+		 (match_operand:SI 2 "add_operand" "rI,N")))]
+  ""
+  "@
+   add %0,%1,%2
+   sub %0,%1,%n2")
+
+(define_insn "adddi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
+  ""
+  "add %L0,%L1,%L2\;addc %0,%1,%2"
+  [(set_attr "type" "multi")])
+
+;; AND/ANDN
+(define_insn "andsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+		(match_operand:SI 2 "and_operand" "rI,K")))]
+  ""
+  "@
+   and %0,%1,%2
+   andn %0,%1,%C2")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
+		(match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
+  ""
+  "@
+   andn %0,%2,%1
+   nor %0,%1,%C2")
+
+;; CALLI
+;;
+;; Each call pattern is duplicated so that we can add CLOBBERs to the
+;; resulting insn.
+;;
+;; We indicate that LR0 is clobbered in the CALL_INSN itself.  Otherwise,
+;; reorg will think it is just clobbered by the called function.
+
+(define_expand "call"
+  [(use (match_operand:SI 0 "" ""))
+   (use (match_operand 1 "" ""))
+   (use (match_operand 2 "" ""))]
+  ""
+  "
+{ rtx insn = emit_call_insn (gen_call_internal (operands[0], operands[1]));
+  a29k_clobbers_to (insn, operands[2]);
+
+  DONE;
+}")
+ 
+(define_expand "call_internal"
+  [(parallel [(call (match_operand:SI 0 "" "")
+		    (match_operand 1 "" ""))
+	      (clobber (scratch:SI))])]
+  ""
+  "
+{
+  if (GET_CODE (operands[0]) != MEM)
+    abort ();
+
+  /* We tell here whether this is a recursive call, since this insn may
+     later be inlined into another function.  */
+  if (! TARGET_SMALL_MEMORY
+      && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
+    operands[0] = gen_rtx (MEM, SImode,
+			   force_reg (Pmode, XEXP (operands[0], 0)));
+}")
+ 
+(define_expand "call_value"
+  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
+   (use (match_operand:SI 1 "" ""))
+   (use (match_operand 2 "" ""))
+   (use (match_operand 3 "" ""))]
+  ""
+  "
+{ rtx insn = emit_call_insn (gen_call_value_internal (operands[0], operands[1],
+						      operands[2]));
+
+  a29k_clobbers_to (insn, operands[3]);
+  DONE;
+}")
+ 
+(define_expand "call_value_internal"
+  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
+		   (call (match_operand:SI 1 "" "")
+			 (match_operand 2 "" "")))
+		   (clobber (scratch:SI))])]
+  ""
+  "
+{
+  if (GET_CODE (operands[1]) != MEM)
+    abort ();
+
+  /* We tell here whether this is a recursive call, since this insn may
+     later be inlined into another function.  */
+  if (! TARGET_SMALL_MEMORY
+      && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
+    operands[1] = gen_rtx (MEM, SImode,
+			   force_reg (Pmode, XEXP (operands[1], 0)));
+
+}")
+ 
+(define_insn ""
+  [(call (match_operand:SI 0 "memory_operand" "m")
+	 (match_operand 1 "" ""))
+   (clobber (match_scratch:SI 2 "=&l"))]
+  "GET_CODE (XEXP (operands[0], 0)) != CONST_INT"
+  "calli lr0,%0%#"
+  [(set_attr "type" "call")])
+
+(define_insn ""
+  [(call (mem:SI (match_operand:SI 0 "call_operand" "i"))
+	 (match_operand:SI 1 "general_operand" "g"))
+   (clobber (match_scratch:SI 2 "=&l"))]
+  ""
+  "call lr0,%F0"
+  [(set_attr "type" "call")])
+
+(define_insn ""
+  [(set (match_operand 0 "gpc_reg_operand" "=r")
+	(call (match_operand:SI 1 "memory_operand" "m")
+	      (match_operand 2 "" "")))
+   (clobber (match_scratch:SI 3 "=&l"))]
+  "GET_CODE (XEXP (operands[1], 0)) != CONST_INT"
+  "calli lr0,%1%#"
+  [(set_attr "type" "call")])
+
+(define_insn ""
+  [(set (match_operand 0 "gpc_reg_operand" "=r")
+	(call (mem:SI (match_operand:SI 1 "call_operand" "i"))
+	      (match_operand:SI 2 "general_operand" "g")))
+   (clobber (match_scratch:SI 3 "=&l"))]
+  ""
+  "call lr0,%F1"
+  [(set_attr "type" "call")])
+
+(define_expand "probe"
+  [(call (mem:SI (symbol_ref:SI "_msp_check"))
+	 (const_int 1))]
+  "TARGET_STACK_CHECK"
+  "")
+
+;; This is used for internal routine calls via TPC.  Currently used only
+;; in probe, above.
+(define_insn ""
+  [(call (mem:SI (match_operand:SI 0 "immediate_operand" "s"))
+	 (const_int 1))]
+  ""
+  "call %*,%0"
+  [(set_attr "type" "call")])
+
+;; CONST, CONSTH, CONSTN
+;;
+;; Many of these are generated from move insns.
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(and:SI (match_operand:SI 1 "immediate_operand" "i")
+		(const_int 65535)))]
+  ""
+  "const %0,%1")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+			 (const_int 16)
+			 (match_operand:SI 1 "const_0_operand" ""))
+	(ashiftrt:SI (match_operand:SI 2 "immediate_operand" "i")
+		     (const_int 16)))]
+  ""
+  "consth %0,%2")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+			 (const_int 16)
+			 (match_operand:SI 1 "const_0_operand" ""))
+	(match_operand:SI 2 "cint_16_operand" "J"))]
+  ""
+  "consth %0,%m2")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0"))
+		(match_operand:SI 2 "const_int_operand" "n")))]
+  "(INTVAL (operands[2]) & 0xffff) == 0"
+  "consth %0,%2")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0"))
+		(and:SI (match_operand:SI 2 "immediate_operand" "i")
+			(const_int -65536))))]
+  ""
+  "consth %0,%2")
+
+;; CONVERT
+(define_insn "fix_truncsfsi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(fix:SI (match_operand:SF 1 "register_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "convert %0,%1,0,3,0,1")
+
+(define_insn "fix_truncdfsi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(fix:SI (match_operand:DF 1 "register_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "convert %0,%1,0,3,0,2")
+
+(define_insn "fixuns_truncsfsi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "convert %0,%1,1,3,0,1")
+
+(define_insn "fixuns_truncdfsi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "convert %0,%1,1,3,0,2")
+
+(define_insn "truncdfsf2"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "convert %0,%1,0,4,1,2")
+
+(define_insn "extendsfdf2"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "convert %0,%1,0,4,2,1")
+
+(define_insn "floatsisf2"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "convert %0,%1,0,4,1,0")
+
+(define_insn "floatsidf2"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "convert %0,%1,0,4,2,0")
+
+(define_insn "floatunssisf2"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "convert %0,%1,1,4,1,0")
+
+(define_insn "floatunssidf2"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "convert %0,%1,1,4,2,0")
+
+;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(match_operator 3 "comparison_operator"
+			[(match_operand:SI 1 "gpc_reg_operand" "r")
+			 (match_operand:SI 2 "srcb_operand" "rI")]))]
+  ""
+  "cp%J3 %0,%1,%2")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(match_operator 3 "fp_comparison_operator"
+			[(match_operand:SF 1 "register_operand" "r")
+			 (match_operand:SF 2 "register_operand" "r")]))]
+  "! TARGET_SOFT_FLOAT"
+  "f%J3 %0,%1,%2"
+  [(set_attr "type" "fadd")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(match_operator 3 "fp_comparison_operator"
+			[(match_operand:DF 1 "register_operand" "r")
+			 (match_operand:DF 2 "register_operand" "r")]))]
+  "! TARGET_SOFT_FLOAT"
+  "d%J3 %0,%1,%2"
+  [(set_attr "type" "fadd")])
+
+;; DADD
+(define_expand "adddf3"
+  [(set (match_operand:DF 0 "register_operand" "")
+	(plus:DF (match_operand:DF 1 "register_operand" "")
+		 (match_operand:DF 2 "register_operand" "")))]
+  "! TARGET_SOFT_FLOAT"
+  "")
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(plus:DF (match_operand:DF 1 "register_operand" "%r")
+		 (match_operand:DF 2 "register_operand" "r")))]
+  "! TARGET_29050 "
+  "dadd %0,%1,%2"
+  [(set_attr "type" "fadd")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=r,a")
+	(plus:DF (match_operand:DF 1 "register_operand" "%r,r")
+		 (match_operand:DF 2 "register_operand" "r,0")))]
+  "TARGET_29050"
+  "@
+   dadd %0,%1,%2
+   dmac 8,%0,%1,%1"
+  [(set_attr "type" "fadd,dam")])
+
+;; DDIV
+(define_insn "divdf3"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(div:DF (match_operand:DF 1 "register_operand" "=r")
+		(match_operand:DF 2 "register_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "ddiv %0,%1,%2"
+  [(set_attr "type" "ddiv")])
+
+;; DIVIDE
+;;
+;; We must set Q to the sign extension of the dividend first.  For MOD, we
+;; must get the remainder from Q.
+;;
+;; For divmod: operand 1 is divided by operand 2; quotient goes to operand
+;; 0 and remainder to operand 3.
+(define_expand "divmodsi4"
+  [(set (match_dup 4)
+	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
+		     (const_int 31)))
+   (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
+		   (div:SI (match_dup 1)
+			   (match_operand:SI 2 "gpc_reg_operand" "")))
+	      (set (match_operand:SI 3 "gpc_reg_operand" "")
+		   (mod:SI (match_dup 1)
+			   (match_dup 2)))
+	      (use (match_dup 4))])]
+  ""
+  "
+{
+  operands[4] = gen_reg_rtx (SImode);
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+		(match_operand:SI 2 "gpc_reg_operand" "r")))
+   (set (match_operand:SI 3 "register_operand" "=q")
+	(mod:SI (match_dup 1)
+		(match_dup 2)))
+   (use (match_operand:SI 4 "register_operand" "3"))]
+  ""
+  "divide %0,%1,%2")
+
+;; DIVIDU
+;;
+;; Similar to DIVIDE.
+(define_expand "udivmodsi4"
+  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
+		   (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
+			    (match_operand:SI 2 "gpc_reg_operand" "")))
+	      (set (match_operand:SI 3 "gpc_reg_operand" "")
+		   (umod:SI (match_dup 1)
+			    (match_dup 2)))
+	      (use (const_int 0))])]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+		 (match_operand:SI 2 "gpc_reg_operand" "r")))
+   (set (match_operand:SI 3 "register_operand" "=q")
+	(umod:SI (match_dup 1)
+		 (match_dup 2)))
+   (use (match_operand:SI 4 "const_int_operand" "3"))]
+  ""
+  "dividu %0,%1,%2")
+
+;; DMAC/DMSM
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=a,*r")
+	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r,A")
+			  (match_operand:DF 2 "register_operand" "r,r"))
+		 (match_operand:DF 3 "register_operand" "0,*r")))]
+  "TARGET_29050"
+  "@
+   dmac 0,%0,%1,%2
+   dmsm %0,%2,%3"
+  [(set_attr "type" "dam")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=a")
+	(plus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
+			  (match_operand:DF 2 "register_operand" "r"))
+		 (match_operand:DF 3 "register_operand" "0")))]
+  "TARGET_29050"
+  "dmac 1,%0,%2,%1"
+  [(set_attr "type" "dam")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=a")
+	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%r")
+			   (match_operand:DF 2 "register_operand" "r"))
+		  (match_operand:DF 3 "register_operand" "0")))]
+  "TARGET_29050"
+  "dmac 2,%0,%1,%2"
+  [(set_attr "type" "dam")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=a")
+	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "r")
+			   (neg:DF (match_operand:DF 2 "register_operand" "r")))
+		  (match_operand:DF 3 "register_operand" "0")))]
+  "TARGET_29050"
+  "dmac 3,%0,%1,%2"
+  [(set_attr "type" "dam")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=a")
+	(mult:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
+		 (match_operand:DF 2 "register_operand" "r")))]
+  "TARGET_29050"
+  "dmac 5,%0,%2,%1"
+  [(set_attr "type" "dam")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=a")
+	(minus:DF (neg:DF (match_operand:DF 1 "register_operand" "r"))
+		  (match_operand:DF 2 "register_operand" "0")))]
+  "TARGET_29050"
+  "dmac 11,%0,%1,%1"
+  [(set_attr "type" "dam")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=a")
+	(neg:DF (plus:DF (match_operand:DF 1 "register_operand" "%r")
+			 (match_operand:DF 2 "register_operand" "0"))))]
+  "TARGET_29050"
+  "dmac 11,%0,%1,%1"
+  [(set_attr "type" "dam")])
+
+(define_insn ""
+ [(set (match_operand:DF 0 "register_operand" "=r,r,a")
+       (neg:DF (match_operand:DF 1 "register_operand" "0,r,r")))
+  (clobber (match_scratch:SI 2 "=&r,&r,X"))]
+ "TARGET_29050"
+ "@
+  cpeq %2,gr1,gr1\;xor %0,%1,%2
+  cpeq %2,gr1,gr1\;xor %0,%1,%2\;sll %L0,%L1,0
+  dmac 13,%0,%1,%1"
+ [(set_attr "type" "multi,multi,dam")])
+
+;; DMUL
+(define_expand "muldf3"
+  [(set (match_operand:DF 0 "register_operand" "")
+	(mult:DF (match_operand:DF 1 "register_operand" "")
+		 (match_operand:DF 2 "register_operand" "")))]
+  "! TARGET_SOFT_FLOAT"
+  "")
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(mult:DF (match_operand:DF 1 "register_operand" "%r")
+		 (match_operand:DF 2 "register_operand" "r")))]
+  "! TARGET_29050"
+  "dmul %0,%1,%2"
+  [(set_attr "type" "dmul")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=r,a")
+	(mult:DF (match_operand:DF 1 "register_operand" "%r,r")
+		 (match_operand:DF 2 "register_operand" "r,r")))]
+  "TARGET_29050"
+  "@
+   dmul %0,%1,%2
+   dmac 4,%0,%1,%2"
+  [(set_attr "type" "dmul,dam")])
+
+;; DSUB
+(define_expand "subdf3"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(minus:DF (match_operand:DF 1 "register_operand" "r")
+		  (match_operand:DF 2 "register_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "")
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(minus:DF (match_operand:DF 1 "register_operand" "r")
+		  (match_operand:DF 2 "register_operand" "r")))]
+  "! TARGET_29050"
+  "dsub %0,%1,%2"
+  [(set_attr "type" "fadd")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=r,a,a")
+	(minus:DF (match_operand:DF 1 "register_operand" "r,0,r")
+		  (match_operand:DF 2 "register_operand" "r,r,0")))]
+  "TARGET_29050"
+  "@
+   dsub %0,%1,%2
+   dmac 9,%0,%2,%2
+   dmac 10,%0,%1,%1"
+  [(set_attr "type" "fadd,dam,dam")])
+
+;; EXBYTE
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
+			(const_int -256))
+		(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
+				 (const_int 8)
+				 (ashift:PSI
+				  (match_operand:PSI 3 "register_operand" "b")
+				  (const_int 3)))))]
+  ""
+  "exbyte %0,%2,%1")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			 (const_int 8)
+			 (ashift:PSI
+			  (match_operand:PSI 2 "register_operand" "b")
+			  (const_int 3))))]
+  ""
+  "exbyte %0,%1,0")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+			 (const_int 8)
+			 (match_operand:PSI 1 "const_24_operand" ""))
+	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
+			 (const_int 8)
+			 (ashift:PSI
+			  (match_operand:PSI 3 "register_operand" "b")
+			  (const_int 3))))]
+  ""
+  "exbyte %0,%2,%0")
+
+(define_expand "extzv"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
+			 (match_operand:SI 2 "general_operand" "")
+			 (match_operand:SI 3 "general_operand" "")))]
+  ""
+  "
+{
+  int size, pos;
+
+  if (GET_CODE (operands[2]) != CONST_INT
+      || GET_CODE (operands[3]) != CONST_INT)
+    FAIL;
+
+  size = INTVAL (operands[2]);
+  pos = INTVAL (operands[3]);
+
+  /* Can't do this unless a byte extraction.  If extracting the high
+     or low byte, don't do this because a shift or AND is shorter.
+     Don't do 16-bit extracts, since the only two are the high and low
+     ends, and it is faster to do them with CONSTH and SRL.  */
+
+  if (size != 8 || (pos != 8 && pos != 16))
+    FAIL;
+
+  operands[3] = gen_rtx (ASHIFT, PSImode,
+			 force_reg (PSImode, GEN_INT (pos / 8)),
+			 GEN_INT (3));
+
+}")
+
+;; EXHW
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI (match_operand:SI 1 "srcb_operand" "rI")
+		(const_int -65536))
+		(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
+				 (const_int 16)
+				 (ashift:PSI
+				  (match_operand:PSI 3 "register_operand" "b")
+				  (const_int 3)))))]
+  ""
+  "exhw %0,%2,%1")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			 (const_int 16)
+			 (ashift:PSI
+			  (match_operand:PSI 2 "register_operand" "b")
+			  (const_int 3))))]
+  ""
+  "exhw %0,%1,0")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+			 (const_int 16)
+			 (match_operand:PSI 1 "const_16_operand" ""))
+	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
+			 (const_int 16)
+			 (ashift:PSI
+			  (match_operand:PSI 3 "register_operand" "b")
+			  (const_int 3))))]
+  ""
+  "exhw %0,%2,%0")
+
+;; EXHWS
+;;
+;; This is probably unused.  The high-order 16-bits are obtained with an SRA
+;; insn.  The low-order 16 bits are a sign-extend, which is a pair of
+;; shifts.  Setting BP followed by the insn is equivalent, so we don't
+;; bother going to any trouble to generate this insn.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(sign_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			 (const_int 16)
+			 (ashift:PSI
+			  (match_operand:PSI 2 "register_operand" "b")
+			  (const_int 3))))]
+  ""
+  "exhws %0,%1")
+
+;; EXTRACT
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+		   (match_operand:PSI 2 "register_operand" "f")))]
+  ""
+  "extract %0,%1,%1")
+
+(define_expand "rotlsi3"
+  [(set (match_dup 3)
+	(match_operand:SI 2 "gpc_reg_or_immediate_operand" ""))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
+		   (match_dup 3)))]
+  ""
+  "
+{ operands[2] = gen_lowpart (PSImode, operands[2]);
+  operands[3] = gen_reg_rtx (PSImode);
+}")
+
+;; It would be nice to be able to have a define_split corresponding to the
+;; above, but there is no way to tell combine we need a PSImode temporary.
+;; If we put a (clobber (scratch:PSI)) there, combine would merge the above
+;; two insns.  This is bad because it then thinks only one insn is needed.
+
+;; FADD
+(define_expand "addsf3"
+  [(set (match_operand:SF 0 "register_operand" "")
+	(plus:SF (match_operand:SF 1 "register_operand" "")
+		 (match_operand:SF 2 "register_operand" "")))]
+  "! TARGET_SOFT_FLOAT"
+  "")
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(plus:SF (match_operand:SF 1 "register_operand" "%r")
+		 (match_operand:SF 2 "register_operand" "r")))]
+  "! TARGET_29050"
+  "fadd %0,%1,%2"
+  [(set_attr "type" "fadd")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=r,a")
+	(plus:SF (match_operand:SF 1 "register_operand" "%r,r")
+		 (match_operand:SF 2 "register_operand" "r,0")))]
+  "TARGET_29050"
+  "@
+   fadd %0,%1,%2
+   fmac 8,%0,%1,%1"
+  [(set_attr "type" "fadd,fam")])
+
+;; FDIV
+(define_insn "divsf3"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(div:SF (match_operand:SF 1 "register_operand" "=r")
+		(match_operand:SF 2 "register_operand" "r")))]
+  "! TARGET_SOFT_FLOAT"
+  "fdiv %0,%1,%2"
+  [(set_attr "type" "fdiv")])
+
+;; FDMUL
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r"))
+		 (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
+  "! TARGET_SOFT_FLOAT"
+  "fdmul %0,%1,%2")
+
+;; FMAC/FMSM
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=a,*r")
+	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r,A")
+			  (match_operand:SF 2 "register_operand" "r,r"))
+		 (match_operand:SF 3 "register_operand" "0,*r")))]
+  "TARGET_29050"
+  "@
+   fmac 0,%0,%1,%2
+   fmsm %0,%2,%3"
+  [(set_attr "type" "fam")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=a")
+	(plus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
+			  (match_operand:SF 2 "register_operand" "r"))
+		 (match_operand:SF 3 "register_operand" "0")))]
+  "TARGET_29050"
+  "fmac 1,%0,%2,%1"
+  [(set_attr "type" "fam")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=a")
+	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%r")
+			   (match_operand:SF 2 "register_operand" "r"))
+		  (match_operand:SF 3 "register_operand" "0")))]
+  "TARGET_29050"
+  "fmac 2,%0,%1,%2"
+  [(set_attr "type" "fam")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=a")
+	(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
+			   (match_operand:SF 2 "register_operand" "r"))
+		  (match_operand:SF 3 "register_operand" "0")))]
+  "TARGET_29050"
+  "fmac 3,%0,%2,%1"
+  [(set_attr "type" "fam")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=a")
+	(mult:SF (neg:SF (match_operand:SF 1 "register_operand" "r"))
+		 (match_operand:SF 2 "register_operand" "r")))]
+  "TARGET_29050"
+  "fmac 5,%0,%2,%1"
+  [(set_attr "type" "fam")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=a")
+	(minus:SF (neg:SF (match_operand:SF 1 "register_operand" "%r"))
+		  (match_operand:SF 2 "register_operand" "0")))]
+  "TARGET_29050"
+  "fmac 11,%0,%1,%1"
+  [(set_attr "type" "fam")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=a")
+	(neg:SF (plus:SF (match_operand:SF 1 "register_operand" "%r")
+			 (match_operand:SF 2 "register_operand" "0"))))]
+  "TARGET_29050"
+  "fmac 11,%0,%1,%1"
+  [(set_attr "type" "fam")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=r,a")
+	(neg:SF (match_operand:SF 1 "register_operand" "r,r")))
+   (clobber (match_scratch:SI 2 "=&r,X"))]
+  "TARGET_29050"
+  "@
+   cpeq %2,gr1,gr1\;xor %0,%1,%2
+   fmac 13,%0,%1,%1"
+  [(set_attr "type" "multi,fam")])
+
+;; FMUL
+(define_expand "mulsf3"
+  [(set (match_operand:SF 0 "register_operand" "")
+	(mult:SF (match_operand:SF 1 "register_operand" "")
+		 (match_operand:SF 2 "register_operand" "")))]
+  "! TARGET_SOFT_FLOAT"
+  "")
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(mult:SF (match_operand:SF 1 "register_operand" "%r")
+		 (match_operand:SF 2 "register_operand" "r")))]
+  "! TARGET_29050"
+  "fmul %0,%1,%2"
+  [(set_attr "type" "fmul")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=r,a")
+	(mult:SF (match_operand:SF 1 "register_operand" "%r,r")
+		 (match_operand:SF 2 "register_operand" "r,r")))]
+  "TARGET_29050"
+  "@
+   fmul %0,%1,%2
+   fmac 4,%0,%1,%2"
+  [(set_attr "type" "fmul,fam")])
+
+;; FSUB
+(define_expand "subsf3"
+  [(set (match_operand:SF 0 "register_operand" "")
+	(minus:SF (match_operand:SF 1 "register_operand" "")
+		  (match_operand:SF 2 "register_operand" "")))]
+  "! TARGET_SOFT_FLOAT"
+  "")
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(minus:SF (match_operand:SF 1 "register_operand" "r")
+		  (match_operand:SF 2 "register_operand" "r")))]
+  "! TARGET_29050"
+  "fsub %0,%1,%2"
+  [(set_attr "type" "fadd")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=r,a,a")
+	(minus:SF (match_operand:SF 1 "register_operand" "r,0,r")
+		  (match_operand:SF 2 "register_operand" "r,r,0")))]
+  "TARGET_29050"
+  "@
+   fsub %0,%1,%2
+   fmac 9,%0,%2,%2
+   fmac 10,%0,%1,%1"
+  [(set_attr "type" "fadd,fam,fam")])
+
+;; INBYTE
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+			 (const_int 8)
+			 (ashift:PSI
+			  (match_operand:PSI 2 "register_operand" "b")
+			  (const_int 3)))
+	(match_operand:SI 1 "srcb_operand" "rI"))]
+  ""
+  "inbyte %0,%0,%1")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI
+		 (not:SI
+		  (ashift:SI (const_int 255)
+			     (ashift:PSI
+			      (match_operand:PSI 3 "register_operand" "b")
+			      (const_int 3))))
+		 (match_operand:SI 1 "gpc_reg_operand" "r"))
+		(ashift:SI (zero_extend:SI
+			    (match_operand:QI 2 "srcb_operand" "rI"))
+			   (ashift:PSI (match_dup 3) (const_int 3)))))]
+  ""
+  "inbyte %0,%1,%2")
+
+;; INHW
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
+			 (const_int 16)
+			 (ashift:PSI
+			  (match_operand:PSI 2 "register_operand" "b")
+			  (const_int 3)))
+	(match_operand:SI 1 "srcb_operand" "rI"))]
+  ""
+  "inhw %0,%0,%1")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI
+		 (not:SI
+		  (ashift:SI (const_int 65535)
+			     (ashift:PSI
+			      (match_operand:PSI 3 "register_operand" "b")
+			      (const_int 3))))
+		 (match_operand:SI 1 "gpc_reg_operand" "r"))
+		(ashift:SI (zero_extend:SI
+			    (match_operand:HI 2 "srcb_operand" "rI"))
+			   (ashift:PSI (match_dup 3) (const_int 3)))))]
+  ""
+  "inhw %0,%1,%2")
+
+(define_expand "insv"
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "")
+			 (match_operand:SI 1 "general_operand" "")
+			 (match_operand:SI 2 "general_operand" ""))
+	(match_operand:SI 3 "srcb_operand" ""))]
+  ""
+  "
+{
+  int size, pos;
+
+  if (GET_CODE (operands[1]) != CONST_INT
+      || GET_CODE (operands[2]) != CONST_INT)
+    FAIL;
+
+  size = INTVAL (operands[1]);
+  pos = INTVAL (operands[2]);
+  if ((size != 8 && size != 16) || pos % size != 0)
+    FAIL;
+
+  operands[2] = gen_rtx (ASHIFT, PSImode,
+			 force_reg (PSImode, GEN_INT (pos / 8)),
+			 GEN_INT (3));
+}")
+
+;; LOAD (also used by move insn).
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			(const_int -4))))
+   (set (match_operand:PSI 2 "register_operand" "=b")
+	(truncate:PSI (match_dup 1)))]
+  "! TARGET_DW_ENABLE"
+  "load 0,16,%0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
+  "TARGET_DW_ENABLE"
+  "load 0,1,%0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
+	(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
+  "TARGET_DW_ENABLE"
+  "load 0,1,%0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
+  "TARGET_DW_ENABLE"
+  "load 0,2,%0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))
+   (clobber (match_scratch:PSI 2 "=&b"))]
+  "TARGET_DW_ENABLE"
+  "load 0,17,%0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
+	(sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))
+   (clobber (match_scratch:PSI 2 "=&b"))]
+  "TARGET_DW_ENABLE"
+  "load 0,17,%0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))
+   (clobber (match_scratch:PSI 2 "=&b"))]
+  "TARGET_DW_ENABLE"
+  "load 0,18,%0,%1"
+  [(set_attr "type" "load")])
+
+;; LOADM
+(define_expand "load_multiple"
+  [(set (match_dup 4)
+	(match_operand:PSI 2 "const_int_operand" ""))
+   (match_par_dup 3 [(set (match_operand:SI 0 "" "")
+			  (match_operand:SI 1 "" ""))])]
+  ""
+  "
+{
+  int regno;
+  int count;
+  rtx from;
+  int i;
+
+  /* Support only loading a constant number of hard registers from memory.  */
+  if (GET_CODE (operands[2]) != CONST_INT
+      || operands[2] == const1_rtx
+      || GET_CODE (operands[1]) != MEM
+      || GET_CODE (operands[0]) != REG
+      || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
+    FAIL;
+
+  count = INTVAL (operands[2]);
+  regno = REGNO (operands[0]);
+
+  /* CR gets set to the number of registers minus one.  */
+  operands[2] = GEN_INT(count - 1);
+
+  operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2));
+  from = memory_address (SImode, XEXP (operands[1], 0));
+  XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
+					 gen_rtx (REG, SImode, regno),
+					 gen_rtx (MEM, SImode, from));
+  operands[4] = gen_reg_rtx (PSImode);
+
+  XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]);
+  XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]);
+
+  for (i = 1; i < count; i++)
+    XVECEXP (operands[3], 0, i + 2)
+      = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
+		 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
+}")
+
+;; Indicate that CR is used and is then clobbered.
+(define_insn ""
+  [(set (match_operand 0 "gpc_reg_operand" "=r")
+	(match_operand 1 "memory_operand" "m"))
+   (use (match_operand:PSI 2 "register_operand" "+c"))
+   (clobber (match_dup 2))]
+  "GET_MODE (operands[0]) == GET_MODE (operands[1])
+   && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
+  "loadm 0,0,%0,%1"
+  [(set_attr "type" "load")])
+
+(define_insn ""
+  [(match_parallel 0 "load_multiple_operation"
+		   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
+			 (match_operand:SI 2 "memory_operand" "m"))
+		    (use (match_operand:PSI 3 "register_operand" "+c"))
+		    (clobber (match_dup 3))])]
+  ""
+  "loadm 0,0,%1,%2"
+  [(set_attr "type" "load")])
+
+;; MTSR (used also by move insn)
+(define_insn ""
+  [(set (match_operand:SI 0 "spec_reg_operand" "=*h,*h")
+	(and:SI (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")
+		(match_operand:SI 2 "const_int_operand" "n,n")))]
+  "masks_bits_for_special (operands[0], operands[2])"
+  "@
+   mtsr %0,%1
+   mtsrim %0,%1")
+
+(define_insn ""
+  [(set (match_operand:PSI 0 "register_operand" "=h,h")
+	(truncate:PSI
+	 (match_operand:SI 1 "gpc_reg_or_immediate_operand" "r,i")))]
+  ""
+  "@
+   mtsr %0,%1
+   mtsrim %0,%1")
+
+;; MULTIPLY, MULTM, MULTMU
+(define_insn "mulsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
+		 (match_operand:SI 2 "gpc_reg_operand" "r")))
+   (clobber (match_scratch:SI 3 "=&q"))]
+  ""
+  "multiply %0,%1,%2")
+
+(define_insn "mulsidi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
+   (clobber (match_scratch:SI 3 "=&q"))]
+  "TARGET_MULTM"
+  "multiply %L0,%1,%2\;multm %0,%1,%2"
+  [(set_attr "type" "multi")])
+
+(define_split
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
+		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
+   (clobber (reg:SI 180))]
+  "reload_completed"
+  [(parallel [(set (match_dup 3)
+		   (mult:SI (match_dup 1) (match_dup 2)))
+	      (clobber (reg:SI 180))])
+   (parallel [(set (match_dup 4)
+		   (truncate:SI
+		    (lshiftrt:DI
+		     (mult:DI (sign_extend:DI (match_dup 1))
+			      (sign_extend:DI (match_dup 2)))
+		     (const_int 32))))
+	      (clobber (reg:SI 180))])]
+  "
+{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
+  operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
+			    
+(define_insn "umulsidi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
+   (clobber (match_scratch:SI 3 "=&q"))]
+  "TARGET_MULTM"
+  "multiplu %L0,%1,%2\;multmu %0,%1,%2"
+  [(set_attr "type" "multi")])
+
+(define_split
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
+		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))
+   (clobber (reg:SI 180))]
+  "reload_completed"
+  [(parallel [(set (match_dup 3)
+		   (mult:SI (match_dup 1) (match_dup 2)))
+	      (clobber (reg:SI 180))])
+   (parallel [(set (match_dup 4)
+		   (truncate:SI
+		    (lshiftrt:DI
+		     (mult:DI (zero_extend:DI (match_dup 1))
+			      (zero_extend:DI (match_dup 2)))
+		     (const_int 32))))
+	      (clobber (reg:SI 180))])]
+  "
+{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
+  operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
+			    
+(define_insn "smulsi3_highpart"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(truncate:SI
+	 (lshiftrt:DI
+	  (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+		   (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
+	  (const_int 32))))
+   (clobber (match_scratch:SI 3 "=&q"))]
+  "TARGET_MULTM"
+  "multm %0,%1,%2")
+
+(define_insn "umulsi3_highpart"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(truncate:SI
+	 (lshiftrt:DI
+	  (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+		   (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
+	  (const_int 32))))
+   (clobber (match_scratch:SI 3 "=&q"))]
+  "TARGET_MULTM"
+  "multmu %0,%1,%2")
+
+;; NAND
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+  ""
+  "nand %0,%1,%2")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		(match_operand:SI 2 "const_int_operand" "K")))]
+  ; Match TARGET_29050 in "orn" pattern for slightly better reload.
+  "! TARGET_29050 && ((unsigned) ~ INTVAL (operands[2])) < 256"
+  "nand %0,%1,%C2")
+
+;; NOR
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
+  ""
+  "nor %0,%1,%2")
+
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
+  ""
+  "nor %0,%1,0")
+
+;; OR/ORN
+(define_expand "iorsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
+		(match_operand:SI 2 "srcb_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
+		(match_operand:SI 2 "srcb_operand" "rI")))]
+  "! TARGET_29050"
+  "or %0,%1,%2")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+		(match_operand:SI 2 "and_operand" "rI,K")))]
+  "TARGET_29050"
+  "@
+   or %0,%1,%2
+   orn %0,%1,%C2")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
+		(match_operand:SI 2 "cmplsrcb_operand" "r,K")))]
+  "TARGET_29050"
+  "@
+   orn %0,%2,%1
+   nand %0,%1,%C2")
+
+
+;; SLL (also used by move insn)
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "aseq 0x40,gr1,gr1")
+
+(define_insn "ashlsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+		   (match_operand:QI 2 "srcb_operand" "rn")))]
+  ""
+  "sll %0,%1,%Q2")
+
+;; SQRT
+(define_insn "sqrtsf2"
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
+	(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
+  "TARGET_29050"
+  "sqrt %0,%1,1"
+  [(set_attr "type" "fsqrt")])
+
+(define_insn "sqrtdf2"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
+	(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
+  "TARGET_29050"
+  "sqrt %0,%1,2"
+  [(set_attr "type" "dsqrt")])
+
+;; SRA
+(define_insn "ashrsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+		     (match_operand:QI 2 "srcb_operand" "rn")))]
+  ""
+  "sra %0,%1,%Q2")
+
+;; SRL
+(define_insn "lshrsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+		     (match_operand:QI 2 "srcb_operand" "rn")))]
+  ""
+  "srl %0,%1,%Q2")
+
+;; STORE
+;;
+;; These somewhat bogus patterns exist to set OPT = 001/010 for partial-word
+;; stores on systems with DW not set.
+(define_insn ""
+  [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
+			(const_int -4)))
+	(match_operand:SI 1 "gpc_reg_operand" "r"))]
+  "! TARGET_DW_ENABLE"
+  "store 0,1,%1,%0"
+  [(set_attr "type" "store")])
+
+(define_insn ""
+  [(set (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "r")
+			(const_int -3)))
+	(match_operand:SI 1 "gpc_reg_operand" "r"))]
+  "! TARGET_DW_ENABLE"
+  "store 0,2,%1,%0"
+  [(set_attr "type" "store")])
+
+;; STOREM
+(define_expand "store_multiple"
+  [(use (match_operand 0 "" ""))
+   (use (match_operand 1 "" ""))
+   (use (match_operand 2 "" ""))]
+  ""
+  "
+{ rtx pat;
+
+ if (TARGET_NO_STOREM_BUG)
+    pat = gen_store_multiple_no_bug (operands[0], operands[1], operands[2]);
+  else
+    pat = gen_store_multiple_bug (operands[0], operands[1], operands[2]);
+
+  if (pat)
+    emit_insn (pat);
+  else
+    FAIL;
+
+  DONE;
+}")
+
+(define_expand "store_multiple_no_bug"
+  [(set (match_dup 4)
+	(match_operand:PSI 2 "const_int_operand" ""))
+   (match_par_dup 3 [(set (match_operand:SI 0 "" "")
+			  (match_operand:SI 1 "" ""))])]
+  ""
+  "
+{
+  int regno;
+  int count;
+  rtx from;
+  int i;
+
+  /* Support only storing a constant number of hard registers to memory.  */
+  if (GET_CODE (operands[2]) != CONST_INT
+      || operands[2] == const1_rtx
+      || GET_CODE (operands[0]) != MEM
+      || GET_CODE (operands[1]) != REG
+      || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
+    FAIL;
+
+  count = INTVAL (operands[2]);
+  regno = REGNO (operands[1]);
+
+  /* CR gets set to the number of registers minus one.  */
+  operands[2] = GEN_INT(count - 1);
+
+  operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 2));
+  from = memory_address (SImode, XEXP (operands[0], 0));
+  XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
+					 gen_rtx (MEM, SImode, from),
+					 gen_rtx (REG, SImode, regno));
+  operands[4] = gen_reg_rtx (PSImode);
+  XVECEXP (operands[3], 0, 1) = gen_rtx (USE, VOIDmode, operands[4]);
+  XVECEXP (operands[3], 0, 2) = gen_rtx (CLOBBER, VOIDmode, operands[4]);
+
+  for (i = 1; i < count; i++)
+    XVECEXP (operands[3], 0, i + 2)
+      = gen_rtx (SET, VOIDmode,
+		 gen_rtx (MEM, SImode, plus_constant (from, i * 4)),
+		 gen_rtx (REG, SImode, regno + i));
+}")
+
+(define_expand "store_multiple_bug"
+  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
+			  (match_operand:SI 1 "" ""))
+		     (use (match_operand:SI 2 "" ""))])]
+  ""
+  "
+{
+  int regno;
+  int count;
+  rtx from;
+  int i;
+
+  /* Support only storing a constant number of hard registers to memory.  */
+  if (GET_CODE (operands[2]) != CONST_INT
+      || operands[2] == const1_rtx
+      || GET_CODE (operands[0]) != MEM
+      || GET_CODE (operands[1]) != REG
+      || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
+    FAIL;
+
+  count = INTVAL (operands[2]);
+  regno = REGNO (operands[1]);
+
+  operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
+  from = memory_address (SImode, XEXP (operands[0], 0));
+  XVECEXP (operands[3], 0, 0) = gen_rtx (SET, VOIDmode,
+					 gen_rtx (MEM, SImode, from),
+					 gen_rtx (REG, SImode, regno));
+  XVECEXP (operands[3], 0, 1)
+    = gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, PSImode));
+
+  for (i = 1; i < count; i++)
+    XVECEXP (operands[3], 0, i + 1)
+      = gen_rtx (SET, VOIDmode,
+		 gen_rtx (MEM, SImode, plus_constant (from, i * 4)),
+		 gen_rtx (REG, SImode, regno + i));
+}")
+
+(define_insn ""
+  [(set (match_operand 0 "memory_operand" "=m")
+	(match_operand 1 "gpc_reg_operand" "r"))
+   (clobber (match_scratch:PSI 2 "=&c"))]
+  "!TARGET_NO_STOREM_BUG
+   && GET_MODE (operands[0]) == GET_MODE (operands[1])
+   && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
+  "mtsrim cr,%S1\;storem 0,0,%1,%0"
+  [(set_attr "type" "multi")])
+
+(define_insn ""
+  [(match_parallel 0 "store_multiple_operation"
+		   [(set (match_operand:SI 1 "memory_operand" "=m")
+			 (match_operand:SI 2 "gpc_reg_operand" "r"))
+		    (clobber (match_scratch:PSI 3 "=&c"))])]
+  "!TARGET_NO_STOREM_BUG"
+  "mtsrim cr,%V0\;storem 0,0,%2,%1"
+  [(set_attr "type" "multi")])
+
+(define_insn ""
+  [(set (match_operand 0 "memory_operand" "=m")
+	(match_operand 1 "gpc_reg_operand" "r"))
+   (use (match_operand:PSI 2 "register_operand" "+c"))
+   (clobber (match_dup 2))]
+  "TARGET_NO_STOREM_BUG
+   && GET_MODE (operands[0]) == GET_MODE (operands[1])
+   && GET_MODE_SIZE (GET_MODE (operands[0])) > UNITS_PER_WORD"
+  "storem 0,0,%1,%0"
+  [(set_attr "type" "store")])
+
+(define_insn ""
+  [(match_parallel 0 "store_multiple_operation"
+		   [(set (match_operand:SI 1 "memory_operand" "=m")
+			 (match_operand:SI 2 "gpc_reg_operand" "r"))
+		    (use (match_operand:PSI 3 "register_operand" "+c"))
+		    (clobber (match_dup 3))])]
+  "TARGET_NO_STOREM_BUG"
+  "storem 0,0,%2,%1"
+  [(set_attr "type" "store")])
+
+;; SUB
+;;
+;; Either operand can be a register or an 8-bit constant, but both cannot be
+;; constants (can't usually occur anyway).
+(define_expand "subsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(minus:SI (match_operand:SI 1 "srcb_operand" "")
+		  (match_operand:SI 2 "srcb_operand" "")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[0]) == CONST_INT
+      && GET_CODE (operands[1]) == CONST_INT)
+    operands[1] = force_reg (SImode, operands[1]);
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(minus:SI (match_operand:SI 1 "srcb_operand" "r,I")
+		  (match_operand:SI 2 "srcb_operand" "rI,r")))]
+  "register_operand (operands[1], SImode)
+   || register_operand (operands[2], SImode)"
+  "@
+   sub %0,%1,%2
+   subr %0,%2,%1")
+
+(define_insn "subdi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		  (match_operand:DI 2 "gpc_reg_operand" "r")))]
+  ""
+  "sub %L0,%L1,%L2\;subc %0,%1,%2"
+  [(set_attr "type" "multi")])
+
+;; SUBR (also used above in SUB)
+(define_insn "negdi2"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
+  ""
+  "subr %L0,%L1,0\;subrc %0,%1,0"
+  [(set_attr "type" "multi")])
+
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
+  ""
+  "subr %0,%1,0")
+
+;; XNOR
+(define_insn ""
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
+			(match_operand:SI 2 "gpc_reg_operand" "r"))))]
+  ""
+  "xnor %0,%1,%2")
+
+;; XOR
+
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
+		(match_operand:SI 2 "and_operand" "rI,K")))]
+  ""
+  "@
+   xor %0,%1,%2
+   xnor %0,%1,%C2")
+
+;; Can use XOR to negate floating-point values, but we are better off not doing
+;; it that way on the 29050 so it can combine with the fmac insns.
+(define_expand "negsf2"
+  [(parallel [(set (match_operand:SF 0 "register_operand" "")
+		   (neg:SF (match_operand:SF 1 "register_operand" "")))
+	      (clobber (match_scratch:SI 2 ""))])]
+  "! TARGET_SOFT_FLOAT"
+  "
+{
+  rtx result;
+  rtx target;
+
+  if (! TARGET_29050)
+    {
+      target = operand_subword_force (operands[0], 0, SFmode);
+      result = expand_binop (SImode, xor_optab,
+			     operand_subword_force (operands[1], 0, SFmode),
+			     GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
+      if (result == 0)
+	abort ();
+
+      if (result != target)
+	emit_move_insn (result, target);
+
+      /* Make a place for REG_EQUAL.  */
+      emit_move_insn (operands[0], operands[0]);
+      DONE;
+    }
+}")
+
+(define_expand "negdf2"
+  [(parallel [(set (match_operand:DF 0 "register_operand" "")
+		   (neg:DF (match_operand:DF 1 "register_operand" "")))
+	      (clobber (match_scratch:SI 2 ""))])]
+  "! TARGET_SOFT_FLOAT"
+  "
+{
+  rtx result;
+  rtx target;
+  rtx insns;
+
+  if (! TARGET_29050)
+    {
+      start_sequence ();
+      target = operand_subword (operands[0], 0, 1, DFmode);
+      result = expand_binop (SImode, xor_optab,
+			     operand_subword_force (operands[1], 0, DFmode),
+			     GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
+      if (result == 0)
+	abort ();
+
+      if (result != target)
+	emit_move_insn (result, target);
+  
+      emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
+		      operand_subword_force (operands[1], 1, DFmode));
+
+      insns = get_insns ();
+      end_sequence ();
+
+      emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
+      DONE;
+    }
+}")
+
+;; Sign extend and truncation operations.
+(define_insn "zero_extendqihi2"
+  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
+	(zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
+  ""
+  "and %0,%1,255")
+
+(define_insn "zero_extendqisi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
+  ""
+  "and %0,%1,255")
+
+(define_insn "zero_extendhisi2"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "0")))]
+  ""
+  "consth %0,0")
+
+(define_expand "extendqihi2"
+  [(set (match_dup 2)
+	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
+		   (const_int 24)))
+   (set (match_operand:HI 0 "gpc_reg_operand" "")
+	(ashiftrt:SI (match_dup 2)
+		     (const_int 24)))]
+  ""
+  "
+{ operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_reg_rtx (SImode); }")
+
+(define_expand "extendqisi2"
+  [(set (match_dup 2)
+	(ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
+		   (const_int 24)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+	(ashiftrt:SI (match_dup 2)
+		     (const_int 24)))]
+  ""
+  "
+{ operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_reg_rtx (SImode); }")
+
+(define_expand "extendhisi2"
+  [(set (match_dup 2)
+	(ashift:SI (match_operand:HI 1 "gpc_reg_operand" "")
+		   (const_int 16)))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+	(ashiftrt:SI (match_dup 2)
+		     (const_int 16)))]
+  ""
+  "
+{ operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_reg_rtx (SImode); }")
+
+;; Define the methods used to move data around.
+;;
+;; movsi:
+;;
+;; If storing into memory, force source into register.
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(match_operand:SI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if (GET_CODE (operands[0]) == MEM && ! gpc_reg_operand (operands[1], SImode))
+    operands[1] = copy_to_mode_reg (SImode, operands[1]);
+  else if (spec_reg_operand (operands[0], SImode)
+	   && ! (register_operand (operands[1], SImode)
+		 || cint_16_operand (operands[1], SImode)))
+    operands[1] = force_reg (SImode, operands[1]);
+}")
+
+(define_expand "movpsi"
+  [(set (match_operand:PSI 0 "general_operand" "")
+	(match_operand:PSI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if (GET_CODE (operands[0]) == MEM
+      && ! gpc_reg_operand (operands[1], PSImode))
+    operands[1] = copy_to_mode_reg (PSImode, operands[1]);
+  else if (spec_reg_operand (operands[0], PSImode)
+	   && ! (register_operand (operands[1], PSImode)
+		 || cint_16_operand (operands[1], PSImode)))
+    operands[1] = force_reg (PSImode, operands[1]);
+}")
+
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(match_operand:SI 1 "long_const_operand" ""))]
+  ""
+  [(set (match_dup 0)
+	(and:SI (match_dup 1)
+		(const_int 65535)))
+   (set (match_dup 0)
+	(ior:SI (zero_extend:SI (match_dup 2))
+		(and:SI (match_dup 1)
+			(const_int -65536))))]
+  " operands[2] = gen_lowpart (HImode, operands[0]); ")
+
+;; Subroutines to load/store halfwords.  Operands 0 and 1 are the output and
+;; input, respectively, except that the address is passed for a MEM instead 
+;; of the MEM itself and the short item is passed in QImode.
+;;
+;; Operand 2 is a scratch general register and operand 3 is a scratch register
+;; used for BP.  When called before reload, pseudos are passed for both
+;; operands.  During reload, R_TAV is used for the general register, and
+;; a reload register of class BR_REGS (R_VP) for BP.
+;;
+;; We have two versions of the store operations, for when halfword writes are
+;; supported and when they are not.
+(define_expand "loadhi"
+  [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
+		   (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
+				   (const_int -4))))
+	      (set (match_operand:PSI 3 "register_operand" "")
+		   (truncate:PSI (match_dup 1)))])
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+	(zero_extract:SI (match_dup 2)
+			 (const_int 16)
+			 (ashift:PSI (match_dup 3) (const_int 3))))]
+  ""
+  "")
+
+(define_expand "storehinhww"
+ [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
+		   (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
+				   (const_int -4))))
+	      (set (match_operand:PSI 3 "register_operand" "")
+		   (truncate:PSI (match_dup 0)))])
+   (set (zero_extract:SI (match_dup 2)
+			 (const_int 16)
+			 (ashift:PSI (match_dup 3) (const_int 3)))
+	(match_operand:SI 1 "gpc_reg_operand" ""))
+   (set (mem:SI (match_dup 0))
+	(match_dup 2))]
+  ""
+  "")
+
+(define_expand "storehihww"
+  [(set (match_operand:PSI 3 "register_operand" "")
+	(truncate:PSI (match_operand:SI 0 "gpc_reg_operand" "")))
+   (set (match_operand:SI 2 "gpc_reg_operand" "")
+	(ior:SI (and:SI (not:SI (ashift:SI (const_int 65535)
+					   (ashift:PSI (match_dup 3)
+						       (const_int 3))))
+			(match_operand:SI 1 "gpc_reg_operand" ""))
+		(ashift:SI (zero_extend:SI (match_dup 4))
+			   (ashift:PSI (match_dup 3) (const_int 3)))))
+   (set (mem:SI (and:SI (match_dup 0)
+			(const_int -3)))
+	(match_dup 2))]
+  ""
+  "
+{ operands[4] = gen_lowpart (HImode, operands[1]); }")
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "general_operand" "")
+	(match_operand:HI 1 "general_operand" ""))]
+  ""
+  "
+{ if (GET_CODE (operands[0]) == MEM) 
+    {
+      if (! gpc_reg_operand (operands[1], HImode))
+	operands[1] = copy_to_mode_reg (HImode, operands[1]);
+      if (! TARGET_DW_ENABLE)
+	{
+	  rtx general = gen_reg_rtx (SImode);
+	  rtx bp = gen_reg_rtx (PSImode);
+	  rtx (*fcn) ()
+	    = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww;
+	  rtx seq = (*fcn) (XEXP (operands[0], 0),
+			    gen_lowpart (SImode, operands[1]),
+			    general, bp);
+	    
+	  a29k_set_memflags (seq, operands[0]);
+	  emit_insn (seq);
+	  DONE;
+	}
+    }
+  else if (GET_CODE (operands[1]) == MEM)
+    {
+      if (! TARGET_DW_ENABLE)
+	{
+	  rtx general = gen_reg_rtx (SImode);
+	  rtx bp = gen_reg_rtx (PSImode);
+	  rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]),
+				XEXP (operands[1], 0), general, bp);
+
+	  a29k_set_memflags (seq, operands[1]);
+	  emit_insn (seq);
+	  DONE;
+	}
+    }
+}")
+
+(define_expand "reload_inhi"
+  [(parallel [(match_operand:SI 0 "register_operand" "=r")
+	      (match_operand:SI 1 "reload_memory_operand" "m")
+	      (match_operand:PSI 2 "register_operand" "=b")])]
+  "! TARGET_DW_ENABLE"
+  "
+{ rtx seq = gen_loadhi (gen_lowpart (SImode, operands[0]),
+			a29k_get_reloaded_address (operands[1]),
+			gen_rtx (REG, SImode, R_TAV),
+			operands[2]);
+
+  a29k_set_memflags (seq, operands[1]);
+  emit_insn (seq);
+  DONE;
+}")
+
+(define_expand "reload_outhi"
+  [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m")
+	      (match_operand:SI 1 "register_operand" "m")
+	      (match_operand:PSI 2 "register_operand" "=b")])]
+  "! TARGET_DW_ENABLE"
+  "
+{ rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storehihww : gen_storehinhww;
+  rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]),
+		    gen_lowpart (SImode, operands[1]),
+		    gen_rtx (REG, SImode, R_TAV), operands[2]);
+
+  a29k_set_memflags (seq, operands[0]);
+  emit_insn (seq);
+  DONE;
+}")
+
+;; Subroutines to load/store bytes.  Operands 0 and 1 are the output and
+;; input, respectively, except that the address is passed for a MEM instead 
+;; of the MEM itself and the short item is passed in QImode.
+;;
+;; Operand 2 is a scratch general register and operand 3 is a scratch register
+;; used for BP.  When called before reload, pseudos are passed for both
+;; operands.  During reload, R_TAV is used for the general register, and
+;; a reload register of class BR_REGS (R_VP) for BP.
+;;
+;; We have two versions of the store operations, for when byte writes are
+;; supported and when they are not.
+(define_expand "loadqi"
+  [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
+		   (mem:SI (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
+				   (const_int -4))))
+	      (set (match_operand:PSI 3 "register_operand" "")
+		   (truncate:PSI (match_dup 1)))])
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+	(zero_extract:SI (match_dup 2)
+			 (const_int 8)
+			 (ashift:PSI (match_dup 3) (const_int 3))))]
+  ""
+  "")
+
+(define_expand "storeqinhww"
+  [(parallel [(set (match_operand:SI 2 "gpc_reg_operand" "")
+		   (mem:SI (and:SI (match_operand:SI 0 "gpc_reg_operand" "")
+				   (const_int -4))))
+	      (set (match_operand:PSI 3 "register_operand" "")
+		   (truncate:PSI (match_dup 0)))])
+   (set (zero_extract:SI (match_dup 2)
+			 (const_int 8)
+			 (ashift:PSI (match_dup 3)
+				     (const_int 3)))
+	(match_operand:SI 1 "gpc_reg_operand" ""))
+   (set (mem:SI (match_dup 0))
+	(match_dup 2))]
+  ""
+  "")
+
+(define_expand "storeqihww"
+  [(set (match_operand:PSI 3 "register_operand" "")
+	(truncate:PSI (match_operand:SI 0 "gpc_reg_operand" "")))
+   (set (match_operand:SI 2 "gpc_reg_operand" "")
+	(ior:SI (and:SI (not:SI (ashift:SI (const_int 255)
+					   (ashift:PSI (match_dup 3)
+						       (const_int 3))))
+			(match_operand:SI 1 "gpc_reg_operand" ""))
+		(ashift:SI (zero_extend:SI (match_dup 4))
+			   (ashift:PSI (match_dup 3)
+				       (const_int 3)))))
+   (set (mem:SI (and:SI (match_dup 0)
+		        (const_int -4)))
+	(match_dup 2))]
+  ""
+  "
+{ operands[4] = gen_lowpart (QImode, operands[1]); }")
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "general_operand" "")
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+  "
+{ if (GET_CODE (operands[0]) == MEM)
+    {
+      if (! gpc_reg_operand (operands[1], QImode))
+	operands[1] = copy_to_mode_reg (QImode, operands[1]);
+      if (! TARGET_DW_ENABLE)
+	{
+	  rtx general = gen_reg_rtx (SImode);
+	  rtx bp = gen_reg_rtx (PSImode);
+	  rtx (*fcn) ()
+	    = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww;
+	  rtx seq = (*fcn) (XEXP (operands[0], 0),
+			    gen_lowpart (SImode, operands[1]),
+			    general, bp);
+	    
+	  a29k_set_memflags (seq, operands[0]);
+	  emit_insn (seq);
+	  DONE;
+	}
+    }
+  else if (GET_CODE (operands[1]) == MEM)
+    {
+      if (! TARGET_DW_ENABLE)
+	{
+	  rtx general = gen_reg_rtx (SImode);
+	  rtx bp = gen_reg_rtx (PSImode);
+	  rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]),
+				XEXP (operands[1], 0), general, bp);
+
+	  a29k_set_memflags (seq, operands[1]);
+	  emit_insn (seq);
+	  DONE;
+	}
+    }
+}")
+
+(define_expand "reload_inqi"
+  [(parallel [(match_operand:SI 0 "register_operand" "=r")
+	      (match_operand:SI 1 "reload_memory_operand" "m")
+	      (match_operand:PSI 2 "register_operand" "=b")])]
+  "! TARGET_DW_ENABLE"
+  "
+{ rtx seq = gen_loadqi (gen_lowpart (SImode, operands[0]),
+			a29k_get_reloaded_address (operands[1]),
+			gen_rtx (REG, SImode, R_TAV),
+			operands[2]);
+
+  a29k_set_memflags (seq, operands[1]);
+  emit_insn (seq);
+  DONE;
+}")
+
+(define_expand "reload_outqi"
+  [(parallel [(match_operand:SI 0 "reload_memory_operand" "=m")
+	      (match_operand:SI 1 "register_operand" "m")
+	      (match_operand:PSI 2 "register_operand" "=b")])]
+  "! TARGET_DW_ENABLE"
+  "
+{ rtx (*fcn) () = TARGET_BYTE_WRITES ? gen_storeqihww : gen_storeqinhww;
+  rtx seq = (*fcn) (a29k_get_reloaded_address (operands[0]),
+		    gen_lowpart (SImode, operands[1]),
+		    gen_rtx (REG, SImode, R_TAV), operands[2]);
+
+  a29k_set_memflags (seq, operands[0]);
+  emit_insn (seq);
+  DONE;
+}")
+
+;; Now the actual insns used to move data around.  We include here the
+;; DEFINE_SPLITs that may be needed.  In some cases these will be
+;; split again.  For floating-point, if we can look inside the constant,
+;; always split it.  This can eliminate unnecessary insns.
+(define_insn ""
+  [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m")
+	(match_operand:SF 1 "in_operand" "r,E,F,m,r"))]
+  "(gpc_reg_operand (operands[0], SFmode)
+    || gpc_reg_operand (operands[1], SFmode))
+   && ! TARGET_29050"
+  "@
+   sll %0,%1,0
+   #
+   const %0,%1\;consth %0,%1
+   load 0,0,%0,%1
+   store 0,0,%1,%0"
+  [(set_attr "type" "misc,multi,multi,load,store")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "out_operand" "=r,r,r,r,m,*a,r")
+	(match_operand:SF 1 "in_operand" "r,E,F,m,r,r,*a"))]
+  "(gpc_reg_operand (operands[0], SFmode)
+    || gpc_reg_operand (operands[1], SFmode))
+   && TARGET_29050"
+  "@
+   sll %0,%1,0
+   #
+   const %0,%1\;consth %0,%1
+   load 0,0,%0,%1
+   store 0,0,%1,%0
+   mtacc %1,1,%0
+   mfacc %0,1,%1"
+  [(set_attr "type" "misc,multi,multi,load,store,fadd,fadd")])
+
+;; Turn this into SImode.  It will then be split up that way.
+(define_split
+  [(set (match_operand:SF 0 "register_operand" "")
+	(match_operand:SF 1 "float_const_operand" ""))]
+  "HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT"
+  [(set (match_dup 0)
+	(match_dup 1))]
+  "
+{ operands[0] = operand_subword (operands[0], 0, 0, SFmode);
+  operands[1] = operand_subword (operands[1], 0, 0, SFmode);
+
+  if (operands[0] == 0 || operands[1] == 0)
+    FAIL;
+}")
+
+(define_insn ""
+  [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m")
+	(match_operand:DF 1 "in_operand" "rE,F,m,r"))
+   (clobber (match_scratch:PSI 2 "=X,X,&c,&c"))]
+  "(gpc_reg_operand (operands[0], DFmode)
+    || gpc_reg_operand (operands[1], DFmode))
+   && ! TARGET_29050"
+  "@
+   #
+   const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1
+   mtsrim cr,1\;loadm 0,0,%0,%1
+   mtsrim cr,1\;storem 0,0,%1,%0"
+  [(set_attr "type" "multi")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "out_operand" "=?r,?r,r,m,?*a,?r")
+	(match_operand:DF 1 "in_operand" "rE,F,m,r,r,*a"))
+   (clobber (match_scratch:PSI 2 "=X,X,&c,&c,X,X"))]
+  "(gpc_reg_operand (operands[0], DFmode)
+    || gpc_reg_operand (operands[1], DFmode))
+   && TARGET_29050"
+  "@
+   #
+   const %0,%1\;consth %0,%1\;const %L0,%L1\;consth %L0,%L1
+   mtsrim cr,1\;loadm 0,0,%0,%1
+   mtsrim cr,1\;storem 0,0,%1,%0
+   mtacc %1,2,%0
+   mfacc %0,2,%1"
+  [(set_attr "type" "multi,multi,multi,multi,fadd,fadd")])
+
+;; Split register-register copies and constant loads into two SImode loads,
+;; one for each word.  In the constant case, they will get further split.
+;; Don't so this until register allocation, though, since it will
+;; interfere with register allocation.  Normally copy the lowest-addressed
+;; word first; the exception is if we are copying register to register and
+;; the lowest register of the first operand is the highest register of the
+;; second operand.
+(define_split
+  [(set (match_operand:DF 0 "gpc_reg_operand" "")
+	(match_operand:DF 1 "gpc_reg_or_float_constant_operand" ""))
+   (clobber (match_scratch:PSI 2 ""))]
+  "reload_completed"
+  [(set (match_dup 3) (match_dup 4))
+   (set (match_dup 5) (match_dup 6))]
+  "
+{ if (GET_CODE (operands[1]) == REG
+      && REGNO (operands[0]) == REGNO (operands[1]) + 1)
+    {
+      operands[3] = operand_subword (operands[0], 1, 1, DFmode);
+      operands[4] = operand_subword (operands[1], 1, 1, DFmode);
+      operands[5] = operand_subword (operands[0], 0, 1, DFmode);
+      operands[6] = operand_subword (operands[1], 0, 1, DFmode);
+    }
+  else
+    {
+      operands[3] = operand_subword (operands[0], 0, 1, DFmode);
+      operands[4] = operand_subword (operands[1], 0, 1, DFmode);
+      operands[5] = operand_subword (operands[0], 1, 1, DFmode);
+      operands[6] = operand_subword (operands[1], 1, 1, DFmode);
+    }
+
+  if (operands[3] == 0 || operands[4] == 0
+      || operands[5] == 0 || operands[6] == 0)
+    FAIL;
+}")
+
+;; Split memory loads and stores into the MTSR and LOADM/STOREM.
+(define_split
+  [(set (match_operand:DF 0 "out_operand" "")
+	(match_operand:DF 1 "in_operand" ""))
+   (clobber (reg:PSI 179))]
+  "TARGET_NO_STOREM_BUG
+   && (memory_operand (operands[0], DFmode)
+       || memory_operand (operands[1], DFmode))"
+  [(set (reg:PSI 179) (const_int 1))
+   (parallel [(set (match_dup 0) (match_dup 1))
+	      (use (reg:PSI 179))
+	      (clobber (reg:PSI 179))])]
+  "")
+
+;; DI move is similar to DF move.
+(define_insn ""
+  [(set (match_operand:DI 0 "out_operand" "=?r,r,m")
+	(match_operand:DI 1 "in_operand" "rn,m,r"))
+   (clobber (match_scratch:PSI 2 "=X,&c,&c"))]
+  "(gpc_reg_operand (operands[0], DImode)
+     || gpc_reg_operand (operands[1], DImode))"
+  "@
+   #
+   mtsrim cr,1\;loadm 0,0,%0,%1
+   mtsrim cr,1\;storem 0,0,%1,%0"
+  [(set_attr "type" "multi")])
+
+(define_split
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(match_operand:DI 1 "gpc_reg_or_integer_constant_operand" ""))
+   (clobber (match_scratch:PSI 2 ""))]
+  "reload_completed"
+  [(set (match_dup 3) (match_dup 4))
+   (set (match_dup 5) (match_dup 6))]
+  "
+{ if (GET_CODE (operands[1]) == REG
+      && REGNO (operands[0]) == REGNO (operands[1]) + 1)
+    {
+      operands[3] = operand_subword (operands[0], 1, 1, DImode);
+      operands[4] = operand_subword (operands[1], 1, 1, DImode);
+      operands[5] = operand_subword (operands[0], 0, 1, DImode);
+      operands[6] = operand_subword (operands[1], 0, 1, DImode);
+    }
+  else
+    {
+      operands[3] = operand_subword (operands[0], 0, 1, DImode);
+      operands[4] = operand_subword (operands[1], 0, 1, DImode);
+      operands[5] = operand_subword (operands[0], 1, 1, DImode);
+      operands[6] = operand_subword (operands[1], 1, 1, DImode);
+    }
+}")
+
+(define_split
+  [(set (match_operand:DI 0 "out_operand" "")
+	(match_operand:DI 1 "in_operand" ""))
+   (clobber (reg:PSI 179))]
+  "TARGET_NO_STOREM_BUG
+   && (memory_operand (operands[0], DImode)
+       || memory_operand (operands[1], DImode))"
+  [(set (reg:PSI 179) (const_int 1))
+   (parallel [(set (match_dup 0) (match_dup 1))
+	      (use (reg:PSI 179))
+	      (clobber (reg:PSI 179))])]
+  "")
+
+;; TImode moves are very similar to DImode moves, except that we can't
+;; have constants.
+(define_insn ""
+  [(set (match_operand:TI 0 "out_operand" "=?r,r,m")
+	(match_operand:TI 1 "in_operand" "r,m,r"))
+   (clobber (match_scratch:PSI 2 "=X,&c,&c"))]
+  "(gpc_reg_operand (operands[0], TImode)
+    || gpc_reg_operand (operands[1], TImode))"
+  "@
+   #
+   mtsrim cr,3\;loadm 0,0,%0,%1
+   mtsrim cr,3\;storem 0,0,%1,%0"
+  [(set_attr "type" "multi,multi,multi")])
+
+(define_split
+  [(set (match_operand:TI 0 "gpc_reg_operand" "")
+	(match_operand:TI 1 "gpc_reg_operand" ""))
+   (clobber (match_scratch:PSI 2 ""))]
+  "reload_completed"
+  [(set (match_dup 3) (match_dup 4))
+   (set (match_dup 5) (match_dup 6))
+   (set (match_dup 7) (match_dup 8))
+   (set (match_dup 9) (match_dup 10))]
+  "
+{
+  if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
+      && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
+    {
+      operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3);
+      operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3);
+      operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
+      operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
+      operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+      operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+      operands[9] = gen_rtx (REG, SImode, REGNO (operands[0]));
+      operands[10] = gen_rtx (REG, SImode, REGNO (operands[1]));
+    }
+  else
+    {
+      operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]));
+      operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]));
+      operands[5] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
+      operands[6] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
+      operands[7] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2);
+      operands[8] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
+      operands[9] = gen_rtx (REG, SImode, REGNO (operands[0]) + 3);
+      operands[10] = gen_rtx (REG, SImode, REGNO (operands[1]) + 3); 
+    }
+}")
+
+(define_split
+  [(set (match_operand:TI 0 "out_operand" "")
+	(match_operand:TI 1 "in_operand" ""))
+   (clobber (reg:PSI 179))]
+  "TARGET_NO_STOREM_BUG
+   && (memory_operand (operands[0], TImode)
+       || memory_operand (operands[1], TImode))"
+  [(set (reg:PSI 179) (const_int 3))
+   (parallel [(set (match_dup 0) (match_dup 1))
+	      (use (reg:PSI 179))
+	      (clobber (reg:PSI 179))])]
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h")
+        (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))]
+  "(gpc_reg_operand (operands[0], SImode)
+    || gpc_reg_operand (operands[1], SImode)
+    || (spec_reg_operand (operands[0], SImode)
+        && cint_16_operand (operands[1], SImode)))
+   && ! TARGET_29050"
+  "@
+   sll %0,%1,0
+   const %0,%1
+   constn %0,%M1
+   cpeq %0,gr1,gr1
+   #
+   load 0,0,%0,%1
+   mfsr %0,%1
+   store 0,0,%1,%0
+   mtsr %0,%1
+   mtsrim %0,%1"
+  [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "out_operand" "=r,r,r,r,r,r,r,m,*h,*h")
+        (match_operand:SI 1 "in_operand" "r,J,M,O,i,m,*h,r,r,J"))]
+  "(gpc_reg_operand (operands[0], SImode)
+    || gpc_reg_operand (operands[1], SImode)
+    || (spec_reg_operand (operands[0], SImode)
+        && cint_16_operand (operands[1], SImode)))
+   && TARGET_29050"
+  "@
+   sll %0,%1,0
+   const %0,%1
+   constn %0,%M1
+   consthz %0,%1
+   #
+   load 0,0,%0,%1
+   mfsr %0,%1
+   store 0,0,%1,%0
+   mtsr %0,%1
+   mtsrim %0,%1"
+  [(set_attr "type" "misc,misc,misc,misc,multi,load,misc,store,misc,misc")])
+
+(define_insn ""
+  [(set (match_operand:PSI 0 "out_operand" "=*r,*r,*r,*r,m,h,h")
+        (match_operand:PSI 1 "in_operand" "r,i,m,h,r,r,J"))]
+  "(gpc_reg_operand (operands[0], PSImode)
+    || gpc_reg_operand (operands[1], PSImode)
+    || (spec_reg_operand (operands[0], PSImode)
+        && cint_16_operand (operands[1], PSImode)))"
+  "@
+   sll %0,%1,0
+   const %0,%1
+   load 0,0,%0,%1
+   mfsr %0,%1
+   store 0,0,%1,%0
+   mtsr %0,%1
+   mtsrim %0,%1"
+  [(set_attr "type" "misc,multi,load,misc,store,misc,misc")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "out_operand" "=r,r,r,m,r,*h,*h")
+        (match_operand:HI 1 "in_operand" "r,i,m,r,*h,r,i"))]
+  "gpc_reg_operand (operands[0], HImode)
+   || gpc_reg_operand (operands[1], HImode)
+   || (spec_reg_operand (operands[0], HImode)
+       && cint_16_operand (operands[1], HImode))"
+  "@
+   sll %0,%1,0
+   const %0,%1
+   load 0,2,%0,%1
+   store 0,2,%1,%0
+   mfsr %0,%1
+   mtsr %0,%1
+   mtsrim %0,%1"
+  [(set_attr "type" "misc,misc,load,store,misc,misc,misc")])
+
+(define_insn ""
+  [(set (match_operand:QI 0 "out_operand" "=r,r,r,m,r,*h,*h")
+        (match_operand:QI 1 "in_operand" "r,i,m,r,*h,r,i"))]
+  "gpc_reg_operand (operands[0], QImode)
+   || gpc_reg_operand (operands[1], QImode)
+   || (spec_reg_operand (operands[0], HImode)
+       && cint_16_operand (operands[1], HImode))"
+  "@
+   sll %0,%1,0
+   const %0,%1
+   load 0,1,%0,%1
+   store 0,1,%1,%0
+   mfsr %0,%1
+   mtsr %0,%1
+   mtsrim %0,%1"
+  [(set_attr "type" "misc,misc,load,store,misc,misc,misc")])
+
+;; Define move insns for DI, TI, SF, and DF.
+;;
+;; In no case do we support mem->mem directly.
+;;
+;; For DI move of constant to register, split apart at this time since these
+;; can require anywhere from 2 to 4 insns and determining which is complex.
+;;
+;; In other cases, handle similarly to SImode moves.
+;;
+;; However, indicate that DI, TI, and DF moves may clobber CR (reg 179).
+(define_expand "movdi"
+  [(parallel [(set (match_operand:DI 0 "general_operand" "")
+		   (match_operand:DI 1 "general_operand" ""))
+	      (clobber (scratch:PSI))])]
+  ""
+  "
+{
+  if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (DImode, operands[1]);
+}")
+
+(define_expand "movsf"
+  [(set (match_operand:SF 0 "general_operand" "")
+	(match_operand:SF 1 "general_operand" ""))]
+  ""
+  "
+{ if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (SFmode, operands[1]);
+}")
+
+(define_expand "movdf"
+  [(parallel [(set (match_operand:DF 0 "general_operand" "")
+		   (match_operand:DF 1 "general_operand" ""))
+	      (clobber (scratch:PSI))])]
+  ""
+  "
+{ if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (DFmode, operands[1]);
+}")
+
+(define_expand "movti"
+  [(parallel [(set (match_operand:TI 0 "general_operand" "")
+		   (match_operand:TI 1 "general_operand" ""))
+	      (clobber (scratch:PSI))])]
+  ""
+  "
+{
+  if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (TImode, operands[1]);
+
+  /* We can't handle constants in general because there is no rtl to represent
+     128 bit constants.  Splitting happens to work for CONST_INTs so we split
+     them for good code.  Other constants will get forced to memory.  */
+
+  if (GET_CODE (operands[1]) == CONST_INT)
+    {
+     rtx part0, part1, part2, part3;
+
+     part0 = operand_subword (operands[0], 0, 1, TImode);
+     part1 = operand_subword (operands[0], 1, 1, TImode);
+     part2 = operand_subword (operands[0], 2, 1, TImode);
+     part3 = operand_subword (operands[0], 3, 1, TImode);
+
+     emit_move_insn (part0, const0_rtx);
+     emit_move_insn (part1, const0_rtx);
+     emit_move_insn (part2, const0_rtx);
+     emit_move_insn (part3, const0_rtx);
+
+     DONE;
+    }
+  else if (CONSTANT_P (operands[1]))
+    {
+      operands[1] = force_const_mem (TImode, operands[1]);
+      if (! memory_address_p (TImode, XEXP (operands[1], 0))
+	  && ! reload_in_progress)
+        operands[1] = change_address (operands[1], TImode,
+				      XEXP (operands[1], 0));
+    }
+}")
+
+;; Here are the variants of the above for use during reload.
+
+(define_expand "reload_indf"
+  [(parallel [(set (match_operand:DF 0 "register_operand" "=r")
+		   (match_operand:DF 1 "reload_memory_operand" "m"))
+	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
+  ""
+  "")
+
+(define_expand "reload_outdf"
+  [(parallel [(set (match_operand:DF 0 "reload_memory_operand" "=m")
+		   (match_operand:DF 1 "register_operand" "r"))
+	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
+  ""
+  "")
+
+(define_expand "reload_indi"
+  [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
+		   (match_operand:DI 1 "reload_memory_operand" "m"))
+	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
+  ""
+  "")
+
+(define_expand "reload_outdi"
+  [(parallel [(set (match_operand:DI 0 "reload_memory_operand" "=m")
+		   (match_operand:DI 1 "register_operand" "r"))
+	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
+  ""
+  "")
+
+(define_expand "reload_inti"
+  [(parallel [(set (match_operand:TI 0 "register_operand" "=r")
+		   (match_operand:TI 1 "reload_memory_operand" "m"))
+	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
+  ""
+  "")
+
+(define_expand "reload_outti"
+  [(parallel [(set (match_operand:TI 0 "reload_memory_operand" "=m")
+		   (match_operand:TI 1 "register_operand" "r"))
+	      (clobber (match_operand:PSI 2 "register_operand" "=&c"))])]
+  ""
+  "")
+
+;; For compare operations, we simply store the comparison operands and
+;; do nothing else.  The following branch or scc insn will output whatever
+;; is needed.
+(define_expand "cmpsi"
+  [(set (cc0)
+	(compare (match_operand:SI 0 "gpc_reg_operand" "")
+		 (match_operand:SI 1 "srcb_operand" "")))]
+  ""
+  "
+{
+  a29k_compare_op0 = operands[0];
+  a29k_compare_op1 = operands[1];
+  a29k_compare_fp_p = 0;
+  DONE;
+}")
+
+(define_expand "cmpsf"
+  [(set (cc0)
+	(compare (match_operand:SF 0 "gpc_reg_operand" "")
+		 (match_operand:SF 1 "gpc_reg_operand" "")))]
+  "! TARGET_SOFT_FLOAT"
+  "
+{
+  a29k_compare_op0 = operands[0];
+  a29k_compare_op1 = operands[1];
+  a29k_compare_fp_p = 1;
+  DONE;
+}")
+
+(define_expand "cmpdf"
+  [(set (cc0)
+	(compare (match_operand:DF 0 "gpc_reg_operand" "")
+		 (match_operand:DF 1 "gpc_reg_operand" "")))]
+  "! TARGET_SOFT_FLOAT"
+  "
+{
+  a29k_compare_op0 = operands[0];
+  a29k_compare_op1 = operands[1];
+  a29k_compare_fp_p = 1;
+  DONE;
+}")
+
+;; We can generate bit-tests better if we use NE instead of EQ, but we
+;; don't have an NE for floating-point.  So we have to have two patterns
+;; for EQ and two for NE.
+
+(define_expand "beq"
+  [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3)))
+   (set (pc)
+	(if_then_else (ge (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT)
+    {
+      emit_insn (gen_beq_fp (operands[0]));
+      DONE;
+    }
+
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = a29k_compare_op0;
+  operands[3] = a29k_compare_op1;
+}")
+
+(define_expand "beq_fp"
+  [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3)))
+   (set (pc)
+	(if_then_else (lt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = a29k_compare_op0;
+  operands[3] = a29k_compare_op1;
+}")
+
+(define_expand "bne"
+  [(set (match_dup 1) (ne:SI (match_dup 2) (match_dup 3)))
+   (set (pc)
+	(if_then_else (lt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (GET_MODE_CLASS (GET_MODE (a29k_compare_op0)) == MODE_FLOAT)
+    {
+      emit_insn (gen_bne_fp (operands[0]));
+      DONE;
+    }
+
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = a29k_compare_op0;
+  operands[3] = a29k_compare_op1;
+}")
+
+(define_expand "bne_fp"
+  [(set (match_dup 1) (eq:SI (match_dup 2) (match_dup 3)))
+   (set (pc)
+	(if_then_else (ge (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = a29k_compare_op0;
+  operands[3] = a29k_compare_op1;
+}")
+
+;; We don't have a floating-point "lt" insn, so we have to use "gt" in that
+;; case with the operands swapped.  The operands must both be registers in
+;; the floating-point case, so we know that swapping them is OK.
+(define_expand "blt"
+  [(set (match_dup 1) (match_dup 2))
+   (set (pc)
+	(if_then_else (lt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (SImode);
+  if (a29k_compare_fp_p)
+    operands[2] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0);
+  else
+    operands[2] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1);
+}")
+
+;; Similarly for "le".
+(define_expand "ble"
+  [(set (match_dup 1) (match_dup 2))
+   (set (pc)
+	(if_then_else (lt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (SImode);
+  if (a29k_compare_fp_p)
+    operands[2] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0);
+  else
+    operands[2] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1);
+}")
+
+(define_expand "bltu"
+  [(set (match_dup 1) (ltu:SI (match_dup 2) (match_dup 3)))
+   (set (pc)
+	(if_then_else (lt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = a29k_compare_op0;
+  operands[3] = a29k_compare_op1;
+}")
+
+(define_expand "bleu"
+  [(set (match_dup 1) (leu:SI (match_dup 2) (match_dup 3)))
+   (set (pc)
+	(if_then_else (lt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = a29k_compare_op0;
+  operands[3] = a29k_compare_op1;
+}")
+
+(define_expand "bgt"
+  [(set (match_dup 1) (gt:SI (match_dup 2) (match_dup 3)))
+   (set (pc)
+	(if_then_else (lt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = a29k_compare_op0;
+  operands[3] = a29k_compare_op1;
+}")
+
+(define_expand "bge"
+  [(set (match_dup 1) (ge:SI (match_dup 2) (match_dup 3)))
+   (set (pc)
+	(if_then_else (lt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = a29k_compare_op0;
+  operands[3] = a29k_compare_op1;
+}")
+
+(define_expand "bgtu"
+  [(set (match_dup 1) (gtu:SI (match_dup 2) (match_dup 3)))
+   (set (pc)
+	(if_then_else (lt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = a29k_compare_op0;
+  operands[3] = a29k_compare_op1;
+}")
+
+(define_expand "bgeu"
+  [(set (match_dup 1) (geu:SI (match_dup 2) (match_dup 3)))
+   (set (pc)
+	(if_then_else (lt (match_dup 1) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (SImode);
+  operands[2] = a29k_compare_op0;
+  operands[3] = a29k_compare_op1;
+}")
+
+(define_expand "seq"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(eq:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "
+{
+  operands[1] = a29k_compare_op0;
+  operands[2] = a29k_compare_op1;
+}")
+		 
+;; This is the most complicated case, because we don't have a floating-point
+;; "ne" insn.  If integer, handle normally.  If floating-point, write the
+;; compare and then write an insn to reverse the test.
+(define_expand "sne_fp"
+  [(set (match_dup 3)
+	(eq:SI (match_operand 1 "gpc_reg_operand" "")
+	       (match_operand 2 "gpc_reg_operand" "")))
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
+	(ge:SI (match_dup 3) (const_int 0)))]
+  "! TARGET_SOFT_FLOAT"
+  "
+{ operands[3] = gen_reg_rtx (SImode);
+}");
+
+(define_expand "sne"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(ne:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "
+{
+  operands[1] = a29k_compare_op0;
+  operands[2] = a29k_compare_op1;
+
+  if (a29k_compare_fp_p)
+    {
+      emit_insn (gen_sne_fp (operands[0], operands[1], operands[2]));
+      DONE;
+    }
+}")
+		 
+;; We don't have a floating-point "lt" insn, so use "gt" and swap the
+;; operands, the same as we do "blt".
+(define_expand "slt"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "
+{
+  if (a29k_compare_fp_p)
+    operands[1] = gen_rtx (GT, SImode, a29k_compare_op1, a29k_compare_op0);
+  else
+    operands[1] = gen_rtx (LT, SImode, a29k_compare_op0, a29k_compare_op1);
+}")
+
+;; Similarly for "le"
+(define_expand "sle"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(match_dup 1))]
+  ""
+  "
+{
+  if (a29k_compare_fp_p)
+    operands[1] = gen_rtx (GE, SImode, a29k_compare_op1, a29k_compare_op0);
+  else
+    operands[1] = gen_rtx (LE, SImode, a29k_compare_op0, a29k_compare_op1);
+}")
+
+(define_expand "sltu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(ltu:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "
+{
+  operands[1] = a29k_compare_op0;
+  operands[2] = a29k_compare_op1;
+}")
+
+(define_expand "sleu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(leu:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "
+{
+  operands[1] = a29k_compare_op0;
+  operands[2] = a29k_compare_op1;
+}")
+
+(define_expand "sgt"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(gt:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "
+{
+  operands[1] = a29k_compare_op0;
+  operands[2] = a29k_compare_op1;
+}")
+
+(define_expand "sge"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(ge:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "
+{
+  operands[1] = a29k_compare_op0;
+  operands[2] = a29k_compare_op1;
+}")
+		 
+(define_expand "sgtu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(gtu:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "
+{
+  operands[1] = a29k_compare_op0;
+  operands[2] = a29k_compare_op1;
+}")
+
+(define_expand "sgeu"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(geu:SI (match_dup 1) (match_dup 2)))]
+  ""
+  "
+{
+  operands[1] = a29k_compare_op0;
+  operands[2] = a29k_compare_op1;
+}")
+
+;; Now define the actual jump insns.
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator 0 "branch_operator"
+				      [(match_operand:SI 1 "gpc_reg_operand" "r")
+				       (const_int 0)])
+		      (label_ref (match_operand 2 "" ""))
+		      (pc)))]
+  ""
+  "jmp%b0 %1,%l2%#"
+  [(set_attr "type" "branch")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator 0 "branch_operator"
+				      [(match_operand:SI 1 "gpc_reg_operand" "r")
+				       (const_int 0)])
+		      (return)
+		      (pc)))]
+  "null_epilogue ()"
+  "jmp%b0i %1,lr0%#"
+  [(set_attr "type" "branch")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator 0 "branch_operator"
+				      [(match_operand:SI 1 "gpc_reg_operand" "r")
+				       (const_int 0)])
+		      (pc)
+		      (label_ref (match_operand 2 "" ""))))]
+  ""
+  "jmp%B0 %1,%l2%#"
+  [(set_attr "type" "branch")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator 0 "branch_operator"
+				      [(match_operand:SI 1 "gpc_reg_operand" "r")
+				       (const_int 0)])
+		      (pc)
+		      (return)))]
+  "null_epilogue ()"
+  "jmp%B0i %1,lr0%#"
+  [(set_attr "type" "branch")])
+
+(define_insn "jump"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  ""
+  "jmp %e0%E0"
+  [(set_attr "type" "branch")])
+
+(define_insn "return"
+  [(return)]
+  "null_epilogue ()"
+  "jmpi lr0%#"
+  [(set_attr "type" "branch")])
+
+(define_insn "indirect_jump"
+  [(set (pc)
+	(match_operand:SI 0 "gpc_reg_operand" "r"))]
+  ""
+  "jmpi %0%#"
+  [(set_attr "type" "branch")])
+
+(define_insn "tablejump"
+  [(set (pc)
+	(match_operand:SI 0 "gpc_reg_operand" "r"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "jmpi %0%#"
+  [(set_attr "type" "branch")])
+
+;; JMPFDEC
+(define_insn ""
+  [(set (pc)
+	(if_then_else (ge (match_operand:SI 0 "gpc_reg_operand" "r")
+			  (const_int 0))
+		      (label_ref (match_operand 1 "" ""))
+		      (pc)))
+   (set (match_dup 0)
+	(plus:SI (match_dup 0)
+		 (const_int -1)))]
+  ""
+  "jmpfdec %0,%l1%#"
+  [(set_attr "type" "branch")])
diff --git a/gcc/config/a29k/t-a29k b/gcc/config/a29k/t-a29k
new file mode 100755
index 0000000..7468422
--- /dev/null
+++ b/gcc/config/a29k/t-a29k
@@ -0,0 +1,5 @@
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+# We need crt0.o.
+LIBGCC1_TEST =
diff --git a/gcc/config/a29k/t-a29kbare b/gcc/config/a29k/t-a29kbare
new file mode 100755
index 0000000..21ba24f
--- /dev/null
+++ b/gcc/config/a29k/t-a29kbare
@@ -0,0 +1,19 @@
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+# We need crt0.o.
+LIBGCC1_TEST =
+
+# These are really part of libgcc1, but this will cause them to be
+# built correctly, so... 
+
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	cat $(srcdir)/config/fp-bit.c > dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+
diff --git a/gcc/config/a29k/t-vx29k b/gcc/config/a29k/t-vx29k
new file mode 100755
index 0000000..293674e
--- /dev/null
+++ b/gcc/config/a29k/t-vx29k
@@ -0,0 +1,17 @@
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+# We need crt0.o.
+LIBGCC1_TEST =
+
+# We don't want to put exit in libgcc.a for VxWorks, because VxWorks
+# does not have _exit.
+TARGET_LIBGCC2_CFLAGS = -Dexit=unused_exit
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	cat $(srcdir)/config/fp-bit.c > dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
diff --git a/gcc/config/a29k/udi.h b/gcc/config/a29k/udi.h
new file mode 100755
index 0000000..400ffbb
--- /dev/null
+++ b/gcc/config/a29k/udi.h
@@ -0,0 +1,94 @@
+/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU
+   running over UDI using COFF.
+   Copyright (C) 1994, 1996 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Support the ctors and dtors sections for g++.  */
+
+#define CTORS_SECTION_ASM_OP	"\t.use .ctors"
+#define DTORS_SECTION_ASM_OP	"\t.use .dtors"
+
+/* A list of other sections which the compiler might be "in" at any
+   given time.  */
+
+#undef EXTRA_SECTIONS
+#define EXTRA_SECTIONS readonly_data, in_ctors, in_dtors
+
+/* A list of extra section function definitions.  */
+
+#undef EXTRA_SECTION_FUNCTIONS
+#define EXTRA_SECTION_FUNCTIONS						\
+  READONLY_DATA_FUNCTION						\
+  CTORS_SECTION_FUNCTION						\
+  DTORS_SECTION_FUNCTION
+
+#define READONLY_DATA_FUNCTION					\
+void								\
+literal_section ()						\
+{								\
+  if (in_section != readonly_data)				\
+    {								\
+      fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
+      in_section = readonly_data;				\
+    }								\
+}								\
+
+#define CTORS_SECTION_FUNCTION						\
+void									\
+ctors_section ()							\
+{									\
+  if (in_section != in_ctors)						\
+    {									\
+      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
+      in_section = in_ctors;						\
+    }									\
+}
+
+#define DTORS_SECTION_FUNCTION						\
+void									\
+dtors_section ()							\
+{									\
+  if (in_section != in_dtors)						\
+    {									\
+      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
+      in_section = in_dtors;						\
+    }									\
+}
+
+#define INT_ASM_OP ".word"
+
+/* A C statement (sans semicolon) to output an element in the table of
+   global constructors.  */
+#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
+  do {									\
+    ctors_section ();							\
+    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
+    assemble_name (FILE, NAME);						\
+    fprintf (FILE, "\n");						\
+  } while (0)
+
+/* A C statement (sans semicolon) to output an element in the table of
+   global destructors.  */
+#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
+  do {									\
+    dtors_section ();                   				\
+    fprintf (FILE, "\t%s\t ", INT_ASM_OP);				\
+    assemble_name (FILE, NAME);              				\
+    fprintf (FILE, "\n");						\
+  } while (0)
diff --git a/gcc/config/a29k/unix.h b/gcc/config/a29k/unix.h
new file mode 100755
index 0000000..f05f258
--- /dev/null
+++ b/gcc/config/a29k/unix.h
@@ -0,0 +1,92 @@
+/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU, Unix.
+   Copyright (C) 1991, 1993, 1994, 1996 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+/* We define unix instead of EPI and define unix-style machine names.  */
+
+/* Set our default target to be the 29050; that is the more interesting chip
+   for Unix systems.  */
+
+#undef TARGET_DEFAULT
+#define TARGET_DEFAULT (1+2+16+128)
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dam29k -Da29k -Dam29000 -Asystem(unix) -Acpu(a29k) -Amachine(a29k)"
+
+#undef CPP_SPEC
+#define CPP_SPEC "%{!m29000:-Dam29050 -D__am29050__}"
+
+/* Use a default linker configuration file.  */
+#undef LINK_SPEC
+#define LINK_SPEC "-T default.gld%s"
+
+/* Define the magic numbers that we recognize as COFF.  */
+
+#define MY_ISCOFF(magic) ((magic) == SIPFBOMAGIC || (magic) == SIPRBOMAGIC)
+
+/* For some systems, it is best if double-word objects are aligned on a 
+   doubleword boundary.  We want to maintain compatibility with MetaWare in
+   a29k.h, but do not feel constrained to do so here.  */
+
+#undef BIGGEST_ALIGNMENT
+#define BIGGEST_ALIGNMENT 64
+
+/* Add shared data as a kludge for now.  */
+
+#undef ASM_FILE_START
+#define ASM_FILE_START(FILE)					\
+{ char *p, *after_dir = main_input_filename;			\
+  if (TARGET_29050)						\
+    fprintf (FILE, "\t.cputype 29050\n");			\
+  for (p = main_input_filename; *p; p++)			\
+    if (*p == '/')						\
+      after_dir = p + 1;					\
+  fprintf (FILE, "\t.file ");					\
+  output_quoted_string (FILE, after_dir);			\
+  fprintf (FILE, "\n");						\
+  if (flag_shared_data)						\
+    fprintf (FILE, "\t.sect .shdata,data\n");			\
+  fprintf (FILE, "\t.sect .lit,lit\n");  }
+
+/* Output before shared  data.  */
+
+#define SHARED_SECTION_ASM_OP "\t.use .shdata"
+
+/* If we want shared data, we have to turn off commons.  */
+
+#define OVERRIDE_OPTIONS if (flag_shared_data) flag_no_common = 1;
+
+/* Default to -fno-pcc-struct-return, since we don't have to worry about
+   compatibility.  */
+#define DEFAULT_PCC_STRUCT_RETURN 0
+
+#if 0 /* This would be needed except that the 29k doesn't have strict
+	 alignment requirements.  */
+
+#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)				\
+  (((TYPE) != 0)							\
+	? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY)				\
+		? PARM_BOUNDARY						\
+		: TYPE_ALIGN(TYPE))					\
+	: ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)			\
+		? PARM_BOUNDARY						\
+		: GET_MODE_ALIGNMENT(MODE)))
+#endif
diff --git a/gcc/config/a29k/vx29k.h b/gcc/config/a29k/vx29k.h
new file mode 100755
index 0000000..8739b1b
--- /dev/null
+++ b/gcc/config/a29k/vx29k.h
@@ -0,0 +1,46 @@
+/* Definitions of target machine for GNU compiler.  Vxworks 29k version.
+   Copyright (C) 1994, 1995, 1996 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* This file just exists to give specs for the 29k running on VxWorks.  */
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#undef  CPP_PREDEFINES
+#define CPP_PREDEFINES "-D_AM29K -D_AM29000 -Acpu(a29k) -Amachine(a29k) -D__vxworks -D__vxworks_5"
+
+/* Vxworks header files require that the macro CPU be set.
+   We could define it in CPP_PREDEFINES, but the value is (or will be)
+   dependent upon GCC options.  */
+
+#undef CPP_SPEC
+#define CPP_SPEC "-DCPU=AM29200"
+
+/* VxWorks does all the library stuff itself.  */
+
+#undef LIB_SPEC
+#define LIB_SPEC ""
+
+/* VxWorks provides the functionality of crt0.o and friends itself.  */
+
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "crtbegin.o%s"
+
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC "crtend.o%s"
diff --git a/gcc/config/a29k/x-unix b/gcc/config/a29k/x-unix
new file mode 100755
index 0000000..ed85ea3
--- /dev/null
+++ b/gcc/config/a29k/x-unix
@@ -0,0 +1,2 @@
+# Needed for missing functions in Sym1.
+CLIB=-liberty -lld
diff --git a/gcc/config/a29k/xm-a29k.h b/gcc/config/a29k/xm-a29k.h
new file mode 100755
index 0000000..774e34b
--- /dev/null
+++ b/gcc/config/a29k/xm-a29k.h
@@ -0,0 +1,41 @@
+/* Configuration for GNU C-compiler for AMD Am29000 processor. 
+   Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+/* #defines that need visibility everywhere.  */
+#define FALSE 0
+#define TRUE 1
+
+/* This describes the machine the compiler is hosted on.  */
+#define HOST_BITS_PER_CHAR 8
+#define HOST_BITS_PER_SHORT 16
+#define HOST_BITS_PER_INT 32
+#define HOST_BITS_PER_LONG 32
+#define HOST_BITS_PER_LONGLONG 64
+
+#define HOST_WORDS_BIG_ENDIAN
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.   */
+#include "tm.h"
+
+/* Arguments to use with `exit'.  */
+#define SUCCESS_EXIT_CODE 0
+#define FATAL_EXIT_CODE 33
diff --git a/gcc/config/a29k/xm-unix.h b/gcc/config/a29k/xm-unix.h
new file mode 100755
index 0000000..206d8fd
--- /dev/null
+++ b/gcc/config/a29k/xm-unix.h
@@ -0,0 +1,43 @@
+/* Configuration for GNU C-compiler for AMD Am29000 processor. 
+   Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* #defines that need visibility everywhere.  */
+#define FALSE 0
+#define TRUE 1
+
+/* This describes the machine the compiler is hosted on.  */
+#define HOST_BITS_PER_CHAR 8
+#define HOST_BITS_PER_SHORT 16
+#define HOST_BITS_PER_INT 32
+#define HOST_BITS_PER_LONG 32
+#define HOST_BITS_PER_LONGLONG 64
+
+#define HOST_WORDS_BIG_ENDIAN
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.   */
+#include "tm.h"
+
+/* Arguments to use with `exit'.  */
+#define SUCCESS_EXIT_CODE 0
+#define FATAL_EXIT_CODE 33
+
+/* Ultra is V7, which is closest to USG.  */
+#define USG