initial commit

96 files changed, 30322 insertions, 0 deletions

diff --git a/gcc/config/mips/abi64.h b/gcc/config/mips/abi64.h
new file mode 100755
index 0000000..3af89dc
--- /dev/null
+++ b/gcc/config/mips/abi64.h
@@ -0,0 +1,251 @@
+/* Definitions of target machine for GNU compiler.  64 bit ABI support.
+   Copyright (C) 1994, 1995, 1996, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Macros to implement the 64 bit ABI.  This file is meant to be included
+   after mips.h.  */
+
+#undef SUBTARGET_TARGET_OPTIONS
+#define SUBTARGET_TARGET_OPTIONS\
+  { "abi=", &mips_abi_string	},
+
+#undef STACK_BOUNDARY
+#define STACK_BOUNDARY \
+  ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
+   ? 64 : 128)
+
+#undef MIPS_STACK_ALIGN
+#define MIPS_STACK_ALIGN(LOC)						\
+  ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)	\
+   ? ((LOC) + 7) & ~7							\
+   : ((LOC) + 15) & ~15)
+
+#undef GP_ARG_LAST
+#define GP_ARG_LAST  ((mips_abi == ABI_32 || mips_abi == ABI_O64)	\
+		      ? GP_REG_FIRST + 7 : GP_REG_FIRST + 11)
+#undef FP_ARG_LAST
+#define FP_ARG_LAST  ((mips_abi == ABI_32 || mips_abi == ABI_O64)	\
+		      ? FP_REG_FIRST + 15 : FP_REG_FIRST + 19)
+
+#undef SUBTARGET_CONDITIONAL_REGISTER_USAGE
+#define SUBTARGET_CONDITIONAL_REGISTER_USAGE \
+{									\
+  /* fp20-23 are now caller saved.  */					\
+  if (mips_abi == ABI_64)						\
+    {									\
+      int regno;							\
+      for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) \
+	call_used_regs[regno] = 1;					\
+    }									\
+  /* odd registers from fp21 to fp31 are now caller saved.  */		\
+  if (mips_abi == ABI_N32)						\
+    {									\
+      int regno;							\
+      for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) \
+	call_used_regs[regno] = 1;					\
+    }									\
+}
+
+#undef MAX_ARGS_IN_REGISTERS
+#define MAX_ARGS_IN_REGISTERS ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
+			       ? 4 : 8)
+
+#undef REG_PARM_STACK_SPACE
+#define REG_PARM_STACK_SPACE(FNDECL) 					 \
+  ((mips_abi == ABI_32 || mips_abi == ABI_O64)				 \
+   ? (MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
+   : 0)
+
+#define FUNCTION_ARG_PADDING(MODE, TYPE)				\
+  (! BYTES_BIG_ENDIAN							\
+   ? upward								\
+   : (((MODE) == BLKmode						\
+       ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST		\
+	  && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
+       : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY			\
+	  && (mips_abi == ABI_32					\
+	      || mips_abi == ABI_O64					\
+	      || mips_abi == ABI_EABI					\
+	      || GET_MODE_CLASS (MODE) == MODE_INT)))			\
+      ? downward : upward))
+
+#undef RETURN_IN_MEMORY
+#define RETURN_IN_MEMORY(TYPE)						\
+  ((mips_abi == ABI_32 || mips_abi == ABI_O64)				\
+   ? TYPE_MODE (TYPE) == BLKmode					\
+   : (int_size_in_bytes (TYPE)						\
+      > (mips_abi == ABI_EABI ? 2 * UNITS_PER_WORD : 16)))
+
+extern struct rtx_def *mips_function_value ();
+#undef FUNCTION_VALUE
+#define FUNCTION_VALUE(VALTYPE, FUNC)	mips_function_value (VALTYPE, FUNC)
+
+/* For varargs, we must save the current argument, because it is the fake
+   argument va_alist, and will need to be converted to the real argument.
+   For stdarg, we do not need to save the current argument, because it
+   is a real argument.  */
+#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)	\
+{ int mips_off = (! current_function_varargs) && (! (CUM).last_arg_fp);	\
+  int mips_fp_off = (! current_function_varargs) && ((CUM).last_arg_fp); \
+  if (((mips_abi != ABI_32 && mips_abi != ABI_O64)			\
+       && (CUM).arg_words < MAX_ARGS_IN_REGISTERS - mips_off)		\
+      || (mips_abi == ABI_EABI						\
+	  && ! TARGET_SOFT_FLOAT					\
+	  && (CUM).fp_arg_words < MAX_ARGS_IN_REGISTERS - mips_fp_off))	\
+    {									\
+      int mips_save_gp_regs =						\
+        MAX_ARGS_IN_REGISTERS - (CUM).arg_words - mips_off;		\
+      int mips_save_fp_regs =						\
+        (mips_abi != ABI_EABI ? 0					\
+	 : MAX_ARGS_IN_REGISTERS - (CUM).fp_arg_words - mips_fp_off);	\
+									\
+      if (mips_save_gp_regs < 0)					\
+	mips_save_gp_regs = 0;						\
+      if (mips_save_fp_regs < 0)					\
+	mips_save_fp_regs = 0;						\
+      PRETEND_SIZE = ((mips_save_gp_regs * UNITS_PER_WORD)		\
+		      + (mips_save_fp_regs * UNITS_PER_FPREG));		\
+									\
+      if (! (NO_RTL))							\
+	{								\
+	  if ((CUM).arg_words < MAX_ARGS_IN_REGISTERS - mips_off)	\
+	    {								\
+	      rtx ptr, mem;						\
+	      if (mips_abi != ABI_EABI)					\
+		ptr = virtual_incoming_args_rtx;			\
+	      else							\
+		ptr = plus_constant (virtual_incoming_args_rtx,		\
+				     - (mips_save_gp_regs		\
+					* UNITS_PER_WORD));		\
+	      mem = gen_rtx (MEM, BLKmode, ptr);			\
+	      /* va_arg is an array access in this case, which causes	\
+		 it to get MEM_IN_STRUCT_P set.  We must set it here	\
+		 so that the insn scheduler won't assume that these	\
+		 stores can't possibly overlap with the va_arg loads.  */ \
+	      if (mips_abi != ABI_EABI && BYTES_BIG_ENDIAN)		\
+	        MEM_SET_IN_STRUCT_P (mem, 1);				\
+	      move_block_from_reg					\
+		((CUM).arg_words + GP_ARG_FIRST + mips_off,		\
+		 mem,							\
+		 mips_save_gp_regs,					\
+		 mips_save_gp_regs * UNITS_PER_WORD);			\
+	    }								\
+	  if (mips_abi == ABI_EABI					\
+	      && ! TARGET_SOFT_FLOAT					\
+	      && (CUM).fp_arg_words < MAX_ARGS_IN_REGISTERS - mips_fp_off) \
+	    {								\
+	      enum machine_mode mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode; \
+	      int size = GET_MODE_SIZE (mode);				\
+	      int off;							\
+	      int i;							\
+	      /* We can't use move_block_from_reg, because it will use	\
+                 the wrong mode.  */					\
+	      off = - (mips_save_gp_regs * UNITS_PER_WORD);		\
+	      if (! TARGET_SINGLE_FLOAT)				\
+	        off &= ~ 7;						\
+	      if (! TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)		\
+		off -= (mips_save_fp_regs / 2) * size;			\
+	      else							\
+		off -= mips_save_fp_regs * size;			\
+	      for (i = 0; i < mips_save_fp_regs; i++)			\
+		{							\
+		  rtx tem =						\
+		    gen_rtx (MEM, mode,					\
+			     plus_constant (virtual_incoming_args_rtx,	\
+					    off));			\
+		  emit_move_insn (tem,					\
+				  gen_rtx (REG, mode,			\
+					   ((CUM).fp_arg_words		\
+					    + FP_ARG_FIRST		\
+					    + i				\
+					    + mips_fp_off)));		\
+		  off += size;						\
+		  if (! TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)		\
+		    ++i;						\
+		}							\
+	    }								\
+	}								\
+    }									\
+}
+
+#define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
+
+/* A C expression that indicates when an argument must be passed by
+   reference.  If nonzero for an argument, a copy of that argument is
+   made in memory and a pointer to the argument is passed instead of the
+   argument itself.  The pointer is passed in whatever way is appropriate
+   for passing a pointer to that type.  */
+#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
+  (mips_abi == ABI_EABI							\
+   && function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED))
+
+/* A C expression that indicates when it is the called function's
+   responsibility to make a copy of arguments passed by invisible
+   reference.  Normally, the caller makes a copy and passes the
+   address of the copy to the routine being called.  When
+   FUNCTION_ARG_CALLEE_COPIES is defined and is nonzero, the caller
+   does not make a copy.  Instead, it passes a pointer to the "live"
+   value.  The called function must not modify this value.  If it can
+   be determined that the value won't be modified, it need not make a
+   copy; otherwise a copy must be made.
+
+   ??? The MIPS EABI says that the caller should copy in ``K&R mode.''
+   I don't know how to detect that here, since flag_traditional is not
+   a back end flag.  */
+#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED)		\
+  (mips_abi == ABI_EABI && (NAMED)					\
+   && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
+
+/* Define LONG_MAX correctly for all users.  We need to handle 32 bit EABI,
+   64 bit EABI, N32, and N64 as possible defaults.  The checks performed here
+   are the same as the checks in override_options in mips.c that determines
+   whether MASK_LONG64 will be set.
+
+   This does not handle inappropriate options or ununusal option
+   combinations.  */
+
+#undef LONG_MAX_SPEC
+#if ((MIPS_ABI_DEFAULT == ABI_64) || ((MIPS_ABI_DEFAULT == ABI_EABI) && ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_64BIT)))
+#define LONG_MAX_SPEC \
+  "%{!mabi=n32:%{!mno-long64:%{!mgp32:%{!mips1:%{!mips2:-D__LONG_MAX__=9223372036854775807L}}}}}"
+#else
+  /* CYGNUS LOCAL gavin */
+#define LONG_MAX_SPEC \
+  "%{mabi=64:-D__LONG_MAX__=9223372036854775807L} \
+   %{mabi=eabi:%{!mips1:%{!mips2:-D__LONG_MAX__=9223372036854775807L}}} \
+   %{mlong64:-D__LONG_MAX__=9223372036854775807L} \
+   %{mgp64:-D__LONG_MAX__=9223372036854775807L}"
+#endif
+
+/* ??? Unimplemented stuff follows.  */
+
+/* ??? Add support for 16 byte/128 bit long doubles here when
+   mips_abi != ABI32.  */
+
+/* ??? Make main return zero if user did not specify return value.  */
+
+/* ??? Add support for .interfaces section, so as to get linker warnings
+   when stdarg functions called without prototype in scope?  */
+
+/* ??? Could optimize structure passing by putting the right register rtx
+   into the field decl, so that if we use the field, we can take the value from
+   a register instead of from memory.  */
+
+
+
diff --git a/gcc/config/mips/big.h b/gcc/config/mips/big.h
new file mode 100755
index 0000000..a165b09
--- /dev/null
+++ b/gcc/config/mips/big.h
@@ -0,0 +1,24 @@
+/* CYGNUS LOCAL: Entire file.  */
+
+/* Definitions of target machine for GNU compiler.
+   Little-endian flavor.
+   Copyright (c) 1997 Cygnus Support Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
+#define MULTILIB_ENDIAN_DEFAULT "EB"
diff --git a/gcc/config/mips/bsd-4.h b/gcc/config/mips/bsd-4.h
new file mode 100755
index 0000000..c2aee83
--- /dev/null
+++ b/gcc/config/mips/bsd-4.h
@@ -0,0 +1,46 @@
+/* Definitions of target machine for GNU compiler.  MIPS RISC-OS BSD version.
+   Copyright (C) 1991 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_BSD43
+
+#define CPP_PREDEFINES "\
+-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
+-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
+-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
+
+#define STANDARD_INCLUDE_DIR "/bsd43/usr/include"
+
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+-systype /bsd43/"
+		    
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}"
+
+#define MACHINE_TYPE "RISC-OS BSD Mips"
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
+
+/* Override defaults for finding the MIPS tools.  */
+#define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
+#define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
diff --git a/gcc/config/mips/bsd-5.h b/gcc/config/mips/bsd-5.h
new file mode 100755
index 0000000..f97af5e
--- /dev/null
+++ b/gcc/config/mips/bsd-5.h
@@ -0,0 +1,67 @@
+/* Definitions of target machine for GNU compiler.
+   MIPS RISC-OS, 5.0 BSD version.
+   Copyright (C) 1991 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_BSD43
+
+#define CPP_PREDEFINES "\
+-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
+-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
+-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
+
+#define STANDARD_INCLUDE_DIR "/bsd43/usr/include"
+
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+%{call_shared} %{no_archive} %{exact_version} \
+%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
+-systype /bsd43/"
+		    
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}"
+
+#define MACHINE_TYPE "RISC-OS BSD Mips"
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
+
+/* Override defaults for finding the MIPS tools.  */
+#define MD_STARTFILE_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
+#define MD_EXEC_PREFIX "/bsd43/usr/lib/cmplrs/cc/"
+
+#include "mips/mips.h"
+
+/* Some assemblers have a bug that causes backslash escaped chars in .ascii
+   to be misassembled, so we just completely avoid it.  */
+#undef ASM_OUTPUT_ASCII
+#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
+do {							\
+  unsigned char *s;					\
+  int i;						\
+  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
+    {							\
+      if ((i % 8) == 0)					\
+	fputs ("\n\t.byte\t", (FILE));			\
+      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
+    }							\
+  fputs ("\n", (FILE));					\
+} while (0)
diff --git a/gcc/config/mips/cross64.h b/gcc/config/mips/cross64.h
new file mode 100755
index 0000000..4462e5e
--- /dev/null
+++ b/gcc/config/mips/cross64.h
@@ -0,0 +1,34 @@
+/* Configuration for an Irix 5 host and Irix 6 target using SGI's cross64
+   package.  */
+
+#define STANDARD_INCLUDE_DIR "/usr/cross64/usr/include"
+#undef MD_EXEC_PREFIX
+#define MD_EXEC_PREFIX "/usr/cross64/usr/bin/"
+#undef MD_STARTFILE_PREFIX
+#define MD_STARTFILE_PREFIX "/usr/cross64/usr/lib/lib64/"
+
+/* Must add TOOLROOT to the environment, or else the assembler will not
+   work.  */
+#define INIT_ENVIRONMENT	\
+  "TOOLROOT=/usr/cross64"
+
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC \
+  "%{mips1:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \
+   %{mips2:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \
+   %{!mips1:%{!mips2:%{pg:/usr/cross64/usr/lib64/mips4/gcrt1.o}		    \
+   %{!pg:%{p:/usr/cross64/usr/lib64/mips4/mcrt1.o			    \
+     /usr/cross64/usr/lib64/mips4/libprof1.a}				    \
+   %{!p:/usr/cross64/usr/lib64/mips4/crt1.o}}}}"
+
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC \
+  "%{mips1:crtn.o%s}%{mips2:crtn.o%s}%{!mips1:%{!mips2:/usr/cross64/usr/lib64/mips4/crtn.o}}"
+
+#undef LINK_SPEC
+#define LINK_SPEC "\
+-64 -_SYSTYPE_SVR4 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
+%{bestGnum} %{shared} %{non_shared} \
+%{call_shared} %{no_archive} %{exact_version} \
+%{!shared: %{!non_shared: %{!call_shared: -call_shared -no_unresolved}}} \
+%{!mips1:%{!mips2:-L/usr/cross64/usr/lib64/mips4 -L/usr/cross64/usr/lib64}}"
diff --git a/gcc/config/mips/dec-bsd.h b/gcc/config/mips/dec-bsd.h
new file mode 100755
index 0000000..126353b
--- /dev/null
+++ b/gcc/config/mips/dec-bsd.h
@@ -0,0 +1,53 @@
+/* Definitions for DECstation running BSD as target machine for GNU compiler.
+   Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define DECSTATION
+
+#ifndef CPP_PREDEFINES
+#define CPP_PREDEFINES "-D__ANSI_COMPAT \
+-DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -Dbsd4_4 -Dhost_mips -Dmips \
+-Dunix -D_mips -D_unix -D_host_mips -D_MIPSEL -D_R3000 \
+-Asystem(unix) -Asystem(bsd) -Amachine(mips)"
+#endif
+
+/* Always uses GNU ld.  */
+#ifndef LINK_SPEC
+#define LINK_SPEC "%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3}"
+#endif
+
+#define LIB_SPEC ""
+#define STARTFILE_SPEC ""
+
+#ifndef MACHINE_TYPE
+#define MACHINE_TYPE "DECstation running BSD 4.4"
+#endif
+
+#define TARGET_DEFAULT MASK_GAS
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+
+#include "mips/mips.h"
+
+/* Since gas and gld are standard on 4.4 BSD, we don't need these */
+#undef MD_EXEC_PREFIX
+#undef MD_STARTFILE_PREFIX
+#undef ASM_FINAL_SPEC
+#undef LIB_SPEC
+#undef STARTFILE_SPEC
+
diff --git a/gcc/config/mips/dec-osf1.h b/gcc/config/mips/dec-osf1.h
new file mode 100755
index 0000000..ee7e787
--- /dev/null
+++ b/gcc/config/mips/dec-osf1.h
@@ -0,0 +1,55 @@
+/* Definitions of target machine for GNU compiler.  DECstation (OSF/1) version.
+   Copyright (C) 1992, 1996, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define DEC_OSF1
+
+#define CPP_PREDEFINES "\
+-D__ANSI_COMPAT -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD \
+-Dbsd4_2 -Dhost_mips -Dmips -Dosf -Dunix \
+-Asystem(unix) -Asystem(xpg4) -Acpu(mips) -Amachine(mips)"
+
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+%{call_shared} %{no_archive} %{exact_version} \
+%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}"
+
+#include "mips/ultrix.h"
+#include "mips/mips.h"
+
+/* Specify size_t and wchar_t types.  */
+#undef	SIZE_TYPE
+#undef	WCHAR_TYPE
+#undef	WCHAR_TYPE_SIZE
+
+#define SIZE_TYPE	"long unsigned int"
+#define WCHAR_TYPE	"short unsigned int"
+#define WCHAR_TYPE_SIZE SHORT_TYPE_SIZE
+
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mlong64:-D__PTRDIFF_TYPE__=long\\ int} \
+%{!mlong64:-D__PTRDIFF_TYPE__=int}"
+
+/* turn off collect2 COFF support, since ldfcn now has elf declaration */
+#undef OBJECT_FORMAT_COFF
+
+#undef MACHINE_TYPE
+#define MACHINE_TYPE "DECstation running DEC OSF/1"
diff --git a/gcc/config/mips/ecoff.h b/gcc/config/mips/ecoff.h
new file mode 100755
index 0000000..dcc00a4
--- /dev/null
+++ b/gcc/config/mips/ecoff.h
@@ -0,0 +1,35 @@
+/* Definitions of target machine for GNU compiler.  MIPS version with
+   GOFAST floating point library.
+   Copyright (C) 1994, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* US Software GOFAST library support.  */
+#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS
+
+#include "mips/mips.h"
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR3000 -D_mips -D_MIPSEB -D_R3000"
+
+/* Use memcpy, et. al., rather than bcopy.  */
+#define TARGET_MEM_FUNCTIONS
+
+/* Don't assume anything about startfiles.  The linker script will load the
+   appropriate startfiles.  */
+#define STARTFILE_SPEC ""
diff --git a/gcc/config/mips/ecoffl.h b/gcc/config/mips/ecoffl.h
new file mode 100755
index 0000000..9fe90e8
--- /dev/null
+++ b/gcc/config/mips/ecoffl.h
@@ -0,0 +1,30 @@
+/* Definitions of target machine for GNU compiler.  Little endian MIPS
+   version with GOFAST floating point library.
+   Copyright (C) 1994, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* This is a little endian version of ecoff.h.  */
+
+#define TARGET_ENDIAN_DEFAULT 0
+
+#include "gofast.h"
+#include "mips/ecoff.h"
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000"
diff --git a/gcc/config/mips/elf.h b/gcc/config/mips/elf.h
new file mode 100755
index 0000000..8603047
--- /dev/null
+++ b/gcc/config/mips/elf.h
@@ -0,0 +1,352 @@
+/* Definitions of target machine for GNU compiler.  MIPS R3000 version with
+   GOFAST floating point library.
+   Copyright (C) 1994, 1997, 1999 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Use ELF.  */
+#define OBJECT_FORMAT_ELF
+
+/* Until we figure out what MIPS ELF targets normally use, just do
+   stabs in ELF.  */
+#ifndef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+#endif
+
+/* Mostly like ECOFF.  */
+#include "gofast.h"
+#include "mips/ecoff.h"
+
+/* We need to use .esize and .etype instead of .size and .type to
+   avoid conflicting with ELF directives.  */
+#undef PUT_SDB_SIZE
+#define PUT_SDB_SIZE(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.esize\t%d;", (a));	\
+} while (0)
+
+#undef PUT_SDB_TYPE
+#define PUT_SDB_TYPE(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a));	\
+} while (0)
+
+/* Biggest alignment supported by the object file format of this
+   machine.  Use this macro to limit the alignment which can be
+   specified using the `__attribute__ ((aligned (N)))' construct.  If
+   not defined, the default value is `BIGGEST_ALIGNMENT'.  */
+
+#define MAX_OFILE_ALIGNMENT (32768*8)
+
+/* A C statement to output something to the assembler file to switch to section
+   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
+   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
+   define this macro in such cases.  */
+
+#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \
+do {								\
+  extern FILE *asm_out_text_file;				\
+  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)		\
+    fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \
+  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))	\
+    fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME));	\
+  else								\
+    fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME));	\
+} while (0)
+
+/* The following macro defines the format used to output the second
+   operand of the .type assembler directive.  Different svr4 assemblers
+   expect various different forms for this operand.  The one given here
+   is just a default.  You may need to override it in your machine-
+   specific tm.h file (depending upon the particulars of your assembler).  */
+
+#define TYPE_OPERAND_FMT        "@%s"
+
+/* Define the strings used for the special svr4 .type and .size directives.
+   These strings generally do not vary from one system running svr4 to
+   another, but if a given system (e.g. m88k running svr) needs to use
+   different pseudo-op names for these, they may be overridden in the
+   file which includes this one.  */
+
+#undef TYPE_ASM_OP
+#undef SIZE_ASM_OP
+#define TYPE_ASM_OP	".type"
+#define SIZE_ASM_OP	".size"
+
+/* If defined, a C expression whose value is a string containing the
+   assembler operation to identify the following data as
+   uninitialized global data.  If not defined, and neither
+   `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
+   uninitialized global data will be output in the data section if
+   `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
+   used.  */
+#ifndef BSS_SECTION_ASM_OP
+#define BSS_SECTION_ASM_OP	".section\t.bss"
+#endif
+
+/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
+   separate, explicit argument.  If you define this macro, it is used
+   in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
+   handling the required alignment of the variable.  The alignment is
+   specified as the number of bits.
+
+   Try to use function `asm_output_aligned_bss' defined in file
+   `varasm.c' when defining this macro. */
+#ifndef ASM_OUTPUT_ALIGNED_BSS
+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
+  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
+#endif
+
+/* These macros generate the special .type and .size directives which
+   are used to set the corresponding fields of the linker symbol table
+   entries in an ELF object file under SVR4.  These macros also output
+   the starting labels for the relevant functions/objects.  */
+
+/* Write the extra assembler code needed to declare an object properly.  */
+
+#undef ASM_DECLARE_OBJECT_NAME
+#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
+  do {									\
+    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
+    assemble_name (FILE, NAME);						\
+    putc (',', FILE);							\
+    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
+    putc ('\n', FILE);							\
+    size_directive_output = 0;						\
+    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
+      {									\
+	size_directive_output = 1;					\
+	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
+	assemble_name (FILE, NAME);					\
+	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
+      }									\
+    mips_declare_object (FILE, NAME, "", ":\n", 0);			\
+  } while (0)
+
+/* Output the size directive for a decl in rest_of_decl_compilation
+   in the case where we did not do so before the initializer.
+   Once we find the error_mark_node, we know that the value of
+   size_directive_output was set
+   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
+
+#undef ASM_FINISH_DECLARE_OBJECT
+#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
+do {									 \
+     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
+     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
+         && ! AT_END && TOP_LEVEL					 \
+	 && DECL_INITIAL (DECL) == error_mark_node			 \
+	 && !size_directive_output)					 \
+       {								 \
+	 size_directive_output = 1;					 \
+	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
+	 assemble_name (FILE, name);					 \
+	 fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL)));  \
+       }								 \
+   } while (0)
+
+#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)                            \
+ do { fputc ( '\t', FILE);                                            \
+      assemble_name (FILE, LABEL1);                                   \
+      fputs ( " = ", FILE);                                           \
+      assemble_name (FILE, LABEL2);                                   \
+      fputc ( '\n', FILE);                                            \
+ } while (0)
+
+/* Note about .weak vs. .weakext
+   The mips native assemblers support .weakext, but not .weak.
+   mips-elf gas supports .weak, but not .weakext.
+   mips-elf gas has been changed to support both .weak and .weakext,
+   but until that support is generally available, the 'if' below
+   should serve. */
+
+#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
+#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE)	\
+ do {						\
+  if (TARGET_GAS)                               \
+      fputs ("\t.weak\t", FILE);		\
+  else                                          \
+      fputs ("\t.weakext\t", FILE);		\
+  assemble_name (FILE, NAME);			\
+  if (VALUE)					\
+    {						\
+      fputc (' ', FILE);			\
+      assemble_name (FILE, VALUE);		\
+    }						\
+  fputc ('\n', FILE);				\
+ } while (0)
+
+#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
+#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
+#define UNIQUE_SECTION(DECL,RELOC)					   \
+do {									   \
+  int len, size, sec;							   \
+  char *name, *string, *prefix;						   \
+  static char *prefixes[4][2] = {					   \
+    { ".text.", ".gnu.linkonce.t." },					   \
+    { ".rodata.", ".gnu.linkonce.r." },					   \
+    { ".data.", ".gnu.linkonce.d." },					   \
+    { ".sdata.", ".gnu.linkonce.s." }					   \
+  };									   \
+									   \
+  name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL));		   \
+  size = int_size_in_bytes (TREE_TYPE (decl));				   \
+									   \
+  /* Determine the base section we are interested in:			   \
+     0=text, 1=rodata, 2=data, 3=sdata.  */				   \
+  if (TREE_CODE (DECL) == FUNCTION_DECL)				   \
+    sec = 0;								   \
+  else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)			   \
+      && TREE_CODE (decl) == STRING_CST					   \
+      && !flag_writable_strings)					   \
+    {									   \
+      /* For embedded position independent code, put constant strings	   \
+	 in the text section, because the data section is limited to	   \
+	 64K in size.  For mips16 code, put strings in the text		   \
+	 section so that a PC relative load instruction can be used to	   \
+	 get their address.  */						   \
+      sec = 0;								   \
+    }									   \
+  else if (TARGET_EMBEDDED_DATA)					   \
+    {									   \
+      /* For embedded applications, always put an object in read-only data \
+	 if possible, in order to reduce RAM usage.  */			   \
+									   \
+      if (DECL_READONLY_SECTION (DECL, RELOC))				   \
+	sec = 1;							   \
+      else if (size > 0 && size <= mips_section_threshold)		   \
+	sec = 3;							   \
+      else								   \
+	sec = 2;							   \
+    }									   \
+  else									   \
+    {									   \
+      /* For hosted applications, always put an object in small data if	   \
+	 possible, as this gives the best performance.  */		   \
+									   \
+      if (size > 0 && size <= mips_section_threshold)			   \
+	sec = 3;							   \
+      else if (DECL_READONLY_SECTION (DECL, RELOC))			   \
+	sec = 1;							   \
+      else								   \
+	sec = 2;							   \
+    }									   \
+									   \
+  prefix = prefixes[sec][DECL_ONE_ONLY (DECL)];				   \
+  len = strlen (name) + strlen (prefix);				   \
+  string = alloca (len + 1);						   \
+  sprintf (string, "%s%s", prefix, name);				   \
+									   \
+  DECL_SECTION_NAME (DECL) = build_string (len, string);		   \
+} while (0)
+
+/* Support the ctors/dtors and other sections.  */
+ 
+/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
+ 
+   Note that we want to give these sections the SHF_WRITE attribute
+   because these sections will actually contain data (i.e. tables of
+   addresses of functions in the current root executable or shared library
+   file) and, in the case of a shared library, the relocatable addresses
+   will have to be properly resolved/relocated (and then written into) by
+   the dynamic linker when it actually attaches the given shared library
+   to the executing process.  (Note that on SVR4, you may wish to use the
+   `-z text' option to the ELF linker, when building a shared library, as
+   an additional check that you are doing everything right.  But if you do
+   use the `-z text' option when building a shared library, you will get
+   errors unless the .ctors and .dtors sections are marked as writable
+   via the SHF_WRITE attribute.)  */
+
+#define CTORS_SECTION_ASM_OP    "\t.section\t.ctors,\"aw\""
+#define DTORS_SECTION_ASM_OP    "\t.section\t.dtors,\"aw\""
+ 
+/* A list of other sections which the compiler might be "in" at any
+   given time.  */
+#undef EXTRA_SECTIONS
+#define EXTRA_SECTIONS in_sdata, in_rdata, in_ctors, in_dtors
+ 
+#define INVOKE__main
+#define NAME__MAIN "__gccmain"
+#define SYMBOL__MAIN __gccmain
+
+#undef EXTRA_SECTION_FUNCTIONS
+#define EXTRA_SECTION_FUNCTIONS                                         \
+  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(ctors_section, in_ctors, CTORS_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(dtors_section, in_dtors, DTORS_SECTION_ASM_OP)
+
+#define SECTION_FUNCTION_TEMPLATE(FN, ENUM, OP)                               \
+void FN ()                                                            \
+{                                                                     \
+  if (in_section != ENUM)                                             \
+    {                                                                 \
+      fprintf (asm_out_file, "%s\n", OP);                             \
+      in_section = ENUM;                                              \
+    }                                                                 \
+}
+
+
+/* A C statement (sans semicolon) to output an element in the table of
+   global constructors.  */
+#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)                             \
+  do {                                                                \
+    ctors_section ();                                                 \
+    fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word");     \
+    assemble_name (FILE, NAME);                                       \
+    fprintf (FILE, "\n");                                             \
+  } while (0)
+
+
+/* A C statement (sans semicolon) to output an element in the table of
+   global destructors.  */
+#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)                              \
+  do {                                                                \
+    dtors_section ();                                                 \
+    fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word");     \
+    assemble_name (FILE, NAME);                                       \
+    fprintf (FILE, "\n");                                             \
+  } while (0)
+
+#define CTOR_LIST_BEGIN                                 \
+asm (CTORS_SECTION_ASM_OP);                             \
+func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) }
+ 
+#define CTOR_LIST_END                                   \
+asm (CTORS_SECTION_ASM_OP);                             \
+func_ptr __CTOR_END__[1] = { (func_ptr) 0 };
+ 
+#define DTOR_LIST_BEGIN                                 \
+asm (DTORS_SECTION_ASM_OP);                             \
+func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) }
+
+#define DTOR_LIST_END                                   \
+asm (DTORS_SECTION_ASM_OP);                             \
+func_ptr __DTOR_END__[1] = { (func_ptr) 0 };
+
+/* Don't set the target flags, this is done by the linker script */
+#undef LIB_SPEC
+#define LIB_SPEC ""
+
+#undef  STARTFILE_SPEC
+#define STARTFILE_SPEC "crtbegin%O%s crt0%O%s"
+
+#undef  ENDFILE_SPEC
+#define ENDFILE_SPEC "crtend%O%s"
diff --git a/gcc/config/mips/elf5400.h b/gcc/config/mips/elf5400.h
new file mode 100755
index 0000000..1a6d9fc
--- /dev/null
+++ b/gcc/config/mips/elf5400.h
@@ -0,0 +1,50 @@
+/* CYGNUS LOCAL: Entire file.  */
+
+/* Definitions of target machine for GNU compiler.
+   NEC VR5400 version.
+   Copyright (c) 1997 Cygnus Support Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#define MIPS_CPU_STRING_DEFAULT "VR5400"
+
+#define MIPS_ABI_DEFAULT ABI_EABI
+
+#include "mips/elf64.h"
+#include "mips/abi64.h"
+
+#undef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT }
+
+#undef CPP_PREDEFINES
+#if TARGET_ENDIAN_DEFAULT == 0
+#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR5400 -D_mips -D_MIPSEL -D_R5400"
+#else
+#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR5400 -D_mips -D_MIPSEB -D_R5400"
+#endif
+
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "\
+%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}}\
+%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}}"
+
+#undef MIPS_ISA_DEFAULT
+#define MIPS_ISA_DEFAULT 4
diff --git a/gcc/config/mips/elf64.h b/gcc/config/mips/elf64.h
new file mode 100755
index 0000000..4c72334
--- /dev/null
+++ b/gcc/config/mips/elf64.h
@@ -0,0 +1,354 @@
+/* Definitions of target machine for GNU compiler.  MIPS R4000 version with
+   GOFAST floating point library.
+   Copyright (C) 1994, 1995, 1996, 1997, 1999 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define OBJECT_FORMAT_ELF
+
+/* Default to -mips3.  */
+#define TARGET_DEFAULT MASK_FLOAT64|MASK_64BIT
+#define MIPS_ISA_DEFAULT 3
+
+/* Until we figure out what MIPS ELF targets normally use, just do
+   stabs in ELF.  */
+#ifndef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+#endif
+
+/* US Software GOFAST library support.  */
+#include "gofast.h"
+#define INIT_SUBTARGET_OPTABS INIT_GOFAST_OPTABS
+
+#include "mips/mips.h"
+
+/* This must be done after mips.h, because mips.h defines
+   TARGET_ENDIAN_DEFAULT.  */
+#undef MULTILIB_DEFAULTS
+#if TARGET_ENDIAN_DEFAULT == 0
+#define MULTILIB_DEFAULTS { "EL", "mips3" }
+#else
+#define MULTILIB_DEFAULTS { "EB", "mips3" }
+#endif
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000"
+
+/* I would rather put this in CPP_PREDEFINES, but the gcc driver
+   doesn't handle -U options in CPP_PREDEFINES.  */
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "\
+%{!mips1:%{!mips2:-U__mips -D__mips=3 %{!mgp32: -D__mips64}}}"
+
+/* Use memcpy, et. al., rather than bcopy.  */
+#define TARGET_MEM_FUNCTIONS
+
+/* Biggest alignment supported by the object file format of this
+   machine.  Use this macro to limit the alignment which can be
+   specified using the `__attribute__ ((aligned (N)))' construct.  If
+   not defined, the default value is `BIGGEST_ALIGNMENT'.  */
+
+#define MAX_OFILE_ALIGNMENT (32768*8)
+
+/* We need to use .esize and .etype instead of .size and .type to
+   avoid conflicting with ELF directives.  */
+#undef PUT_SDB_SIZE
+#define PUT_SDB_SIZE(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.esize\t%d;", (a));	\
+} while (0)
+
+#undef PUT_SDB_TYPE
+#define PUT_SDB_TYPE(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a));	\
+} while (0)
+
+/* A C statement to output something to the assembler file to switch to section
+   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
+   NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
+   define this macro in such cases.  */
+
+#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC) \
+do {								\
+  extern FILE *asm_out_text_file;				\
+  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)		\
+    fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \
+  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))	\
+    fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME));	\
+  else								\
+    fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME));	\
+} while (0)
+
+/* The following macro defines the format used to output the second
+   operand of the .type assembler directive.  Different svr4 assemblers
+   expect various different forms for this operand.  The one given here
+   is just a default.  You may need to override it in your machine-
+   specific tm.h file (depending upon the particulars of your assembler).  */
+
+#define TYPE_OPERAND_FMT        "@%s"
+
+/* Define the strings used for the special svr4 .type and .size directives.
+   These strings generally do not vary from one system running svr4 to
+   another, but if a given system (e.g. m88k running svr) needs to use
+   different pseudo-op names for these, they may be overridden in the
+   file which includes this one.  */
+
+#undef TYPE_ASM_OP
+#undef SIZE_ASM_OP
+#define TYPE_ASM_OP	".type"
+#define SIZE_ASM_OP	".size"
+
+/* These macros generate the special .type and .size directives which
+   are used to set the corresponding fields of the linker symbol table
+   entries in an ELF object file under SVR4.  These macros also output
+   the starting labels for the relevant functions/objects.  */
+
+/* Write the extra assembler code needed to declare an object properly.  */
+
+#undef ASM_DECLARE_OBJECT_NAME
+#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
+  do {									\
+    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
+    assemble_name (FILE, NAME);						\
+    putc (',', FILE);							\
+    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
+    putc ('\n', FILE);							\
+    size_directive_output = 0;						\
+    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
+      {									\
+	size_directive_output = 1;					\
+	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
+	assemble_name (FILE, NAME);					\
+	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
+      }									\
+    mips_declare_object (FILE, NAME, "", ":\n", 0);			\
+  } while (0)
+
+/* Output the size directive for a decl in rest_of_decl_compilation
+   in the case where we did not do so before the initializer.
+   Once we find the error_mark_node, we know that the value of
+   size_directive_output was set
+   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
+
+#undef ASM_FINISH_DECLARE_OBJECT
+#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
+do {									 \
+     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
+     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
+         && ! AT_END && TOP_LEVEL					 \
+	 && DECL_INITIAL (DECL) == error_mark_node			 \
+	 && !size_directive_output)					 \
+       {								 \
+	 size_directive_output = 1;					 \
+	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
+	 assemble_name (FILE, name);					 \
+	 fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL)));  \
+       }								 \
+   } while (0)
+
+#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)                            \
+ do { fputc ( '\t', FILE);                                            \
+      assemble_name (FILE, LABEL1);                                   \
+      fputs ( " = ", FILE);                                           \
+      assemble_name (FILE, LABEL2);                                   \
+      fputc ( '\n', FILE);                                            \
+ } while (0)
+
+/* Note about .weak vs. .weakext
+   The mips native assemblers support .weakext, but not .weak.
+   mips-elf gas supports .weak, but not .weakext.
+   mips-elf gas has been changed to support both .weak and .weakext,
+   but until that support is generally available, the 'if' below
+   should serve. */
+
+#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
+#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE)	\
+ do {						\
+  if (TARGET_GAS)                               \
+      fputs ("\t.weak\t", FILE);		\
+  else                                          \
+      fputs ("\t.weakext\t", FILE);		\
+  assemble_name (FILE, NAME);			\
+  if (VALUE)					\
+    {						\
+      fputc (' ', FILE);			\
+      assemble_name (FILE, VALUE);		\
+    }						\
+  fputc ('\n', FILE);				\
+ } while (0)
+
+#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
+#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
+#define UNIQUE_SECTION(DECL,RELOC)					   \
+do {									   \
+  int len, size, sec;							   \
+  char *name, *string, *prefix;						   \
+  static char *prefixes[4][2] = {					   \
+    { ".text.", ".gnu.linkonce.t." },					   \
+    { ".rodata.", ".gnu.linkonce.r." },					   \
+    { ".data.", ".gnu.linkonce.d." },					   \
+    { ".sdata.", ".gnu.linkonce.s." }					   \
+  };									   \
+									   \
+  name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL));		   \
+  size = int_size_in_bytes (TREE_TYPE (decl));				   \
+									   \
+  /* Determine the base section we are interested in:			   \
+     0=text, 1=rodata, 2=data, 3=sdata.  */				   \
+  if (TREE_CODE (DECL) == FUNCTION_DECL)				   \
+    sec = 0;								   \
+  else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)			   \
+      && TREE_CODE (decl) == STRING_CST					   \
+      && !flag_writable_strings)					   \
+    {									   \
+      /* For embedded position independent code, put constant strings	   \
+	 in the text section, because the data section is limited to	   \
+	 64K in size.  For mips16 code, put strings in the text		   \
+	 section so that a PC relative load instruction can be used to	   \
+	 get their address.  */						   \
+      sec = 0;								   \
+    }									   \
+  else if (TARGET_EMBEDDED_DATA)					   \
+    {									   \
+      /* For embedded applications, always put an object in read-only data \
+	 if possible, in order to reduce RAM usage.  */			   \
+									   \
+      if (DECL_READONLY_SECTION (DECL, RELOC))				   \
+	sec = 1;							   \
+      else if (size > 0 && size <= mips_section_threshold)		   \
+	sec = 3;							   \
+      else								   \
+	sec = 2;							   \
+    }									   \
+  else									   \
+    {									   \
+      /* For hosted applications, always put an object in small data if	   \
+	 possible, as this gives the best performance.  */		   \
+									   \
+      if (size > 0 && size <= mips_section_threshold)			   \
+	sec = 3;							   \
+      else if (DECL_READONLY_SECTION (DECL, RELOC))			   \
+	sec = 1;							   \
+      else								   \
+	sec = 2;							   \
+    }									   \
+									   \
+  prefix = prefixes[sec][DECL_ONE_ONLY (DECL)];				   \
+  len = strlen (name) + strlen (prefix);				   \
+  string = alloca (len + 1);						   \
+  sprintf (string, "%s%s", prefix, name);				   \
+									   \
+  DECL_SECTION_NAME (DECL) = build_string (len, string);		   \
+} while (0)
+
+/* Support the ctors/dtors and other sections.  */
+ 
+/* Define the pseudo-ops used to switch to the .ctors and .dtors sections.
+ 
+   Note that we want to give these sections the SHF_WRITE attribute
+   because these sections will actually contain data (i.e. tables of
+   addresses of functions in the current root executable or shared library
+   file) and, in the case of a shared library, the relocatable addresses
+   will have to be properly resolved/relocated (and then written into) by
+   the dynamic linker when it actually attaches the given shared library
+   to the executing process.  (Note that on SVR4, you may wish to use the
+   `-z text' option to the ELF linker, when building a shared library, as
+   an additional check that you are doing everything right.  But if you do
+   use the `-z text' option when building a shared library, you will get
+   errors unless the .ctors and .dtors sections are marked as writable
+   via the SHF_WRITE attribute.)  */
+
+#define CTORS_SECTION_ASM_OP    "\t.section\t.ctors,\"aw\""
+#define DTORS_SECTION_ASM_OP    "\t.section\t.dtors,\"aw\""
+ 
+/* A list of other sections which the compiler might be "in" at any
+   given time.  */
+#undef EXTRA_SECTIONS
+#define EXTRA_SECTIONS in_sdata, in_rdata, in_ctors, in_dtors
+ 
+#define INVOKE__main
+#define NAME__MAIN "__gccmain"
+#define SYMBOL__MAIN __gccmain
+
+#undef EXTRA_SECTION_FUNCTIONS
+#define EXTRA_SECTION_FUNCTIONS                                         \
+  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(ctors_section, in_ctors, CTORS_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(dtors_section, in_dtors, DTORS_SECTION_ASM_OP)
+
+#define SECTION_FUNCTION_TEMPLATE(FN, ENUM, OP)                               \
+void FN ()                                                            \
+{                                                                     \
+  if (in_section != ENUM)                                             \
+    {                                                                 \
+      fprintf (asm_out_file, "%s\n", OP);                             \
+      in_section = ENUM;                                              \
+    }                                                                 \
+}
+
+
+/* A C statement (sans semicolon) to output an element in the table of
+   global constructors.  */
+#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)                             \
+  do {                                                                \
+    ctors_section ();                                                 \
+    fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word");     \
+    assemble_name (FILE, NAME);                                       \
+    fprintf (FILE, "\n");                                             \
+  } while (0)
+
+
+/* A C statement (sans semicolon) to output an element in the table of
+   global destructors.  */
+#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)                              \
+  do {                                                                \
+    dtors_section ();                                                 \
+    fprintf (FILE, "\t%s\t", TARGET_LONG64 ? ".dword" : ".word");     \
+    assemble_name (FILE, NAME);                                       \
+    fprintf (FILE, "\n");                                             \
+  } while (0)
+
+#define CTOR_LIST_BEGIN                                 \
+asm (CTORS_SECTION_ASM_OP);                             \
+func_ptr __CTOR_LIST__[1] = { (func_ptr) (-1) }
+ 
+#define CTOR_LIST_END                                   \
+asm (CTORS_SECTION_ASM_OP);                             \
+func_ptr __CTOR_END__[1] = { (func_ptr) 0 };
+ 
+#define DTOR_LIST_BEGIN                                 \
+asm (DTORS_SECTION_ASM_OP);                             \
+func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) }
+
+#define DTOR_LIST_END                                   \
+asm (DTORS_SECTION_ASM_OP);                             \
+func_ptr __DTOR_END__[1] = { (func_ptr) 0 };
+
+/* Don't set the target flags, this is done by the linker script */
+#undef LIB_SPEC
+#define LIB_SPEC ""
+
+#undef  STARTFILE_SPEC
+#define STARTFILE_SPEC "crtbegin%O%s crt0%O%s"
+
+#undef  ENDFILE_SPEC
+#define ENDFILE_SPEC "crtend%O%s"
diff --git a/gcc/config/mips/elfb4100.h b/gcc/config/mips/elfb4100.h
new file mode 100755
index 0000000..bdba495
--- /dev/null
+++ b/gcc/config/mips/elfb4100.h
@@ -0,0 +1,61 @@
+/* Definitions of target machine for GNU compiler.
+   NEC VR4100 version.
+   Copyright (c) 1995 Cygnus Support Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#define MIPS_CPU_STRING_DEFAULT "VR4100"
+
+/* Use the MIPS EABI by default.  */
+#define MIPS_ABI_DEFAULT ABI_EABI
+
+/* The following is needed because -mips3 and -mips4 set gp64 which in
+   combination with abi=eabi, causes long64 to be set. */
+#define SUBTARGET_CPP_SIZE_SPEC "\
+-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int"
+
+/* Debugging */
+
+#define DWARF2_DEBUGGING_INFO
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+
+/* For the 'preferred' cases ("gN" and "ggdbN") we need to tell the 
+   gnu assembler not to generate debugging information. */
+   
+#define SUBTARGET_ASM_DEBUGGING_SPEC "\
+%{!mmips-as: \
+  %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \
+  %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \
+  %{gdwarf-2*:-g0}} \
+%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
+%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
+%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
+
+#include "mips/elf64.h"
+
+#undef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { "EB", "mno-mips16" }
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "\
+%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}} \
+%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}}"
+
+/* __mips_soft_float must be defined by default because libgloss uses it.  */
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4100 -D_mips -D_MIPSEB -D_R4100 -D__mips_soft_float"
diff --git a/gcc/config/mips/elfb4300.h b/gcc/config/mips/elfb4300.h
new file mode 100755
index 0000000..d12cb46
--- /dev/null
+++ b/gcc/config/mips/elfb4300.h
@@ -0,0 +1,41 @@
+/* Definitions of target machine for GNU compiler.
+   NEC VR4300 version.
+   Copyright (c) 1995 Cygnus Support Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#define MIPS_CPU_STRING_DEFAULT "VR4300"
+
+#define DWARF2_DEBUGGING_INFO
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+
+#define SUBTARGET_ASM_DEBUGGING_SPEC "\
+%{!mmips-as: \
+  %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \
+  %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \
+  %{gdwarf-2*:-g0}} \
+%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
+%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
+%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
+
+#include "mips/elf64.h"
+
+#undef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { "EB" }
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4300 -D_mips -D_MIPSEB -D_R4300"
diff --git a/gcc/config/mips/elfb5000.h b/gcc/config/mips/elfb5000.h
new file mode 100755
index 0000000..63ca5ee
--- /dev/null
+++ b/gcc/config/mips/elfb5000.h
@@ -0,0 +1,48 @@
+/* CYGNUS LOCAL: Entire file.  */
+
+/* Definitions of target machine for GNU compiler.
+   NEC VR5000 version.
+   Copyright (c) 1996 Cygnus Support Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#define MIPS_CPU_STRING_DEFAULT "VR5000"
+
+/* We use the MIPS EABI by default.  */
+#define MIPS_ABI_DEFAULT ABI_EABI
+
+#include "mips/elf64.h"
+#include "mips/abi64.h"
+
+#undef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { "EB" }
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR5000 -D_mips -D_MIPSEB -D_R5000"
+
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "\
+%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}}\
+%{m5400: -DR5400 -D_R5400}\
+%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}}"
+
+#undef MIPS_ISA_DEFAULT
+#define MIPS_ISA_DEFAULT 4
diff --git a/gcc/config/mips/elfl.h b/gcc/config/mips/elfl.h
new file mode 100755
index 0000000..7575e3d
--- /dev/null
+++ b/gcc/config/mips/elfl.h
@@ -0,0 +1,29 @@
+/* Definitions of target machine for GNU compiler.  Little endian MIPS
+   R3000 version with GOFAST floating point library.
+   Copyright (C) 1994 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* This is a little endian version of elf.h.  */
+
+#define TARGET_ENDIAN_DEFAULT 0
+
+#include "mips/elf.h"
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000"
diff --git a/gcc/config/mips/elfl4100.h b/gcc/config/mips/elfl4100.h
new file mode 100755
index 0000000..41b583d
--- /dev/null
+++ b/gcc/config/mips/elfl4100.h
@@ -0,0 +1,61 @@
+/* Definitions of target machine for GNU compiler.
+   NEC VR4100 little-endian version.
+   Copyright (c) 1995 Cygnus Support Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#define MIPS_CPU_STRING_DEFAULT "VR4100"
+
+/* Use the MIPS EABI by default.  */
+#define MIPS_ABI_DEFAULT ABI_EABI
+
+/* The following is needed because -mips3 and -mips4 set gp64 which in
+   combination with abi=eabi, causes long64 to be set. */
+#define SUBTARGET_CPP_SIZE_SPEC "\
+-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int"
+
+/* Debugging */
+
+#define DWARF2_DEBUGGING_INFO
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+
+/* For the 'preferred' cases ("gN" and "ggdbN") we need to tell the 
+   gnu assembler not to generate debugging information. */
+   
+#define SUBTARGET_ASM_DEBUGGING_SPEC "\
+%{!mmips-as: \
+  %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \
+  %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \
+  %{gdwarf-2*:-g0}} \
+%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
+%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
+%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
+
+#include "mips/elfl64.h"
+
+#undef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { "EL", "mno-mips16" }
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "\
+%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}} \
+%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}}"
+
+/* __mips_soft_float must be defined by default because libgloss uses it.  */
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR4100 -D_mips -D_MIPSEL -D_R4100 -D__mips_soft_float"
diff --git a/gcc/config/mips/elfl4300.h b/gcc/config/mips/elfl4300.h
new file mode 100755
index 0000000..4bad15b
--- /dev/null
+++ b/gcc/config/mips/elfl4300.h
@@ -0,0 +1,41 @@
+/* Definitions of target machine for GNU compiler.
+   NEC VR4300 little-endian version.
+   Copyright (c) 1995 Cygnus Support Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#define MIPS_CPU_STRING_DEFAULT "VR4300"
+
+#define DWARF2_DEBUGGING_INFO
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+
+#define SUBTARGET_ASM_DEBUGGING_SPEC "\
+%{!mmips-as: \
+  %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \
+  %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \
+  %{gdwarf-2*:-g0}} \
+%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
+%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
+%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
+
+#include "mips/elfl64.h"
+
+#undef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { "EL" }
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR4300 -D_mips -D_MIPSEL -D_R4300"
diff --git a/gcc/config/mips/elfl5000.h b/gcc/config/mips/elfl5000.h
new file mode 100755
index 0000000..439e177
--- /dev/null
+++ b/gcc/config/mips/elfl5000.h
@@ -0,0 +1,48 @@
+/* CYGNUS LOCAL: Entire file.  */
+
+/* Definitions of target machine for GNU compiler.
+   NEC VR5000 little-endian version.
+   Copyright (c) 1995 Cygnus Support Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#define MIPS_CPU_STRING_DEFAULT "VR5000"
+
+/* We use the MIPS EABI by default.  */
+#define MIPS_ABI_DEFAULT ABI_EABI
+
+#include "mips/elfl64.h"
+#include "mips/abi64.h"
+
+#undef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { "EL" }
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR5000 -D_mips -D_MIPSEL -D_R5000"
+
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "\
+%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}}\
+%{m5400: -DR5400 -D_R5400}\
+%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}}"
+
+#undef MIPS_ISA_DEFAULT
+#define MIPS_ISA_DEFAULT 4
diff --git a/gcc/config/mips/elfl64.h b/gcc/config/mips/elfl64.h
new file mode 100755
index 0000000..5e18c09
--- /dev/null
+++ b/gcc/config/mips/elfl64.h
@@ -0,0 +1,29 @@
+/* Definitions of target machine for GNU compiler.  Little endian MIPS
+   R4000 version with GOFAST floating point library.
+   Copyright (C) 1994 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* This is a little endian version of elf64.h.  */
+
+#define TARGET_ENDIAN_DEFAULT 0
+
+#include "mips/elf64.h"
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR4000 -D_mips -D_MIPSEL -D_R4000"
diff --git a/gcc/config/mips/elflorion.h b/gcc/config/mips/elflorion.h
new file mode 100755
index 0000000..4b7f111
--- /dev/null
+++ b/gcc/config/mips/elflorion.h
@@ -0,0 +1,24 @@
+/* Definitions of target machine for GNU compiler.  MIPS ORION version with
+   GOFAST floating point library.
+   Copyright (C) 1994 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_CPU_STRING_DEFAULT "orion"
+
+#include "mips/elfl64.h"
diff --git a/gcc/config/mips/elforion.h b/gcc/config/mips/elforion.h
new file mode 100755
index 0000000..aa1a058
--- /dev/null
+++ b/gcc/config/mips/elforion.h
@@ -0,0 +1,22 @@
+/* Definitions of target machine for GNU compiler.  MIPS ORION version with
+   GOFAST floating point library.
+   Copyright (C) 1994, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_CPU_STRING_DEFAULT "orion"
diff --git a/gcc/config/mips/gnu.h b/gcc/config/mips/gnu.h
new file mode 100755
index 0000000..bf48bc4
--- /dev/null
+++ b/gcc/config/mips/gnu.h
@@ -0,0 +1,129 @@
+/* Definitions of target machine for GNU compiler.  MIPS GNU Hurd version.
+   Copyright (C) 1995, 1996 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define TARGET_DEFAULT MASK_GAS
+
+#include <mips/mips.h>
+
+#undef SWITCH_TAKES_ARG
+#undef ASM_FILE_END
+#undef ASM_OUTPUT_IDENT
+#undef ASM_OUTPUT_SOURCE_LINE
+#undef READONLY_DATA_SECTION
+#undef SELECT_SECTION
+#undef ASM_DECLARE_FUNCTION_NAME
+#undef ASM_DECLARE_OBJECT_NAME
+/* #undef PREFERRED_DEBUGGING_TYPE */
+
+#include <svr4.h>
+
+#undef MD_EXEC_PREFIX
+#undef MD_STARTFILE_PREFIX
+#undef TARGET_VERSION
+#define TARGET_VERSION fprintf (stderr, " (MIPS GNU/ELF)");
+
+/* Output at beginning of assembler file.  */
+/* The .file command should always begin the output.  */
+#undef ASM_FILE_START
+#define ASM_FILE_START(FILE)						\
+  do {									\
+	mips_asm_file_start (FILE);					\
+	fprintf (FILE, "\t.version\t\"01.01\"\n");			\
+  } while (0)
+
+#undef ASM_FILE_END
+#define ASM_FILE_END(FILE)						\
+  do {				 					\
+	mips_asm_file_end(FILE);					\
+	fprintf ((FILE), "\t%s\t\"GCC: (GNU) %s\"\n",			\
+		IDENT_ASM_OP, version_string);				\
+  } while (0)
+
+#undef ASM_OUTPUT_SOURCE_LINE
+#define ASM_OUTPUT_SOURCE_LINE(FILE, LINE)				\
+  do {									\
+      ++sym_lineno;							\
+      fprintf ((FILE), ".LM%d:\n\t%s %d,0,%d,.LM%d\n",			\
+	       sym_lineno, ASM_STABN_OP, N_SLINE, (LINE), sym_lineno);	\
+  } while (0)
+
+#undef ASM_DECLARE_FUNCTION_NAME
+#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL)			\
+  do {									\
+    extern FILE *asm_out_text_file;					\
+									\
+    if (TARGET_GP_OPT)							\
+      STREAM = asm_out_text_file;					\
+    fprintf (STREAM, "\t%s\t ", TYPE_ASM_OP);				\
+    assemble_name (STREAM, NAME);					\
+    putc (',', STREAM);							\
+    fprintf (STREAM, TYPE_OPERAND_FMT, "function");			\
+    putc ('\n', STREAM);						\
+    ASM_DECLARE_RESULT (STREAM, DECL_RESULT (DECL));			\
+    HALF_PIC_DECLARE (NAME);						\
+  } while (0)
+
+/* Switch  Recognition by gcc.c.  Add -G xx support */
+#undef SWITCH_TAKES_ARG
+#define SWITCH_TAKES_ARG(CHAR)						\
+  (DEFAULT_SWITCH_TAKES_ARG(CHAR) || (CHAR) == 'G')
+
+#undef DEFAULT_PCC_STRUCT_RETURN
+#define DEFAULT_PCC_STRUCT_RETURN 1
+
+#undef DBX_REGISTER_NUMBER
+#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
+
+#define MIPS_GNU
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -Acpu(mips) -Amachine(mips) \
+-Dunix -Asystem(unix)  -DMACH -Asystem(mach) -D__GNU__ -Asystem(gnu) \
+-DMIPSEB -DR3000 -D_MIPSEB -D_R3000 \
+-D_MIPS_SZINT=32 -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32"
+
+#undef LINK_SPEC
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+%{call_shared} %{no_archive} %{exact_version} \
+%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
+-systype /gnu/ "
+		    
+#undef LIB_SPEC
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
+
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC  "%{pg:gcrt0.o%s} %{!pg:%{p:gcrt0.o%s} %{!p:crt0.o%s}} %{static:-static}"
+
+#undef MACHINE_TYPE
+#define MACHINE_TYPE "GNU MIPS/ELF"
+
+#undef YES_UNDERSCORE
+
+#undef SDB_DEBUGGING_INFO
+#undef DBX_DEBUGGING_INFO
+#undef MIPS_DEBUGGING_INFO
+#define DWARF_DEBUGGING_INFO
+
+#define NO_MIPS_SELECT_SECTION
+
+/* Get machine-independent configuration parameters for the GNU system.  */
+#include <gnu.h>
diff --git a/gcc/config/mips/iris3.h b/gcc/config/mips/iris3.h
new file mode 100755
index 0000000..1f690ff
--- /dev/null
+++ b/gcc/config/mips/iris3.h
@@ -0,0 +1,72 @@
+/* Definitions of target machine for GNU compiler.  Iris version.
+   Copyright (C) 1991, 1993, 1995, 1996, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define SGI_TARGET 1		/* inform other mips files this is SGI */
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#define CPP_PREDEFINES	"\
+-Dunix -Dmips -Dsgi -DSVR3 -Dhost_mips -DMIPSEB -DSYSTYPE_SYSV \
+-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)"
+
+#define STARTFILE_SPEC	"%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
+
+#define SUBTARGET_CPP_SPEC "\
+%{!ansi:-D__EXTENSIONS__} -D_MIPSEB -D_SYSTYPE_SYSV"
+
+#define LIB_SPEC	\
+	"%{!p:%{!pg:%{!static:%{!g*:-lc_s}} -lc}}%{p:-lc_p}%{pg:-lc_p} crtn.o%s"
+
+#define MACHINE_TYPE	"Silicon Graphics Mips"
+
+/* Always use 1 for .file number.  I [meissner@osf.org] wonder why
+   IRIS needs this.  */
+
+#define SET_FILE_NUMBER() num_source_filenames = 1
+
+/* Put out a label after a .loc.  I [meissner@osf.org] wonder why
+   IRIS needs this.  */
+
+#define LABEL_AFTER_LOC(STREAM) fprintf (STREAM, "LM%d:\n", ++sym_lineno)
+
+#define STACK_ARGS_ADJUST(SIZE)                                         \
+{                                                                       \
+  SIZE.constant += 4;                                                   \
+  if (SIZE.constant < 32)						\
+    SIZE.constant = 32;                                                 \
+}
+
+/* Do not allow `$' in identifiers.  */
+
+#define DOLLARS_IN_IDENTIFIERS 0
+
+/* Tell G++ not to create constructors or destructors with $'s in them.  */
+
+#define NO_DOLLAR_IN_LABEL 1
+
+/* Specify wchar_t type.  */
+#define WCHAR_TYPE	"unsigned char"
+#define WCHAR_TYPE_SIZE BITS_PER_UNIT
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
+
+/* Plain char is unsigned in the SGI compiler.  */
+#define DEFAULT_SIGNED_CHAR 0
diff --git a/gcc/config/mips/iris4.h b/gcc/config/mips/iris4.h
new file mode 100755
index 0000000..7ca0459
--- /dev/null
+++ b/gcc/config/mips/iris4.h
@@ -0,0 +1,48 @@
+/* Definitions of target machine for GNU compiler.  Iris version 4.
+   Copyright (C) 1991, 1993 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Use atexit for static constructors/destructors, instead of defining
+   our own exit function.  */
+#define HAVE_ATEXIT
+
+/* Profiling is supported via libprof1.a not -lc_p as in Irix 3.  */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC \
+  "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}"
+
+#undef LIB_SPEC
+#define LIB_SPEC \
+  "%{!p:%{!pg:%{!static:%{!g*:-lc_s}}}}%{p:libprof1.a%s}%{pg:libprof1.a%s} -lc crtn.o%s"
+
+/* Some assemblers have a bug that causes backslash escaped chars in .ascii
+   to be misassembled, so we just completely avoid it.  */
+#undef ASM_OUTPUT_ASCII
+#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
+do {							\
+  unsigned char *s;					\
+  int i;						\
+  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
+    {							\
+      if ((i % 8) == 0)					\
+	fputs ("\n\t.byte\t", (FILE));			\
+      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
+    }							\
+  fputs ("\n", (FILE));					\
+} while (0)
diff --git a/gcc/config/mips/iris4loser.h b/gcc/config/mips/iris4loser.h
new file mode 100755
index 0000000..426c822
--- /dev/null
+++ b/gcc/config/mips/iris4loser.h
@@ -0,0 +1,5 @@
+/* Like iris4.h, but always inhibits assembler optimization for MIPS as.
+   Use this via mips-sgi-iris4loser if you need it.  */
+
+#define SUBTARGET_MIPS_AS_ASM_SPEC "-O0 %{v}"
+#define SUBTARGET_ASM_OPTIMIZING_SPEC ""
diff --git a/gcc/config/mips/iris5.h b/gcc/config/mips/iris5.h
new file mode 100755
index 0000000..7910eef
--- /dev/null
+++ b/gcc/config/mips/iris5.h
@@ -0,0 +1,164 @@
+/* Definitions of target machine for GNU compiler.  Iris version 5.
+   Copyright (C) 1993, 1995, 1996, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#ifndef TARGET_DEFAULT
+#define	TARGET_DEFAULT	MASK_ABICALLS
+#endif
+#define ABICALLS_ASM_OP ".option pic2"
+
+#include "mips/iris3.h"
+#include "mips/mips.h"
+#include "mips/iris4.h"
+
+/* Irix 5 doesn't use COFF, so disable special COFF handling in collect2.c.  */
+#undef OBJECT_FORMAT_COFF
+
+/* ??? This is correct, but not very useful, because there is no file that
+   uses this macro.  */
+/* ??? The best way to handle global constructors under ELF is to use .init
+   and .fini sections.  Unfortunately, there is apparently no way to get
+   the Irix 5.x (x <= 2) assembler to create these sections.  So we instead
+   use collect.  The linker can create these sections via -init and -fini
+   options, but using this would require modifying how crtstuff works, and
+   I will leave that for another time (or someone else).  */
+#define OBJECT_FORMAT_ELF
+#define HAS_INIT_SECTION
+#define LD_INIT_SWITCH "-init"
+#define LD_FINI_SWITCH "-fini"
+
+/* Specify wchar_t types.  */
+#undef	WCHAR_TYPE
+#undef	WCHAR_TYPE_SIZE
+#undef	MAX_WCHAR_TYPE_SIZE
+
+#define WCHAR_TYPE	"long int"
+#define WCHAR_TYPE_SIZE	LONG_TYPE_SIZE
+#define MAX_WCHAR_TYPE_SIZE	MAX_LONG_TYPE_SIZE
+
+#define WORD_SWITCH_TAKES_ARG(STR)			\
+ (DEFAULT_WORD_SWITCH_TAKES_ARG (STR)			\
+  || !strcmp (STR, "rpath"))
+
+#undef SUBTARGET_CC1_SPEC
+#define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}"
+
+/* ??? _MIPS_SIM and _MIPS_SZPTR should eventually depend on options when
+   options for them exist.  */
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES \
+ "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \
+  -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \
+  -D_MIPS_SIM=_MIPS_SIM_ABI32 -D_MIPS_SZPTR=32 \
+  -Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(sgi)"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "\
+%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE -D_LONGLONG} \
+%{!mfp64: -D_MIPS_FPSET=16}%{mfp64: -D_MIPS_FPSET=32} \
+%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
+%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
+%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
+%{!mips1: %{!mips2: %{!mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS1}}} \
+%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \
+%{!mlong64: -D_MIPS_SZLONG=32}%{mlong64: -D_MIPS_SZLONG=64}"
+
+#undef LINK_SPEC
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+%{call_shared} %{no_archive} %{exact_version} \
+%{static: -non_shared} \
+%{!static: \
+  %{!shared:%{!non_shared:%{!call_shared: -call_shared -no_unresolved}}}} \
+%{rpath} \
+-_SYSTYPE_SVR4"
+
+/* We now support shared libraries.  */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "\
+%{!static: \
+  %{!shared:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}}} \
+%{static: \
+  %{pg:gcrt1.o%s} \
+  %{!pg:%{p:/usr/lib/nonshared/mcrt1.o%s libprof1.a%s} \
+  %{!p:/usr/lib/nonshared/crt1.o%s}}}"
+
+#undef LIB_SPEC
+#define LIB_SPEC "%{!shared:%{p:-lprof1} %{pg:-lprof1} -lc}"
+
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC "%{!shared:crtn.o%s}"
+
+/* We do not want to run mips-tfile!  */
+#undef ASM_FINAL_SPEC
+
+/* The system header files are C++ aware. */
+/* ??? Unfortunately, most but not all of the headers are C++ aware.
+   Specifically, curses.h is not, and as a consequence, defining this
+   used to prevent libg++ building.  This is no longer the case so
+   define it again to prevent other problems, e.g. with getopt in
+   unistd.h.  We still need some way to fix just those files that need
+   fixing.  */
+#define NO_IMPLICIT_EXTERN_C 1
+
+/* We don't support debugging info for now. */
+#undef DBX_DEBUGGING_INFO
+#undef SDB_DEBUGGING_INFO
+#undef MIPS_DEBUGGING_INFO
+#undef PREFERRED_DEBUGGING_TYPE
+
+/* Likewise, the assembler doesn't handle DWARF2 directives.  */
+#define DWARF2_UNWIND_INFO 0
+
+#undef MACHINE_TYPE
+#define MACHINE_TYPE "SGI running IRIX 5.x"
+
+ /* Dollar signs are OK in Irix5 but not in Irix3.  */
+#undef DOLLARS_IN_IDENTIFIERS
+#undef NO_DOLLAR_IN_LABEL
+
+/* -G is incompatible with -KPIC which is the default, so only allow objects
+   in the small data section if the user explicitly asks for it.  */
+#undef MIPS_DEFAULT_GVALUE
+#define MIPS_DEFAULT_GVALUE 0
+
+/* In Irix 5, we must output a `.global name .text' directive for every used
+   but undefined function.  If we don't, the linker may perform an optimization
+   (skipping over the insns that set $gp) when it is unsafe.  This is used
+   indirectly by ASM_OUTPUT_EXTERNAL.  */
+#define ASM_OUTPUT_UNDEF_FUNCTION(FILE, NAME)	\
+do {						\
+  fputs ("\t.globl ", FILE);			\
+  assemble_name (FILE, NAME);			\
+  fputs (" .text\n", FILE);			\
+} while (0)
+
+/* Also do this for libcalls.  */
+#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN)	\
+  mips_output_external_libcall (FILE, XSTR (FUN, 0))
+
+/* This does for functions what ASM_DECLARE_OBJECT_NAME does for variables.
+   This is used indirectly by ASM_OUTPUT_EXTERNAL.  */
+#define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL)	\
+do {							\
+  tree name_tree = get_identifier (NAME);		\
+  TREE_ASM_WRITTEN (name_tree) = 1;			\
+} while (0)
diff --git a/gcc/config/mips/iris5gas.h b/gcc/config/mips/iris5gas.h
new file mode 100755
index 0000000..477a55f
--- /dev/null
+++ b/gcc/config/mips/iris5gas.h
@@ -0,0 +1,34 @@
+/* Definitions of target machine for GNU compiler.  Irix version 5 with gas. */
+
+/* Enable debugging.  */
+#define DBX_DEBUGGING_INFO
+#define SDB_DEBUGGING_INFO
+#define MIPS_DEBUGGING_INFO
+#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
+
+/* GNU as does handle DWARF2 directives.  */
+#undef DWARF2_UNWIND_INFO
+#define DWARF2_UNWIND_INFO 1
+
+/* Irix 5 does not have some strange restrictions that Irix 3 had.  */
+#undef SET_FILE_NUMBER
+#define SET_FILE_NUMBER() ++num_source_filenames
+#undef LABEL_AFTER_LOC
+#define LABEL_AFTER_LOC(STREAM)
+
+/* We need to use .esize and .etype instead of .size and .type to
+   avoid conflicting with ELF directives.  These are only recognized
+   by gas, anyhow, not the native assembler.  */
+#undef PUT_SDB_SIZE
+#define PUT_SDB_SIZE(a)                                       \
+do {                                                  \
+  extern FILE *asm_out_text_file;                     \
+  fprintf (asm_out_text_file, "\t.esize\t%d;", (a));  \
+} while (0)
+
+#undef PUT_SDB_TYPE
+#define PUT_SDB_TYPE(a)                                       \
+do {                                                  \
+  extern FILE *asm_out_text_file;                     \
+  fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a));        \
+} while (0)
diff --git a/gcc/config/mips/iris6.h b/gcc/config/mips/iris6.h
new file mode 100755
index 0000000..3a456b5
--- /dev/null
+++ b/gcc/config/mips/iris6.h
@@ -0,0 +1,567 @@
+/* Definitions of target machine for GNU compiler.  Iris version 6.
+   Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Default to -mabi=n32 and -mips3.  */
+#define MIPS_ISA_DEFAULT 3
+#define MIPS_ABI_DEFAULT ABI_N32
+#define MULTILIB_DEFAULTS { "mabi=n32" }
+
+#ifndef TARGET_DEFAULT
+#define TARGET_DEFAULT (MASK_ABICALLS|MASK_FLOAT64|MASK_64BIT)
+#endif
+
+#include "mips/iris5.h"
+#include "mips/abi64.h"
+
+/* Irix6 assembler does handle DWARF2 directives.  Override setting in
+ irix5.h file.  */
+#undef DWARF2_UNWIND_INFO
+
+/* For Irix 6, -mabi=64 implies TARGET_LONG64.  */
+/* This is handled in override_options.  */
+
+#undef SUBTARGET_CC1_SPEC
+#define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}"
+
+/* We must pass -D_LONGLONG always, even when -ansi is used, because irix6
+   system header files require it.  This is OK, because gcc never warns
+   when long long is used in system header files.  Alternatively, we can
+   add support for the SGI builtin type __long_long.  */
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES \
+ "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \
+  -D_LONGLONG -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \
+  -Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(sgi)"
+
+#undef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mabi=32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+%{mabi=n32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+%{mabi=64: -D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+%{!mabi*: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
+
+/* We must make -mips3 do what -mlong64 used to do.  */
+/* ??? If no mipsX option given, but a mabi=X option is, then should set
+   _MIPS_ISA based on the mabi=X option.  */
+/* ??? If no mabi=X option give, but a mipsX option is, then should set
+   _MIPS_SIM based on the mipsX option.  */
+/* ??? Same for _MIPS_SZINT.  */
+/* ??? Same for _MIPS_SZPTR.  */
+/* ??? Same for __SIZE_TYPE and __PTRDIFF_TYPE.  */
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "\
+%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE} \
+%{mfp32: -D_MIPS_FPSET=16}%{!mfp32: -D_MIPS_FPSET=32} \
+%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
+%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
+%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
+%{mips4: -D_MIPS_ISA=_MIPS_ISA_MIPS4} \
+%{!mips*: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
+%{mabi=32: -D_MIPS_SIM=_MIPS_SIM_ABI32}	\
+%{mabi=n32: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \
+%{mabi=64: -D_ABI64=3 -D_MIPS_SIM=_ABI64} \
+%{!mabi*: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \
+%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \
+%{mabi=32: -D_MIPS_SZLONG=32} \
+%{mabi=n32: -D_MIPS_SZLONG=32} \
+%{mabi=64: -D_MIPS_SZLONG=64} \
+%{!mabi*: -D_MIPS_SZLONG=32} \
+%{mabi=32: -D_MIPS_SZPTR=32} \
+%{mabi=n32: -D_MIPS_SZPTR=32} \
+%{mabi=64: -D_MIPS_SZPTR=64} \
+%{!mabi*: -D_MIPS_SZPTR=32} \
+%{!mips1:%{!mips2: -D_COMPILER_VERSION=601}}		\
+%{!mips*: -U__mips -D__mips=3} \
+%{mabi=32: -U__mips64} \
+%{mabi=n32: -D__mips64} \
+%{mabi=64: -D__mips64} \
+%{!mabi*: -D__mips64}"
+
+/* Irix 6 uses DWARF-2.  */
+#define DWARF2_DEBUGGING_INFO
+#define MIPS_DEBUGGING_INFO
+#undef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+
+/* Force the generation of dwarf .debug_frame sections even if not
+   compiling -g.  This guarantees that we can unwind the stack. */
+#define DWARF2_FRAME_INFO 1
+/* The size in bytes of a DWARF field indicating an offset or length
+   relative to a debug info section, specified to be 4 bytes in the DWARF-2
+   specification.  The SGI/MIPS ABI defines it to be the same as PTR_SIZE.  */
+#define DWARF_OFFSET_SIZE PTR_SIZE
+
+/* There is no GNU as port for Irix6 yet, so we set MD_EXEC_PREFIX so that
+   gcc will automatically find SGI as instead of searching the user's path.
+   The latter can fail when building a cross compiler if the user has . in
+   the path before /usr/bin, since then gcc will find and try to use the link
+   to the cross assembler which can't possibly work.  */
+
+#undef MD_EXEC_PREFIX
+#define MD_EXEC_PREFIX "/usr/bin/"
+
+/* We have no need for MD_STARTFILE_PREFIX.  */
+#undef MD_STARTFILE_PREFIX
+
+#undef MACHINE_TYPE
+#define MACHINE_TYPE "SGI running IRIX 6.x"
+
+/* The Irix 6.0.1 assembler doesn't like labels in the text section, so
+   just avoid emitting them.  */
+#define ASM_IDENTIFY_GCC(x) ((void)0)
+#define ASM_IDENTIFY_LANGUAGE(x) ((void)0)
+
+/* Irix 5 stuff that we don't need for Irix 6.  */
+/* ??? We do need this for the -mabi=32 switch though.  */
+#undef ASM_OUTPUT_UNDEF_FUNCTION
+#undef ASM_OUTPUT_EXTERNAL_LIBCALL
+#undef ASM_DECLARE_FUNCTION_SIZE
+
+/* Stuff we need for Irix 6 that isn't in Irix 5.  */
+
+/* The SGI assembler doesn't like labels before the .ent, so we must output
+   the .ent and function name here, which is the normal place for it.  */
+
+#undef ASM_DECLARE_FUNCTION_NAME
+#define ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL)			\
+  do {									\
+    fputs ("\t.ent\t", STREAM);						\
+    assemble_name (STREAM, NAME);					\
+    fputs ("\n", STREAM);						\
+    assemble_name (STREAM, NAME);					\
+    fputs (":\n", STREAM);						\
+  } while (0)
+
+/* Likewise, the SGI assembler doesn't like labels after the .end, so we
+   must output the .end here.  */
+#define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL)			\
+  do {									\
+    fputs ("\t.end\t", STREAM);						\
+    assemble_name (STREAM, NAME);					\
+    fputs ("\n", STREAM);						\
+  } while (0)
+
+/* Tell function_prologue in mips.c that we have already output the .ent/.end
+   pseudo-ops.  */
+#define FUNCTION_NAME_ALREADY_DECLARED
+
+#undef SET_ASM_OP	/* Has no equivalent.  See ASM_OUTPUT_DEF below.  */
+
+#if 0
+/* This is *NOT* how to equate one symbol to another symbol.  The assembler
+   '=' syntax just equates a name to a constant expression.
+   See ASM_OUTPUT_WEAK_ALIAS.  */
+
+#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)				\
+ do {	fprintf ((FILE), "\t");						\
+	assemble_name (FILE, LABEL1);					\
+	fprintf (FILE, " = ");						\
+	assemble_name (FILE, LABEL2);					\
+	fprintf (FILE, "\n");						\
+  } while (0)
+#endif
+
+/* Define the strings used for the special svr4 .type and .size directives.  */
+
+#define TYPE_ASM_OP	".type"
+#define SIZE_ASM_OP	".size"
+
+/* This is how we tell the assembler that a symbol is weak.  */
+
+#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE)	\
+ do {						\
+  ASM_GLOBALIZE_LABEL (FILE, NAME);		\
+  fputs ("\t.weakext\t", FILE);			\
+  assemble_name (FILE, NAME);			\
+  if (VALUE)					\
+    {						\
+      fputc (' ', FILE);			\
+      assemble_name (FILE, VALUE);		\
+    }						\
+  fputc ('\n', FILE);				\
+ } while (0)
+
+#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,0)
+
+#define POPSECTION_ASM_OP	".popsection"
+
+#define DEBUG_INFO_SECTION	".debug_info,0x7000001e,0,0,1"
+#define DEBUG_LINE_SECTION	".debug_line,0x7000001e,0,0,1"
+#define SFNAMES_SECTION		".debug_sfnames,0x7000001e,0,0,1"
+#define SRCINFO_SECTION		".debug_srcinfo,0x7000001e,0,0,1"
+#define MACINFO_SECTION		".debug_macinfo,0x7000001e,0,0,1"
+#define PUBNAMES_SECTION	".debug_pubnames,0x7000001e,0,0,1"
+#define ARANGES_SECTION		".debug_aranges,0x7000001e,0,0,1"
+#define FRAME_SECTION		".debug_frame,0x7000001e,0x08000000,0,1"
+#define ABBREV_SECTION		".debug_abbrev,0x7000001e,0,0,1"
+
+/* ??? If no mabi=X option give, but a mipsX option is, then should depend
+   on the mipsX option.  */
+#undef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC "%{!mabi*:-n32}"
+
+/* Must pass -g0 to the assembler, otherwise it may overwrite our
+   debug info with its own debug info. */
+/* Must pass -show instead of -v.  */
+/* Must pass -G 0 to the assembler, otherwise we may get warnings about
+   GOT overflow.  */
+/* ??? We pass -w to disable all assembler warnings.  The `label should be
+   inside .ent/.end block' warning that we get for DWARF II debug info labels
+   is particularly annoying.  */
+#undef SUBTARGET_MIPS_AS_ASM_SPEC
+#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v:-show} -G 0 -w"
+
+#undef SUBTARGET_ASM_DEBUGGING_SPEC
+#define SUBTARGET_ASM_DEBUGGING_SPEC "-g0"
+
+/* Stuff for constructors.  Start here.  */
+
+/* The assembler now accepts .section pseudo-ops, but it does not allow
+   one to change the section in the middle of a function, so we can't use
+   the INIT_SECTION_ASM_OP code in crtstuff.  But we can build up the ctor
+   and dtor lists this way, so we use -init and -fini to invoke the
+   do_global_* functions instead of running collect2.  */
+
+#define BSS_SECTION_ASM_OP	".section\t.bss"
+#define CONST_SECTION_ASM_OP_32	"\t.rdata"
+#define CONST_SECTION_ASM_OP_64	".section\t.rodata"
+
+/* The IRIX 6 assembler .section directive takes four additional args:
+   section type, flags, entry size, and alignment.  The alignment of the
+   .ctors and .dtors sections needs to be the same as the size of a pointer
+   so that the linker doesn't add padding between elements.  */
+#if defined (CRT_BEGIN) || defined (CRT_END)
+
+/* If we are included from crtstuff.c, these need to be plain strings.
+   _MIPS_SZPTR is defined in SUBTARGET_CPP_SPEC above.  */
+#if _MIPS_SZPTR == 64
+#define CTORS_SECTION_ASM_OP ".section\t.ctors,1,2,0,8"
+#define DTORS_SECTION_ASM_OP ".section\t.dtors,1,2,0,8"
+#else /* _MIPS_SZPTR != 64 */
+#define CTORS_SECTION_ASM_OP ".section\t.ctors,1,2,0,4"
+#define DTORS_SECTION_ASM_OP ".section\t.dtors,1,2,0,4"
+#endif /* _MIPS_SZPTR == 64 */
+
+#else /* ! (defined (CRT_BEGIN) || defined (CRT_END)) */
+
+/* If we are included from varasm.c, these need to depend on -mabi.  */
+#define CTORS_SECTION_ASM_OP \
+  (TARGET_LONG64 ? ".section\t.ctors,1,2,0,8" : ".section\t.ctors,1,2,0,4")
+#define DTORS_SECTION_ASM_OP \
+  (TARGET_LONG64 ? ".section\t.dtors,1,2,0,8" : ".section\t.dtors,1,2,0,4")
+#endif /* defined (CRT_BEGIN) || defined (CRT_END) */
+
+/* dwarf2out will handle padding this data properly.  We definitely don't
+   want it 8-byte aligned on n32.  */
+#define EH_FRAME_SECTION_ASM_OP ".section\t.eh_frame,1,2,0,1"
+
+/* A default list of other sections which we might be "in" at any given
+   time.  For targets that use additional sections (e.g. .tdesc) you
+   should override this definition in the target-specific file which
+   includes this file.  */
+
+#undef EXTRA_SECTIONS
+#define EXTRA_SECTIONS in_sdata, in_rdata, in_const, in_ctors, in_dtors
+
+/* A default list of extra section function definitions.  For targets
+   that use additional sections (e.g. .tdesc) you should override this
+   definition in the target-specific file which includes this file.  */
+
+/* ??? rdata_section is now same as svr4 const_section.  */
+
+#undef EXTRA_SECTION_FUNCTIONS
+#define EXTRA_SECTION_FUNCTIONS						\
+void									\
+sdata_section ()							\
+{									\
+  if (in_section != in_sdata)						\
+    {									\
+      fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);		\
+      in_section = in_sdata;						\
+    }									\
+}									\
+									\
+void									\
+rdata_section ()							\
+{									\
+  if (in_section != in_rdata)						\
+    {									\
+      if (mips_abi != ABI_32 && mips_abi != ABI_O64)			\
+	fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP_64);	\
+      else								\
+	fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP_32);	\
+      in_section = in_rdata;						\
+    }									\
+}									\
+  CTORS_SECTION_FUNCTION						\
+  DTORS_SECTION_FUNCTION
+
+#define CTORS_SECTION_FUNCTION						\
+void									\
+ctors_section ()							\
+{									\
+  if (in_section != in_ctors)						\
+    {									\
+      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
+      in_section = in_ctors;						\
+    }									\
+}
+
+#define DTORS_SECTION_FUNCTION						\
+void									\
+dtors_section ()							\
+{									\
+  if (in_section != in_dtors)						\
+    {									\
+      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
+      in_section = in_dtors;						\
+    }									\
+}
+
+/* A C statement (sans semicolon) to output an element in the table of
+   global constructors.  */
+#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)				\
+  do {									\
+    ctors_section ();							\
+    fprintf (FILE, "\t%s\t ",						\
+	     TARGET_LONG64 ? ".dword" : ".word");			\
+    assemble_name (FILE, NAME);						\
+    fprintf (FILE, "\n");						\
+  } while (0)
+
+/* A C statement (sans semicolon) to output an element in the table of
+   global destructors.  */
+#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)       				\
+  do {									\
+    dtors_section ();                   				\
+    fprintf (FILE, "\t%s\t ",						\
+	     TARGET_LONG64 ? ".dword" : ".word");			\
+    assemble_name (FILE, NAME);              				\
+    fprintf (FILE, "\n");						\
+  } while (0)
+
+/* A C statement to output something to the assembler file to switch to section
+   NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
+   NULL_TREE.  */
+
+#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC)			\
+do {									\
+  extern FILE *asm_out_text_file;					\
+  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)			\
+    fprintf (asm_out_text_file, "\t.section %s,1,6,4,4\n", (NAME));	\
+  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))		\
+    fprintf (F, "\t.section %s,1,2,0,8\n", (NAME));			\
+  else									\
+    fprintf (F, "\t.section %s,1,3,0,8\n", (NAME));			\
+} while (0)
+
+/* Stuff for constructors.  End here.  */
+
+/* ??? Perhaps just include svr4.h in this file?  */
+
+/* ??? SGI assembler may core dump when compiling with -g.
+   Sometimes as succeeds, but then we get a linker error. (cmds.c in 072.sc)
+   Getting rid of .file solves both problems.  */
+#undef ASM_OUTPUT_FILENAME
+#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
+do								\
+  {								\
+    fprintf (STREAM, "\t#.file\t%d ", NUM_SOURCE_FILENAMES);	\
+    output_quoted_string (STREAM, NAME);			\
+    fputs ("\n", STREAM);					\
+  }								\
+while (0)
+
+/* ??? SGI assembler gives warning whenever .lcomm is used.  */
+#undef ASM_OUTPUT_LOCAL
+#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN)		   \
+do									   \
+  {									   \
+    if (mips_abi != ABI_32 && mips_abi != ABI_O64)			   \
+      {									   \
+	fprintf (STREAM, "%s\n", BSS_SECTION_ASM_OP);			   \
+	mips_declare_object (STREAM, NAME, "", ":\n", 0);		   \
+	ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT));	   \
+	ASM_OUTPUT_SKIP (STREAM, SIZE);					   \
+	fprintf (STREAM, "\t%s\n", POPSECTION_ASM_OP);			   \
+      }									   \
+    else								   \
+      mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE)); \
+  }									   \
+while (0)
+
+/* A C statement (sans semicolon) to output to the stdio stream
+   FILE the assembler definition of uninitialized global DECL named
+   NAME whose size is SIZE bytes and alignment is ALIGN bytes.
+   Try to use asm_output_aligned_bss to implement this macro.  */
+
+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
+  asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
+
+/* Write the extra assembler code needed to declare an object properly.  */
+
+#undef ASM_DECLARE_OBJECT_NAME
+#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL)			\
+do									\
+ {									\
+   size_directive_output = 0;						\
+   if (!flag_inhibit_size_directive && DECL_SIZE (DECL))	\
+     {									\
+       size_directive_output = 1;					\
+       fprintf (STREAM, "\t%s\t ", SIZE_ASM_OP);			\
+       assemble_name (STREAM, NAME);					\
+       fprintf (STREAM, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL)));	\
+     }									\
+   mips_declare_object (STREAM, NAME, "", ":\n", 0);			\
+ }									\
+while (0)
+
+/* Output the size directive for a decl in rest_of_decl_compilation
+   in the case where we did not do so before the initializer.
+   Once we find the error_mark_node, we know that the value of
+   size_directive_output was set
+   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
+
+#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
+do {									 \
+     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
+     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
+         && ! AT_END && TOP_LEVEL					 \
+	 && DECL_INITIAL (DECL) == error_mark_node			 \
+	 && !size_directive_output)					 \
+       {								 \
+	 size_directive_output = 1;					 \
+	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
+	 assemble_name (FILE, name);					 \
+	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
+       }								 \
+   } while (0)
+
+#undef LOCAL_LABEL_PREFIX
+#define LOCAL_LABEL_PREFIX ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
+			    ? "$" : ".")
+
+/* Profiling is supported via libprof1.a not -lc_p as in Irix 3.  */
+/* ??? If no mabi=X option give, but a mipsX option is, then should depend
+   on the mipsX option.  */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC \
+  "%{!static:%{!shared: \
+     %{mabi=32:%{pg:gcrt1.o%s} \
+       %{!pg:%{p:mcrt1.o%s libprof1.a%s}%{!p:crt1.o%s}}} \
+     %{mabi=n32: \
+       %{mips4:%{pg:/usr/lib32/mips4/gcrt1.o%s} \
+         %{!pg:%{p:/usr/lib32/mips4/mcrt1.o%s /usr/lib32/mips4/libprof1.a%s} \
+           %{!p:/usr/lib32/mips4/crt1.o%s}}} \
+       %{!mips4:%{pg:/usr/lib32/mips3/gcrt1.o%s} \
+         %{!pg:%{p:/usr/lib32/mips3/mcrt1.o%s /usr/lib32/mips3/libprof1.a%s} \
+           %{!p:/usr/lib32/mips3/crt1.o%s}}}} \
+     %{mabi=64: \
+       %{mips4:%{pg:/usr/lib64/mips4/gcrt1.o} \
+         %{!pg:%{p:/usr/lib64/mips4/mcrt1.o /usr/lib64/mips4/libprof1.a} \
+           %{!p:/usr/lib64/mips4/crt1.o}}} \
+       %{!mips4:%{pg:/usr/lib64/mips3/gcrt1.o} \
+         %{!pg:%{p:/usr/lib64/mips3/mcrt1.o /usr/lib64/mips3/libprof1.a} \
+           %{!p:/usr/lib64/mips3/crt1.o}}}} \
+     %{!mabi*: \
+       %{mips4:%{pg:/usr/lib32/mips4/gcrt1.o%s} \
+         %{!pg:%{p:/usr/lib32/mips4/mcrt1.o%s /usr/lib32/mips4/libprof1.a%s} \
+           %{!p:/usr/lib32/mips4/crt1.o%s}}} \
+       %{!mips4:%{pg:/usr/lib32/mips3/gcrt1.o%s} \
+         %{!pg:%{p:/usr/lib32/mips3/mcrt1.o%s /usr/lib32/mips3/libprof1.a%s} \
+           %{!p:/usr/lib32/mips3/crt1.o%s}}}}}} \
+   %{static: \
+     %{mabi=32:%{pg:/usr/lib/nonshared/gcrt1.o%s} \
+       %{!pg:%{p:/usr/lib/nonshared/mcrt1.o%s /usr/lib/nonshared/libprof1.a%s} \
+         %{!p:/usr/lib/nonshared/crt1.o%s}}} \
+     %{mabi=n32: \
+       %{mips4:%{pg:/usr/lib32/mips4/nonshared/gcrt1.o%s} \
+         %{!pg:%{p:/usr/lib32/mips4/nonshared/mcrt1.o%s \
+             /usr/lib32/mips4/nonshared/libprof1.a%s} \
+           %{!p:/usr/lib32/mips4/nonshared/crt1.o%s}}} \
+       %{!mips4:%{pg:/usr/lib32/mips3/nonshared/gcrt1.o%s} \
+         %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \
+             /usr/lib32/mips3/nonshared/libprof1.a%s} \
+           %{!p:/usr/lib32/mips3/nonshared/crt1.o%s}}}} \
+     %{mabi=64: \
+       %{mips4:%{pg:/usr/lib64/mips4/nonshared/gcrt1.o} \
+         %{!pg:%{p:/usr/lib64/mips4/nonshared/mcrt1.o \
+             /usr/lib64/mips4/nonshared/libprof1.a} \
+           %{!p:/usr/lib64/mips4/nonshared/crt1.o}}} \
+       %{!mips4:%{pg:/usr/lib64/mips3/nonshared/gcrt1.o} \
+         %{!pg:%{p:/usr/lib64/mips3/nonshared/mcrt1.o \
+             /usr/lib64/mips3/nonshared/libprof1.a} \
+           %{!p:/usr/lib64/mips3/nonshared/crt1.o}}}} \
+     %{!mabi*: \
+       %{mips4:%{pg:/usr/lib32/mips4/nonshared/gcrt1.o%s} \
+         %{!pg:%{p:/usr/lib32/mips4/nonshared/mcrt1.o%s \
+             /usr/lib32/mips4/nonshared/libprof1.a%s} \
+           %{!p:/usr/lib32/mips4/nonshared/crt1.o%s}}} \
+       %{!mips4:%{pg:/usr/lib32/mips3/nonshared/gcrt1.o%s} \
+         %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \
+           /usr/lib32/mips3/nonshared/libprof1.a%s} \
+         %{!pg:%{p:/usr/lib32/mips3/nonshared/mcrt1.o%s \
+             /usr/lib32/mips3/nonshared/libprof1.a%s} \
+           %{!p:/usr/lib32/mips3/nonshared/crt1.o%s}}}}}} \
+   crtbegin.o%s"
+
+#undef LIB_SPEC
+#define LIB_SPEC \
+  "%{mabi=n32: %{mips4:-L/usr/lib32/mips4} %{!mips4:-L/usr/lib32/mips3} \
+     -L/usr/lib32} \
+   %{mabi=64: %{mips4:-L/usr/lib64/mips4} %{!mips4:-L/usr/lib64/mips3} \
+     -L/usr/lib64} \
+   %{!mabi*: %{mips4:-L/usr/lib32/mips4} %{!mips4:-L/usr/lib32/mips3} \
+     -L/usr/lib32} \
+   %{!shared: \
+     -dont_warn_unused %{p:libprof1.a%s}%{pg:libprof1.a%s} -lc -warn_unused}"
+
+/* Avoid getting two warnings for libgcc.a everytime we link.  */
+#undef LIBGCC_SPEC
+#define LIBGCC_SPEC "-dont_warn_unused -lgcc -warn_unused"
+
+/* ??? If no mabi=X option give, but a mipsX option is, then should depend
+   on the mipsX option.  */
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC \
+  "crtend.o%s \
+   %{!shared: \
+     %{mabi=32:crtn.o%s}\
+     %{mabi=n32:%{mips4:/usr/lib32/mips4/crtn.o%s}\
+       %{!mips4:/usr/lib32/mips3/crtn.o%s}}\
+     %{mabi=64:%{mips4:/usr/lib64/mips4/crtn.o%s}\
+       %{!mips4:/usr/lib64/mips3/crtn.o%s}}\
+     %{!mabi*:%{mips4:/usr/lib32/mips4/crtn.o%s}\
+       %{!mips4:/usr/lib32/mips3/crtn.o%s}}}"
+
+/* ??? If no mabi=X option give, but a mipsX option is, then should depend
+   on the mipsX option.  */
+#undef LINK_SPEC
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
+%{bestGnum} %{shared} %{non_shared} \
+%{call_shared} %{no_archive} %{exact_version} %{w} \
+%{static: -non_shared} \
+%{!static: \
+  %{!shared: %{!non_shared: %{!call_shared: -call_shared -no_unresolved}}}} \
+%{rpath} -init __do_global_ctors -fini __do_global_dtors \
+%{shared:-hidden_symbol __do_global_ctors,__do_global_dtors,__EH_FRAME_BEGIN__,__frame_dummy} \
+-_SYSTYPE_SVR4 -woff 131 \
+%{mabi=32: -32}%{mabi=n32: -n32}%{mabi=64: -64}%{!mabi*: -n32}"
diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
new file mode 100755
index 0000000..f4ed424
--- /dev/null
+++ b/gcc/config/mips/linux.h
@@ -0,0 +1,99 @@
+/* Definitions for MIPS running Linux-based GNU systems with ELF format.
+   Copyright (C) 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Required to keep collect2.c happy */
+#undef OBJECT_FORMAT_COFF 
+
+#define HAVE_ATEXIT
+
+/* If we don't set MASK_ABICALLS, we can't default to PIC. */
+#undef TARGET_DEFAULT
+#define TARGET_DEFAULT (MASK_ABICALLS|MASK_GAS)
+
+
+/* Provide a STARTFILE_SPEC appropriate for GNU/Linux.  Here we add
+   the GNU/Linux magical crtbegin.o file (see crtstuff.c) which
+   provides part of the support for getting C++ file-scope static
+   object constructed before entering `main'. */
+
+#undef  STARTFILE_SPEC
+#define STARTFILE_SPEC \
+  "%{!shared: \
+     %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\
+   crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
+
+/* Provide a ENDFILE_SPEC appropriate for GNU/Linux.  Here we tack on
+   the GNU/Linux magical crtend.o file (see crtstuff.c) which
+   provides part of the support for getting C++ file-scope static
+   object constructed before entering `main', followed by a normal
+   GNU/Linux "finalizer" file, `crtn.o'.  */
+
+#undef  ENDFILE_SPEC
+#define ENDFILE_SPEC \
+  "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s"
+
+/* From iris5.h */
+/* -G is incompatible with -KPIC which is the default, so only allow objects
+   in the small data section if the user explicitly asks for it.  */
+#undef MIPS_DEFAULT_GVALUE
+#define MIPS_DEFAULT_GVALUE 0
+
+/* Borrowed from sparc/linux.h */
+#undef LINK_SPEC
+#define LINK_SPEC "-Y P,/usr/lib %{shared:-shared} \
+  %{!shared: \
+    %{!ibcs: \
+      %{!static: \
+        %{rdynamic:-export-dynamic} \
+        %{!dynamic-linker:-dynamic-linker /lib/ld.so.1}} \
+        %{static:-static}}}"
+
+
+#undef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC "-KPIC"
+
+/* Undefine the following which were defined in elf.h.  This will cause the linux
+   port to continue to use collect2 for constructors/destructors.  These may be removed
+   when .ctor/.dtor section support is desired. */
+
+#undef CTORS_SECTION_ASM_OP
+#undef DTORS_SECTION_ASM_OP
+
+#undef EXTRA_SECTIONS
+#define EXTRA_SECTIONS in_sdata, in_rdata
+
+#undef INVOKE__main
+#undef NAME__MAIN
+#undef SYMBOL__MAIN
+
+#undef EXTRA_SECTION_FUNCTIONS
+#define EXTRA_SECTION_FUNCTIONS                                         \
+  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP)
+
+#undef ASM_OUTPUT_CONSTRUCTOR
+#undef ASM_OUTPUT_DESTRUCTOR
+
+#undef CTOR_LIST_BEGIN
+#undef CTOR_LIST_END
+#undef DTOR_LIST_BEGIN
+#undef DTOR_LIST_END
+
+/*  End of undefines to turn off .ctor/.dtor section support */
diff --git a/gcc/config/mips/little.h b/gcc/config/mips/little.h
new file mode 100755
index 0000000..0ce01b4
--- /dev/null
+++ b/gcc/config/mips/little.h
@@ -0,0 +1,24 @@
+/* CYGNUS LOCAL: Entire file.  */
+
+/* Definitions of target machine for GNU compiler.
+   Little-endian flavor.
+   Copyright (c) 1997 Cygnus Support Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#define TARGET_ENDIAN_DEFAULT 0
+#define MULTILIB_ENDIAN_DEFAULT "EL"
diff --git a/gcc/config/mips/mips-5.h b/gcc/config/mips/mips-5.h
new file mode 100755
index 0000000..f8b0941
--- /dev/null
+++ b/gcc/config/mips/mips-5.h
@@ -0,0 +1,46 @@
+/* Definitions of target machine for GNU compiler.  MIPS RISC-OS 5.0
+   default version.
+   Copyright (C) 1992 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+%{call_shared} %{no_archive} %{exact_version} \
+%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}"
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s crtn.o%s}}"
+
+#include "mips/mips.h"
+
+/* Some assemblers have a bug that causes backslash escaped chars in .ascii
+   to be misassembled, so we just completely avoid it.  */
+#undef ASM_OUTPUT_ASCII
+#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
+do {							\
+  unsigned char *s;					\
+  int i;						\
+  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
+    {							\
+      if ((i % 8) == 0)					\
+	fputs ("\n\t.byte\t", (FILE));			\
+      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
+    }							\
+  fputs ("\n", (FILE));					\
+} while (0)
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
new file mode 100755
index 0000000..c4c217c
--- /dev/null
+++ b/gcc/config/mips/mips.c
@@ -0,0 +1,8711 @@
+/* Subroutines for insn-output.c for MIPS
+   Copyright (C) 1989, 90, 91, 93-97, 1998 Free Software Foundation, Inc.
+   Contributed by A. Lichnewsky, lich@inria.inria.fr.
+   Changes by Michael Meissner, meissner@osf.org.
+   64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+   Brendan Eich, brendan@microunity.com.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
+   calling convention in 64 bit mode.  It doesn't work though, and should
+   be replaced with something better designed.  */
+
+#include "config.h"
+#include "system.h"
+#include <signal.h>
+
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "insn-attr.h"
+#include "insn-codes.h"
+#include "recog.h"
+#include "toplev.h"
+
+#undef MAX			/* sys/param.h may also define these */
+#undef MIN
+
+#include "tree.h"
+#include "expr.h"
+#include "flags.h"
+#include "reload.h"
+#include "output.h"
+
+#if defined(USG) || !defined(HAVE_STAB_H)
+#include "gstab.h"  /* If doing DBX on sysV, use our own stab.h.  */
+#else
+#include <stab.h>  /* On BSD, use the system's stab.h.  */
+#endif /* not USG */
+
+#ifdef __GNU_STAB__
+#define STAB_CODE_TYPE enum __stab_debug_code
+#else
+#define STAB_CODE_TYPE int
+#endif
+
+extern char  *mktemp ();
+extern tree   lookup_name ();
+
+/* Enumeration for all of the relational tests, so that we can build
+   arrays indexed by the test type, and not worry about the order
+   of EQ, NE, etc. */
+
+enum internal_test {
+    ITEST_EQ,
+    ITEST_NE,
+    ITEST_GT,
+    ITEST_GE,
+    ITEST_LT,
+    ITEST_LE,
+    ITEST_GTU,
+    ITEST_GEU,
+    ITEST_LTU,
+    ITEST_LEU,
+    ITEST_MAX
+  };
+
+
+struct constant;
+static enum internal_test map_test_to_internal_test	PROTO ((enum rtx_code));
+static int mips16_simple_memory_operand		PROTO ((rtx, rtx,
+							enum machine_mode));
+static int m16_check_op				PROTO ((rtx, int, int, int));
+static void block_move_loop			PROTO ((rtx, rtx, int, int,
+							rtx, rtx));
+static void block_move_call			PROTO ((rtx, rtx, rtx));
+static FILE *make_temp_file			PROTO ((void));
+static void save_restore_insns			PROTO ((int, rtx,
+							long, FILE *));
+static void mips16_output_gp_offset		PROTO ((FILE *, rtx));
+static void mips16_fp_args			PROTO ((FILE *, int, int));
+static void build_mips16_function_stub		PROTO ((FILE *));
+static void mips16_optimize_gp			PROTO ((rtx));
+static rtx add_constant				PROTO ((struct constant **,
+							rtx,
+							enum machine_mode));
+static void dump_constants			PROTO ((struct constant *,
+							rtx));
+static rtx mips_find_symbol			PROTO ((rtx));
+
+
+/* Global variables for machine-dependent things.  */
+
+/* Threshold for data being put into the small data/bss area, instead
+   of the normal data area (references to the small data/bss area take
+   1 instruction, and use the global pointer, references to the normal
+   data area takes 2 instructions).  */
+int mips_section_threshold = -1;
+
+/* Count the number of .file directives, so that .loc is up to date.  */
+int num_source_filenames = 0;
+
+/* Count the number of sdb related labels are generated (to find block
+   start and end boundaries).  */
+int sdb_label_count = 0;
+
+/* Next label # for each statement for Silicon Graphics IRIS systems. */
+int sym_lineno = 0;
+
+/* Non-zero if inside of a function, because the stupid MIPS asm can't
+   handle .files inside of functions.  */
+int inside_function = 0;
+
+/* Files to separate the text and the data output, so that all of the data
+   can be emitted before the text, which will mean that the assembler will
+   generate smaller code, based on the global pointer.  */
+FILE *asm_out_data_file;
+FILE *asm_out_text_file;
+
+/* Linked list of all externals that are to be emitted when optimizing
+   for the global pointer if they haven't been declared by the end of
+   the program with an appropriate .comm or initialization.  */
+
+struct extern_list
+{
+  struct extern_list *next;	/* next external */
+  char *name;			/* name of the external */
+  int size;			/* size in bytes */
+} *extern_head = 0;
+
+/* Name of the file containing the current function.  */
+char *current_function_file = "";
+
+/* Warning given that Mips ECOFF can't support changing files
+   within a function.  */
+int file_in_function_warning = FALSE;
+
+/* Whether to suppress issuing .loc's because the user attempted
+   to change the filename within a function.  */
+int ignore_line_number = FALSE;
+
+/* Number of nested .set noreorder, noat, nomacro, and volatile requests.  */
+int set_noreorder;
+int set_noat;
+int set_nomacro;
+int set_volatile;
+
+/* The next branch instruction is a branch likely, not branch normal.  */
+int mips_branch_likely;
+
+/* Count of delay slots and how many are filled.  */
+int dslots_load_total;
+int dslots_load_filled;
+int dslots_jump_total;
+int dslots_jump_filled;
+
+/* # of nops needed by previous insn */
+int dslots_number_nops;
+
+/* Number of 1/2/3 word references to data items (ie, not jal's).  */
+int num_refs[3];
+
+/* registers to check for load delay */
+rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
+
+/* Cached operands, and operator to compare for use in set/branch on
+   condition codes.  */
+rtx branch_cmp[2];
+
+/* what type of branch to use */
+enum cmp_type branch_type;
+
+/* Number of previously seen half-pic pointers and references.  */
+static int prev_half_pic_ptrs = 0;
+static int prev_half_pic_refs = 0;
+
+/* which cpu are we scheduling for */
+enum processor_type mips_cpu;
+
+/* which instruction set architecture to use.  */
+int mips_isa;
+
+#ifdef MIPS_ABI_DEFAULT
+/* Which ABI to use.  This is defined to a constant in mips.h if the target
+   doesn't support multiple ABIs.  */
+int mips_abi;
+#endif
+
+/* Strings to hold which cpu and instruction set architecture to use.  */
+char *mips_cpu_string;		/* for -mcpu=<xxx> */
+char *mips_isa_string;		/* for -mips{1,2,3,4} */
+char *mips_abi_string;		/* for -mabi={32,n32,64,eabi} */
+
+/* Whether we are generating mips16 code.  This is a synonym for
+   TARGET_MIPS16, and exists for use as an attribute.  */
+int mips16;
+
+/* This variable is set by -mno-mips16.  We only care whether
+   -mno-mips16 appears or not, and using a string in this fashion is
+   just a way to avoid using up another bit in target_flags.  */
+char *mips_no_mips16_string;
+
+/* Whether we are generating mips16 hard float code.  In mips16 mode
+   we always set TARGET_SOFT_FLOAT; this variable is nonzero if
+   -msoft-float was not specified by the user, which means that we
+   should arrange to call mips32 hard floating point code.  */
+int mips16_hard_float;
+
+/* This variable is set by -mentry.  We only care whether -mentry
+   appears or not, and using a string in this fashion is just a way to
+   avoid using up another bit in target_flags.  */
+char *mips_entry_string;
+
+/* Whether we should entry and exit pseudo-ops in mips16 mode.  */
+int mips_entry;
+
+/* If TRUE, we split addresses into their high and low parts in the RTL.  */
+int mips_split_addresses;
+
+/* Generating calls to position independent functions?  */
+enum mips_abicalls_type mips_abicalls;
+
+/* High and low marks for floating point values which we will accept
+   as legitimate constants for LEGITIMATE_CONSTANT_P.  These are
+   initialized in override_options.  */
+REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
+
+/* Array giving truth value on whether or not a given hard register
+   can support a given mode.  */
+char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
+
+/* The mode that will be used to save a given gpr on the stack.  Note
+   the entry for $0 is special; it indicates the generic size of a gpr
+   save/restore by the prologue/epilogue and must be the maximum mode
+   ever used to save a GPR.  This is typically WORD_MODE.  */
+enum machine_mode mips_reg_mode[GP_REG_NUM];
+
+/* Current frame information calculated by compute_frame_size.  */
+struct mips_frame_info current_frame_info;
+
+/* Zero structure to initialize current_frame_info.  */
+struct mips_frame_info zero_frame_info;
+
+/* Temporary filename used to buffer .text until end of program
+   for -mgpopt.  */
+static char *temp_filename;
+
+/* Pseudo-reg holding the address of the current function when
+   generating embedded PIC code.  Created by LEGITIMIZE_ADDRESS, used
+   by mips_finalize_pic if it was created.  */
+rtx embedded_pic_fnaddr_rtx;
+
+/* The length of all strings seen when compiling for the mips16.  This
+   is used to tell how many strings are in the constant pool, so that
+   we can see if we may have an overflow.  This is reset each time the
+   constant pool is output.  */
+int mips_string_length;
+
+/* Pseudo-reg holding the value of $28 in a mips16 function which
+   refers to GP relative global variables.  */
+rtx mips16_gp_pseudo_rtx;
+
+/* In mips16 mode, we build a list of all the string constants we see
+   in a particular function.  */
+
+struct string_constant
+{
+  struct string_constant *next;
+  char *label;
+};
+
+static struct string_constant *string_constants;
+
+/* CYGNUS LOCAL law */
+/* Specify power of two alignment for loop starts, labels after barriers
+   and functions.  Also specify maximum fill/skip allowed to achieve those
+   alignments (in bytes).
+
+   These are strings filled in by the generic code with the user arguments,
+   they are parsed in OVERRIDE_OPTIONS, then never referenced again.  */
+char *mips_align_loops_string;
+char *mips_max_skip_loops_string;
+char *mips_align_jumps_string;
+char *mips_max_skip_jumps_string;
+char *mips_align_funcs_string;
+char *mips_max_skip_funcs_string;
+
+/* Specify power of two alignment for loop starts, labels after barriers
+   and functions.  Also specify maximum fill/skip allowed to achieve those
+   alignments (in bytes).
+
+   Once the above strings are parsed, the resulting values are placed in
+   these variables.  */
+int mips_align_loops;
+int mips_max_skip_loops;
+int mips_align_jumps;
+int mips_max_skip_jumps;
+int mips_align_funcs;
+int mips_max_skip_funcs;
+/* END CYGNUS LOCAL */
+
+/* List of all MIPS punctuation characters used by print_operand.  */
+char mips_print_operand_punct[256];
+
+/* Map GCC register number to debugger register number.  */
+int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
+
+/* Buffer to use to enclose a load/store operation with %{ %} to
+   turn on .set volatile.  */
+static char volatile_buffer[60];
+
+/* Hardware names for the registers.  If -mrnames is used, this
+   will be overwritten with mips_sw_reg_names.  */
+
+char mips_reg_names[][8] =
+{
+ "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
+ "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
+ "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
+ "$24",  "$25",  "$26",  "$27",  "$28",  "$sp",  "$fp",  "$31",
+ "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
+ "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
+ "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
+ "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
+ "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
+ "$fcc5","$fcc6","$fcc7","$rap"
+};
+
+/* Mips software names for the registers, used to overwrite the
+   mips_reg_names array.  */
+
+char mips_sw_reg_names[][8] =
+{
+  "$zero","$at",  "$v0",  "$v1",  "$a0",  "$a1",  "$a2",  "$a3",
+  "$t0",  "$t1",  "$t2",  "$t3",  "$t4",  "$t5",  "$t6",  "$t7",
+  "$s0",  "$s1",  "$s2",  "$s3",  "$s4",  "$s5",  "$s6",  "$s7",
+  "$t8",  "$t9",  "$k0",  "$k1",  "$gp",  "$sp",  "$fp",  "$ra",
+  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
+  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
+  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
+  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
+  "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
+  "$fcc5","$fcc6","$fcc7","$rap"
+};
+
+/* Map hard register number to register class */
+enum reg_class mips_regno_to_class[] =
+{
+  GR_REGS,	GR_REGS,	M16_NA_REGS,	M16_NA_REGS,
+  M16_REGS,	M16_REGS,	M16_REGS,	M16_REGS,
+  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,
+  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,
+  M16_NA_REGS,	M16_NA_REGS,	GR_REGS,	GR_REGS,
+  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,
+  T_REG,	GR_REGS,	GR_REGS,	GR_REGS,
+  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,
+  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
+  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
+  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
+  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
+  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
+  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
+  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
+  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,
+  HI_REG,	LO_REG,		HILO_REG,	ST_REGS,
+  ST_REGS,	ST_REGS,	ST_REGS,	ST_REGS,
+  ST_REGS,	ST_REGS,	ST_REGS,	GR_REGS
+};
+
+/* Map register constraint character to register class.  */
+enum reg_class mips_char_to_class[256] =
+{
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
+};
+
+
+/* Return truth value of whether OP can be used as an operands
+   where a register or 16 bit unsigned integer is needed.  */
+
+int
+uns_arith_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
+    return 1;
+
+  return register_operand (op, mode);
+}
+
+/* Return truth value of whether OP can be used as an operands
+   where a 16 bit integer is needed  */
+
+int
+arith_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
+    return 1;
+
+  /* On the mips16, a GP relative value is a signed 16 bit offset.  */
+  if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
+    return 1;
+
+  return register_operand (op, mode);
+}
+
+/* Return truth value of whether OP can be used as an operand in a two
+   address arithmetic insn (such as set 123456,%o4) of mode MODE.  */
+
+int
+arith32_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == CONST_INT)
+    return 1;
+
+  return register_operand (op, mode);
+}
+
+/* Return truth value of whether OP is a integer which fits in 16 bits  */
+
+int
+small_int (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
+}
+
+/* Return truth value of whether OP is a 32 bit integer which is too big to
+   be loaded with one instruction.  */
+
+int
+large_int (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  HOST_WIDE_INT value;
+
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+
+  value = INTVAL (op);
+
+  /* ior reg,$r0,value */
+  if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
+    return 0;
+
+  /* subu reg,$r0,value */
+  if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
+    return 0;
+
+  /* lui reg,value>>16 */
+  if ((value & 0x0000ffff) == 0)
+    return 0;
+
+  return 1;
+}
+
+/* Return truth value of whether OP is a register or the constant 0.
+   In mips16 mode, we only accept a register, since the mips16 does
+   not have $0.  */
+
+int
+reg_or_0_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  switch (GET_CODE (op))
+    {
+    case CONST_INT:
+      if (TARGET_MIPS16)
+	return 0;
+      return INTVAL (op) == 0;
+
+    case CONST_DOUBLE:
+      if (TARGET_MIPS16)
+	return 0;
+      return op == CONST0_RTX (mode);
+
+    case REG:
+    case SUBREG:
+      return register_operand (op, mode);
+
+    default:
+      break;
+    }
+
+  return 0;
+}
+
+
+/* Return truth value of whether OP is a register or the constant 0,
+   even in mips16 mode. */
+
+int
+true_reg_or_0_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  switch (GET_CODE (op))
+    {
+    case CONST_INT:
+      return INTVAL (op) == 0;
+
+    case CONST_DOUBLE:
+      return op == CONST0_RTX (mode);
+
+    case REG:
+    case SUBREG:
+      return register_operand (op, mode);
+
+    default:
+      break;
+    }
+
+  return 0;
+}
+
+/* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */
+
+int
+mips_const_double_ok (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  REAL_VALUE_TYPE d;
+
+  if (GET_CODE (op) != CONST_DOUBLE)
+    return 0;
+
+  if (mode == VOIDmode)
+    return 1;
+
+  if (mode != SFmode && mode != DFmode)
+    return 0;
+
+  if (op == CONST0_RTX (mode))
+    return 1;
+
+  /* ??? li.s does not work right with SGI's Irix 6 assembler.  */
+  if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
+    return 0;
+
+  REAL_VALUE_FROM_CONST_DOUBLE (d, op);
+
+  if (REAL_VALUE_ISNAN (d))
+    return FALSE;
+
+  if (REAL_VALUE_NEGATIVE (d))
+    d = REAL_VALUE_NEGATE (d);
+
+  if (mode == DFmode)
+    {
+      if (REAL_VALUES_LESS (d, dfhigh)
+	  && REAL_VALUES_LESS (dflow, d))
+	return 1;
+    }
+  else
+    {
+      if (REAL_VALUES_LESS (d, sfhigh)
+	  && REAL_VALUES_LESS (sflow, d))
+	return 1;
+    }
+
+  return 0;
+}
+
+/* Accept the floating point constant 1 in the appropriate mode.  */
+
+int
+const_float_1_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  REAL_VALUE_TYPE d;
+  static REAL_VALUE_TYPE onedf;
+  static REAL_VALUE_TYPE onesf;
+  static int one_initialized;
+
+  if (GET_CODE (op) != CONST_DOUBLE
+      || mode != GET_MODE (op)
+      || (mode != DFmode && mode != SFmode))
+    return 0;
+
+  REAL_VALUE_FROM_CONST_DOUBLE (d, op);
+
+  /* We only initialize these values if we need them, since we will
+     never get called unless mips_isa >= 4.  */
+  if (! one_initialized)
+    {
+      onedf = REAL_VALUE_ATOF ("1.0", DFmode);
+      onesf = REAL_VALUE_ATOF ("1.0", SFmode);
+      one_initialized = 1;
+    }
+
+  if (mode == DFmode)
+    return REAL_VALUES_EQUAL (d, onedf);
+  else
+    return REAL_VALUES_EQUAL (d, onesf);
+}
+
+/* Return true if a memory load or store of REG plus OFFSET in MODE
+   can be represented in a single word on the mips16.  */
+
+static int
+mips16_simple_memory_operand (reg, offset, mode)
+     rtx reg;
+     rtx offset;
+     enum machine_mode mode;
+{
+  int size, off;
+
+  if (mode == BLKmode)
+    {
+      /* We can't tell, because we don't know how the value will
+         eventually be accessed.  Returning 0 here does no great
+         harm; it just prevents some possible instruction scheduling.  */
+      return 0;
+    }
+
+  size = GET_MODE_SIZE (mode);
+
+  if (INTVAL (offset) % size != 0)
+    return 0;
+  if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
+    off = 0x100;
+  else
+    off = 0x20;
+  if (INTVAL (offset) >= 0 && INTVAL (offset) < off * size)
+    return 1;
+  return 0;
+}
+
+/* Return truth value if a memory operand fits in a single instruction
+   (ie, register + small offset).  */
+
+int
+simple_memory_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  rtx addr, plus0, plus1;
+
+  /* Eliminate non-memory operations */
+  if (GET_CODE (op) != MEM)
+    return 0;
+
+  /* dword operations really put out 2 instructions, so eliminate them.  */
+  /* ??? This isn't strictly correct.  It is OK to accept multiword modes
+     here, since the length attributes are being set correctly, but only
+     if the address is offsettable.  LO_SUM is not offsettable.  */
+  if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
+    return 0;
+
+  /* Decode the address now.  */
+  addr = XEXP (op, 0);
+  switch (GET_CODE (addr))
+    {
+    case REG:
+    case LO_SUM:
+      return 1;
+
+    case CONST_INT:
+      if (TARGET_MIPS16)
+	return 0;
+      return SMALL_INT (op);
+
+    case PLUS:
+      plus0 = XEXP (addr, 0);
+      plus1 = XEXP (addr, 1);
+      if (GET_CODE (plus0) == REG
+	  && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
+	  && (! TARGET_MIPS16
+	      || mips16_simple_memory_operand (plus0, plus1, mode)))
+	return 1;
+
+      else if (GET_CODE (plus1) == REG
+	       && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
+	       && (! TARGET_MIPS16
+		   || mips16_simple_memory_operand (plus1, plus0, mode)))
+	return 1;
+
+      else
+	return 0;
+
+#if 0
+      /* We used to allow small symbol refs here (ie, stuff in .sdata
+	 or .sbss), but this causes some bugs in G++.  Also, it won't
+	 interfere if the MIPS linker rewrites the store instruction
+	 because the function is PIC.  */
+
+    case LABEL_REF:		/* never gp relative */
+      break;
+
+    case CONST:
+      /* If -G 0, we can never have a GP relative memory operation.
+	 Also, save some time if not optimizing.  */
+      if (!TARGET_GP_OPT)
+	return 0;
+
+      {
+	rtx offset = const0_rtx;
+	addr = eliminate_constant_term (XEXP (addr, 0), &offset);
+	if (GET_CODE (op) != SYMBOL_REF)
+	  return 0;
+
+	/* let's be paranoid.... */
+	if (! SMALL_INT (offset))
+	  return 0;
+      }
+
+      /* fall through */
+
+    case SYMBOL_REF:
+      return SYMBOL_REF_FLAG (addr);
+#endif
+
+      /* This SYMBOL_REF case is for the mips16.  If the above case is
+         reenabled, this one should be merged in.  */
+    case SYMBOL_REF:
+      /* References to the constant pool on the mips16 use a small
+         offset if the function is small.  The only time we care about
+         getting this right is during delayed branch scheduling, so
+         don't need to check until then.  The machine_dependent_reorg
+         function will set the total length of the instructions used
+         in the function in current_frame_info.  If that is small
+         enough, we know for sure that this is a small offset.  It
+         would be better if we could take into account the location of
+         the instruction within the function, but we can't, because we
+         don't know where we are.  */
+      if (TARGET_MIPS16
+	  && CONSTANT_POOL_ADDRESS_P (addr)
+	  && current_frame_info.insns_len > 0)
+	{
+	  long size;
+
+	  size = current_frame_info.insns_len + get_pool_size ();
+	  if (GET_MODE_SIZE (mode) == 4)
+	    return size < 4 * 0x100;
+	  else if (GET_MODE_SIZE (mode) == 8)
+	    return size < 8 * 0x20;
+	  else
+	    return 0;
+	}
+
+      return 0;
+
+    default:
+      break;
+    }
+
+  return 0;
+}
+
+/* Return nonzero for a memory address that can be used to load or store
+   a doubleword.  */
+
+int
+double_memory_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  rtx addr;
+
+  if (GET_CODE (op) != MEM
+      || ! memory_operand (op, mode))
+    {
+      /* During reload, we accept a pseudo register if it has an
+	 appropriate memory address.  If we don't do this, we will
+	 wind up reloading into a register, and then reloading that
+	 register from memory, when we could just reload directly from
+	 memory.  */
+      if (reload_in_progress
+	  && GET_CODE (op) == REG
+	  && REGNO (op) >= FIRST_PSEUDO_REGISTER
+	  && reg_renumber[REGNO (op)] < 0
+	  && reg_equiv_mem[REGNO (op)] != 0
+	  && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
+	return 1;
+
+      /* All reloaded addresses are valid in TARGET_64BIT mode.  This is
+	 the same test performed for 'm' in find_reloads.  */
+
+      if (reload_in_progress
+	  && TARGET_64BIT
+	  && (GET_CODE (op) == MEM
+	      || (GET_CODE (op) == REG
+		  && REGNO (op) >= FIRST_PSEUDO_REGISTER
+		  && reg_renumber[REGNO (op)] < 0)))
+	return 1;
+
+      if (reload_in_progress
+	  && TARGET_MIPS16
+	  && GET_CODE (op) == MEM)
+	{
+	  rtx addr;
+
+	  addr = XEXP (op, 0);
+
+	  /* During reload on the mips16, we accept a large offset
+	     from the frame pointer or the stack pointer.  This large
+	     address will get reloaded anyhow.  */
+	  if (GET_CODE (addr) == PLUS
+	      && GET_CODE (XEXP (addr, 0)) == REG
+	      && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
+		  || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
+	      && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
+		   && ! SMALL_INT (XEXP (addr, 1)))
+		  || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
+		      && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
+	    return 1;
+
+	  /* Similarly, we accept a case where the memory address is
+             itself on the stack, and will be reloaded. */
+	  if (GET_CODE (addr) == MEM)
+	    {
+	      rtx maddr;
+
+	      maddr = XEXP (addr, 0);
+	      if (GET_CODE (maddr) == PLUS
+		  && GET_CODE (XEXP (maddr, 0)) == REG
+		  && (REGNO (XEXP (maddr, 0)) == HARD_FRAME_POINTER_REGNUM
+		      || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
+		  && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
+		       && ! SMALL_INT (XEXP (maddr, 1)))
+		      || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
+			  && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
+		return 1;
+	    }
+
+	  /* We also accept the same case when we have a 16 bit signed
+	     offset mixed in as well.  The large address will get
+	     reloaded, and the 16 bit offset will be OK.  */
+	  if (GET_CODE (addr) == PLUS
+	      && GET_CODE (XEXP (addr, 0)) == MEM
+	      && GET_CODE (XEXP (addr, 1)) == CONST_INT
+	      && SMALL_INT (XEXP (addr, 1)))
+	    {
+	      addr = XEXP (XEXP (addr, 0), 0);
+	      if (GET_CODE (addr) == PLUS
+		  && GET_CODE (XEXP (addr, 0)) == REG
+		  && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
+		      || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
+		  && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
+		       && ! SMALL_INT (XEXP (addr, 1)))
+		      || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
+			  && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
+		return 1;
+	    }
+	}
+
+      return 0;
+    }
+
+  if (TARGET_64BIT)
+    {
+      /* In this case we can use an instruction like sd.  */
+      return 1;
+    }
+
+  /* Make sure that 4 added to the address is a valid memory address.
+     This essentially just checks for overflow in an added constant.  */
+
+  addr = XEXP (op, 0);
+
+  if (CONSTANT_ADDRESS_P (addr))
+    return 1;
+
+  return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
+			    ? SImode
+			    : SFmode),
+			   plus_constant_for_output (addr, 4));
+}
+
+/* Return nonzero if the code of this rtx pattern is EQ or NE.  */
+
+int
+equality_op (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (mode != GET_MODE (op))
+    return 0;
+
+  return GET_CODE (op) == EQ || GET_CODE (op) == NE;
+}
+
+/* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
+
+int
+cmp_op (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (mode != GET_MODE (op))
+    return 0;
+
+  return GET_RTX_CLASS (GET_CODE (op)) == '<';
+}
+
+/* Return nonzero if the operand is either the PC or a label_ref.  */
+
+int
+pc_or_label_operand (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  if (op == pc_rtx)
+    return 1;
+
+  if (GET_CODE (op) == LABEL_REF)
+    return 1;
+
+  return 0;
+}
+
+/* Test for a valid operand for a call instruction.
+   Don't allow the arg pointer register or virtual regs
+   since they may change into reg + const, which the patterns
+   can't handle yet.  */
+
+int
+call_insn_operand (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return (CONSTANT_ADDRESS_P (op)
+	  || (GET_CODE (op) == REG && op != arg_pointer_rtx
+	      && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
+		    && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
+}
+
+/* Return nonzero if OPERAND is valid as a source operand for a move
+   instruction.  */
+
+int
+move_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  /* Accept any general operand after reload has started; doing so
+     avoids losing if reload does an in-place replacement of a register
+     with a SYMBOL_REF or CONST.  */
+  return (general_operand (op, mode)
+	  && (! (mips_split_addresses && mips_check_split (op, mode))
+	      || reload_in_progress || reload_completed)
+	  && ! (TARGET_MIPS16
+		&& GET_CODE (op) == SYMBOL_REF
+		&& ! mips16_constant (op, mode, 1, 0)));
+}
+
+/* Return nonzero if OPERAND is valid as a source operand for movdi.
+   This accepts not only general_operand, but also sign extended
+   constants and registers.  We need to accept sign extended constants
+   in case a sign extended register which is used in an expression,
+   and is equivalent to a constant, is spilled.  */
+
+int
+movdi_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (TARGET_64BIT
+      && mode == DImode
+      && GET_CODE (op) == SIGN_EXTEND
+      && GET_MODE (op) == DImode
+      && (GET_MODE (XEXP (op, 0)) == SImode
+	  || (GET_CODE (XEXP (op, 0)) == CONST_INT
+	      && GET_MODE (XEXP (op, 0)) == VOIDmode))
+      && (register_operand (XEXP (op, 0), SImode)
+	  || immediate_operand (XEXP (op, 0), SImode)))
+    return 1;
+
+  return (general_operand (op, mode)
+	  && ! (TARGET_MIPS16
+		&& GET_CODE (op) == SYMBOL_REF
+		&& ! mips16_constant (op, mode, 1, 0)));
+}
+
+/* Like register_operand, but when in 64 bit mode also accept a sign
+   extend of a 32 bit register, since the value is known to be already
+   sign extended.  */
+
+int
+se_register_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (TARGET_64BIT
+      && mode == DImode
+      && GET_CODE (op) == SIGN_EXTEND
+      && GET_MODE (op) == DImode
+      && GET_MODE (XEXP (op, 0)) == SImode
+      && register_operand (XEXP (op, 0), SImode))
+    return 1;
+
+  return register_operand (op, mode);
+}
+
+/* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
+   extend of a 32 bit register, since the value is known to be already
+   sign extended.  */
+
+int
+se_reg_or_0_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (TARGET_64BIT
+      && mode == DImode
+      && GET_CODE (op) == SIGN_EXTEND
+      && GET_MODE (op) == DImode
+      && GET_MODE (XEXP (op, 0)) == SImode
+      && register_operand (XEXP (op, 0), SImode))
+    return 1;
+
+  return reg_or_0_operand (op, mode);
+}
+
+/* Like uns_arith_operand, but when in 64 bit mode also accept a sign
+   extend of a 32 bit register, since the value is known to be already
+   sign extended.  */
+
+int
+se_uns_arith_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (TARGET_64BIT
+      && mode == DImode
+      && GET_CODE (op) == SIGN_EXTEND
+      && GET_MODE (op) == DImode
+      && GET_MODE (XEXP (op, 0)) == SImode
+      && register_operand (XEXP (op, 0), SImode))
+    return 1;
+
+  return uns_arith_operand (op, mode);
+}
+
+/* Like arith_operand, but when in 64 bit mode also accept a sign
+   extend of a 32 bit register, since the value is known to be already
+   sign extended.  */
+
+int
+se_arith_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (TARGET_64BIT
+      && mode == DImode
+      && GET_CODE (op) == SIGN_EXTEND
+      && GET_MODE (op) == DImode
+      && GET_MODE (XEXP (op, 0)) == SImode
+      && register_operand (XEXP (op, 0), SImode))
+    return 1;
+
+  return arith_operand (op, mode);
+}
+
+/* Like nonmemory_operand, but when in 64 bit mode also accept a sign
+   extend of a 32 bit register, since the value is known to be already
+   sign extended.  */
+
+int
+se_nonmemory_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (TARGET_64BIT
+      && mode == DImode
+      && GET_CODE (op) == SIGN_EXTEND
+      && GET_MODE (op) == DImode
+      && GET_MODE (XEXP (op, 0)) == SImode
+      && register_operand (XEXP (op, 0), SImode))
+    return 1;
+
+  return nonmemory_operand (op, mode);
+}
+
+/* Like nonimmediate_operand, but when in 64 bit mode also accept a
+   sign extend of a 32 bit register, since the value is known to be
+   already sign extended.  */
+
+int
+se_nonimmediate_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (TARGET_64BIT
+      && mode == DImode
+      && GET_CODE (op) == SIGN_EXTEND
+      && GET_MODE (op) == DImode
+      && GET_MODE (XEXP (op, 0)) == SImode
+      && register_operand (XEXP (op, 0), SImode))
+    return 1;
+
+  return nonimmediate_operand (op, mode);
+}
+
+/* Accept any operand that can appear in a mips16 constant table
+   instruction.  We can't use any of the standard operand functions
+   because for these instructions we accept values that are not
+   accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs.  */
+
+int
+consttable_operand (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return CONSTANT_P (op);
+}
+
+/* Return nonzero if we split the address into high and low parts.  */
+
+/* ??? We should also handle reg+array somewhere.  We get four
+   instructions currently, lui %hi/addui %lo/addui reg/lw.  Better is
+   lui %hi/addui reg/lw %lo.  Fixing GO_IF_LEGITIMATE_ADDRESS to accept
+   (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
+   out of the address, then we have 4 instructions to combine.  Perhaps
+   add a 3->2 define_split for combine.  */
+
+/* ??? We could also split a CONST_INT here if it is a large_int().
+   However, it doesn't seem to be very useful to have %hi(constant).
+   We would be better off by doing the masking ourselves and then putting
+   the explicit high part of the constant in the RTL.  This will give better
+   optimization.  Also, %hi(constant) needs assembler changes to work.
+   There is already a define_split that does this.  */
+
+int
+mips_check_split (address, mode)
+     rtx address;
+     enum machine_mode mode;
+{     
+  /* ??? This is the same check used in simple_memory_operand.
+     We use it here because LO_SUM is not offsettable.  */
+  if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+    return 0;
+
+  if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
+      || (GET_CODE (address) == CONST
+	  && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
+	  && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
+      || GET_CODE (address) == LABEL_REF)
+    return 1;
+
+  return 0;
+}
+
+/* We need a lot of little routines to check constant values on the
+   mips16.  These are used to figure out how long the instruction will
+   be.  It would be much better to do this using constraints, but
+   there aren't nearly enough letters available.  */
+
+static int
+m16_check_op (op, low, high, mask)
+     rtx op;
+     int low;
+     int high;
+     int mask;
+{
+  return (GET_CODE (op) == CONST_INT
+	  && INTVAL (op) >= low
+	  && INTVAL (op) <= high
+	  && (INTVAL (op) & mask) == 0);
+}
+
+int
+m16_uimm3_b (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, 0x1, 0x8, 0);
+}
+
+int
+m16_simm4_1 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, - 0x8, 0x7, 0);
+}
+
+int
+m16_nsimm4_1 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, - 0x7, 0x8, 0);
+}
+
+int
+m16_simm5_1 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, - 0x10, 0xf, 0);
+}
+
+int
+m16_nsimm5_1 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, - 0xf, 0x10, 0);
+}
+
+int
+m16_uimm5_4 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
+}
+
+int
+m16_nuimm5_4 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
+}
+
+int
+m16_simm8_1 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, - 0x80, 0x7f, 0);
+}
+
+int
+m16_nsimm8_1 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, - 0x7f, 0x80, 0);
+}
+
+int
+m16_uimm8_1 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, 0x0, 0xff, 0);
+}
+
+int
+m16_nuimm8_1 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, - 0xff, 0x0, 0);
+}
+
+int
+m16_uimm8_m1_1 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, - 0x1, 0xfe, 0);
+}
+
+int
+m16_uimm8_4 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, 0x0, 0xff << 2, 3);
+}
+
+int
+m16_nuimm8_4 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
+}
+
+int
+m16_simm8_8 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
+}
+
+int
+m16_nsimm8_8 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
+}
+
+/* References to the string table on the mips16 only use a small
+   offset if the function is small.  See the comment in the SYMBOL_REF
+   case in simple_memory_operand.  We can't check for LABEL_REF here,
+   because the offset is always large if the label is before the
+   referencing instruction.  */
+
+int
+m16_usym8_4 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  if (GET_CODE (op) == SYMBOL_REF
+      && SYMBOL_REF_FLAG (op)
+      && current_frame_info.insns_len > 0
+      && XSTR (op, 0)[0] == '*'
+      && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
+		  sizeof LOCAL_LABEL_PREFIX - 1) == 0
+      && (current_frame_info.insns_len + get_pool_size () + mips_string_length
+	  < 4 * 0x100))
+    {
+      struct string_constant *l;
+
+      /* Make sure this symbol is on thelist of string constants to be
+         output for this function.  It is possible that it has already
+         been output, in which case this requires a large offset.  */
+      for (l = string_constants; l != NULL; l = l->next)
+	if (strcmp (l->label, XSTR (op, 0)) == 0)
+	  return 1;
+    }
+
+  return 0;
+}
+
+int
+m16_usym5_4 (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  if (GET_CODE (op) == SYMBOL_REF
+      && SYMBOL_REF_FLAG (op)
+      && current_frame_info.insns_len > 0
+      && XSTR (op, 0)[0] == '*'
+      && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
+		  sizeof LOCAL_LABEL_PREFIX - 1) == 0
+      && (current_frame_info.insns_len + get_pool_size () + mips_string_length
+	  < 4 * 0x20))
+    {
+      struct string_constant *l;
+
+      /* Make sure this symbol is on thelist of string constants to be
+         output for this function.  It is possible that it has already
+         been output, in which case this requires a large offset.  */
+      for (l = string_constants; l != NULL; l = l->next)
+	if (strcmp (l->label, XSTR (op, 0)) == 0)
+	  return 1;
+    }
+
+  return 0;
+}
+
+/* Returns an operand string for the given instruction's delay slot,
+   after updating filled delay slot statistics.
+
+   We assume that operands[0] is the target register that is set.
+
+   In order to check the next insn, most of this functionality is moved
+   to FINAL_PRESCAN_INSN, and we just set the global variables that
+   it needs.  */
+
+/* ??? This function no longer does anything useful, because final_prescan_insn
+   now will never emit a nop.  */
+
+char *
+mips_fill_delay_slot (ret, type, operands, cur_insn)
+     char *ret;			/* normal string to return */
+     enum delay_type type;	/* type of delay */
+     rtx operands[];		/* operands to use */
+     rtx cur_insn;		/* current insn */
+{
+  register rtx set_reg;
+  register enum machine_mode mode;
+  register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
+  register int num_nops;
+
+  if (type == DELAY_LOAD || type == DELAY_FCMP)
+    num_nops = 1;
+
+  else if (type == DELAY_HILO)
+    num_nops = 2;
+
+
+  else
+    num_nops = 0;
+
+  /* Make sure that we don't put nop's after labels.  */
+  next_insn = NEXT_INSN (cur_insn);
+  while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
+    next_insn = NEXT_INSN (next_insn);
+
+  dslots_load_total += num_nops;
+  if (TARGET_DEBUG_F_MODE
+      || !optimize
+      || type == DELAY_NONE
+      || operands == 0
+      || cur_insn == 0
+      || next_insn == 0
+      || GET_CODE (next_insn) == CODE_LABEL
+      || (set_reg = operands[0]) == 0)
+    {
+      dslots_number_nops = 0;
+      mips_load_reg  = 0;
+      mips_load_reg2 = 0;
+      mips_load_reg3 = 0;
+      mips_load_reg4 = 0;
+      return ret;
+    }
+
+  set_reg = operands[0];
+  if (set_reg == 0)
+    return ret;
+
+  while (GET_CODE (set_reg) == SUBREG)
+    set_reg = SUBREG_REG (set_reg);
+
+  mode = GET_MODE (set_reg);
+  dslots_number_nops = num_nops;
+  mips_load_reg = set_reg;
+  if (GET_MODE_SIZE (mode)
+      > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
+    mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1);
+  else
+    mips_load_reg2 = 0;
+
+  if (type == DELAY_HILO)
+    {
+      mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST);
+      mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1);
+    }
+  else
+    {
+      mips_load_reg3 = 0;
+      mips_load_reg4 = 0;
+    }
+
+  return ret;
+}
+
+
+/* Determine whether a memory reference takes one (based off of the GP
+   pointer), two (normal), or three (label + reg) instructions, and bump the
+   appropriate counter for -mstats.  */
+
+void
+mips_count_memory_refs (op, num)
+     rtx op;
+     int num;
+{
+  int additional = 0;
+  int n_words = 0;
+  rtx addr, plus0, plus1;
+  enum rtx_code code0, code1;
+  int looping;
+
+  if (TARGET_DEBUG_B_MODE)
+    {
+      fprintf (stderr, "\n========== mips_count_memory_refs:\n");
+      debug_rtx (op);
+    }
+
+  /* Skip MEM if passed, otherwise handle movsi of address.  */
+  addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
+
+  /* Loop, going through the address RTL.  */
+  do
+    {
+      looping = FALSE;
+      switch (GET_CODE (addr))
+	{
+	case REG:
+	case CONST_INT:
+	case LO_SUM:
+	  break;
+
+	case PLUS:
+	  plus0 = XEXP (addr, 0);
+	  plus1 = XEXP (addr, 1);
+	  code0 = GET_CODE (plus0);
+	  code1 = GET_CODE (plus1);
+
+	  if (code0 == REG)
+	    {
+	      additional++;
+	      addr = plus1;
+	      looping = 1;
+	      continue;
+	    }
+
+	  if (code0 == CONST_INT)
+	    {
+	      addr = plus1;
+	      looping = 1;
+	      continue;
+	    }
+
+	  if (code1 == REG)
+	    {
+	      additional++;
+	      addr = plus0;
+	      looping = 1;
+	      continue;
+	    }
+
+	  if (code1 == CONST_INT)
+	    {
+	      addr = plus0;
+	      looping = 1;
+	      continue;
+	    }
+
+	  if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
+	    {
+	      addr = plus0;
+	      looping = 1;
+	      continue;
+	    }
+
+	  if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
+	    {
+	      addr = plus1;
+	      looping = 1;
+	      continue;
+	    }
+
+	  break;
+
+	case LABEL_REF:
+	  n_words = 2;		/* always 2 words */
+	  break;
+
+	case CONST:
+	  addr = XEXP (addr, 0);
+	  looping = 1;
+	  continue;
+
+	case SYMBOL_REF:
+	  n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
+	  break;
+
+	default:
+	  break;
+	}
+    }
+  while (looping);
+
+  if (n_words == 0)
+    return;
+
+  n_words += additional;
+  if (n_words > 3)
+    n_words = 3;
+
+  num_refs[n_words-1] += num;
+}
+
+
+/* Return RTL for the offset from the current function to the argument.
+
+   ??? Which argument is this?  */
+
+rtx
+embedded_pic_offset (x)
+     rtx x;
+{
+  if (embedded_pic_fnaddr_rtx == NULL)
+    {
+      rtx seq;
+
+      embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
+      
+      /* Output code at function start to initialize the pseudo-reg.  */
+      /* ??? We used to do this in FINALIZE_PIC, but that does not work for
+	 inline functions, because it is called after RTL for the function
+	 has been copied.  The pseudo-reg in embedded_pic_fnaddr_rtx however
+	 does not get copied, and ends up not matching the rest of the RTL.
+	 This solution works, but means that we get unnecessary code to
+	 initialize this value every time a function is inlined into another
+	 function.  */
+      start_sequence ();
+      emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
+				 XEXP (DECL_RTL (current_function_decl), 0)));
+      seq = gen_sequence ();
+      end_sequence ();
+      push_topmost_sequence ();
+      emit_insn_after (seq, get_insns ());
+      pop_topmost_sequence ();
+    }
+
+  return gen_rtx (CONST, Pmode,
+		  gen_rtx (MINUS, Pmode, x,
+			   XEXP (DECL_RTL (current_function_decl), 0)));
+}
+
+/* Return the appropriate instructions to move one operand to another.  */
+
+char *
+mips_move_1word (operands, insn, unsignedp)
+     rtx operands[];
+     rtx insn;
+     int unsignedp;
+{
+  char *ret = 0;
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  enum rtx_code code0 = GET_CODE (op0);
+  enum rtx_code code1 = GET_CODE (op1);
+  enum machine_mode mode = GET_MODE (op0);
+  int subreg_word0 = 0;
+  int subreg_word1 = 0;
+  enum delay_type delay = DELAY_NONE;
+
+  while (code0 == SUBREG)
+    {
+      subreg_word0 += SUBREG_WORD (op0);
+      op0 = SUBREG_REG (op0);
+      code0 = GET_CODE (op0);
+    }
+
+  while (code1 == SUBREG)
+    {
+      subreg_word1 += SUBREG_WORD (op1);
+      op1 = SUBREG_REG (op1);
+      code1 = GET_CODE (op1);
+    }
+
+  /* For our purposes, a condition code mode is the same as SImode.  */
+  if (mode == CCmode)
+    mode = SImode;
+
+  if (code0 == REG)
+    {
+      int regno0 = REGNO (op0) + subreg_word0;
+
+      if (code1 == REG)
+	{
+	  int regno1 = REGNO (op1) + subreg_word1;
+
+	  /* Just in case, don't do anything for assigning a register
+	     to itself, unless we are filling a delay slot.  */
+	  if (regno0 == regno1 && set_nomacro == 0)
+	    ret = "";
+
+	  else if (GP_REG_P (regno0))
+	    {
+	      if (GP_REG_P (regno1))
+		ret = "move\t%0,%1";
+
+	      else if (MD_REG_P (regno1))
+		{
+		  delay = DELAY_HILO;
+		  if (regno1 != HILO_REGNUM)
+		    ret = "mf%1\t%0";
+		  else
+		    ret = "mflo\t%0";
+		}
+
+
+	      else if (ST_REG_P (regno1) && mips_isa >= 4)
+		ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
+
+	      else
+		{
+		  delay = DELAY_LOAD;
+		  if (FP_REG_P (regno1))
+		    ret = "mfc1\t%0,%1";
+
+		  else if (regno1 == FPSW_REGNUM && mips_isa < 4)
+		    ret = "cfc1\t%0,$31";
+		}
+	    }
+
+	  else if (FP_REG_P (regno0))
+	    {
+	      if (GP_REG_P (regno1))
+		{
+		  delay = DELAY_LOAD;
+		  ret = "mtc1\t%1,%0";
+		}
+
+	      if (FP_REG_P (regno1))
+		ret = "mov.s\t%0,%1";
+	    }
+
+	  else if (MD_REG_P (regno0))
+	    {
+	      if (GP_REG_P (regno1))
+		{
+		  delay = DELAY_HILO;
+		  if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
+		    ret = "mt%0\t%1";
+		}
+	    }
+
+
+	  else if (regno0 == FPSW_REGNUM && mips_isa < 4)
+	    {
+	      if (GP_REG_P (regno1))
+		{
+		  delay = DELAY_LOAD;
+		  ret = "ctc1\t%0,$31";
+		}
+	    }
+	}
+
+      else if (code1 == MEM)
+	{
+	  delay = DELAY_LOAD;
+
+	  if (TARGET_STATS)
+	    mips_count_memory_refs (op1, 1);
+
+	  if (GP_REG_P (regno0))
+	    {
+	      /* For loads, use the mode of the memory item, instead of the
+		 target, so zero/sign extend can use this code as well.  */
+	      switch (GET_MODE (op1))
+		{
+		default:
+		  break;
+		case SFmode:
+		  ret = "lw\t%0,%1";
+		  break;
+		case SImode:
+		case CCmode:
+		  ret = ((unsignedp && TARGET_64BIT)
+			 ? "lwu\t%0,%1"
+			 : "lw\t%0,%1");
+		  break;
+		case HImode:
+		  ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
+		  break;
+		case QImode:
+		  ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
+		  break;
+		}
+	    }
+
+	  else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
+	    ret = "l.s\t%0,%1";
+
+	  if (ret != (char *)0 && MEM_VOLATILE_P (op1))
+	    {
+	      size_t i = strlen (ret);
+	      if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
+		abort ();
+
+	      sprintf (volatile_buffer, "%%{%s%%}", ret);
+	      ret = volatile_buffer;
+	    }
+	}
+
+      else if (code1 == CONST_INT
+	       || (code1 == CONST_DOUBLE
+		   && GET_MODE (op1) == VOIDmode))
+	{
+	  if (code1 == CONST_DOUBLE)
+	    {
+	      /* This can happen when storing constants into long long
+                 bitfields.  Just store the least significant word of
+                 the value.  */
+	      operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
+	    }
+
+	  if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
+	    {
+	      if (GP_REG_P (regno0))
+		ret = "move\t%0,%z1";
+
+	      else if (FP_REG_P (regno0))
+		{
+		  delay = DELAY_LOAD;
+		  ret = "mtc1\t%z1,%0";
+		}
+
+	      else if (MD_REG_P (regno0))
+		{
+		  delay = DELAY_HILO;
+		  ret = "mt%0\t%.";
+		}
+
+	    }
+
+	  else if (GP_REG_P (regno0))
+	    {
+	      /* Don't use X format, because that will give out of
+		 range numbers for 64 bit host and 32 bit target.  */
+	      if (! TARGET_MIPS16)
+		ret = "li\t%0,%1\t\t\t# %X1";
+	      else
+		{
+		  if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
+		    ret = "li\t%0,%1";
+		  else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
+		    ret = "li\t%0,%n1\n\tneg\t%0";
+		}
+	    }
+	}
+
+      else if (code1 == CONST_DOUBLE && mode == SFmode)
+	{
+	  if (op1 == CONST0_RTX (SFmode))
+	    {
+	      if (GP_REG_P (regno0))
+		ret = "move\t%0,%.";
+
+	      else if (FP_REG_P (regno0))
+		{
+		  delay = DELAY_LOAD;
+		  ret = "mtc1\t%.,%0";
+		}
+	    }
+
+	  else
+	    {
+	      delay = DELAY_LOAD;
+	      ret = "li.s\t%0,%1";
+	    }
+	}
+
+      else if (code1 == LABEL_REF)
+	{
+	  if (TARGET_STATS)
+	    mips_count_memory_refs (op1, 1);
+
+	  ret = "la\t%0,%a1";
+	}
+
+      else if (code1 == SYMBOL_REF || code1 == CONST)
+	{
+	  if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
+	    {
+	      rtx offset = const0_rtx;
+
+	      if (GET_CODE (op1) == CONST)
+		op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
+
+	      if (GET_CODE (op1) == SYMBOL_REF)
+		{
+		  operands[2] = HALF_PIC_PTR (op1);
+
+		  if (TARGET_STATS)
+		    mips_count_memory_refs (operands[2], 1);
+
+		  if (INTVAL (offset) == 0)
+		    {
+		      delay = DELAY_LOAD;
+		      ret = (unsignedp && TARGET_64BIT
+			     ? "lwu\t%0,%2"
+			     : "lw\t%0,%2");
+		    }
+		  else
+		    {
+		      dslots_load_total++;
+		      operands[3] = offset;
+		      if (unsignedp && TARGET_64BIT)
+			ret = (SMALL_INT (offset)
+			       ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
+			       : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
+		      else
+			ret = (SMALL_INT (offset)
+			       ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
+			       : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
+		    }
+		}
+	    }
+	  else if (TARGET_MIPS16
+		   && code1 == CONST
+		   && GET_CODE (XEXP (op1, 0)) == REG
+		   && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
+	    {
+	      /* This case arises on the mips16; see
+                 mips16_gp_pseudo_reg.  */
+	      ret = "move\t%0,%+";
+	    }
+	  else if (TARGET_MIPS16
+		   && code1 == SYMBOL_REF
+		   && SYMBOL_REF_FLAG (op1)
+		   && (XSTR (op1, 0)[0] != '*'
+		       || strncmp (XSTR (op1, 0) + 1,
+				   LOCAL_LABEL_PREFIX,
+				   sizeof LOCAL_LABEL_PREFIX - 1) != 0))
+	    {
+	      /* This can occur when reloading the address of a GP
+                 relative symbol on the mips16.  */
+	      ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
+	    }
+	  else
+	    {
+	      if (TARGET_STATS)
+		mips_count_memory_refs (op1, 1);
+
+	      ret = "la\t%0,%a1";
+	    }
+	}
+
+      else if (code1 == PLUS)
+	{
+	  rtx add_op0 = XEXP (op1, 0);
+	  rtx add_op1 = XEXP (op1, 1);
+
+	  if (GET_CODE (XEXP (op1, 1)) == REG
+	      && GET_CODE (XEXP (op1, 0)) == CONST_INT)
+	    add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
+
+	  operands[2] = add_op0;
+	  operands[3] = add_op1;
+	  ret = "add%:\t%0,%2,%3";
+	}
+
+      else if (code1 == HIGH)
+	{
+	  operands[1] = XEXP (op1, 0);
+	  ret = "lui\t%0,%%hi(%1)";
+	}
+    }
+
+  else if (code0 == MEM)
+    {
+      if (TARGET_STATS)
+	mips_count_memory_refs (op0, 1);
+
+      if (code1 == REG)
+	{
+	  int regno1 = REGNO (op1) + subreg_word1;
+
+	  if (GP_REG_P (regno1))
+	    {
+	      switch (mode)
+		{
+		case SFmode: ret = "sw\t%1,%0"; break;
+		case SImode: ret = "sw\t%1,%0"; break;
+		case HImode: ret = "sh\t%1,%0"; break;
+		case QImode: ret = "sb\t%1,%0"; break;
+		default: break;
+		}
+	    }
+
+	  else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
+	    ret = "s.s\t%1,%0";
+	}
+
+      else if (code1 == CONST_INT && INTVAL (op1) == 0)
+	{
+	  switch (mode)
+	    {
+	    case SFmode: ret = "sw\t%z1,%0"; break;
+	    case SImode: ret = "sw\t%z1,%0"; break;
+	    case HImode: ret = "sh\t%z1,%0"; break;
+	    case QImode: ret = "sb\t%z1,%0"; break;
+	    default: break;
+	    }
+	}
+
+      else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
+	{
+	  switch (mode)
+	    {
+	    case SFmode: ret = "sw\t%.,%0"; break;
+	    case SImode: ret = "sw\t%.,%0"; break;
+	    case HImode: ret = "sh\t%.,%0"; break;
+	    case QImode: ret = "sb\t%.,%0"; break;
+	    default: break;
+	    }
+	}
+
+      if (ret != 0 && MEM_VOLATILE_P (op0))
+	{
+	  size_t i = strlen (ret);
+
+	  if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
+	    abort ();
+	  
+	  sprintf (volatile_buffer, "%%{%s%%}", ret);
+	  ret = volatile_buffer;
+	}
+    }
+
+  if (ret == 0)
+    {
+      abort_with_insn (insn, "Bad move");
+      return 0;
+    }
+
+  if (delay != DELAY_NONE)
+    return mips_fill_delay_slot (ret, delay, operands, insn);
+
+  return ret;
+}
+
+
+/* Return the appropriate instructions to move 2 words */
+
+char *
+mips_move_2words (operands, insn)
+     rtx operands[];
+     rtx insn;
+{
+  char *ret = 0;
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  enum rtx_code code0 = GET_CODE (operands[0]);
+  enum rtx_code code1 = GET_CODE (operands[1]);
+  int subreg_word0 = 0;
+  int subreg_word1 = 0;
+  enum delay_type delay = DELAY_NONE;
+
+  while (code0 == SUBREG)
+    {
+      subreg_word0 += SUBREG_WORD (op0);
+      op0 = SUBREG_REG (op0);
+      code0 = GET_CODE (op0);
+    }
+
+  if (code1 == SIGN_EXTEND)
+    {
+      op1 = XEXP (op1, 0);
+      code1 = GET_CODE (op1);
+    }
+
+  while (code1 == SUBREG)
+    {
+      subreg_word1 += SUBREG_WORD (op1);
+      op1 = SUBREG_REG (op1);
+      code1 = GET_CODE (op1);
+    }
+      
+  /* Sanity check.  */
+  if (GET_CODE (operands[1]) == SIGN_EXTEND
+      && code1 != REG
+      && code1 != CONST_INT
+      /* The following three can happen as the result of a questionable
+	 cast.  */
+      && code1 != LABEL_REF
+      && code1 != SYMBOL_REF
+      && code1 != CONST)
+    abort ();
+
+  if (code0 == REG)
+    {
+      int regno0 = REGNO (op0) + subreg_word0;
+
+      if (code1 == REG)
+	{
+	  int regno1 = REGNO (op1) + subreg_word1;
+
+	  /* Just in case, don't do anything for assigning a register
+	     to itself, unless we are filling a delay slot.  */
+	  if (regno0 == regno1 && set_nomacro == 0)
+	    ret = "";
+
+	  else if (FP_REG_P (regno0))
+	    {
+	      if (FP_REG_P (regno1))
+		ret = "mov.d\t%0,%1";
+
+	      else
+		{
+		  delay = DELAY_LOAD;
+		  if (TARGET_FLOAT64)
+		    {
+		      if (!TARGET_64BIT)
+			abort_with_insn (insn, "Bad move");
+
+#ifdef TARGET_FP_CALL_32
+		      if (FP_CALL_GP_REG_P (regno1))
+			ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
+		      else
+#endif
+			ret = "dmtc1\t%1,%0";
+		    }
+		  else
+		    ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
+		}
+	    }
+
+	  else if (FP_REG_P (regno1))
+	    {
+	      delay = DELAY_LOAD;
+	      if (TARGET_FLOAT64)
+		{
+		  if (!TARGET_64BIT)
+		    abort_with_insn (insn, "Bad move");
+
+#ifdef TARGET_FP_CALL_32
+		  if (FP_CALL_GP_REG_P (regno0))
+		    ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
+		  else
+#endif
+		    ret = "dmfc1\t%0,%1";
+		}
+	      else
+		ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
+	    }
+
+	  else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
+	    {
+	      delay = DELAY_HILO;
+	      if (TARGET_64BIT)
+		{
+		  if (regno0 != HILO_REGNUM)
+		    ret = "mt%0\t%1";
+		  else if (regno1 == 0)
+		    ret = "mtlo\t%.\n\tmthi\t%.";
+		}
+	      else
+		ret = "mthi\t%M1\n\tmtlo\t%L1";
+	    }
+
+
+	  else if (GP_REG_P (regno0) && MD_REG_P (regno1))
+	    {
+	      delay = DELAY_HILO;
+	      if (TARGET_64BIT)
+		{
+		  if (regno1 != HILO_REGNUM)
+		    ret = "mf%1\t%0";
+		}
+	      else
+		ret = "mfhi\t%M0\n\tmflo\t%L0";
+	    }
+
+
+	  else if (TARGET_64BIT)
+	    ret = "move\t%0,%1";
+
+	  else if (regno0 != (regno1+1))
+	    ret = "move\t%0,%1\n\tmove\t%D0,%D1";
+
+	  else
+	    ret = "move\t%D0,%D1\n\tmove\t%0,%1";
+	}
+
+      else if (code1 == CONST_DOUBLE)
+	{
+	  /* Move zero from $0 unless !TARGET_64BIT and recipient
+	     is 64-bit fp reg, in which case generate a constant.  */
+	  if (op1 != CONST0_RTX (GET_MODE (op1))
+	      || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
+	    {
+	      if (GET_MODE (op1) == DFmode)
+		{
+		  delay = DELAY_LOAD;
+
+#ifdef TARGET_FP_CALL_32
+		  if (FP_CALL_GP_REG_P (regno0))
+		    {
+		      if (TARGET_FLOAT64 && !TARGET_64BIT)
+			{
+			  split_double (op1, operands + 2, operands + 3);
+			  ret = "li\t%0,%2\n\tli\t%D0,%3";
+			}
+		      else
+			ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
+		    }
+		  else
+#endif
+		    {
+		      /* GNU as emits 64-bit code for li.d if the ISA is 3
+			 or higher. To avoid this we must use two li
+			 instructions for 32-bit targets. */
+		      if (mips_isa >= 3 && !TARGET_64BIT && !FP_REG_P (regno0))
+			{
+			  split_double (op1, operands + 2, operands + 3);
+			  ret = "li\t%0,%2\n\tli\t%D0,%3";
+			}
+		      else
+			ret = "li.d\t%0,%1";
+		    }
+		}
+
+	      else if (TARGET_64BIT)
+		{
+		  if (! TARGET_MIPS16)
+		    ret = "dli\t%0,%1";
+		}
+
+	      else
+		{
+		  split_double (op1, operands + 2, operands + 3);
+		  ret = "li\t%0,%2\n\tli\t%D0,%3";
+		}
+	    }
+
+	  else
+	    {
+	      if (GP_REG_P (regno0))
+		ret = (TARGET_64BIT
+#ifdef TARGET_FP_CALL_32
+		       && ! FP_CALL_GP_REG_P (regno0)
+#endif
+		       ? "move\t%0,%."
+		       : "move\t%0,%.\n\tmove\t%D0,%.");
+
+	      else if (FP_REG_P (regno0))
+		{
+		  delay = DELAY_LOAD;
+		  ret = (TARGET_64BIT
+			 ? "dmtc1\t%.,%0"
+			 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
+		}
+	    }
+	}
+
+      else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
+	{
+	  if (GP_REG_P (regno0))
+	    ret = (TARGET_64BIT
+		   ? "move\t%0,%."
+		   : "move\t%0,%.\n\tmove\t%D0,%.");
+
+	  else if (FP_REG_P (regno0))
+	    {
+	      delay = DELAY_LOAD;
+	      ret = (TARGET_64BIT
+		     ? "dmtc1\t%.,%0"
+		     : (TARGET_FLOAT64
+			? "li.d\t%0,%1"
+			: "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
+	    }
+	  else if (MD_REG_P (regno0))
+	    {
+	      delay = DELAY_HILO;
+	      ret =  (regno0 == HILO_REGNUM
+		      ? "mtlo\t%.\n\tmthi\t%."
+		      : "mt%0\t%.\n");
+	    }
+	}
+	
+      else if (code1 == CONST_INT && GET_MODE (op0) == DImode
+	       && GP_REG_P (regno0))
+	{
+	  if (TARGET_64BIT)
+	    {
+	      if (TARGET_MIPS16)
+		{
+		  if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
+		    ret = "li\t%0,%1";
+		  else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
+		    ret = "li\t%0,%n1\n\tneg\t%0";
+		}
+	      else if (GET_CODE (operands[1]) == SIGN_EXTEND)
+		ret = "li\t%0,%1\t\t# %X1";
+	      else if (HOST_BITS_PER_WIDE_INT < 64)
+		/* We can't use 'X' for negative numbers, because then we won't
+		   get the right value for the upper 32 bits.  */
+		ret = (INTVAL (op1) < 0
+		       ? "dli\t%0,%1\t\t\t# %X1"
+		       : "dli\t%0,%X1\t\t# %1");
+	      else
+		/* We must use 'X', because otherwise LONG_MIN will print as
+		   a number that the assembler won't accept.  */
+		ret = "dli\t%0,%X1\t\t# %1";
+	    }
+	  else if (HOST_BITS_PER_WIDE_INT < 64)
+	    {
+	      operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
+	      if (TARGET_MIPS16)
+		{
+		  if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
+		    ret = "li\t%M0,%2\n\tli\t%L0,%1";
+		  else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
+		    {
+		      operands[2] = GEN_INT (1);
+		      ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
+		    }
+		}
+	      else
+		ret = "li\t%M0,%2\n\tli\t%L0,%1";
+	    }
+	  else
+	    {
+	      /* We use multiple shifts here, to avoid warnings about out
+		 of range shifts on 32 bit hosts.  */
+	      operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
+	      operands[1]
+		= GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
+	      ret = "li\t%M0,%2\n\tli\t%L0,%1";
+	    }
+	}
+
+      else if (code1 == MEM)
+	{
+	  delay = DELAY_LOAD;
+
+	  if (TARGET_STATS)
+	    mips_count_memory_refs (op1, 2);
+
+	  if (FP_REG_P (regno0))
+	    ret = "l.d\t%0,%1";
+
+	  else if (TARGET_64BIT)
+	    {
+
+#ifdef TARGET_FP_CALL_32
+	      if (FP_CALL_GP_REG_P (regno0))
+		ret = (double_memory_operand (op1, GET_MODE (op1))
+		       ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
+		       : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
+	      else
+#endif
+		ret = "ld\t%0,%1";
+	    }
+
+	  else if (double_memory_operand (op1, GET_MODE (op1)))
+	    {
+	      operands[2] = adj_offsettable_operand (op1, 4);
+	      ret = (reg_mentioned_p (op0, op1)
+		     ? "lw\t%D0,%2\n\tlw\t%0,%1"
+		     : "lw\t%0,%1\n\tlw\t%D0,%2");
+	    }
+
+	  if (ret != 0 && MEM_VOLATILE_P (op1))
+	    {
+	      size_t i = strlen (ret);
+
+	      if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
+		abort ();
+
+	      sprintf (volatile_buffer, "%%{%s%%}", ret);
+	      ret = volatile_buffer;
+	    }
+	}
+
+      else if (code1 == LABEL_REF)
+	{
+	  if (TARGET_STATS)
+	    mips_count_memory_refs (op1, 2);
+
+	  if (GET_CODE (operands[1]) == SIGN_EXTEND)
+	    /* We deliberately remove the 'a' from '%1', so that we don't
+	       have to add SIGN_EXTEND support to print_operand_address.
+	       print_operand will just call print_operand_address in this
+	       case, so there is no problem.  */
+	    ret = "la\t%0,%1";
+	  else
+	    ret = "dla\t%0,%a1";
+	}
+      else if (code1 == SYMBOL_REF || code1 == CONST)
+	{
+	  if (TARGET_MIPS16
+	      && code1 == CONST
+	      && GET_CODE (XEXP (op1, 0)) == REG
+	      && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
+	    {
+	      /* This case arises on the mips16; see
+                 mips16_gp_pseudo_reg.  */
+	      ret = "move\t%0,%+";
+	    }
+	  else if (TARGET_MIPS16
+		   && code1 == SYMBOL_REF
+		   && SYMBOL_REF_FLAG (op1)
+		   && (XSTR (op1, 0)[0] != '*'
+		       || strncmp (XSTR (op1, 0) + 1,
+				   LOCAL_LABEL_PREFIX,
+				   sizeof LOCAL_LABEL_PREFIX - 1) != 0))
+	    {
+	      /* This can occur when reloading the address of a GP
+                 relative symbol on the mips16.  */
+	      ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
+	    }
+	  else
+	    {
+	      if (TARGET_STATS)
+		mips_count_memory_refs (op1, 2);
+
+	      if (GET_CODE (operands[1]) == SIGN_EXTEND)
+		/* We deliberately remove the 'a' from '%1', so that we don't
+		   have to add SIGN_EXTEND support to print_operand_address.
+		   print_operand will just call print_operand_address in this
+		   case, so there is no problem.  */
+		ret = "la\t%0,%1";
+	      else
+		ret = "dla\t%0,%a1";
+	    }
+	}
+    }
+
+  else if (code0 == MEM)
+    {
+      if (code1 == REG)
+	{
+	  int regno1 = REGNO (op1) + subreg_word1;
+
+	  if (FP_REG_P (regno1))
+	    ret = "s.d\t%1,%0";
+
+	  else if (TARGET_64BIT)
+	    {
+
+#ifdef TARGET_FP_CALL_32
+	      if (FP_CALL_GP_REG_P (regno1))
+		ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
+	      else
+#endif
+		ret = "sd\t%1,%0";
+	    }
+
+	  else if (double_memory_operand (op0, GET_MODE (op0)))
+	    {
+	      operands[2] = adj_offsettable_operand (op0, 4);
+	      ret = "sw\t%1,%0\n\tsw\t%D1,%2";
+	    }
+	}
+
+      else if (((code1 == CONST_INT && INTVAL (op1) == 0)
+		|| (code1 == CONST_DOUBLE
+		    && op1 == CONST0_RTX (GET_MODE (op1))))
+	       && (TARGET_64BIT
+		   || double_memory_operand (op0, GET_MODE (op0))))
+	{
+	  if (TARGET_64BIT)
+	    ret = "sd\t%.,%0";
+	  else
+	    {
+	      operands[2] = adj_offsettable_operand (op0, 4);
+	      ret = "sw\t%.,%0\n\tsw\t%.,%2";
+	    }
+	}
+
+      if (TARGET_STATS)
+	mips_count_memory_refs (op0, 2);
+
+      if (ret != 0 && MEM_VOLATILE_P (op0))
+	{
+	  size_t i = strlen (ret);
+
+	  if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
+	    abort ();
+	  
+	  sprintf (volatile_buffer, "%%{%s%%}", ret);
+	  ret = volatile_buffer;
+	}
+    }
+
+  if (ret == 0)
+    {
+      abort_with_insn (insn, "Bad move");
+      return 0;
+    }
+
+  if (delay != DELAY_NONE)
+    return mips_fill_delay_slot (ret, delay, operands, insn);
+
+  return ret;
+}
+
+/* Provide the costs of an addressing mode that contains ADDR.
+   If ADDR is not a valid address, its cost is irrelevant.  */
+
+int
+mips_address_cost (addr)
+     rtx addr;
+{
+  switch (GET_CODE (addr))
+    {
+    case LO_SUM:
+      return 1;
+
+    case LABEL_REF:
+      return 2;
+
+    case CONST:
+      {
+	rtx offset = const0_rtx;
+	addr = eliminate_constant_term (XEXP (addr, 0), &offset);
+	if (GET_CODE (addr) == LABEL_REF)
+	  return 2;
+
+	if (GET_CODE (addr) != SYMBOL_REF)
+	  return 4;
+
+	if (! SMALL_INT (offset))
+	  return 2;
+      }
+
+      /* ... fall through ... */
+
+    case SYMBOL_REF:
+      return SYMBOL_REF_FLAG (addr) ? 1 : 2;
+
+    case PLUS:
+      {
+	register rtx plus0 = XEXP (addr, 0);
+	register rtx plus1 = XEXP (addr, 1);
+
+	if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
+	  plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
+
+	if (GET_CODE (plus0) != REG)
+	  break;
+
+	switch (GET_CODE (plus1))
+	  {
+	  case CONST_INT:
+	    return SMALL_INT (plus1) ? 1 : 2;
+
+	  case CONST:
+	  case SYMBOL_REF:
+	  case LABEL_REF:
+	  case HIGH:
+	  case LO_SUM:
+	    return mips_address_cost (plus1) + 1;
+
+	  default:
+	    break;
+	  }
+      }
+
+    default:
+      break;
+    }
+
+  return 4;
+}
+
+/* Return nonzero if X is an address which needs a temporary register when 
+   reloaded while generating PIC code.  */
+
+int
+pic_address_needs_scratch (x)
+     rtx x;
+{
+  /* An address which is a symbolic plus a non SMALL_INT needs a temp reg.  */
+  if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
+      && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+      && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
+    return 1;
+
+  return 0;
+}
+
+/* Make normal rtx_code into something we can index from an array */
+
+static enum internal_test
+map_test_to_internal_test (test_code)
+     enum rtx_code test_code;
+{
+  enum internal_test test = ITEST_MAX;
+
+  switch (test_code)
+    {
+    case EQ:  test = ITEST_EQ;  break;
+    case NE:  test = ITEST_NE;  break;
+    case GT:  test = ITEST_GT;  break;
+    case GE:  test = ITEST_GE;  break;
+    case LT:  test = ITEST_LT;  break;
+    case LE:  test = ITEST_LE;  break;
+    case GTU: test = ITEST_GTU; break;
+    case GEU: test = ITEST_GEU; break;
+    case LTU: test = ITEST_LTU; break;
+    case LEU: test = ITEST_LEU; break;
+    default:			break;
+    }
+
+  return test;
+}
+
+
+/* Generate the code to compare two integer values.  The return value is:
+   (reg:SI xx)		The pseudo register the comparison is in
+   0		       	No register, generate a simple branch.
+
+   ??? This is called with result nonzero by the Scond patterns in
+   mips.md.  These patterns are called with a target in the mode of
+   the Scond instruction pattern.  Since this must be a constant, we
+   must use SImode.  This means that if RESULT is non-zero, it will
+   always be an SImode register, even if TARGET_64BIT is true.  We
+   cope with this by calling convert_move rather than emit_move_insn.
+   This will sometimes lead to an unnecessary extension of the result;
+   for example:
+
+   long long
+   foo (long long i)
+   {
+     return i < 5;
+   }
+
+   */
+
+rtx
+gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
+     enum rtx_code test_code;	/* relational test (EQ, etc) */
+     rtx result;		/* result to store comp. or 0 if branch */
+     rtx cmp0;			/* first operand to compare */
+     rtx cmp1;			/* second operand to compare */
+     int *p_invert;		/* NULL or ptr to hold whether branch needs */
+				/* to reverse its test */
+{
+  struct cmp_info
+  {
+    enum rtx_code test_code;	/* code to use in instruction (LT vs. LTU) */
+    int const_low;		/* low bound of constant we can accept */
+    int const_high;		/* high bound of constant we can accept */
+    int const_add;		/* constant to add (convert LE -> LT) */
+    int reverse_regs;		/* reverse registers in test */
+    int invert_const;		/* != 0 if invert value if cmp1 is constant */
+    int invert_reg;		/* != 0 if invert value if cmp1 is register */
+    int unsignedp;		/* != 0 for unsigned comparisons.  */
+  };
+
+  static struct cmp_info info[ (int)ITEST_MAX ] = {
+
+    { XOR,	 0,  65535,  0,	 0,  0,	 0, 0 },	/* EQ  */
+    { XOR,	 0,  65535,  0,	 0,  1,	 1, 0 },	/* NE  */
+    { LT,   -32769,  32766,  1,	 1,  1,	 0, 0 },	/* GT  */
+    { LT,   -32768,  32767,  0,	 0,  1,	 1, 0 },	/* GE  */
+    { LT,   -32768,  32767,  0,	 0,  0,	 0, 0 },	/* LT  */
+    { LT,   -32769,  32766,  1,	 1,  0,	 1, 0 },	/* LE  */
+    { LTU,  -32769,  32766,  1,	 1,  1,	 0, 1 },	/* GTU */
+    { LTU,  -32768,  32767,  0,	 0,  1,	 1, 1 },	/* GEU */
+    { LTU,  -32768,  32767,  0,	 0,  0,	 0, 1 },	/* LTU */
+    { LTU,  -32769,  32766,  1,	 1,  0,	 1, 1 },	/* LEU */
+  };
+
+  enum internal_test test;
+  enum machine_mode mode;
+  struct cmp_info *p_info;
+  int branch_p;
+  int eqne_p;
+  int invert;
+  rtx reg;
+  rtx reg2;
+
+  test = map_test_to_internal_test (test_code);
+  if (test == ITEST_MAX)
+    abort ();
+
+  p_info = &info[(int) test];
+  eqne_p = (p_info->test_code == XOR);
+
+  mode = GET_MODE (cmp0);
+  if (mode == VOIDmode)
+    mode = GET_MODE (cmp1);
+
+  /* Eliminate simple branches */
+  branch_p = (result == 0);
+  if (branch_p)
+    {
+      if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
+	{
+	  /* Comparisons against zero are simple branches */
+	  if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
+	      && (! TARGET_MIPS16 || eqne_p))
+	    return 0;
+
+	  /* Test for beq/bne.  */
+	  if (eqne_p && ! TARGET_MIPS16)
+	    return 0;
+	}
+
+      /* allocate a pseudo to calculate the value in.  */
+      result = gen_reg_rtx (mode);
+    }
+
+  /* Make sure we can handle any constants given to us.  */
+  if (GET_CODE (cmp0) == CONST_INT)
+    cmp0 = force_reg (mode, cmp0);
+
+  if (GET_CODE (cmp1) == CONST_INT)
+    {
+      HOST_WIDE_INT value = INTVAL (cmp1);
+
+      if (value < p_info->const_low
+	  || value > p_info->const_high
+	  /* ??? Why?  And why wasn't the similar code below modified too?  */
+	  || (TARGET_64BIT
+	      && HOST_BITS_PER_WIDE_INT < 64
+	      && p_info->const_add != 0
+	      && ((p_info->unsignedp
+		   ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
+		      > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
+		   : (value + p_info->const_add) > INTVAL (cmp1))
+		  != (p_info->const_add > 0))))
+	cmp1 = force_reg (mode, cmp1);
+    }
+
+  /* See if we need to invert the result.  */
+  invert = (GET_CODE (cmp1) == CONST_INT
+	    ? p_info->invert_const : p_info->invert_reg);
+
+  if (p_invert != (int *)0)
+    {
+      *p_invert = invert;
+      invert = 0;
+    }
+
+  /* Comparison to constants, may involve adding 1 to change a LT into LE.
+     Comparison between two registers, may involve switching operands.  */
+  if (GET_CODE (cmp1) == CONST_INT)
+    {
+      if (p_info->const_add != 0)
+	{
+	  HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
+
+	  /* If modification of cmp1 caused overflow,
+	     we would get the wrong answer if we follow the usual path;
+	     thus, x > 0xffffffffU would turn into x > 0U.  */
+	  if ((p_info->unsignedp
+	       ? (unsigned HOST_WIDE_INT) new >
+	       (unsigned HOST_WIDE_INT) INTVAL (cmp1)
+	       : new > INTVAL (cmp1))
+	      != (p_info->const_add > 0))
+	    {
+	      /* This test is always true, but if INVERT is true then
+		 the result of the test needs to be inverted so 0 should
+		 be returned instead.  */
+	      emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
+	      return result;
+	    }
+	  else
+	    cmp1 = GEN_INT (new);
+	}
+    }
+
+  else if (p_info->reverse_regs)
+    {
+      rtx temp = cmp0;
+      cmp0 = cmp1;
+      cmp1 = temp;
+    }
+
+  if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
+    reg = cmp0;
+  else
+    {
+      reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
+      convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
+    }
+
+  if (test == ITEST_NE)
+    {
+      if (! TARGET_MIPS16)
+	{
+	  convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
+	  invert = 0;
+	}
+      else
+	{
+	  reg2 = invert ? gen_reg_rtx (mode) : result;
+	  convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
+	  reg = reg2;
+	}
+    }
+
+  else if (test == ITEST_EQ)
+    {
+      reg2 = invert ? gen_reg_rtx (mode) : result;
+      convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
+      reg = reg2;
+    }
+
+  if (invert)
+    {
+      rtx one;
+
+      if (! TARGET_MIPS16)
+	one = const1_rtx;
+      else
+	{
+	  /* The value is in $24.  Copy it to another register, so
+             that reload doesn't think it needs to store the $24 and
+             the input to the XOR in the same location.  */
+	  reg2 = gen_reg_rtx (mode);
+	  emit_move_insn (reg2, reg);
+	  reg = reg2;
+	  one = force_reg (mode, const1_rtx);
+	}
+      convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
+    }
+
+  return result;
+}
+
+/* Emit the common code for doing conditional branches.
+   operand[0] is the label to jump to.
+   The comparison operands are saved away by cmp{si,di,sf,df}.  */
+
+void
+gen_conditional_branch (operands, test_code)
+     rtx operands[];
+     enum rtx_code test_code;
+{
+  enum cmp_type type = branch_type;
+  rtx cmp0 = branch_cmp[0];
+  rtx cmp1 = branch_cmp[1];
+  enum machine_mode mode;
+  rtx reg;
+  int invert;
+  rtx label1, label2;
+
+  switch (type)
+    {
+    case CMP_SI:
+    case CMP_DI:
+      mode = type == CMP_SI ? SImode : DImode;
+      invert = 0;
+      reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
+
+      if (reg)
+	{
+	  cmp0 = reg;
+	  cmp1 = const0_rtx;
+	  test_code = NE;
+	}
+      else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
+	/* We don't want to build a comparison against a non-zero
+	   constant.  */
+	cmp1 = force_reg (mode, cmp1);
+
+      break;
+
+    case CMP_SF:
+    case CMP_DF:
+      if (mips_isa < 4)
+	reg = gen_rtx (REG, CCmode, FPSW_REGNUM);
+      else
+	reg = gen_reg_rtx (CCmode);
+
+      /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
+         0 in the instruction built below.  The MIPS FPU handles
+         inequality testing by testing for equality and looking for a
+         false result.  */
+      emit_insn (gen_rtx (SET, VOIDmode, reg,
+			  gen_rtx (test_code == NE ? EQ : test_code,
+				   CCmode, cmp0, cmp1)));
+
+      test_code = test_code == NE ? EQ : NE;
+      mode = CCmode;
+      cmp0 = reg;
+      cmp1 = const0_rtx;
+      invert = 0;
+      break;
+
+    default:
+      abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
+    }
+
+  /* Generate the branch.  */
+
+  label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
+  label2 = pc_rtx;
+
+  if (invert)
+    {
+      label2 = label1;
+      label1 = pc_rtx;
+    }
+
+  emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
+			   gen_rtx (IF_THEN_ELSE, VOIDmode,
+				    gen_rtx (test_code, mode, cmp0, cmp1),
+				    label1, label2)));
+}
+
+/* Emit the common code for conditional moves.  OPERANDS is the array
+   of operands passed to the conditional move defined_expand.  */
+
+void
+gen_conditional_move (operands)
+     rtx *operands;
+{
+  rtx op0 = branch_cmp[0];
+  rtx op1 = branch_cmp[1];
+  enum machine_mode mode = GET_MODE (branch_cmp[0]);
+  enum rtx_code cmp_code = GET_CODE (operands[1]);
+  enum rtx_code move_code = NE;
+  enum machine_mode op_mode = GET_MODE (operands[0]);
+  enum machine_mode cmp_mode;
+  rtx cmp_reg;
+
+  if (GET_MODE_CLASS (mode) != MODE_FLOAT)
+    {
+      switch (cmp_code)
+	{
+	case EQ:
+	  cmp_code = XOR;
+	  move_code = EQ;
+	  break;
+	case NE:
+	  cmp_code = XOR;
+	  break;
+	case LT:
+	  break;
+	case GE:
+	  cmp_code = LT;
+	  move_code = EQ;
+	  break;
+	case GT:
+	  cmp_code = LT;
+	  op0 = force_reg (mode, branch_cmp[1]);
+	  op1 = branch_cmp[0];
+	  break;
+	case LE:
+	  cmp_code = LT;
+	  op0 = force_reg (mode, branch_cmp[1]);
+	  op1 = branch_cmp[0];
+	  move_code = EQ;
+	  break;
+	case LTU:
+	  break;
+	case GEU:
+	  cmp_code = LTU;
+	  move_code = EQ;
+	  break;
+	case GTU:
+	  cmp_code = LTU;
+	  op0 = force_reg (mode, branch_cmp[1]);
+	  op1 = branch_cmp[0];
+	  break;
+	case LEU:
+	  cmp_code = LTU;
+	  op0 = force_reg (mode, branch_cmp[1]);
+	  op1 = branch_cmp[0];
+	  move_code = EQ;
+	  break;
+	default:
+	  abort ();
+	}
+    }
+  else if (cmp_code == NE)
+    cmp_code = EQ, move_code = EQ;
+	  
+  if (mode == SImode || mode == DImode)
+    cmp_mode = mode;
+  else if (mode == SFmode || mode == DFmode)
+    cmp_mode = CCmode;
+  else
+    abort ();
+
+  cmp_reg = gen_reg_rtx (cmp_mode);
+  emit_insn (gen_rtx (SET, cmp_mode, cmp_reg,
+		      gen_rtx (cmp_code, cmp_mode, op0, op1)));
+
+  emit_insn (gen_rtx (SET, op_mode, operands[0],
+		      gen_rtx (IF_THEN_ELSE, op_mode,
+			       gen_rtx (move_code, VOIDmode,
+					cmp_reg, CONST0_RTX (SImode)),
+			       operands[2], operands[3])));
+}
+
+/* Write a loop to move a constant number of bytes.
+   Generate load/stores as follows:
+
+   do {
+     temp1 = src[0];
+     temp2 = src[1];
+     ...
+     temp<last> = src[MAX_MOVE_REGS-1];
+     dest[0] = temp1;
+     dest[1] = temp2;
+     ...
+     dest[MAX_MOVE_REGS-1] = temp<last>;
+     src += MAX_MOVE_REGS;
+     dest += MAX_MOVE_REGS;
+   } while (src != final);
+
+   This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
+   registers are needed.
+
+   Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
+   cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
+   (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses.  */
+
+#define MAX_MOVE_REGS 4
+#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
+
+static void
+block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
+     rtx dest_reg;		/* register holding destination address */
+     rtx src_reg;		/* register holding source address */
+     int bytes;			/* # bytes to move */
+     int align;			/* alignment */
+     rtx orig_dest;		/* original dest for change_address */
+     rtx orig_src;		/* original source for making a reg note */
+{
+  rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
+  rtx src_mem = change_address (orig_src, BLKmode, src_reg);
+  rtx align_rtx = GEN_INT (align);
+  rtx label;
+  rtx final_src;
+  rtx bytes_rtx;
+  int leftover;
+
+  if (bytes < 2 * MAX_MOVE_BYTES)
+    abort ();
+
+  leftover = bytes % MAX_MOVE_BYTES;
+  bytes -= leftover;
+
+  label = gen_label_rtx ();
+  final_src = gen_reg_rtx (Pmode);
+  bytes_rtx = GEN_INT (bytes);
+
+  if (bytes > 0x7fff)
+    {
+      if (Pmode == DImode)
+	{
+	  emit_insn (gen_movdi (final_src, bytes_rtx));
+	  emit_insn (gen_adddi3 (final_src, final_src, src_reg));
+	}
+      else
+	{
+	  emit_insn (gen_movsi (final_src, bytes_rtx));
+	  emit_insn (gen_addsi3 (final_src, final_src, src_reg));
+	}
+    }
+  else
+    {
+      if (Pmode == DImode)
+	emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
+      else
+	emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
+    }
+
+  emit_label (label);
+
+  bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
+  emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
+
+  if (Pmode == DImode)
+    {
+      emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
+      emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
+      emit_insn (gen_cmpdi (src_reg, final_src));
+    }
+  else
+    {
+      emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
+      emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
+      emit_insn (gen_cmpsi (src_reg, final_src));
+    }
+
+  emit_jump_insn (gen_bne (label));
+
+  if (leftover)
+    emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
+				      align_rtx));
+}
+
+/* Use a library function to move some bytes.  */
+
+static void
+block_move_call (dest_reg, src_reg, bytes_rtx)
+     rtx dest_reg;
+     rtx src_reg;
+     rtx bytes_rtx;
+{
+  /* We want to pass the size as Pmode, which will normally be SImode
+     but will be DImode if we are using 64 bit longs and pointers.  */
+  if (GET_MODE (bytes_rtx) != VOIDmode
+      && GET_MODE (bytes_rtx) != Pmode)
+    bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
+
+#ifdef TARGET_MEM_FUNCTIONS
+  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
+		     VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
+		     convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
+				      TREE_UNSIGNED (sizetype)),
+		     TYPE_MODE (sizetype));
+#else
+  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
+		     VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
+		     convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
+				      TREE_UNSIGNED (integer_type_node)),
+		     TYPE_MODE (integer_type_node));
+#endif
+}
+
+/* Expand string/block move operations.
+
+   operands[0] is the pointer to the destination.
+   operands[1] is the pointer to the source.
+   operands[2] is the number of bytes to move.
+   operands[3] is the alignment.  */
+
+void
+expand_block_move (operands)
+     rtx operands[];
+{
+  rtx bytes_rtx	= operands[2];
+  rtx align_rtx = operands[3];
+  int constp = GET_CODE (bytes_rtx) == CONST_INT;
+  HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
+  int align = INTVAL (align_rtx);
+  rtx orig_src	= operands[1];
+  rtx orig_dest	= operands[0];
+  rtx src_reg;
+  rtx dest_reg;
+
+  if (constp && bytes <= 0)
+    return;
+
+  if (align > UNITS_PER_WORD)
+    align = UNITS_PER_WORD;
+
+  /* Move the address into scratch registers.  */
+  dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
+  src_reg  = copy_addr_to_reg (XEXP (orig_src, 0));
+
+  if (TARGET_MEMCPY)
+    block_move_call (dest_reg, src_reg, bytes_rtx);
+
+  else if (constp && bytes <= 2 * MAX_MOVE_BYTES
+	   && align == UNITS_PER_WORD)
+    move_by_pieces (orig_dest, orig_src, bytes, align);
+	
+  else if (constp && bytes <= 2 * MAX_MOVE_BYTES)
+    emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
+						      dest_reg),
+				      change_address (orig_src, BLKmode,
+						      src_reg),
+				      bytes_rtx, align_rtx));
+
+  else if (constp && align >= UNITS_PER_WORD && optimize)
+    block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
+
+  else if (constp && optimize)
+    {
+      /* If the alignment is not word aligned, generate a test at
+	 runtime, to see whether things wound up aligned, and we
+	 can use the faster lw/sw instead ulw/usw.  */
+
+      rtx temp = gen_reg_rtx (Pmode);
+      rtx aligned_label = gen_label_rtx ();
+      rtx join_label = gen_label_rtx ();
+      int leftover = bytes % MAX_MOVE_BYTES;
+
+      bytes -= leftover;
+
+      if (Pmode == DImode)
+	{
+	  emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
+	  emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
+	  emit_insn (gen_cmpdi (temp, const0_rtx));
+	}
+      else
+	{
+	  emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
+	  emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
+	  emit_insn (gen_cmpsi (temp, const0_rtx));
+	}
+
+      emit_jump_insn (gen_beq (aligned_label));
+
+      /* Unaligned loop.  */
+      block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
+      emit_jump_insn (gen_jump (join_label));
+      emit_barrier ();
+
+      /* Aligned loop.  */
+      emit_label (aligned_label);
+      block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
+		       orig_src);
+      emit_label (join_label);
+
+      /* Bytes at the end of the loop.  */
+      if (leftover)
+	emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
+							  dest_reg),
+					  change_address (orig_src, BLKmode,
+							  src_reg),
+					  GEN_INT (leftover),
+					  GEN_INT (align)));
+    }
+
+  else
+    block_move_call (dest_reg, src_reg, bytes_rtx);
+}
+
+/* Emit load/stores for a small constant block_move. 
+
+   operands[0] is the memory address of the destination.
+   operands[1] is the memory address of the source.
+   operands[2] is the number of bytes to move.
+   operands[3] is the alignment.
+   operands[4] is a temp register.
+   operands[5] is a temp register.
+   ...
+   operands[3+num_regs] is the last temp register.
+
+   The block move type can be one of the following:
+	BLOCK_MOVE_NORMAL	Do all of the block move.
+	BLOCK_MOVE_NOT_LAST	Do all but the last store.
+	BLOCK_MOVE_LAST		Do just the last store. */
+
+char *
+output_block_move (insn, operands, num_regs, move_type)
+     rtx insn;
+     rtx operands[];
+     int num_regs;
+     enum block_move_type move_type;
+{
+  rtx dest_reg = XEXP (operands[0], 0);
+  rtx src_reg = XEXP (operands[1], 0);
+  HOST_WIDE_INT bytes = INTVAL (operands[2]);
+  int align = INTVAL (operands[3]);
+  int num = 0;
+  int offset = 0;
+  int use_lwl_lwr = 0;
+  int last_operand = num_regs + 4;
+  int safe_regs = 4;
+  int i;
+  rtx xoperands[10];
+
+  struct {
+    char *load;			/* load insn without nop */
+    char *load_nop;		/* load insn with trailing nop */
+    char *store;		/* store insn */
+    char *final;		/* if last_store used: NULL or swr */
+    char *last_store;		/* last store instruction */
+    int offset;			/* current offset */
+    enum machine_mode mode;	/* mode to use on (MEM) */
+  } load_store[4];
+
+  /* ??? Detect a bug in GCC, where it can give us a register
+     the same as one of the addressing registers and reduce
+     the number of registers available.  */
+  for (i = 4;
+       i < last_operand
+       && safe_regs < (int)(sizeof(xoperands) / sizeof(xoperands[0]));
+       i++)
+    if (! reg_mentioned_p (operands[i], operands[0])
+	&& ! reg_mentioned_p (operands[i], operands[1]))
+      xoperands[safe_regs++] = operands[i];
+
+  if (safe_regs < last_operand)
+    {
+      xoperands[0] = operands[0];
+      xoperands[1] = operands[1];
+      xoperands[2] = operands[2];
+      xoperands[3] = operands[3];
+      return output_block_move (insn, xoperands, safe_regs - 4, move_type);
+    }
+
+  /* If we are given global or static addresses, and we would be
+     emitting a few instructions, try to save time by using a
+     temporary register for the pointer.  */
+  /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
+     an ldl/ldr instruction pair.  We play it safe, and always move
+     constant addresses into registers when generating N32/N64 code, just
+     in case we might emit an unaligned load instruction.  */
+  if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
+		       || mips_abi == ABI_N32 || mips_abi == ABI_64))
+    {
+      if (CONSTANT_P (src_reg))
+	{
+	  if (TARGET_STATS)
+	    mips_count_memory_refs (operands[1], 1);
+
+	  src_reg = operands[3 + num_regs--];
+	  if (move_type != BLOCK_MOVE_LAST)
+	    {
+	      xoperands[1] = operands[1];
+	      xoperands[0] = src_reg;
+	      if (Pmode == DImode)
+		output_asm_insn ("dla\t%0,%1", xoperands);
+	      else
+		output_asm_insn ("la\t%0,%1", xoperands);
+	    }
+	}
+
+      if (CONSTANT_P (dest_reg))
+	{
+	  if (TARGET_STATS)
+	    mips_count_memory_refs (operands[0], 1);
+
+	  dest_reg = operands[3 + num_regs--];
+	  if (move_type != BLOCK_MOVE_LAST)
+	    {
+	      xoperands[1] = operands[0];
+	      xoperands[0] = dest_reg;
+	      if (Pmode == DImode)
+		output_asm_insn ("dla\t%0,%1", xoperands);
+	      else
+		output_asm_insn ("la\t%0,%1", xoperands);
+	    }
+	}
+    }
+
+  /* ??? We really shouldn't get any LO_SUM addresses here, because they
+     are not offsettable, however, offsettable_address_p says they are
+     offsettable. I think this is a bug in offsettable_address_p.
+     For expediency, we fix this by just loading the address into a register
+     if we happen to get one.  */
+
+  if (GET_CODE (src_reg) == LO_SUM)
+    {
+      src_reg = operands[3 + num_regs--];
+      if (move_type != BLOCK_MOVE_LAST)
+	{
+	  xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
+	  xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
+	  xoperands[0] = src_reg;
+	  if (Pmode == DImode)
+	    output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
+	  else
+	    output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
+	}
+    }
+
+  if (GET_CODE (dest_reg) == LO_SUM)
+    {
+      dest_reg = operands[3 + num_regs--];
+      if (move_type != BLOCK_MOVE_LAST)
+	{
+	  xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
+	  xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
+	  xoperands[0] = dest_reg;
+	  if (Pmode == DImode)
+	    output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
+	  else
+	    output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
+	}
+    }
+
+  if (num_regs > (int)(sizeof (load_store) / sizeof (load_store[0])))
+    num_regs = sizeof (load_store) / sizeof (load_store[0]);
+
+  else if (num_regs < 1)
+    abort_with_insn (insn,
+		     "Cannot do block move, not enough scratch registers");
+
+  while (bytes > 0)
+    {
+      load_store[num].offset = offset;
+
+      if (TARGET_64BIT && bytes >= 8 && align >= 8)
+	{
+	  load_store[num].load = "ld\t%0,%1";
+	  load_store[num].load_nop = "ld\t%0,%1%#";
+	  load_store[num].store = "sd\t%0,%1";
+	  load_store[num].last_store = "sd\t%0,%1";
+	  load_store[num].final = 0;
+	  load_store[num].mode = DImode;
+	  offset += 8;
+	  bytes -= 8;
+	}
+
+      /* ??? Fails because of a MIPS assembler bug?  */
+      else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
+	{
+	  if (BYTES_BIG_ENDIAN)
+	    {
+	      load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
+	      load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
+	      load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
+	      load_store[num].last_store = "sdr\t%0,%2";
+	      load_store[num].final = "sdl\t%0,%1";
+	    }
+	  else
+	    {
+	      load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
+	      load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
+	      load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
+	      load_store[num].last_store = "sdr\t%0,%1";
+	      load_store[num].final = "sdl\t%0,%2";
+	    }
+
+	  load_store[num].mode = DImode;
+	  offset += 8;
+	  bytes -= 8;
+	  use_lwl_lwr = 1;
+	}
+
+      else if (bytes >= 4 && align >= 4)
+	{
+	  load_store[num].load = "lw\t%0,%1";
+	  load_store[num].load_nop = "lw\t%0,%1%#";
+	  load_store[num].store = "sw\t%0,%1";
+	  load_store[num].last_store = "sw\t%0,%1";
+	  load_store[num].final = 0;
+	  load_store[num].mode = SImode;
+	  offset += 4;
+	  bytes -= 4;
+	}
+
+      else if (bytes >= 4 && ! TARGET_MIPS16)
+	{
+	  if (BYTES_BIG_ENDIAN)
+	    {
+	      load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
+	      load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
+	      load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
+	      load_store[num].last_store = "swr\t%0,%2";
+	      load_store[num].final = "swl\t%0,%1";
+	    }
+	  else
+	    {
+	      load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
+	      load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
+	      load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
+	      load_store[num].last_store = "swr\t%0,%1";
+	      load_store[num].final = "swl\t%0,%2";
+	    }
+
+	  load_store[num].mode = SImode;
+	  offset += 4;
+	  bytes -= 4;
+	  use_lwl_lwr = 1;
+	}
+
+      else if (bytes >= 2 && align >= 2)
+	{
+	  load_store[num].load = "lh\t%0,%1";
+	  load_store[num].load_nop = "lh\t%0,%1%#";
+	  load_store[num].store = "sh\t%0,%1";
+	  load_store[num].last_store = "sh\t%0,%1";
+	  load_store[num].final = 0;
+	  load_store[num].mode = HImode;
+	  offset += 2;
+	  bytes -= 2;
+	}
+      else
+	{
+	  load_store[num].load = "lb\t%0,%1";
+	  load_store[num].load_nop = "lb\t%0,%1%#";
+	  load_store[num].store = "sb\t%0,%1";
+	  load_store[num].last_store = "sb\t%0,%1";
+	  load_store[num].final = 0;
+	  load_store[num].mode = QImode;
+	  offset++;
+	  bytes--;
+	}
+
+      if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
+	{
+	  dslots_load_total++;
+	  dslots_load_filled++;
+
+	  if (CONSTANT_P (src_reg))
+	    mips_count_memory_refs (src_reg, 1);
+
+	  if (CONSTANT_P (dest_reg))
+	    mips_count_memory_refs (dest_reg, 1);
+	}
+
+      /* Emit load/stores now if we have run out of registers or are
+	 at the end of the move.  */
+
+      if (++num == num_regs || bytes == 0)
+	{
+	  /* If only load/store, we need a NOP after the load.  */
+	  if (num == 1)
+	    {
+	      load_store[0].load = load_store[0].load_nop;
+	      if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
+		dslots_load_filled--;
+	    }
+
+	  if (move_type != BLOCK_MOVE_LAST)
+	    {
+	      for (i = 0; i < num; i++)
+		{
+		  int offset;
+
+		  if (!operands[i + 4])
+		    abort ();
+
+		  if (GET_MODE (operands[i + 4]) != load_store[i].mode)
+		    operands[i + 4] = gen_rtx (REG, load_store[i].mode,
+					       REGNO (operands[i + 4]));
+
+		  offset = load_store[i].offset;
+		  xoperands[0] = operands[i + 4];
+		  xoperands[1] = gen_rtx (MEM, load_store[i].mode,
+					  plus_constant (src_reg, offset));
+
+		  if (use_lwl_lwr)
+		    {
+		      int extra_offset
+			= GET_MODE_SIZE (load_store[i].mode) - 1;
+
+		      xoperands[2] = gen_rtx (MEM, load_store[i].mode,
+					      plus_constant (src_reg,
+							     extra_offset
+							     + offset));
+		    }
+
+		  output_asm_insn (load_store[i].load, xoperands);
+		}
+	    }
+
+	  for (i = 0; i < num; i++)
+	    {
+	      int last_p = (i == num-1 && bytes == 0);
+	      int offset = load_store[i].offset;
+
+	      xoperands[0] = operands[i + 4];
+	      xoperands[1] = gen_rtx (MEM, load_store[i].mode,
+				      plus_constant (dest_reg, offset));
+
+
+	      if (use_lwl_lwr)
+		{
+		  int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
+		  xoperands[2] = gen_rtx (MEM, load_store[i].mode,
+					  plus_constant (dest_reg,
+							 extra_offset
+							 + offset));
+		}
+
+	      if (move_type == BLOCK_MOVE_NORMAL)
+		output_asm_insn (load_store[i].store, xoperands);
+
+	      else if (move_type == BLOCK_MOVE_NOT_LAST)
+		{
+		  if (!last_p)
+		    output_asm_insn (load_store[i].store, xoperands);
+
+		  else if (load_store[i].final != 0)
+		    output_asm_insn (load_store[i].final, xoperands);
+		}
+
+	      else if (last_p)
+		output_asm_insn (load_store[i].last_store, xoperands);
+	    }
+
+	  num = 0;		/* reset load_store */
+	  use_lwl_lwr = 0;
+	}
+    }
+
+  return "";
+}
+
+/* Argument support functions.  */
+
+/* Initialize CUMULATIVE_ARGS for a function.  */
+
+void
+init_cumulative_args (cum, fntype, libname)
+     CUMULATIVE_ARGS *cum;		/* argument info to initialize */
+     tree fntype;			/* tree ptr for function decl */
+     rtx libname ATTRIBUTE_UNUSED;	/* SYMBOL_REF of library name or 0 */
+{
+  static CUMULATIVE_ARGS zero_cum;
+  tree param, next_param;
+
+  if (TARGET_DEBUG_E_MODE)
+    {
+      fprintf (stderr,
+	       "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
+
+      if (!fntype)
+	fputc ('\n', stderr);
+
+      else
+	{
+	  tree ret_type = TREE_TYPE (fntype);
+	  fprintf (stderr, ", fntype code = %s, ret code = %s\n",
+		   tree_code_name[(int)TREE_CODE (fntype)],
+		   tree_code_name[(int)TREE_CODE (ret_type)]);
+	}
+    }
+
+  *cum = zero_cum;
+
+  /* Determine if this function has variable arguments.  This is
+     indicated by the last argument being 'void_type_mode' if there
+     are no variable arguments.  The standard MIPS calling sequence
+     passes all arguments in the general purpose registers in this case. */
+
+  for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
+       param != 0; param = next_param)
+    {
+      next_param = TREE_CHAIN (param);
+      if (next_param == 0 && TREE_VALUE (param) != void_type_node)
+	cum->gp_reg_found = 1;
+    }
+}
+
+/* Advance the argument to the next argument position.  */
+
+void
+function_arg_advance (cum, mode, type, named)
+     CUMULATIVE_ARGS *cum;	/* current arg information */
+     enum machine_mode mode;	/* current arg mode */
+     tree type;			/* type of the argument or 0 if lib support */
+     int named;			/* whether or not the argument was named */
+{
+  if (TARGET_DEBUG_E_MODE)
+    {
+      fprintf (stderr,
+	       "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
+	       cum->gp_reg_found, cum->arg_number, cum->arg_words,
+	       GET_MODE_NAME (mode));
+      fprintf (stderr, HOST_PTR_PRINTF, type);
+      fprintf (stderr, ", %d )\n\n", named);
+    }
+
+  cum->arg_number++;
+  switch (mode)
+    {
+    case VOIDmode:
+      break;
+
+    default:
+      if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
+	  && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
+	abort ();
+
+      cum->gp_reg_found = 1;
+      cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
+			 / UNITS_PER_WORD);
+      break;
+
+    case BLKmode:
+      cum->gp_reg_found = 1;
+      cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
+			 / UNITS_PER_WORD);
+      break;
+
+    case SFmode:
+      if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
+	cum->fp_arg_words++;
+      else
+	cum->arg_words++;
+      if (! cum->gp_reg_found && cum->arg_number <= 2)
+	cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
+      break;
+
+    case DFmode:
+      if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
+	cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
+      else
+	cum->arg_words += (TARGET_64BIT ? 1 : 2);
+      if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
+	cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
+      break;
+
+    case DImode:
+      cum->gp_reg_found = 1;
+      cum->arg_words += (TARGET_64BIT ? 1 : 2);
+      break;
+
+
+    case QImode:
+    case HImode:
+    case SImode:
+      cum->gp_reg_found = 1;
+      cum->arg_words++;
+      break;
+    }
+}
+
+/* Return an RTL expression containing the register for the given mode,
+   or 0 if the argument is to be passed on the stack.  */
+
+struct rtx_def *
+function_arg (cum, mode, type, named)
+     CUMULATIVE_ARGS *cum;	/* current arg information */
+     enum machine_mode mode;	/* current arg mode */
+     tree type;			/* type of the argument or 0 if lib support */
+     int named;			/* != 0 for normal args, == 0 for ... args */
+{
+  rtx ret;
+  int regbase = -1;
+  int bias = 0;
+  int *arg_words = &cum->arg_words;
+  int struct_p = (type != 0
+		  && (TREE_CODE (type) == RECORD_TYPE
+		      || TREE_CODE (type) == UNION_TYPE
+		      || TREE_CODE (type) == QUAL_UNION_TYPE));
+
+  if (TARGET_DEBUG_E_MODE)
+    {
+      fprintf (stderr,
+	       "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
+	       cum->gp_reg_found, cum->arg_number, cum->arg_words,
+	       GET_MODE_NAME (mode));
+      fprintf (stderr, HOST_PTR_PRINTF, type);
+      fprintf (stderr, ", %d ) = ", named);
+    }
+  
+
+  cum->last_arg_fp = 0;
+  switch (mode)
+    {
+    case SFmode:
+      if (mips_abi == ABI_32 || mips_abi == ABI_O64)
+	{
+	  if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
+	    regbase = GP_ARG_FIRST;
+	  else
+	    {
+	      regbase = FP_ARG_FIRST;
+
+	      /* If the first arg was a float in a floating point register,
+		 then set bias to align this float arg properly.  */
+	      if (cum->arg_words == 1)
+		bias = 1;
+	    }
+	}
+      else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
+	{
+	  if (! TARGET_64BIT)
+	    cum->fp_arg_words += cum->fp_arg_words & 1;
+	  cum->last_arg_fp = 1;
+	  arg_words = &cum->fp_arg_words;
+	  regbase = FP_ARG_FIRST;
+	}
+      else
+	regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
+      break;
+
+    case DFmode:
+      if (! TARGET_64BIT)
+	{
+	  if (mips_abi == ABI_EABI
+	      && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
+	    cum->fp_arg_words += cum->fp_arg_words & 1;
+	  else
+	    cum->arg_words += cum->arg_words & 1;
+	}
+
+      if (mips_abi == ABI_32 || mips_abi == ABI_O64)
+	regbase = ((cum->gp_reg_found
+		    || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
+		    || cum->arg_number >= 2)
+		   ? GP_ARG_FIRST : FP_ARG_FIRST);
+      else if (mips_abi == ABI_EABI
+	       && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
+	{
+	  cum->last_arg_fp = 1;
+	  arg_words = &cum->fp_arg_words;
+	  regbase = FP_ARG_FIRST;
+	}
+      else
+	regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
+		   ? GP_ARG_FIRST : FP_ARG_FIRST);
+      break;
+
+    default:
+      if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
+	  && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
+	abort ();
+
+      /* Drops through.  */
+    case BLKmode:
+      if (type != (tree)0 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
+	  && ! TARGET_64BIT && mips_abi != ABI_EABI)
+	cum->arg_words += (cum->arg_words & 1);
+      regbase = GP_ARG_FIRST;
+      break;
+
+    case VOIDmode:
+    case QImode:
+    case HImode:
+    case SImode:
+      regbase = GP_ARG_FIRST;
+      break;
+
+    case DImode:
+      if (! TARGET_64BIT)
+	cum->arg_words += (cum->arg_words & 1);
+      regbase = GP_ARG_FIRST;
+      break;
+
+    }
+
+  if (*arg_words >= MAX_ARGS_IN_REGISTERS)
+    {
+      if (TARGET_DEBUG_E_MODE)
+	fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
+
+      ret = 0;
+    }
+  else
+    {
+      if (regbase == -1)
+	abort ();
+
+      if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
+	  || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named)
+	ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
+      else
+	{
+	  /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
+	     structure contains a double in its entirety, then that 64 bit
+	     chunk is passed in a floating point register.  */
+	  tree field;
+
+	  /* First check to see if there is any such field.  */
+	  for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
+	    if (TREE_CODE (field) == FIELD_DECL
+		&& TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
+		&& TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
+		&& (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
+		    % BITS_PER_WORD == 0))
+	      break;
+
+	  /* If the whole struct fits a DFmode register,
+	     we don't need the PARALLEL.  */
+	  if (! field || mode == DFmode)
+	    ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
+	  else
+	    {
+	      /* Now handle the special case by returning a PARALLEL
+		 indicating where each 64 bit chunk goes.  */
+	      int chunks;
+	      int bitpos;
+	      int regno;
+	      int i;
+
+	      /* ??? If this is a packed structure, then the last hunk won't
+		 be 64 bits.  */
+
+	      chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD;
+	      if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS)
+		chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
+
+	      /* assign_parms checks the mode of ENTRY_PARM, so we must
+		 use the actual mode here.  */
+	      ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks));
+
+	      bitpos = 0;
+	      regno = regbase + *arg_words + bias;
+	      field = TYPE_FIELDS (type);
+	      for (i = 0; i < chunks; i++)
+		{
+		  rtx reg;
+
+		  for (; field; field = TREE_CHAIN (field))
+		    if (TREE_CODE (field) == FIELD_DECL
+			&& (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
+			    >= bitpos))
+		      break;
+
+		  if (field
+		      && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos
+		      && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
+		      && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
+		    reg = gen_rtx (REG, DFmode,
+				   regno + FP_ARG_FIRST - GP_ARG_FIRST);
+		  else
+		    reg = gen_rtx (REG, word_mode, regno);
+
+		  XVECEXP (ret, 0, i) 
+		    = gen_rtx (EXPR_LIST, VOIDmode, reg,
+			       GEN_INT (bitpos / BITS_PER_UNIT));
+
+		  bitpos += 64;
+		  regno++;
+		}
+	    }
+	}
+
+      if (TARGET_DEBUG_E_MODE)
+	fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
+		 struct_p ? ", [struct]" : "");
+
+      /* The following is a hack in order to pass 1 byte structures
+	 the same way that the MIPS compiler does (namely by passing
+	 the structure in the high byte or half word of the register).
+	 This also makes varargs work.  If we have such a structure,
+	 we save the adjustment RTL, and the call define expands will
+	 emit them.  For the VOIDmode argument (argument after the
+	 last real argument), pass back a parallel vector holding each
+	 of the adjustments.  */
+
+      /* ??? function_arg can be called more than once for each argument.
+	 As a result, we compute more adjustments than we need here.
+	 See the CUMULATIVE_ARGS definition in mips.h.  */
+
+      /* ??? This scheme requires everything smaller than the word size to
+	 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
+	 that would mean every int needs to be shifted left, which is very
+	 inefficient.  Let's not carry this compatibility to the 64 bit
+	 calling convention for now.  */
+
+      if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
+	  && ! TARGET_64BIT && mips_abi != ABI_EABI)
+	{
+	  rtx amount = GEN_INT (BITS_PER_WORD
+				- int_size_in_bytes (type) * BITS_PER_UNIT);
+	  rtx reg = gen_rtx (REG, word_mode, regbase + *arg_words + bias);
+
+	  if (TARGET_64BIT)
+	    cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
+	  else
+	    cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
+	}
+    }
+
+  /* We will be called with a mode of VOIDmode after the last argument
+     has been seen.  Whatever we return will be passed to the call
+     insn.  If we need any shifts for small structures, return them in
+     a PARALLEL; in that case, stuff the mips16 fp_code in as the
+     mode.  Otherwise, if we have need a mips16 fp_code, return a REG
+     with the code stored as the mode.  */
+  if (mode == VOIDmode)
+    {
+      if (cum->num_adjusts > 0)
+	ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
+		       gen_rtvec_v (cum->num_adjusts, cum->adjust));
+      else if (TARGET_MIPS16 && cum->fp_code != 0)
+	ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
+    }
+
+  return ret;
+}
+
+int
+function_arg_partial_nregs (cum, mode, type, named)
+     CUMULATIVE_ARGS *cum;	/* current arg information */
+     enum machine_mode mode;	/* current arg mode */
+     tree type;			/* type of the argument or 0 if lib support */
+     int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
+{
+  if ((mode == BLKmode
+       || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
+       || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
+      && cum->arg_words < MAX_ARGS_IN_REGISTERS
+      && mips_abi != ABI_EABI)
+    {
+      int words;
+      if (mode == BLKmode)
+	words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
+		 / UNITS_PER_WORD);
+      else
+	words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+
+      if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
+	return 0;		/* structure fits in registers */
+
+      if (TARGET_DEBUG_E_MODE)
+	fprintf (stderr, "function_arg_partial_nregs = %d\n",
+		 MAX_ARGS_IN_REGISTERS - cum->arg_words);
+
+      return MAX_ARGS_IN_REGISTERS - cum->arg_words;
+    }
+
+  else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
+	   && ! TARGET_64BIT && mips_abi != ABI_EABI)
+    {
+      if (TARGET_DEBUG_E_MODE)
+	fprintf (stderr, "function_arg_partial_nregs = 1\n");
+
+      return 1;
+    }
+
+  return 0;
+}
+
+/* Abort after printing out a specific insn.  */
+
+void
+abort_with_insn (insn, reason)
+     rtx insn;
+     char *reason;
+{
+  error (reason);
+  debug_rtx (insn);
+  abort ();
+}
+
+/* Write a message to stderr (for use in macros expanded in files that do not
+   include stdio.h).  */
+
+void
+trace (s, s1, s2)
+     char *s, *s1, *s2;
+{
+  fprintf (stderr, s, s1, s2);
+}
+
+/* Set up the threshold for data to go into the small data area, instead
+   of the normal data area, and detect any conflicts in the switches.  */
+
+void
+override_options ()
+{
+  register int i, start;
+  register int regno;
+  register enum machine_mode mode;
+
+  mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
+
+  if (mips_section_threshold <= 0)
+    target_flags &= ~MASK_GPOPT;
+  else if (optimize)
+    target_flags |= MASK_GPOPT;
+
+#ifndef MIPS_ISA_DEFAULT
+#define MIPS_ISA_DEFAULT 1
+#endif
+
+  /* If both single-float and soft-float are set, then clear the one that
+     was set by TARGET_DEFAULT, leaving the one that was set by the
+     user.  We assume here that the specs prevent both being set by the 
+     user. */
+#ifdef TARGET_DEFAULT
+  if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
+    target_flags &= ~(TARGET_DEFAULT&(MASK_SOFT_FLOAT|MASK_SINGLE_FLOAT));
+#endif
+
+  /* Get the architectural level.  */
+  if (mips_isa_string == 0)
+    mips_isa = MIPS_ISA_DEFAULT;
+
+  else if (ISDIGIT (*mips_isa_string))
+    {
+      mips_isa = atoi (mips_isa_string);
+      if (mips_isa == 16)
+	{
+	  /* -mno-mips16 overrides -mips16.  */
+	  if (mips_no_mips16_string == NULL)
+	    {
+	      target_flags |= MASK_MIPS16;
+	      if (TARGET_64BIT)
+		mips_isa = 3;
+	      else
+		mips_isa = MIPS_ISA_DEFAULT;
+	    }
+	  else
+	    {
+	      mips_isa = MIPS_ISA_DEFAULT;
+	    }
+	}
+      else if (mips_isa < 1 || mips_isa > 4)
+	{
+	  error ("-mips%d not supported", mips_isa);
+	  mips_isa = 1;
+	}
+    }
+
+  else
+    {
+      error ("bad value (%s) for -mips switch", mips_isa_string);
+      mips_isa = 1;
+    }
+
+#ifdef MIPS_ABI_DEFAULT
+  /* Get the ABI to use. */
+  if (mips_abi_string == (char *) 0)
+    mips_abi = MIPS_ABI_DEFAULT;
+  else if (! strcmp (mips_abi_string, "32"))
+    mips_abi = ABI_32;
+  else if (! strcmp (mips_abi_string, "o64"))
+    mips_abi = ABI_O64;
+  else if (! strcmp (mips_abi_string, "n32"))
+    mips_abi = ABI_N32;
+  else if (! strcmp (mips_abi_string, "64"))
+    mips_abi = ABI_64;
+  else if (! strcmp (mips_abi_string, "eabi"))
+    mips_abi = ABI_EABI;
+  else
+    error ("bad value (%s) for -mabi= switch", mips_abi_string);
+
+  /* A specified ISA defaults the ABI if it was not specified.  */
+  if (mips_abi_string == 0 && mips_isa_string 
+      && mips_abi != ABI_EABI && mips_abi != ABI_O64)
+    {
+      if (mips_isa <= 2)
+	mips_abi = ABI_32;
+      else
+	mips_abi = ABI_64;
+    }
+
+  /* A specified ABI defaults the ISA if it was not specified.  */
+  else if (mips_isa_string == 0 && mips_abi_string 
+	   && mips_abi != ABI_EABI && mips_abi != ABI_O64)
+    {
+      if (mips_abi == ABI_32)
+	mips_isa = 1;
+      else if (mips_abi == ABI_N32)
+	mips_isa = 3;
+      else
+	mips_isa = 4;
+    }
+
+  /* If both ABI and ISA were specified, check for conflicts.  */
+  else if (mips_isa_string && mips_abi_string)
+    {
+      if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64
+			     || mips_abi == ABI_O64))
+	  || (mips_isa >= 3 && mips_abi == ABI_32))
+	error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
+    }
+
+  /* Override TARGET_DEFAULT if necessary.  */
+  if (mips_abi == ABI_32)
+    target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
+
+  /* In the EABI in 64 bit mode, longs and pointers are 64 bits.  Likewise
+   for the SGI Irix6 N64 ABI.  */
+  if ((mips_abi == ABI_EABI && TARGET_64BIT)
+      || mips_abi == ABI_64)
+    target_flags |= MASK_LONG64;
+
+  /* ??? This doesn't work yet, so don't let people try to use it.  */
+  if (mips_abi == ABI_32)
+    error ("The -mabi=32 support does not work yet.");
+
+#else
+  if (mips_abi_string)
+    error ("This target does not support the -mabi switch.");
+#endif
+
+#ifdef MIPS_CPU_STRING_DEFAULT
+  /* ??? There is a minor inconsistency here.  If the user specifies an ISA
+     greater than that supported by the default processor, then the user gets
+     an error.  Normally, the compiler will just default to the base level cpu
+     for the indicated isa.  */
+  if (mips_cpu_string == 0)
+    mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
+#endif
+
+  /* Identify the processor type */
+  if (mips_cpu_string == 0
+      || !strcmp (mips_cpu_string, "default")
+      || !strcmp (mips_cpu_string, "DEFAULT"))
+    {
+      switch (mips_isa)
+	{
+	default:
+	  mips_cpu_string = "3000";
+	  mips_cpu = PROCESSOR_R3000;
+	  break;
+	case 2:
+	  mips_cpu_string = "6000";
+	  mips_cpu = PROCESSOR_R6000;
+	  break;
+	case 3:
+	  mips_cpu_string = "4000";
+	  mips_cpu = PROCESSOR_R4000;
+	  break;
+	case 4:
+	  mips_cpu_string = "8000";
+	  mips_cpu = PROCESSOR_R8000;
+	  break;
+	}
+    }
+
+  else
+    {
+      char *p = mips_cpu_string;
+      int seen_v = 0;
+
+      /* We need to cope with the various "vr" prefixes for the NEC 4300
+	 and 4100 processors.  */
+      if (*p == 'v' || *p == 'V')
+	seen_v = 1, p++;
+
+      if (*p == 'r' || *p == 'R')
+	p++;
+
+      /* Since there is no difference between a R2000 and R3000 in
+	 terms of the scheduler, we collapse them into just an R3000. */
+
+      mips_cpu = PROCESSOR_DEFAULT;
+      switch (*p)
+	{
+
+	case '2':
+	  if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
+	    mips_cpu = PROCESSOR_R3000;
+	  break;
+
+	case '3':
+	  if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
+	    mips_cpu = PROCESSOR_R3000;
+	  else if (!strcmp (p, "3900"))
+	    mips_cpu = PROCESSOR_R3900;
+	  break;
+
+	case '4':
+	  if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
+	    mips_cpu = PROCESSOR_R4000;
+          /* The vr4100 is a non-FP ISA III processor with some extra
+             instructions.  */
+	  else if (!strcmp (p, "4100"))
+	    {
+              mips_cpu = PROCESSOR_R4100;
+              target_flags |= MASK_SOFT_FLOAT ;
+	    }
+	  /* The vr4300 is a standard ISA III processor, but with a different
+	     pipeline.  */
+	  else if (!strcmp (p, "4300"))
+            mips_cpu = PROCESSOR_R4300;
+	  /* The r4400 is exactly the same as the r4000 from the compiler's
+	     viewpoint.  */
+	  else if (!strcmp (p, "4400"))
+	    mips_cpu = PROCESSOR_R4000;
+	  else if (!strcmp (p, "4600"))
+	    mips_cpu = PROCESSOR_R4600;
+	  else if (!strcmp (p, "4650"))
+	    mips_cpu = PROCESSOR_R4650;
+	  break;
+
+	case '5':
+	  if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
+	    mips_cpu = PROCESSOR_R5000;
+	  /* CYGNUS LOCAL vr5400/raeburn */
+	  else if (!strcmp (p, "5400"))
+	    mips_cpu = PROCESSOR_R5400;
+	  /* END CYGNUS LOCAL vr5400/raeburn */
+	  break;
+
+	case '6':
+	  if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
+	    mips_cpu = PROCESSOR_R6000;
+	  break;
+
+	case '8':
+	  if (!strcmp (p, "8000"))
+	    mips_cpu = PROCESSOR_R8000;
+	  break;
+
+	case 'o':
+	  if (!strcmp (p, "orion"))
+	    mips_cpu = PROCESSOR_R4600;
+	  break;
+	}
+
+      if (seen_v
+	  && mips_cpu != PROCESSOR_R4300
+	  && mips_cpu != PROCESSOR_R4100
+	  && mips_cpu != PROCESSOR_R5400 /* CYGNUS LOCAL vr5400/raeburn */
+	  && mips_cpu != PROCESSOR_R5000)
+	mips_cpu = PROCESSOR_DEFAULT;
+
+      if (mips_cpu == PROCESSOR_DEFAULT)
+	{
+	  error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
+	  mips_cpu_string = "default";
+	}
+    }
+
+  if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
+      || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
+      || ((mips_cpu == PROCESSOR_R4000
+           || mips_cpu == PROCESSOR_R4100
+           || mips_cpu == PROCESSOR_R4300
+	   || mips_cpu == PROCESSOR_R4600
+	   || mips_cpu == PROCESSOR_R4650)
+	  && mips_isa > 3))
+    error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
+
+  /* make sure sizes of ints/longs/etc. are ok */
+  if (mips_isa < 3)
+    {
+      if (TARGET_INT64)
+	fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
+
+      else if (TARGET_LONG64)
+	fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
+
+      else if (TARGET_FLOAT64)
+	fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
+
+      else if (TARGET_64BIT)
+	fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
+    }
+
+  if (mips_abi != ABI_32 && mips_abi != ABI_O64)
+    flag_pcc_struct_return = 0;
+
+  /* Tell halfpic.c that we have half-pic code if we do.  */
+  if (TARGET_HALF_PIC)
+    HALF_PIC_INIT ();
+
+  /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined.  We need
+     to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work.  */
+  /* ??? -non_shared turns off pic code generation, but this is not
+     implemented.  */
+  if (TARGET_ABICALLS)
+    {
+      mips_abicalls = MIPS_ABICALLS_YES;
+      flag_pic = 1;
+      if (mips_section_threshold > 0)
+	warning ("-G is incompatible with PIC code which is the default");
+    }
+  else
+    mips_abicalls = MIPS_ABICALLS_NO;
+
+  /* -membedded-pic is a form of PIC code suitable for embedded
+     systems.  All calls are made using PC relative addressing, and
+     all data is addressed using the $gp register.  This requires gas,
+     which does most of the work, and GNU ld, which automatically
+     expands PC relative calls which are out of range into a longer
+     instruction sequence.  All gcc really does differently is
+     generate a different sequence for a switch.  */
+  if (TARGET_EMBEDDED_PIC)
+    {
+      flag_pic = 1;
+      if (TARGET_ABICALLS)
+	warning ("-membedded-pic and -mabicalls are incompatible");
+
+      if (g_switch_set)
+	warning ("-G and -membedded-pic are incompatible");
+
+      /* Setting mips_section_threshold is not required, because gas
+	 will force everything to be GP addressable anyhow, but
+	 setting it will cause gcc to make better estimates of the
+	 number of instructions required to access a particular data
+	 item.  */
+      mips_section_threshold = 0x7fffffff;
+    }
+
+  /* This optimization requires a linker that can support a R_MIPS_LO16
+     relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
+     GNU ld has this support, but not all other MIPS linkers do, so we enable
+     this optimization only if the user requests it, or if GNU ld is the
+     standard linker for this configuration.  */
+  /* ??? This does not work when target addresses are DImode.
+     This is because we are missing DImode high/lo_sum patterns.  */
+  if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
+      && Pmode == SImode)
+    mips_split_addresses = 1;
+  else
+    mips_split_addresses = 0;
+
+  /* -mrnames says to use the MIPS software convention for register
+     names instead of the hardware names (ie, $a0 instead of $4).
+     We do this by switching the names in mips_reg_names, which the
+     reg_names points into via the REGISTER_NAMES macro.  */
+
+  if (TARGET_NAME_REGS)
+    bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names,
+	   sizeof (mips_reg_names));
+
+  /* When compiling for the mips16, we can not use floating point.  We
+     record the original hard float value in mips16_hard_float.  */
+  if (TARGET_MIPS16)
+    {
+      if (TARGET_SOFT_FLOAT)
+	mips16_hard_float = 0;
+      else
+	mips16_hard_float = 1;
+      target_flags |= MASK_SOFT_FLOAT;
+
+      /* Don't run the scheduler before reload, since it tends to
+         increase register pressure.  */
+      flag_schedule_insns = 0;
+    }
+
+  /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
+     to avoid using up another bit in target_flags.  */
+  if (mips_entry_string != NULL)
+    {
+      if (*mips_entry_string != '\0')
+	error ("Invalid option `entry%s'", mips_entry_string);
+
+      if (! TARGET_MIPS16)
+	warning ("-mentry is only meaningful with -mips-16");
+      else
+	mips_entry = 1;
+    }
+
+  /* We copy TARGET_MIPS16 into the mips16 global variable, so that
+     attributes can access it.  */
+  if (TARGET_MIPS16)
+    mips16 = 1;
+  else
+    mips16 = 0;
+
+  /* Initialize the high and low values for legitimate floating point
+     constants.  Rather than trying to get the accuracy down to the
+     last bit, just use approximate ranges.  */
+  dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
+  dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
+  sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
+  sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
+
+  mips_print_operand_punct['?'] = 1;
+  mips_print_operand_punct['#'] = 1;
+  mips_print_operand_punct['&'] = 1;
+  mips_print_operand_punct['!'] = 1;
+  mips_print_operand_punct['*'] = 1;
+  mips_print_operand_punct['@'] = 1;
+  mips_print_operand_punct['.'] = 1;
+  mips_print_operand_punct['('] = 1;
+  mips_print_operand_punct[')'] = 1;
+  mips_print_operand_punct['['] = 1;
+  mips_print_operand_punct[']'] = 1;
+  mips_print_operand_punct['<'] = 1;
+  mips_print_operand_punct['>'] = 1;
+  mips_print_operand_punct['{'] = 1;
+  mips_print_operand_punct['}'] = 1;
+  mips_print_operand_punct['^'] = 1;
+  mips_print_operand_punct['$'] = 1;
+  mips_print_operand_punct['+'] = 1;
+
+  mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
+  mips_char_to_class['e'] = M16_NA_REGS;
+  mips_char_to_class['t'] = T_REG;
+  mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
+  mips_char_to_class['h'] = HI_REG;
+  mips_char_to_class['l'] = LO_REG;
+  mips_char_to_class['a'] = HILO_REG;
+  mips_char_to_class['x'] = MD_REGS;
+  mips_char_to_class['b'] = ALL_REGS;
+  mips_char_to_class['y'] = GR_REGS;
+  mips_char_to_class['z'] = ST_REGS;
+
+  /* Set up array to map GCC register number to debug register number.
+     Ignore the special purpose register numbers.  */
+
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    mips_dbx_regno[i] = -1;
+
+  start = GP_DBX_FIRST - GP_REG_FIRST;
+  for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
+    mips_dbx_regno[i] = i + start;
+
+  start = FP_DBX_FIRST - FP_REG_FIRST;
+  for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
+    mips_dbx_regno[i] = i + start;
+
+  /* Set up array giving whether a given register can hold a given mode.
+     At present, restrict ints from being in FP registers, because reload
+     is a little enthusiastic about storing extra values in FP registers,
+     and this is not good for things like OS kernels.  Also, due to the
+     mandatory delay, it is as fast to load from cached memory as to move
+     from the FP register.  */
+
+  for (mode = VOIDmode;
+       mode != MAX_MACHINE_MODE;
+       mode = (enum machine_mode) ((int)mode + 1))
+    {
+      register int size		     = GET_MODE_SIZE (mode);
+      register enum mode_class class = GET_MODE_CLASS (mode);
+
+      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+	{
+	  register int temp;
+
+	  if (mode == CCmode)
+	    {
+	      if (mips_isa < 4)
+		temp = (regno == FPSW_REGNUM);
+	      else
+		temp = (ST_REG_P (regno) || GP_REG_P (regno)
+			|| FP_REG_P (regno));
+	    }
+
+
+	  else if (GP_REG_P (regno))
+	    temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
+
+	  else if (FP_REG_P (regno))
+	    temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
+		    && (class == MODE_FLOAT
+			|| class == MODE_COMPLEX_FLOAT
+			|| (TARGET_DEBUG_H_MODE && class == MODE_INT))
+		    && (! TARGET_SINGLE_FLOAT || size <= 4));
+
+	  else if (MD_REG_P (regno))
+	    temp = (class == MODE_INT
+		    && (size <= UNITS_PER_WORD
+			|| (regno == MD_REG_FIRST
+			    && size == 2 * UNITS_PER_WORD)));
+
+
+	  else
+	    temp = 0;
+
+	  mips_hard_regno_mode_ok[(int)mode][regno] = temp;
+	}
+    }
+
+  /* Save GPR registers in word_mode sized hunks.  word_mode hasn't been
+     initialized yet, so we can't use that here.  */
+
+  for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+    {
+      mips_reg_mode[regno] = TARGET_64BIT ? DImode : SImode;
+    }
+
+
+  /* CYGNUS LOCAL law */
+  {
+    int min_align = 2;
+    int max_align = 15;
+    int min_max_skip = 0;
+    int max_max_skip = 32767;
+
+    /* Validate -malign-loops= value, or provide default */
+    if (mips_align_loops_string)
+      {
+	if (TARGET_MIPS16)
+	  fatal ("the combination of -mips16 and -malign-loops is not supported");
+	mips_align_loops = atoi (mips_align_loops_string);
+	if (mips_align_loops < min_align || mips_align_loops > max_align)
+	  fatal ("-malign-loops=%d is not between %d and %d",
+	         mips_align_loops, min_align, max_align);
+      }
+    else
+      {
+	if (TARGET_MIPS16)
+	  mips_align_loops = 0;
+	else
+	  mips_align_loops = DEFAULT_LOOP_ALIGN;
+      }
+
+    /* Validate -malign-jumps= value, or provide default */
+    if (mips_align_jumps_string)
+      {
+	mips_align_jumps = atoi (mips_align_jumps_string);
+	if (mips_align_jumps < min_align || mips_align_jumps > max_align)
+	  fatal ("-malign-jumps=%d is not between %d and %d",
+	         mips_align_jumps, min_align, min_align);
+      }
+    else
+      mips_align_jumps = DEFAULT_JUMP_ALIGN;
+
+    /* Validate -malign-functions= value, or provide default */
+    if (mips_align_funcs_string)
+      {
+	mips_align_funcs = atoi (mips_align_funcs_string);
+	if (mips_align_funcs < min_align || mips_align_funcs > max_align)
+	  fatal ("-malign-functions=%d is not between %d and %d",
+	         mips_align_funcs, min_align, max_align);
+      }
+    else
+      mips_align_funcs = DEFAULT_FUNCTION_ALIGN;
+
+    /* Validate -mmax-skip-loops= value, or provide default */
+    if (mips_max_skip_loops_string)
+      {
+	mips_max_skip_loops = atoi (mips_max_skip_loops_string);
+	if (mips_max_skip_loops < min_max_skip
+	    || mips_max_skip_loops > max_max_skip)
+	  fatal ("-mmax-skip-loops=%d is not between %d and %d",
+		 mips_max_skip_loops, min_max_skip, max_max_skip);
+      }
+    else
+      mips_max_skip_loops = DEFAULT_LOOP_MAX_SKIP;
+
+    /* Validate -mmax-skip-jumps= value, or provide default */
+    if (mips_max_skip_jumps_string)
+      {
+	mips_max_skip_jumps = atoi (mips_max_skip_jumps_string);
+	if (mips_max_skip_jumps < min_max_skip
+	    || mips_max_skip_jumps > max_max_skip)
+	  fatal ("-mmax-skip-jumps=%d is not between %d and %d",
+		 mips_max_skip_jumps, min_max_skip, max_max_skip);
+      }
+    else
+      mips_max_skip_jumps = DEFAULT_JUMP_MAX_SKIP;
+
+    /* Validate -mmax-skip-functions= value, or provide default */
+    if (mips_max_skip_funcs_string)
+      {
+	mips_max_skip_funcs = atoi (mips_max_skip_funcs_string);
+	if (mips_max_skip_funcs < min_max_skip
+	    || mips_max_skip_funcs > max_max_skip)
+	  fatal ("-mmax-skip-functions=%d is not between 3 and %d",
+		 mips_max_skip_funcs, min_max_skip, max_max_skip);
+      }
+    else
+      mips_max_skip_funcs = DEFAULT_FUNCTION_MAX_SKIP;
+  }
+  /* END CYGNUS LOCAL */
+
+}
+/* On the mips16, we want to allocate $24 (T_REG) before other
+   registers for instructions for which it is possible.  This helps
+   avoid shuffling registers around in order to set up for an xor,
+   encouraging the compiler to use a cmp instead.  */
+
+void
+mips_order_regs_for_local_alloc ()
+{
+  register int i;
+
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    reg_alloc_order[i] = i;
+
+  if (TARGET_MIPS16)
+    {
+      /* It really doesn't matter where we put register 0, since it is
+         a fixed register anyhow.  */
+      reg_alloc_order[0] = 24;
+      reg_alloc_order[24] = 0;
+    }
+}
+
+
+/* The MIPS debug format wants all automatic variables and arguments
+   to be in terms of the virtual frame pointer (stack pointer before
+   any adjustment in the function), while the MIPS 3.0 linker wants
+   the frame pointer to be the stack pointer after the initial
+   adjustment.  So, we do the adjustment here.  The arg pointer (which
+   is eliminated) points to the virtual frame pointer, while the frame
+   pointer (which may be eliminated) points to the stack pointer after
+   the initial adjustments.  */
+
+HOST_WIDE_INT
+mips_debugger_offset (addr, offset)
+     rtx addr;
+     HOST_WIDE_INT offset;
+{
+  rtx offset2 = const0_rtx;
+  rtx reg = eliminate_constant_term (addr, &offset2);
+
+  if (offset == 0)
+    offset = INTVAL (offset2);
+
+  if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
+      || reg == hard_frame_pointer_rtx)
+    {
+      HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
+				  ? compute_frame_size (get_frame_size ())
+				  : current_frame_info.total_size;
+
+      /* MIPS16 frame is smaller */
+      if (frame_pointer_needed && TARGET_MIPS16)
+	frame_size -= current_function_outgoing_args_size;
+
+      offset = offset - frame_size;
+    }
+
+  /* sdbout_parms does not want this to crash for unrecognized cases.  */
+#if 0
+  else if (reg != arg_pointer_rtx)
+    abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
+#endif
+
+  return offset;
+}
+
+/* A C compound statement to output to stdio stream STREAM the
+   assembler syntax for an instruction operand X.  X is an RTL
+   expression.
+
+   CODE is a value that can be used to specify one of several ways
+   of printing the operand.  It is used when identical operands
+   must be printed differently depending on the context.  CODE
+   comes from the `%' specification that was used to request
+   printing of the operand.  If the specification was just `%DIGIT'
+   then CODE is 0; if the specification was `%LTR DIGIT' then CODE
+   is the ASCII code for LTR.
+
+   If X is a register, this macro should print the register's name.
+   The names can be found in an array `reg_names' whose type is
+   `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
+
+   When the machine description has a specification `%PUNCT' (a `%'
+   followed by a punctuation character), this macro is called with
+   a null pointer for X and the punctuation character for CODE.
+
+   The MIPS specific codes are:
+
+   'X'  X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
+   'x'  X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
+   'd'  output integer constant in decimal,
+   'z'	if the operand is 0, use $0 instead of normal operand.
+   'D'  print second register of double-word register operand.
+   'L'  print low-order register of double-word register operand.
+   'M'  print high-order register of double-word register operand.
+   'C'  print part of opcode for a branch condition.
+   'N'  print part of opcode for a branch condition, inverted.
+   'S'  X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
+   'B'  print 'z' for EQ, 'n' for NE
+   'b'  print 'n' for EQ, 'z' for NE
+   'T'  print 'f' for EQ, 't' for NE
+   't'  print 't' for EQ, 'f' for NE
+   'Z'  print register and a comma, but print nothing for $fcc0
+   '('	Turn on .set noreorder
+   ')'	Turn on .set reorder
+   '['	Turn on .set noat
+   ']'	Turn on .set at
+   '<'	Turn on .set nomacro
+   '>'	Turn on .set macro
+   '{'	Turn on .set volatile (not GAS)
+   '}'	Turn on .set novolatile (not GAS)
+   '&'	Turn on .set noreorder if filling delay slots
+   '*'	Turn on both .set noreorder and .set nomacro if filling delay slots
+   '!'	Turn on .set nomacro if filling delay slots
+   '#'	Print nop if in a .set noreorder section.
+   '?'	Print 'l' if we are to use a branch likely instead of normal branch.
+   '@'	Print the name of the assembler temporary register (at or $1).
+   '.'	Print the name of the register with a hard-wired zero (zero or $0).
+   '^'	Print the name of the pic call-through register (t9 or $25).
+   '$'	Print the name of the stack pointer register (sp or $29).
+   '+'	Print the name of the gp register (gp or $28).  */
+
+void
+print_operand (file, op, letter)
+     FILE *file;		/* file to write to */
+     rtx op;			/* operand to print */
+     int letter;		/* %<letter> or 0 */
+{
+  register enum rtx_code code;
+
+  if (PRINT_OPERAND_PUNCT_VALID_P (letter))
+    {
+      switch (letter)
+	{
+	case '?':
+	  if (mips_branch_likely)
+	    putc ('l', file);
+	  break;
+
+	case '@':
+	  fputs (reg_names [GP_REG_FIRST + 1], file);
+	  break;
+
+	case '^':
+	  fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
+	  break;
+
+	case '.':
+	  fputs (reg_names [GP_REG_FIRST + 0], file);
+	  break;
+
+	case '$':
+	  fputs (reg_names[STACK_POINTER_REGNUM], file);
+	  break;
+
+	case '+':
+	  fputs (reg_names[GP_REG_FIRST + 28], file);
+	  break;
+
+	case '&':
+	  if (final_sequence != 0 && set_noreorder++ == 0)
+	    fputs (".set\tnoreorder\n\t", file);
+	  break;
+
+	case '*':
+	  if (final_sequence != 0)
+	    {
+	      if (set_noreorder++ == 0)
+		fputs (".set\tnoreorder\n\t", file);
+
+	      if (set_nomacro++ == 0)
+		fputs (".set\tnomacro\n\t", file);
+	    }
+	  break;
+
+	case '!':
+	  if (final_sequence != 0 && set_nomacro++ == 0)
+	    fputs ("\n\t.set\tnomacro", file);
+	  break;
+
+	case '#':
+	  if (set_noreorder != 0)
+	    fputs ("\n\tnop", file);
+	  else if (TARGET_STATS)
+	    fputs ("\n\t#nop", file);
+
+	  break;
+
+	case '(':
+	  if (set_noreorder++ == 0)
+	    fputs (".set\tnoreorder\n\t", file);
+	  break;
+
+	case ')':
+	  if (set_noreorder == 0)
+	    error ("internal error: %%) found without a %%( in assembler pattern");
+
+	  else if (--set_noreorder == 0)
+	    fputs ("\n\t.set\treorder", file);
+
+	  break;
+
+	case '[':
+	  if (set_noat++ == 0)
+	    fputs (".set\tnoat\n\t", file);
+	  break;
+
+	case ']': 
+	  if (set_noat == 0)
+	    error ("internal error: %%] found without a %%[ in assembler pattern");
+	  else if (--set_noat == 0)
+	    fputs ("\n\t.set\tat", file);
+
+	  break;
+
+	case '<':
+	  if (set_nomacro++ == 0)
+	    fputs (".set\tnomacro\n\t", file);
+	  break;
+
+	case '>':
+	  if (set_nomacro == 0)
+	    error ("internal error: %%> found without a %%< in assembler pattern");
+	  else if (--set_nomacro == 0)
+	    fputs ("\n\t.set\tmacro", file);
+
+	  break;
+
+	case '{':
+	  if (set_volatile++ == 0)
+	    fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
+	  break;
+
+	case '}':
+	  if (set_volatile == 0)
+	    error ("internal error: %%} found without a %%{ in assembler pattern");
+	  else if (--set_volatile == 0)
+	    fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
+
+	  break;
+
+	default:
+	  error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
+	  break;
+	}
+
+      return;
+    }
+
+  if (! op)
+    {
+      error ("PRINT_OPERAND null pointer");
+      return;
+    }
+
+  code = GET_CODE (op);
+
+  if (code == SIGN_EXTEND)
+    op = XEXP (op, 0), code = GET_CODE (op);
+
+  if (letter == 'C')
+    switch (code)
+      {
+      case EQ:	fputs ("eq",  file); break;
+      case NE:	fputs ("ne",  file); break;
+      case GT:	fputs ("gt",  file); break;
+      case GE:	fputs ("ge",  file); break;
+      case LT:	fputs ("lt",  file); break;
+      case LE:	fputs ("le",  file); break;
+      case GTU: fputs ("gtu", file); break;
+      case GEU: fputs ("geu", file); break;
+      case LTU: fputs ("ltu", file); break;
+      case LEU: fputs ("leu", file); break;
+      default:
+	abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
+      }
+
+  else if (letter == 'N')
+    switch (code)
+      {
+      case EQ:	fputs ("ne",  file); break;
+      case NE:	fputs ("eq",  file); break;
+      case GT:	fputs ("le",  file); break;
+      case GE:	fputs ("lt",  file); break;
+      case LT:	fputs ("ge",  file); break;
+      case LE:	fputs ("gt",  file); break;
+      case GTU: fputs ("leu", file); break;
+      case GEU: fputs ("ltu", file); break;
+      case LTU: fputs ("geu", file); break;
+      case LEU: fputs ("gtu", file); break;
+      default:
+	abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
+      }
+
+  else if (letter == 'S')
+    {
+      char buffer[100];
+
+      ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
+      assemble_name (file, buffer);
+    }
+
+  else if (letter == 'Z')
+    {
+      register int regnum;
+
+      if (code != REG)
+	abort ();
+
+      regnum = REGNO (op);
+      if (! ST_REG_P (regnum))
+	abort ();
+
+      if (regnum != ST_REG_FIRST)
+	fprintf (file, "%s,", reg_names[regnum]);
+    }
+
+  else if (code == REG || code == SUBREG)
+    {
+      register int regnum;
+
+      if (code == REG)
+	regnum = REGNO (op);
+      else
+	regnum = true_regnum (op);
+
+      if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
+	  || (letter == 'L' && WORDS_BIG_ENDIAN)
+	  || letter == 'D')
+	regnum++;
+
+      fprintf (file, "%s", reg_names[regnum]);
+    }
+
+  else if (code == MEM)
+    output_address (XEXP (op, 0));
+
+  else if (code == CONST_DOUBLE
+	   && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
+    {
+      REAL_VALUE_TYPE d;
+      char s[30];
+
+      REAL_VALUE_FROM_CONST_DOUBLE (d, op);
+      REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
+      fprintf (file, s);
+    }
+
+  else if (letter == 'x' && GET_CODE (op) == CONST_INT)
+    fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
+
+  else if (letter == 'X' && GET_CODE(op) == CONST_INT)
+    fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
+
+  else if (letter == 'd' && GET_CODE(op) == CONST_INT)
+    fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
+
+  else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+    fputs (reg_names[GP_REG_FIRST], file);
+
+  else if (letter == 'd' || letter == 'x' || letter == 'X')
+    fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT",
+	   letter);
+
+  else if (letter == 'B')
+    fputs (code == EQ ? "z" : "n", file);
+  else if (letter == 'b')
+    fputs (code == EQ ? "n" : "z", file);
+  else if (letter == 'T')
+    fputs (code == EQ ? "f" : "t", file);
+  else if (letter == 't')
+    fputs (code == EQ ? "t" : "f", file);
+
+  else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
+    {
+      /* This case arises on the mips16; see mips16_gp_pseudo_reg.  */
+      print_operand (file, XEXP (op, 0), letter);
+    }
+
+  else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
+    {
+      fputs ("%gprel(", file);
+      mips16_output_gp_offset (file, op);
+      fputs (")", file);
+    }
+
+  else
+    output_addr_const (file, op);
+}
+
+/* A C compound statement to output to stdio stream STREAM the
+   assembler syntax for an instruction operand that is a memory
+   reference whose address is ADDR.  ADDR is an RTL expression.
+
+   On some machines, the syntax for a symbolic address depends on
+   the section that the address refers to.  On these machines,
+   define the macro `ENCODE_SECTION_INFO' to store the information
+   into the `symbol_ref', and then check for it here.  */
+
+void
+print_operand_address (file, addr)
+     FILE *file;
+     rtx addr;
+{
+  if (!addr)
+    error ("PRINT_OPERAND_ADDRESS, null pointer");
+
+  else
+    switch (GET_CODE (addr))
+      {
+      case REG:
+	if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
+	  abort_with_insn (addr, "Arg pointer not eliminated.");
+
+	fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
+	break;
+
+      case LO_SUM:
+	{
+	  register rtx arg0 = XEXP (addr, 0);
+	  register rtx arg1 = XEXP (addr, 1);
+
+	  if (! mips_split_addresses)
+	    abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
+
+	  if (GET_CODE (arg0) != REG)
+	    abort_with_insn (addr,
+			     "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
+
+	  fprintf (file, "%%lo(");
+	  print_operand_address (file, arg1);
+	  fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
+	}
+	break;
+
+      case PLUS:
+	{
+	  register rtx reg = 0;
+	  register rtx offset = 0;
+	  register rtx arg0 = XEXP (addr, 0);
+	  register rtx arg1 = XEXP (addr, 1);
+
+	  if (GET_CODE (arg0) == REG)
+	    {
+	      reg = arg0;
+	      offset = arg1;
+	      if (GET_CODE (offset) == REG)
+		abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
+	    }
+
+	  else if (GET_CODE (arg1) == REG)
+	      reg = arg1, offset = arg0;
+	  else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
+	    {
+	      output_addr_const (file, addr);
+	      break;
+	    }
+	  else
+	    abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
+
+	  if (! CONSTANT_P (offset))
+	    abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
+
+	  if (REGNO (reg) == ARG_POINTER_REGNUM)
+	    abort_with_insn (addr, "Arg pointer not eliminated.");
+
+	  if (TARGET_MIPS16
+	      && GET_CODE (offset) == CONST
+	      && mips16_gp_offset_p (offset))
+	    {
+	      fputs ("%gprel(", file);
+	      mips16_output_gp_offset (file, offset);
+	      fputs (")", file);
+	    }
+	  else
+	    output_addr_const (file, offset);
+	  fprintf (file, "(%s)", reg_names [REGNO (reg)]);
+	}
+	break;
+
+      case LABEL_REF:
+      case SYMBOL_REF:
+      case CONST_INT:
+      case CONST:
+	output_addr_const (file, addr);
+	break;
+
+      default:
+	abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
+	break;
+    }
+}
+
+
+/* If optimizing for the global pointer, keep track of all of the externs, so
+   that at the end of the file, we can emit the appropriate .extern
+   declaration for them, before writing out the text section.  We assume all
+   names passed to us are in the permanent obstack, so they will be valid at
+   the end of the compilation.
+
+   If we have -G 0, or the extern size is unknown, or the object is in a user
+   specified section that is not .sbss/.sdata, don't bother emitting the
+   .externs.  In the case of user specified sections this behaviour is
+   required as otherwise GAS will think the object lives in .sbss/.sdata.  */
+
+int
+mips_output_external (file, decl, name)
+     FILE *file ATTRIBUTE_UNUSED;
+     tree decl;
+     char *name;
+{
+  register struct extern_list *p;
+  int len;
+  tree section_name;
+
+  if (TARGET_GP_OPT
+      && TREE_CODE (decl) != FUNCTION_DECL
+      && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
+      && ((section_name = DECL_SECTION_NAME (decl)) == NULL
+	  || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
+	  || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
+    {
+      p = (struct extern_list *) permalloc (sizeof (struct extern_list));
+      p->next = extern_head;
+      p->name = name;
+      p->size = len;
+      extern_head = p;
+    }
+
+#ifdef ASM_OUTPUT_UNDEF_FUNCTION
+  if (TREE_CODE (decl) == FUNCTION_DECL
+      /* ??? Don't include alloca, since gcc will always expand it
+	 inline.  If we don't do this, the C++ library fails to build.  */
+      && strcmp (name, "alloca")
+      /* ??? Don't include __builtin_next_arg, because then gcc will not
+	 bootstrap under Irix 5.1.  */
+      && strcmp (name, "__builtin_next_arg"))
+    {
+      p = (struct extern_list *) permalloc (sizeof (struct extern_list));
+      p->next = extern_head;
+      p->name = name;
+      p->size = -1;
+      extern_head = p;
+    }
+#endif
+
+  return 0;
+}
+
+#ifdef ASM_OUTPUT_UNDEF_FUNCTION
+int
+mips_output_external_libcall (file, name)
+     FILE *file;
+     char *name;
+{
+  register struct extern_list *p;
+
+  p = (struct extern_list *) permalloc (sizeof (struct extern_list));
+  p->next = extern_head;
+  p->name = name;
+  p->size = -1;
+  extern_head = p;
+
+  return 0;
+}
+#endif
+
+/* Compute a string to use as a temporary file name.  */
+
+/* On MSDOS, write temp files in current dir
+   because there's no place else we can expect to use.  */
+#if __MSDOS__
+#ifndef P_tmpdir
+#define P_tmpdir "./"
+#endif
+#endif
+
+static FILE *
+make_temp_file ()
+{
+  FILE *stream;
+  char *base = getenv ("TMPDIR");
+  int len;
+
+  if (base == 0)
+    {
+#ifdef P_tmpdir
+      if (access (P_tmpdir, R_OK | W_OK) == 0)
+	base = P_tmpdir;
+      else
+#endif
+	if (access ("/usr/tmp", R_OK | W_OK) == 0)
+	  base = "/usr/tmp/";
+	else
+	  base = "/tmp/";
+    }
+
+  len = strlen (base);
+  /* temp_filename is global, so we must use malloc, not alloca.  */
+  temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
+  strcpy (temp_filename, base);
+  if (len > 0 && temp_filename[len-1] != '/')
+    temp_filename[len++] = '/';
+
+  strcpy (temp_filename + len, "ctXXXXXX");
+  mktemp (temp_filename);
+
+  stream = fopen (temp_filename, "w+");
+  if (!stream)
+    pfatal_with_name (temp_filename);
+
+#ifndef __MSDOS__
+  /* In MSDOS, we cannot unlink the temporary file until we are finished using
+     it.  Otherwise, we delete it now, so that it will be gone even if the
+     compiler happens to crash.  */
+  unlink (temp_filename);
+#endif
+  return stream;
+}
+
+/* Emit a new filename to a stream.  If this is MIPS ECOFF, watch out
+   for .file's that start within a function.  If we are smuggling stabs, try to
+   put out a MIPS ECOFF file and a stab.  */
+
+void
+mips_output_filename (stream, name)
+     FILE *stream;
+     char *name;
+{
+  static int first_time = 1;
+  char ltext_label_name[100];
+
+  if (first_time)
+    {
+      first_time = 0;
+      SET_FILE_NUMBER ();
+      current_function_file = name;
+      ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
+      /* This tells mips-tfile that stabs will follow.  */
+      if (!TARGET_GAS && write_symbols == DBX_DEBUG)
+	fprintf (stream, "\t#@stabs\n");
+    }
+
+  else if (write_symbols == DBX_DEBUG)
+    {
+      ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
+      fprintf (stream, "%s ", ASM_STABS_OP);
+      output_quoted_string (stream, name);
+      fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
+    }
+
+  else if (name != current_function_file
+      && strcmp (name, current_function_file) != 0)
+    {
+      if (inside_function && !TARGET_GAS)
+	{
+	  if (!file_in_function_warning)
+	    {
+	      file_in_function_warning = 1;
+	      ignore_line_number = 1;
+	      warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
+	    }
+	}
+      else
+	{
+	  SET_FILE_NUMBER ();
+	  current_function_file = name;
+	  ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
+	}
+    }
+}
+
+/* Emit a linenumber.  For encapsulated stabs, we need to put out a stab
+   as well as a .loc, since it is possible that MIPS ECOFF might not be
+   able to represent the location for inlines that come from a different
+   file.  */
+
+void
+mips_output_lineno (stream, line)
+     FILE *stream;
+     int line;
+{
+  if (write_symbols == DBX_DEBUG)
+    {
+      ++sym_lineno;
+      fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
+	       LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
+	       LOCAL_LABEL_PREFIX, sym_lineno);
+    }
+
+  else
+    {
+      fprintf (stream, "\n\t%s.loc\t%d %d\n",
+	       (ignore_line_number) ? "#" : "",
+	       num_source_filenames, line);
+  
+      LABEL_AFTER_LOC (stream);
+    }
+}
+
+/* If defined, a C statement to be executed just prior to the output of
+   assembler code for INSN, to modify the extracted operands so they will be
+   output differently.
+
+   Here the argument OPVEC is the vector containing the operands extracted
+   from INSN, and NOPERANDS is the number of elements of the vector which
+   contain meaningful data for this insn.  The contents of this vector are
+   what will be used to convert the insn template into assembler code, so you
+   can change the assembler output by changing the contents of the vector.
+
+   We use it to check if the current insn needs a nop in front of it because
+   of load delays, and also to update the delay slot statistics.  */
+
+/* ??? There is no real need for this function, because it never actually
+   emits a NOP anymore.  */
+
+void
+final_prescan_insn (insn, opvec, noperands)
+     rtx insn;
+     rtx opvec[] ATTRIBUTE_UNUSED;
+     int noperands ATTRIBUTE_UNUSED;
+{
+  if (dslots_number_nops > 0)
+    {
+      rtx pattern = PATTERN (insn);
+      int length = get_attr_length (insn);
+
+      /* Do we need to emit a NOP? */
+      if (length == 0
+	  || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg,  pattern))
+	  || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
+	  || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
+	  || (mips_load_reg4 != 0
+	      && reg_mentioned_p (mips_load_reg4, pattern)))
+	fputs ("\t#nop\n", asm_out_file);
+
+      else
+	dslots_load_filled++;
+
+      while (--dslots_number_nops > 0)
+	fputs ("\t#nop\n", asm_out_file);
+
+      mips_load_reg = 0;
+      mips_load_reg2 = 0;
+      mips_load_reg3 = 0;
+      mips_load_reg4 = 0;
+    }
+
+  if (TARGET_STATS
+      && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
+    dslots_jump_total++;
+}
+
+/* Output at beginning of assembler file.
+
+   If we are optimizing to use the global pointer, create a temporary file to
+   hold all of the text stuff, and write it out to the end. This is needed
+   because the MIPS assembler is evidently one pass, and if it hasn't seen the
+   relevant .comm/.lcomm/.extern/.sdata declaration when the code is
+   processed, it generates a two instruction sequence.  */
+
+void
+mips_asm_file_start (stream)
+     FILE *stream;
+{
+  ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
+
+  /* Versions of the MIPS assembler before 2.20 generate errors if a branch
+     inside of a .set noreorder section jumps to a label outside of the .set
+     noreorder section.  Revision 2.20 just set nobopt silently rather than
+     fixing the bug.  */
+
+  if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
+    fprintf (stream, "\t.set\tnobopt\n");
+
+  /* Generate the pseudo ops that System V.4 wants.  */
+#ifndef ABICALLS_ASM_OP
+#define ABICALLS_ASM_OP ".abicalls"
+#endif
+  if (TARGET_ABICALLS)
+    /* ??? but do not want this (or want pic0) if -non-shared? */
+    fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
+
+  if (TARGET_MIPS16)
+    fprintf (stream, "\t.set\tmips16\n");
+
+  /* Start a section, so that the first .popsection directive is guaranteed
+     to have a previously defined section to pop back to.  */
+  if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
+    fprintf (stream, "\t.section\t.text\n");
+
+  /* This code exists so that we can put all externs before all symbol
+     references.  This is necessary for the MIPS assembler's global pointer
+     optimizations to work.  */
+  if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
+    {
+      asm_out_data_file = stream;
+      asm_out_text_file = make_temp_file ();
+    }
+
+  else
+    asm_out_data_file = asm_out_text_file = stream;
+
+  if (flag_verbose_asm)
+    fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
+	     ASM_COMMENT_START,
+	     mips_section_threshold, mips_cpu_string, mips_isa);
+}
+
+/* If we are optimizing the global pointer, emit the text section now and any
+   small externs which did not have .comm, etc that are needed.  Also, give a
+   warning if the data area is more than 32K and -pic because 3 instructions
+   are needed to reference the data pointers.  */
+
+void
+mips_asm_file_end (file)
+     FILE *file;
+{
+  char buffer[8192];
+  tree name_tree;
+  struct extern_list *p;
+  int len;
+
+  if (HALF_PIC_P ())
+    {
+      HALF_PIC_FINISH (file);
+    }
+
+  if (extern_head)
+    {
+      fputs ("\n", file);
+
+      for (p = extern_head; p != 0; p = p->next)
+	{
+	  name_tree = get_identifier (p->name);
+
+	  /* Positively ensure only one .extern for any given symbol.  */
+	  if (! TREE_ASM_WRITTEN (name_tree))
+	    {
+	      TREE_ASM_WRITTEN (name_tree) = 1;
+#ifdef ASM_OUTPUT_UNDEF_FUNCTION
+	      if (p->size == -1)
+		ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
+	      else
+#endif
+		{
+		  fputs ("\t.extern\t", file);
+		  assemble_name (file, p->name);
+		  fprintf (file, ", %d\n", p->size);
+		}
+	    }
+	}
+    }
+      
+  if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
+    {
+      fprintf (file, "\n\t.text\n");
+      rewind (asm_out_text_file);
+      if (ferror (asm_out_text_file))
+	fatal_io_error (temp_filename);
+
+      while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
+	if ((int) fwrite (buffer, 1, len, file) != len)
+	  pfatal_with_name (asm_file_name);
+
+      if (len < 0)
+	pfatal_with_name (temp_filename);
+
+      if (fclose (asm_out_text_file) != 0)
+	pfatal_with_name (temp_filename);
+
+#ifdef __MSDOS__
+      unlink (temp_filename);
+#endif
+    }
+}
+
+/* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
+   is used, so that we don't emit an .extern for it in mips_asm_file_end.  */
+
+void
+mips_declare_object (stream, name, init_string, final_string, size)
+     FILE *stream;
+     char *name;
+     char *init_string;
+     char *final_string;
+     int size;
+{
+  fputs (init_string, stream);		/* "", "\t.comm\t", or "\t.lcomm\t" */
+  assemble_name (stream, name);
+  fprintf (stream, final_string, size);	/* ":\n", ",%u\n", ",%u\n" */
+
+  if (TARGET_GP_OPT)
+    {
+      tree name_tree = get_identifier (name);
+      TREE_ASM_WRITTEN (name_tree) = 1;
+    }
+}
+
+/* Output a double precision value to the assembler.  If both the
+   host and target are IEEE, emit the values in hex.  */
+
+void
+mips_output_double (stream, value)
+     FILE *stream;
+     REAL_VALUE_TYPE value;
+{
+#ifdef REAL_VALUE_TO_TARGET_DOUBLE
+  long value_long[2];
+  REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
+
+  fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
+	   value_long[0], value, value_long[1]);
+#else
+  fprintf (stream, "\t.double\t%.20g\n", value);
+#endif
+}
+
+/* Output a single precision value to the assembler.  If both the
+   host and target are IEEE, emit the values in hex.  */
+
+void
+mips_output_float (stream, value)
+     FILE *stream;
+     REAL_VALUE_TYPE value;
+{
+#ifdef REAL_VALUE_TO_TARGET_SINGLE
+  long value_long;
+  REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
+
+  fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
+#else
+  fprintf (stream, "\t.float\t%.12g\n", value);
+#endif
+}
+
+/* Return the bytes needed to compute the frame pointer from the current
+   stack pointer.
+
+   Mips stack frames look like:
+
+             Before call		        After call
+        +-----------------------+	+-----------------------+
+   high |			|       |      			|
+   mem. |		        |	|			|
+        |  caller's temps.    	|       |  caller's temps.    	|
+	|       		|       |       	        |
+        +-----------------------+	+-----------------------+
+ 	|       		|	|		        |
+        |  arguments on stack.  |	|  arguments on stack.  |
+	|       		|	|			|
+        +-----------------------+	+-----------------------+
+ 	|  4 words to save     	|	|  4 words to save	|
+	|  arguments passed	|	|  arguments passed	|
+	|  in registers, even	|	|  in registers, even	|
+    SP->|  if not passed.       |  VFP->|  if not passed.	|
+	+-----------------------+       +-----------------------+
+					|		        |
+                                        |  fp register save     |
+					|			|
+					+-----------------------+
+					|		        |
+                                        |  gp register save     |
+                                        |       		|
+					+-----------------------+
+					|			|
+					|  local variables	|
+					|			|
+					+-----------------------+
+					|			|
+                                        |  alloca allocations   |
+        				|			|
+					+-----------------------+
+					|			|
+					|  GP save for V.4 abi	|
+					|			|
+					+-----------------------+
+					|			|
+                                        |  arguments on stack   |
+        				|		        |
+					+-----------------------+
+                                        |  4 words to save      |
+					|  arguments passed     |
+                                        |  in registers, even   |
+   low                              SP->|  if not passed.       |
+   memory        			+-----------------------+
+
+*/
+
+HOST_WIDE_INT
+compute_frame_size (size)
+     HOST_WIDE_INT size;	/* # of var. bytes allocated */
+{
+  int regno;
+  HOST_WIDE_INT total_size;	/* # bytes that the entire frame takes up */
+  HOST_WIDE_INT var_size;	/* # bytes that variables take up */
+  HOST_WIDE_INT args_size;	/* # bytes that outgoing arguments take up */
+  HOST_WIDE_INT extra_size;	/* # extra bytes */
+  HOST_WIDE_INT gp_reg_rounded;	/* # bytes needed to store gp after rounding */
+  HOST_WIDE_INT gp_reg_size;	/* # bytes needed to store gp regs */
+  HOST_WIDE_INT fp_reg_size;	/* # bytes needed to store fp regs */
+  long mask;			/* mask of saved gp registers */
+  long fmask;			/* mask of saved fp registers */
+  int  fp_inc;			/* 1 or 2 depending on the size of fp regs */
+  long fp_bits;			/* bitmask to use for each fp register */
+
+  gp_reg_size = 0;
+  fp_reg_size = 0;
+  mask = 0;
+  fmask	= 0;
+  extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
+  var_size = MIPS_STACK_ALIGN (size);
+  args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
+
+  /* The MIPS 3.0 linker does not like functions that dynamically
+     allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
+     looks like we are trying to create a second frame pointer to the
+     function, so allocate some stack space to make it happy.  */
+
+  if (args_size == 0 && current_function_calls_alloca)
+    args_size = 4 * UNITS_PER_WORD;
+
+  total_size = var_size + args_size + extra_size;
+
+  /* Calculate space needed for gp registers.  */
+  for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+    {
+      /* $18 is a special case on the mips16.  It may be used to call
+         a function which returns a floating point value, but it is
+         marked in call_used_regs.  $31 is also a special case.  When
+         not using -mentry, it will be used to copy a return value
+         into the floating point registers if the return value is
+         floating point.  */
+      if (MUST_SAVE_REGISTER (regno)
+	  || (TARGET_MIPS16
+	      && regno == GP_REG_FIRST + 18
+	      && regs_ever_live[regno])
+	  || (TARGET_MIPS16
+	      && regno == GP_REG_FIRST + 31
+	      && mips16_hard_float
+	      && ! mips_entry
+	      && ! aggregate_value_p (DECL_RESULT (current_function_decl))
+	      && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
+		  == MODE_FLOAT)
+	      && (! TARGET_SINGLE_FLOAT
+		  || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
+		      <= 4))))
+	{
+	  gp_reg_size += GET_MODE_SIZE (mips_reg_mode[0]);
+	  mask |= 1L << (regno - GP_REG_FIRST);
+
+	  /* The entry and exit pseudo instructions can not save $17
+	     without also saving $16.  */
+	  if (mips_entry
+	      && regno == GP_REG_FIRST + 17
+	      && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
+	    {
+	      gp_reg_size += UNITS_PER_WORD;
+	      mask |= 1L << 16;
+	    }
+	}
+    }
+
+  /* Calculate space needed for fp registers.  */
+  if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
+    {
+      fp_inc = 1;
+      fp_bits = 1;
+    }
+  else
+    {
+      fp_inc = 2;
+      fp_bits = 3;
+    }
+
+  /* This loop must iterate over the same space as its companion in
+     save_restore_regs.  */
+  for (regno = (FP_REG_LAST - fp_inc + 1);
+       regno >= FP_REG_FIRST;
+       regno -= fp_inc)
+    {
+      if (regs_ever_live[regno] && !call_used_regs[regno])
+	{
+	  fp_reg_size += fp_inc * UNITS_PER_FPREG;
+	  fmask |= fp_bits << (regno - FP_REG_FIRST);
+	}
+    }
+
+  gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
+  total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
+
+  /* The gp reg is caller saved in the 32 bit ABI, so there is no need
+     for leaf routines (total_size == extra_size) to save the gp reg.
+     The gp reg is callee saved in the 64 bit ABI, so all routines must
+     save the gp reg.  This is not a leaf routine if -p, because of the
+     call to mcount.  */
+  if (total_size == extra_size 
+      && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
+      && ! profile_flag)
+    total_size = extra_size = 0;
+  else if (TARGET_ABICALLS)
+    {
+      /* Add the context-pointer to the saved registers.  */
+      gp_reg_size += UNITS_PER_WORD;
+      mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
+      total_size -= gp_reg_rounded;
+      gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
+      total_size += gp_reg_rounded;
+    }
+
+  /* Add in space reserved on the stack by the callee for storing arguments
+     passed in registers.  */
+  if (mips_abi != ABI_32 && mips_abi != ABI_O64)
+    total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
+
+  /* The entry pseudo instruction will allocate 32 bytes on the stack.  */
+  if (mips_entry && total_size > 0 && total_size < 32)
+    total_size = 32;
+
+  /* Save other computed information.  */
+  current_frame_info.total_size = total_size;
+  current_frame_info.var_size = var_size;
+  current_frame_info.args_size = args_size;
+  current_frame_info.extra_size = extra_size;
+  current_frame_info.gp_reg_size = gp_reg_size;
+  current_frame_info.fp_reg_size = fp_reg_size;
+  current_frame_info.mask = mask;
+  current_frame_info.fmask = fmask;
+  current_frame_info.initialized = reload_completed;
+  current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
+  current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
+
+  if (mask)
+    {
+      unsigned long offset;
+
+      /* When using mips_entry, the registers are always saved at the
+         top of the stack.  */
+      if (! mips_entry)
+	offset = (args_size + extra_size + var_size
+		  + gp_reg_size - GET_MODE_SIZE (mips_reg_mode[0]));
+      else
+	offset = total_size - GET_MODE_SIZE (mips_reg_mode[0]);
+
+      current_frame_info.gp_sp_offset = offset;
+      current_frame_info.gp_save_offset = offset - total_size;
+    }
+  else
+    {
+      current_frame_info.gp_sp_offset = 0;
+      current_frame_info.gp_save_offset = 0;
+    }
+
+  if (fmask)
+    {
+      unsigned long offset = (args_size + extra_size + var_size
+			      + gp_reg_rounded + fp_reg_size
+			      - fp_inc * UNITS_PER_FPREG);
+      current_frame_info.fp_sp_offset = offset;
+      current_frame_info.fp_save_offset = offset - total_size;
+    }
+  else
+    {
+      current_frame_info.fp_sp_offset = 0;
+      current_frame_info.fp_save_offset = 0;
+    }
+
+  /* Ok, we're done.  */
+  return total_size;
+}
+
+/* Common code to emit the insns (or to write the instructions to a file)
+   to save/restore registers.
+
+   Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
+   is not modified within save_restore_insns.  */
+
+#define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
+
+/* If modifying X uses a larger mode than in mips_reg_mode,
+   indicate that fact by setting mips_reg_mode.  */
+
+static
+void
+mips_check_reg_mode (x, set)
+     rtx x;
+     rtx set;
+{
+  if (GET_CODE (x) == REG 
+      && REGNO (x) <= GP_REG_LAST
+      && (GET_MODE_SIZE (GET_MODE (x))
+	  > GET_MODE_SIZE (mips_reg_mode[REGNO (x)])))
+    {
+      mips_reg_mode[REGNO (x)] = GET_MODE (x);
+    }
+}
+
+static void
+save_restore_insns (store_p, large_reg, large_offset, file)
+     int store_p;	/* true if this is prologue */
+     rtx large_reg;	/* register holding large offset constant or NULL */
+     long large_offset;	/* large constant offset value */
+     FILE *file;	/* file to write instructions instead of making RTL */
+{
+  long mask = current_frame_info.mask;
+  long fmask = current_frame_info.fmask;
+  int regno;
+  rtx base_reg_rtx;
+  HOST_WIDE_INT base_offset;
+  HOST_WIDE_INT gp_offset;
+  HOST_WIDE_INT fp_offset;
+  HOST_WIDE_INT end_offset;
+  rtx insn;
+
+
+  if (frame_pointer_needed
+      && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
+    abort ();
+
+  if (mask == 0 && fmask == 0)
+    return;
+
+  /* Save registers starting from high to low.  The debuggers prefer at least
+     the return register be stored at func+4, and also it allows us not to
+     need a nop in the epilog if at least one register is reloaded in
+     addition to return address.  */
+
+
+  /* Save GP registers if needed.  */
+  if (mask)
+    {
+      /* Pick which pointer to use as a base register.  For small frames, just
+	 use the stack pointer.  Otherwise, use a temporary register.  Save 2
+	 cycles if the save area is near the end of a large frame, by reusing
+	 the constant created in the prologue/epilogue to adjust the stack
+	 frame.  */
+
+      gp_offset = current_frame_info.gp_sp_offset;
+      end_offset
+	= gp_offset - (current_frame_info.gp_reg_size
+		       - GET_MODE_SIZE (mips_reg_mode[0]));
+
+      if (gp_offset < 0 || end_offset < 0)
+	fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
+	       (long) gp_offset, (long) end_offset);
+
+      /* If we see a large frame in mips16 mode, we save the registers
+         before adjusting the stack pointer, and load them afterward.  */
+      else if (TARGET_MIPS16 && large_offset > 32767)
+	base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
+
+      else if (gp_offset < 32768)
+	base_reg_rtx = stack_pointer_rtx, base_offset  = 0;
+
+      else if (large_reg != 0
+	       && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
+	       && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
+	{
+	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
+	  base_offset = large_offset;
+	  if (file == 0)
+	    {
+	      if (Pmode == DImode)
+		insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
+					      stack_pointer_rtx));
+	      else
+		insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
+					      stack_pointer_rtx));
+	      if (store_p)
+		RTX_FRAME_RELATED_P (insn) = 1;
+	    }
+	  else
+	    fprintf (file, "\t%s\t%s,%s,%s\n",
+		     Pmode == DImode ? "daddu" : "addu",
+		     reg_names[MIPS_TEMP2_REGNUM],
+		     reg_names[REGNO (large_reg)],
+		     reg_names[STACK_POINTER_REGNUM]);
+	}
+
+      else
+	{
+	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
+	  base_offset = gp_offset;
+	  if (file == 0)
+	    {
+	      rtx gp_offset_rtx = GEN_INT (gp_offset);
+
+	      /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
+		 bit, so make sure that we don't emit anything that can be
+		 split.  */
+	      /* ??? There is no DImode ori immediate pattern, so we can only
+		 do this for 32 bit code.  */
+	      if (large_int (gp_offset_rtx)
+		  && GET_MODE (base_reg_rtx) == SImode)
+		{
+		  insn = emit_move_insn (base_reg_rtx,
+					 GEN_INT (gp_offset & 0xffff0000));
+		  if (store_p)
+		    RTX_FRAME_RELATED_P (insn) = 1;
+		  insn
+		    = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
+					     GEN_INT (gp_offset & 0x0000ffff)));
+		  if (store_p)
+		    RTX_FRAME_RELATED_P (insn) = 1;
+		}
+	      else
+		{
+		  insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
+		  if (store_p)
+		    RTX_FRAME_RELATED_P (insn) = 1;
+		}
+
+	      if (Pmode == DImode)
+		insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
+				 	      stack_pointer_rtx));
+	      else
+		insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
+					      stack_pointer_rtx));
+	      if (store_p)
+		RTX_FRAME_RELATED_P (insn) = 1;
+	    }
+	  else
+	    {
+	      fprintf (file, "\tli\t%s,0x%.08lx\t# ",
+		       reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
+	      fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
+	      fprintf (file, "\n\t%s\t%s,%s,%s\n",
+		       Pmode == DImode ? "daddu" : "addu",
+		       reg_names[MIPS_TEMP2_REGNUM],
+		       reg_names[MIPS_TEMP2_REGNUM],
+		       reg_names[STACK_POINTER_REGNUM]);
+	    }
+	}
+
+      /* When we restore the registers in MIPS16 mode, then if we are
+         using a frame pointer, and this is not a large frame, the
+         current stack pointer will be offset by
+         current_function_outgoing_args_size.  Doing it this way lets
+         us avoid offsetting the frame pointer before copying it into
+         the stack pointer; there is no instruction to set the stack
+         pointer to the sum of a register and a constant.  */
+      if (TARGET_MIPS16
+	  && ! store_p
+	  && frame_pointer_needed
+	  && large_offset <= 32767)
+	base_offset += current_function_outgoing_args_size;
+
+      for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
+	if (BITSET_P (mask, regno - GP_REG_FIRST))
+	  {
+	    if (file == 0)
+	      {
+		rtx reg_rtx;
+		rtx mem_rtx
+		  = gen_rtx (MEM,
+			     mips_reg_mode[regno],
+			     gen_rtx (PLUS, Pmode, base_reg_rtx,
+				      GEN_INT (gp_offset - base_offset)));
+
+		RTX_UNCHANGING_P (mem_rtx) = 1;
+
+		/* The mips16 does not have an instruction to load
+                   $31, so we load $7 instead, and work things out
+                   in the caller.  */
+		if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
+		  reg_rtx = gen_rtx (REG, mips_reg_mode[7], GP_REG_FIRST + 7);
+		/* The mips16 sometimes needs to save $18.  */
+		else if (TARGET_MIPS16
+			 && regno != GP_REG_FIRST + 31
+			 && ! M16_REG_P (regno))
+		  {
+		    if (! store_p)
+		      reg_rtx = gen_rtx (REG, mips_reg_mode[6], 6);
+		    else
+		      {
+			reg_rtx = gen_rtx (REG, mips_reg_mode[3], 3);
+			emit_move_insn (reg_rtx,
+					gen_rtx (REG, mips_reg_mode[regno],
+						 regno));
+		      }
+		  }
+		else
+		      reg_rtx = gen_rtx (REG,
+					 mips_reg_mode[regno],
+					 regno);
+		if (store_p)
+		  {
+		    insn = emit_move_insn (mem_rtx, reg_rtx);
+		    RTX_FRAME_RELATED_P (insn) = 1;
+		  }
+		else if (!TARGET_ABICALLS 
+			 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
+			 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
+		  {
+		    emit_move_insn (reg_rtx, mem_rtx);
+		    if (TARGET_MIPS16
+			&& regno != GP_REG_FIRST + 31
+			&& ! M16_REG_P (regno))
+		      emit_move_insn (gen_rtx (REG, mips_reg_mode[regno],
+					       regno),
+				      reg_rtx);
+		  }
+	      }
+	    else
+	      {
+		if (store_p || !TARGET_ABICALLS 
+		    || (mips_abi != ABI_32 && mips_abi != ABI_O64)
+		    || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
+		  {
+		    int r = regno;
+
+		    /* The mips16 does not have an instruction to
+                       load $31, so we load $7 instead, and work
+                       things out in the caller.  */
+		    if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
+		      r = GP_REG_FIRST + 7;
+		      /* The mips16 sometimes needs to save $18.  */
+		    if (TARGET_MIPS16
+			&& regno != GP_REG_FIRST + 31
+			&& ! M16_REG_P (regno))
+		      {
+			if (! store_p)
+			  r = GP_REG_FIRST + 6;
+			else
+			  {
+			    r = GP_REG_FIRST + 3;
+			    fprintf (file, "\tmove\t%s,%s\n",
+				     reg_names[r], reg_names[regno]);
+			  }
+		      }
+		    fprintf (file, "\t%s\t%s,",
+			     (TARGET_64BIT
+			      ? (store_p) ? "sd" : "ld"
+			      : (store_p) ? "sw" : "lw"),
+			     reg_names[r]);
+		    fprintf (file, HOST_WIDE_INT_PRINT_DEC, 
+			     gp_offset - base_offset);
+		    fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
+		    if (! store_p
+			&& TARGET_MIPS16
+			&& regno != GP_REG_FIRST + 31
+			&& ! M16_REG_P (regno))
+		      fprintf (file, "\tmove\t%s,%s\n",
+			       reg_names[regno], reg_names[r]);
+		  }
+
+	      }
+	    gp_offset -= GET_MODE_SIZE (mips_reg_mode[0]);
+	  }
+    }
+  else
+    base_reg_rtx = 0, base_offset  = 0;
+
+  /* Save floating point registers if needed.  */
+  if (fmask)
+    {
+      int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
+      int fp_size = fp_inc * UNITS_PER_FPREG;
+
+      /* Pick which pointer to use as a base register.  */
+      fp_offset = current_frame_info.fp_sp_offset;
+      end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
+
+      if (fp_offset < 0 || end_offset < 0)
+	fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
+	       (long) fp_offset, (long) end_offset);
+
+      else if (fp_offset < 32768)
+	base_reg_rtx = stack_pointer_rtx, base_offset  = 0;
+
+      else if (base_reg_rtx != 0
+	       && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
+	       && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
+	;			/* already set up for gp registers above */
+
+      else if (large_reg != (rtx)0
+	       && (((unsigned HOST_WIDE_INT)(large_offset - fp_offset))  < 32768)
+	       && (((unsigned HOST_WIDE_INT)(large_offset - end_offset)) < 32768))
+	{
+	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
+	  base_offset = large_offset;
+	  if (file == 0)
+	    {
+	      if (Pmode == DImode)
+		insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
+					      stack_pointer_rtx));
+	      else
+		insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
+					      stack_pointer_rtx));
+	      if (store_p)
+		RTX_FRAME_RELATED_P (insn) = 1;
+	    }
+
+	  else
+	    fprintf (file, "\t%s\t%s,%s,%s\n",
+		     Pmode == DImode ? "daddu" : "addu",
+		     reg_names[MIPS_TEMP2_REGNUM],
+		     reg_names[REGNO (large_reg)],
+		     reg_names[STACK_POINTER_REGNUM]);
+	}
+
+      else
+	{
+	  base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
+	  base_offset = fp_offset;
+	  if (file == 0)
+	    {
+	      rtx fp_offset_rtx = GEN_INT (fp_offset);
+
+	      /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
+		 bit, so make sure that we don't emit anything that can be
+		 split.  */
+	      /* ??? There is no DImode ori immediate pattern, so we can only
+		 do this for 32 bit code.  */
+	      if (large_int (fp_offset_rtx)
+		  && GET_MODE (base_reg_rtx) == SImode)
+		{
+		  insn = emit_move_insn (base_reg_rtx,
+					 GEN_INT (fp_offset & 0xffff0000));
+		  if (store_p)
+		    RTX_FRAME_RELATED_P (insn) = 1;
+		  insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
+						GEN_INT (fp_offset & 0x0000ffff)));
+		  if (store_p)
+		    RTX_FRAME_RELATED_P (insn) = 1;
+		}
+	      else
+		{
+		  insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
+		  if (store_p)
+		    RTX_FRAME_RELATED_P (insn) = 1;
+		}
+
+	      if (store_p)
+		RTX_FRAME_RELATED_P (insn) = 1;
+	      if (Pmode == DImode)
+		insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx,
+					      stack_pointer_rtx));
+	      else
+		insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx,
+					      stack_pointer_rtx));
+	      if (store_p)
+		RTX_FRAME_RELATED_P (insn) = 1;
+	    }
+	  else
+	    {
+	      fprintf (file, "\tli\t%s,0x%.08lx\t# ",
+		       reg_names[MIPS_TEMP2_REGNUM], (long) base_offset);
+	      fprintf (file, HOST_WIDE_INT_PRINT_DEC, base_offset);
+	      fprintf (file, "\n\t%s\t%s,%s,%s\n",
+		       Pmode == DImode ? "daddu" : "addu",
+		       reg_names[MIPS_TEMP2_REGNUM],
+		       reg_names[MIPS_TEMP2_REGNUM],
+		       reg_names[STACK_POINTER_REGNUM]);
+	    }
+	}
+
+      /* This loop must iterate over the same space as its companion in
+	 compute_frame_size.  */
+      for (regno = (FP_REG_LAST - fp_inc + 1);
+	   regno >= FP_REG_FIRST;
+	   regno -= fp_inc)
+	if (BITSET_P (fmask, regno - FP_REG_FIRST))
+	  {
+	    if (file == 0)
+	      {
+		enum machine_mode sz
+		  = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
+		rtx reg_rtx = gen_rtx (REG, sz, regno);
+		rtx mem_rtx = gen_rtx (MEM, sz,
+				       gen_rtx (PLUS, Pmode, base_reg_rtx,
+						GEN_INT (fp_offset
+							 - base_offset)));
+		RTX_UNCHANGING_P (mem_rtx) = 1;
+
+		if (store_p)
+		  {
+		    insn = emit_move_insn (mem_rtx, reg_rtx);
+		    RTX_FRAME_RELATED_P (insn) = 1;
+		  }
+		else
+		  emit_move_insn (reg_rtx, mem_rtx);
+	      }
+	    else
+	      {
+		fprintf (file, "\t%s\t%s,",
+			 (TARGET_SINGLE_FLOAT
+			  ? (store_p ? "s.s" : "l.s")
+			  : (store_p ? "s.d" : "l.d")),
+			 reg_names[regno]);
+		fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+			 fp_offset - base_offset);
+		fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
+	      }
+
+	    fp_offset -= fp_size;
+	  }
+    }
+}
+
+/* Set up the stack and frame (if desired) for the function.  */
+
+void
+function_prologue (file, size)
+     FILE *file;
+     int size ATTRIBUTE_UNUSED;
+{
+#ifndef FUNCTION_NAME_ALREADY_DECLARED
+  char *fnname;
+#endif
+  long tsize = current_frame_info.total_size;
+
+  ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
+
+#ifdef SDB_DEBUGGING_INFO
+  if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
+    ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
+#endif
+
+  /* In mips16 mode, we may need to generate a 32 bit to handle
+     floating point arguments.  The linker will arrange for any 32 bit
+     functions to call this stub, which will then jump to the 16 bit
+     function proper.  */
+  if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
+      && current_function_args_info.fp_code != 0)
+    build_mips16_function_stub (file);
+
+  inside_function = 1;
+
+#ifndef FUNCTION_NAME_ALREADY_DECLARED
+  /* Get the function name the same way that toplev.c does before calling
+     assemble_start_function.  This is needed so that the name used here
+     exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
+  fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
+
+  if (!flag_inhibit_size_directive)
+    {
+      fputs ("\t.ent\t", file);
+      assemble_name (file, fnname);
+      fputs ("\n", file);
+    }
+
+  assemble_name (file, fnname);
+  fputs (":\n", file);
+#endif
+
+  if (!flag_inhibit_size_directive)
+    {
+      /* .frame FRAMEREG, FRAMESIZE, RETREG */
+      fprintf (file,
+	       "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
+	       (reg_names[(frame_pointer_needed)
+			  ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
+	       ((frame_pointer_needed && TARGET_MIPS16)
+		? (tsize - current_function_outgoing_args_size)
+		: tsize),
+	       reg_names[31 + GP_REG_FIRST],
+	       current_frame_info.var_size,
+	       current_frame_info.num_gp,
+	       current_frame_info.num_fp,
+	       current_function_outgoing_args_size,
+	       current_frame_info.extra_size);
+
+      /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
+      fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
+	       current_frame_info.mask,
+	       current_frame_info.gp_save_offset,
+	       current_frame_info.fmask,
+	       current_frame_info.fp_save_offset);
+
+      /* Require:
+	 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
+	 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
+    }
+
+  if (mips_entry && ! mips_can_use_return_insn ())
+    {
+      int save16 = BITSET_P (current_frame_info.mask, 16);
+      int save17 = BITSET_P (current_frame_info.mask, 17);
+      int save31 = BITSET_P (current_frame_info.mask, 31);
+      int savearg = 0;
+      rtx insn;
+
+      /* Look through the initial insns to see if any of them store
+	 the function parameters into the incoming parameter storage
+	 area.  If they do, we delete the insn, and save the register
+	 using the entry pseudo-instruction instead.  We don't try to
+	 look past a label, jump, or call.  */
+      for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
+	{
+	  rtx note, set, src, dest, base, offset;
+	  int hireg;
+
+	  if (GET_CODE (insn) == CODE_LABEL
+	      || GET_CODE (insn) == JUMP_INSN
+	      || GET_CODE (insn) == CALL_INSN)
+	    break;
+	  if (GET_CODE (insn) != INSN)
+	    continue;
+	  set = PATTERN (insn);
+	  if (GET_CODE (set) != SET)
+	    continue;
+
+	  /* An insn storing a function parameter will still have a
+             REG_EQUIV note on it mentioning the argument pointer.  */
+	  note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
+	  if (note == NULL_RTX)
+	    continue;
+	  if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
+	    continue;
+
+	  src = SET_SRC (set);
+	  if (GET_CODE (src) != REG
+	      || REGNO (src) < GP_REG_FIRST + 4
+	      || REGNO (src) > GP_REG_FIRST + 7)
+	    continue;
+
+	  dest = SET_DEST (set);
+	  if (GET_CODE (dest) != MEM)
+	    continue;
+	  if (GET_MODE_SIZE (GET_MODE (dest)) == UNITS_PER_WORD)
+	    ;
+	  else if (GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
+		   && REGNO (src) < GP_REG_FIRST + 7)
+	    ;
+	  else
+	    continue;
+	  offset = const0_rtx;
+	  base = eliminate_constant_term (XEXP (dest, 0), &offset);
+	  if (GET_CODE (base) != REG
+	      || GET_CODE (offset) != CONST_INT)
+	    continue;
+	  if (REGNO (base) == STACK_POINTER_REGNUM
+	      && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
+	    ;
+	  else if (REGNO (base) == HARD_FRAME_POINTER_REGNUM
+		   && (INTVAL (offset)
+		       == (tsize
+			   + (REGNO (src) - 4) * UNITS_PER_WORD
+			   - current_function_outgoing_args_size)))
+	    ;
+	  else
+	    continue;
+
+	  /* This insn stores a parameter onto the stack, in the same
+             location where the entry pseudo-instruction will put it.
+             Delete the insn, and arrange to tell the entry
+             instruction to save the register.  */
+	  PUT_CODE (insn, NOTE);
+	  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+	  NOTE_SOURCE_FILE (insn) = 0;
+
+	  hireg = (REGNO (src)
+		   + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
+		   - 1);
+	  if (hireg > savearg)
+	    savearg = hireg;
+	}
+
+      /* If this is a varargs function, we need to save all the
+         registers onto the stack anyhow.  */
+      if (current_function_stdarg || current_function_varargs)
+	savearg = GP_REG_FIRST + 7;
+
+      fprintf (file, "\tentry\t");
+      if (savearg > 0)
+	{
+	  if (savearg == GP_REG_FIRST + 4)
+	    fprintf (file, "%s", reg_names[savearg]);
+	  else
+	    fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
+		     reg_names[savearg]);
+	}
+      if (save16 || save17)
+	{
+	  if (savearg > 0)
+	    fprintf (file, ",");
+	  fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
+	  if (save17)
+	    fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
+	}
+      if (save31)
+	{
+	  if (savearg > 0 || save16 || save17)
+	    fprintf (file, ",");
+	  fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
+	}
+      fprintf (file, "\n");
+    }
+
+  if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
+    {
+      char *sp_str = reg_names[STACK_POINTER_REGNUM];
+
+      fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
+	       reg_names[PIC_FUNCTION_ADDR_REGNUM]);
+      if (tsize > 0)
+	{
+	  fprintf (file, "\t%s\t%s,%s,%ld\n",
+		   (Pmode == DImode ? "dsubu" : "subu"),
+		   sp_str, sp_str, tsize);
+	  fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
+	}
+
+      if (dwarf2out_do_frame ())
+	dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
+    }
+}
+
+/* Expand the prologue into a bunch of separate insns.  */
+
+void
+mips_expand_prologue ()
+{
+  int regno;
+  HOST_WIDE_INT tsize;
+  rtx tmp_rtx = 0;
+  char *arg_name = 0;
+  tree fndecl = current_function_decl;
+  tree fntype = TREE_TYPE (fndecl);
+  tree fnargs = DECL_ARGUMENTS (fndecl);
+  rtx next_arg_reg;
+  int i;
+  tree next_arg;
+  tree cur_arg;
+  CUMULATIVE_ARGS args_so_far;
+  rtx reg_18_save = NULL_RTX;
+
+  /* If struct value address is treated as the first argument, make it so.  */
+  if (aggregate_value_p (DECL_RESULT (fndecl))
+      && ! current_function_returns_pcc_struct
+      && struct_value_incoming_rtx == 0)
+    {
+      tree type = build_pointer_type (fntype);
+      tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
+
+      DECL_ARG_TYPE (function_result_decl) = type;
+      TREE_CHAIN (function_result_decl) = fnargs;
+      fnargs = function_result_decl;
+    }
+
+  /* Determine the last argument, and get its name.  */
+
+  INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
+  regno = GP_ARG_FIRST;
+
+  for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
+    {
+      tree passed_type = DECL_ARG_TYPE (cur_arg);
+      enum machine_mode passed_mode = TYPE_MODE (passed_type);
+      rtx entry_parm;
+
+      if (TREE_ADDRESSABLE (passed_type))
+	{
+	  passed_type = build_pointer_type (passed_type);
+	  passed_mode = Pmode;
+	}
+
+      entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
+
+      if (entry_parm)
+	{
+	  int words;
+
+	  /* passed in a register, so will get homed automatically */
+	  if (GET_MODE (entry_parm) == BLKmode)
+	    words = (int_size_in_bytes (passed_type) + 3) / 4;
+	  else
+	    words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
+
+	  regno = REGNO (entry_parm) + words - 1;
+	}
+      else
+	{
+	  regno = GP_ARG_LAST+1;
+	  break;
+	}
+
+      FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
+
+      next_arg = TREE_CHAIN (cur_arg);
+      if (next_arg == 0)
+	{
+	  if (DECL_NAME (cur_arg))
+	    arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
+
+	  break;
+	}
+    }
+
+  /* In order to pass small structures by value in registers compatibly with
+     the MIPS compiler, we need to shift the value into the high part of the
+     register.  Function_arg has encoded a PARALLEL rtx, holding a vector of
+     adjustments to be made as the next_arg_reg variable, so we split up the
+     insns, and emit them separately.  */
+
+  next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
+  if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
+    {
+      rtvec adjust = XVEC (next_arg_reg, 0);
+      int num = GET_NUM_ELEM (adjust);
+
+      for (i = 0; i < num; i++)
+	{
+	  rtx pattern = RTVEC_ELT (adjust, i);
+	  if (GET_CODE (pattern) != SET
+	      || GET_CODE (SET_SRC (pattern)) != ASHIFT)
+	    abort_with_insn (pattern, "Insn is not a shift");
+
+	  PUT_CODE (SET_SRC (pattern), ASHIFTRT);
+	  emit_insn (pattern);
+	}
+    }
+
+  tsize = compute_frame_size (get_frame_size ());
+
+  /* If this function is a varargs function, store any registers that
+     would normally hold arguments ($4 - $7) on the stack.  */
+  if ((mips_abi == ABI_32 || mips_abi == ABI_O64)
+      && (! mips_entry || mips_can_use_return_insn ())
+      && ((TYPE_ARG_TYPES (fntype) != 0
+	   && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
+	       != void_type_node))
+	  || (arg_name != 0
+	      && ((arg_name[0] == '_'
+		   && strcmp (arg_name, "__builtin_va_alist") == 0)
+		  || (arg_name[0] == 'v'
+		      && strcmp (arg_name, "va_alist") == 0)))))
+    {
+      int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
+      rtx ptr = stack_pointer_rtx;
+
+      /* If we are doing svr4-abi, sp has already been decremented by tsize. */
+      if (TARGET_ABICALLS)
+	offset += tsize;
+
+      for (; regno <= GP_ARG_LAST; regno++)
+	{
+	  if (offset != 0)
+	    ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
+	  emit_move_insn (gen_rtx (MEM, mips_reg_mode[regno], ptr),
+			  gen_rtx (REG, mips_reg_mode[regno], regno));
+
+	  offset += GET_MODE_SIZE (mips_reg_mode[0]);
+	}
+    }
+
+  /* If we are using the entry pseudo instruction, it will
+     automatically subtract 32 from the stack pointer, so we don't
+     need to.  The entry pseudo instruction is emitted by
+     function_prologue.  */
+  if (mips_entry && ! mips_can_use_return_insn ())
+    {
+      if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
+	{
+          rtx insn;
+
+	  /* If we are using a frame pointer with a small stack frame,
+             we need to initialize it here since it won't be done
+             below.  */
+	  if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
+	    {
+	      rtx incr = GEN_INT (current_function_outgoing_args_size);
+	      if (Pmode == DImode)
+		insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
+                                              stack_pointer_rtx,
+                                              incr));
+	      else
+		insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
+                                              stack_pointer_rtx,
+                                              incr));
+	    }
+	  else if (Pmode == DImode)
+	    insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
+					 stack_pointer_rtx));
+	  else
+	    insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
+					 stack_pointer_rtx));
+
+          RTX_FRAME_RELATED_P (insn) = 1;
+	}
+
+      /* We may need to save $18, if it is used to call a function
+	 which may return a floating point value.  Set up a sequence
+	 of instructions to do so.  Later on we emit them at the right
+	 moment.  */
+      if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
+	{
+	  rtx reg_rtx = gen_rtx (REG, mips_reg_mode[GP_REG_FIRST + 3],
+				 GP_REG_FIRST + 3);
+	  long gp_offset, base_offset;
+
+	  gp_offset = current_frame_info.gp_sp_offset;
+	  if (BITSET_P (current_frame_info.mask, 16))
+	    gp_offset -= UNITS_PER_WORD;
+	  if (BITSET_P (current_frame_info.mask, 17))
+	    gp_offset -= UNITS_PER_WORD;
+	  if (BITSET_P (current_frame_info.mask, 31))
+	    gp_offset -= UNITS_PER_WORD;
+	  if (tsize > 32767)
+	    base_offset = tsize;
+	  else
+	    base_offset = 0;
+	  start_sequence ();
+	  emit_move_insn (reg_rtx,
+			  gen_rtx (REG, mips_reg_mode[GP_REG_FIRST + 18],
+				   GP_REG_FIRST + 18));
+	  emit_move_insn (gen_rtx (MEM, mips_reg_mode[GP_REG_FIRST + 18],
+				   gen_rtx (PLUS, Pmode, stack_pointer_rtx,
+					    GEN_INT (gp_offset
+						     - base_offset))),
+			  reg_rtx);
+	  reg_18_save = gen_sequence ();
+	  end_sequence ();
+	}
+
+      if (tsize > 32)
+	tsize -= 32;
+      else
+	{
+	  tsize = 0;
+	  if (reg_18_save != NULL_RTX)
+	    emit_insn (reg_18_save);
+	}
+    }
+
+  if (tsize > 0)
+    {
+      rtx tsize_rtx = GEN_INT (tsize);
+
+      /* If we are doing svr4-abi, sp move is done by
+         function_prologue.  In mips16 mode with a large frame, we
+         save the registers before adjusting the stack.  */
+      if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
+	  && (!TARGET_MIPS16 || tsize <= 32767))
+	{
+	  rtx insn;
+
+	  if (tsize > 32767)
+	    {
+	      tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
+
+	      /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
+		 bit, so make sure that we don't emit anything that can be
+		 split.  */
+	      /* ??? There is no DImode ori immediate pattern, so we can only
+		 do this for 32 bit code.  */
+	      if (large_int (tsize_rtx) && GET_MODE (tmp_rtx) == SImode)
+		{
+		  insn = emit_move_insn (tmp_rtx,
+					 GEN_INT (tsize & 0xffff0000));
+		  RTX_FRAME_RELATED_P (insn) = 1;
+		  insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
+						GEN_INT (tsize & 0x0000ffff)));
+		  RTX_FRAME_RELATED_P (insn) = 1;
+		}
+	      else
+		{
+		  insn = emit_move_insn (tmp_rtx, tsize_rtx);
+		  RTX_FRAME_RELATED_P (insn) = 1;
+		}
+
+	      tsize_rtx = tmp_rtx;
+	    }
+
+	  if (Pmode == DImode)
+	    insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
+					  tsize_rtx));
+	  else
+	    insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
+					  tsize_rtx));
+
+	  RTX_FRAME_RELATED_P (insn) = 1;
+	}
+
+      if (! mips_entry)
+	save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
+      else if (reg_18_save != NULL_RTX)
+	emit_insn (reg_18_save);
+
+      if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
+	  && TARGET_MIPS16
+	  && tsize > 32767)
+	{
+	  rtx reg_rtx;
+
+	  if (!frame_pointer_needed)
+	    abort ();
+
+	  reg_rtx = gen_rtx (REG, Pmode, 3);
+  	  emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
+  	  emit_move_insn (reg_rtx, tsize_rtx);
+  	  if (Pmode == DImode)
+	    emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
+				   hard_frame_pointer_rtx,
+				   reg_rtx));
+	  else
+	    emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
+				   hard_frame_pointer_rtx,
+				   reg_rtx));
+	  emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
+	}
+
+      if (frame_pointer_needed)
+	{
+          rtx insn = 0;
+
+	  /* On the mips16, we encourage the use of unextended
+             instructions when using the frame pointer by pointing the
+             frame pointer ahead of the argument space allocated on
+             the stack.  */
+	  if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
+	      && TARGET_MIPS16
+	      && tsize > 32767)
+	    {
+	      /* In this case, we have already copied the stack
+                 pointer into the frame pointer, above.  We need only
+                 adjust for the outgoing argument size.  */
+	      if (current_function_outgoing_args_size != 0)
+		{
+		  rtx incr = GEN_INT (current_function_outgoing_args_size);
+		  if (Pmode == DImode)
+		    insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
+                                                  hard_frame_pointer_rtx,
+                                                  incr));
+		  else
+		    insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
+                                                  hard_frame_pointer_rtx,
+                                                  incr));
+		}
+	    }
+	  else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
+	    {
+	      rtx incr = GEN_INT (current_function_outgoing_args_size);
+	      if (Pmode == DImode)
+		insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
+                                              stack_pointer_rtx,
+                                              incr));
+	      else
+		insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
+                                              stack_pointer_rtx,
+                                              incr));
+	    }
+	  else if (Pmode == DImode)
+	    insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
+					 stack_pointer_rtx));
+	  else
+	    insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
+					 stack_pointer_rtx));
+
+	  if (insn)
+	    RTX_FRAME_RELATED_P (insn) = 1;
+	}
+
+      if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
+	emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
+			       gen_rtx (REG, DImode, 25)));
+    }
+
+  /* If we are profiling, make sure no instructions are scheduled before
+     the call to mcount.  */
+
+  if (profile_flag || profile_block_flag)
+    emit_insn (gen_blockage ());
+}
+
+/* Do any necessary cleanup after a function to restore stack, frame,
+   and regs. */
+
+#define RA_MASK ((long) 0x80000000)	/* 1 << 31 */
+#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
+
+void
+function_epilogue (file, size)
+     FILE *file ATTRIBUTE_UNUSED;
+     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
+{
+  char *fnname;
+
+#ifndef FUNCTION_NAME_ALREADY_DECLARED
+  /* Get the function name the same way that toplev.c does before calling
+     assemble_start_function.  This is needed so that the name used here
+     exactly matches the name used in ASM_DECLARE_FUNCTION_NAME.  */
+  fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
+
+  if (!flag_inhibit_size_directive)
+    {
+      fputs ("\t.end\t", file);
+      assemble_name (file, fnname);
+      fputs ("\n", file);
+    }
+#endif
+
+  if (TARGET_STATS)
+    {
+      int num_gp_regs = current_frame_info.gp_reg_size / 4;
+      int num_fp_regs = current_frame_info.fp_reg_size / 8;
+      int num_regs = num_gp_regs + num_fp_regs;
+      char *name = fnname;
+
+      if (name[0] == '*')
+	name++;
+
+      dslots_load_total += num_regs;
+
+      fprintf (stderr,
+	       "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
+	       name, frame_pointer_needed ? 'y' : 'n',
+	       (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
+	       current_function_calls_alloca ? 'y' : 'n',
+	       current_function_calls_setjmp ? 'y' : 'n',
+	       current_frame_info.total_size,
+	       current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
+	       dslots_load_total, dslots_load_filled,
+	       dslots_jump_total, dslots_jump_filled,
+	       num_refs[0], num_refs[1], num_refs[2]);
+
+      if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
+	{
+	  fprintf (stderr,
+		   " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
+	  prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
+	}
+
+      if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
+	{
+	  fprintf (stderr,
+		   " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
+	  prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
+	}
+
+      fputc ('\n', stderr);
+    }
+
+  /* Reset state info for each function.  */
+  inside_function = 0;
+  ignore_line_number = 0;
+  dslots_load_total = 0;
+  dslots_jump_total = 0;
+  dslots_load_filled = 0;
+  dslots_jump_filled = 0;
+  num_refs[0] = 0;
+  num_refs[1] = 0;
+  num_refs[2] = 0;
+  mips_load_reg = 0;
+  mips_load_reg2 = 0;
+  current_frame_info = zero_frame_info;
+
+  while (string_constants != NULL)
+    {
+      struct string_constant *next;
+
+      next = string_constants->next;
+      free (string_constants);
+      string_constants = next;
+    }
+
+  /* Restore the output file if optimizing the GP (optimizing the GP causes
+     the text to be diverted to a tempfile, so that data decls come before
+     references to the data).  */
+
+  if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
+    asm_out_file = asm_out_data_file;
+}
+
+/* Expand the epilogue into a bunch of separate insns.  */
+
+void
+mips_expand_epilogue ()
+{
+  HOST_WIDE_INT tsize = current_frame_info.total_size;
+  rtx tsize_rtx = GEN_INT (tsize);
+  rtx tmp_rtx = (rtx)0;
+
+  if (mips_can_use_return_insn ())
+    {
+      emit_insn (gen_return ());
+      return;
+    }
+
+  if (mips_entry && ! mips_can_use_return_insn ())
+    tsize -= 32;
+
+  if (tsize > 32767 && ! TARGET_MIPS16)
+    {
+      tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
+      emit_move_insn (tmp_rtx, tsize_rtx);
+      tsize_rtx = tmp_rtx;
+    }
+
+  if (tsize > 0)
+    {
+      long orig_tsize = tsize;
+
+      if (frame_pointer_needed)
+	{
+	  emit_insn (gen_blockage ());
+
+	  /* On the mips16, the frame pointer is offset from the stack
+             pointer by current_function_outgoing_args_size.  We
+             account for that by changing tsize.  Note that this can
+             actually make tsize negative.  */
+	  if (TARGET_MIPS16)
+	    {
+	      tsize -= current_function_outgoing_args_size;
+
+	      /* If we have a large frame, it's easier to add to $17
+                 than to $sp, since the mips16 has no instruction to
+                 add a register to $sp.  */
+	      if (orig_tsize > 32767)
+		{
+		  rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
+
+		  emit_move_insn (g6_rtx, GEN_INT (tsize));
+		  if (Pmode == DImode)
+		    emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
+					   hard_frame_pointer_rtx,
+					   g6_rtx));
+		  else
+		    emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
+					   hard_frame_pointer_rtx,
+					   g6_rtx));
+		  tsize = 0;
+		}
+	      
+	      if (tsize && tsize != orig_tsize)
+		tsize_rtx = GEN_INT (tsize);
+	    }
+
+	  if (Pmode == DImode)
+	    emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
+	  else
+	    emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
+	}
+
+      /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
+	 are going to restore it, then we must emit a blockage insn to
+	 prevent the scheduler from moving the restore out of the epilogue.  */
+      else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
+	       && (current_frame_info.mask
+		   & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
+	emit_insn (gen_blockage ());
+
+      save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
+
+      /* In mips16 mode with a large frame, we adjust the stack
+         pointer before restoring the registers.  In this case, we
+         should always be using a frame pointer, so everything should
+         have been handled above.  */
+      if (tsize > 32767 && TARGET_MIPS16)
+	abort ();
+
+      emit_insn (gen_blockage ());
+      if (Pmode == DImode && tsize != 0)
+	emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
+			       tsize_rtx));
+      else if (tsize != 0)
+	emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
+			       tsize_rtx));
+    }
+
+  /* The mips16 loads the return address into $7, not $31.  */
+  if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
+    emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
+						  GP_REG_FIRST + 7)));
+  else
+    emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
+						  GP_REG_FIRST + 31)));
+}
+
+/* Return nonzero if this function is known to have a null epilogue.
+   This allows the optimizer to omit jumps to jumps if no stack
+   was created.  */
+
+int
+mips_can_use_return_insn ()
+{
+  if (! reload_completed)
+    return 0;
+
+  if (regs_ever_live[31] || profile_flag)
+    return 0;
+
+  /* In mips16 mode, a function which returns a floating point value
+     needs to arrange to copy the return value into the floating point
+     registers.  */
+  if (TARGET_MIPS16
+      && mips16_hard_float
+      && ! aggregate_value_p (DECL_RESULT (current_function_decl))
+      && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
+	  == MODE_FLOAT)
+      && (! TARGET_SINGLE_FLOAT
+	  || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
+	      <= 4)))
+    return 0;
+
+  if (current_frame_info.initialized)
+    return current_frame_info.total_size == 0;
+
+  return compute_frame_size (get_frame_size ()) == 0;
+}
+
+/* Choose the section to use for the constant rtx expression X that has
+   mode MODE.  */
+
+void
+mips_select_rtx_section (mode, x)
+     enum machine_mode mode;
+     rtx x ATTRIBUTE_UNUSED;
+{
+  if (TARGET_MIPS16)
+    {
+      /* In mips16 mode, the constant table always goes in the same section
+         as the function, so that constants can be loaded using PC relative
+         addressing.  */
+      function_section (current_function_decl);
+    }
+  else if (TARGET_EMBEDDED_DATA)
+    {
+      /* For embedded applications, always put constants in read-only data,
+	 in order to reduce RAM usage.  */
+      READONLY_DATA_SECTION ();
+    }
+  else
+    {
+      /* For hosted applications, always put constants in small data if
+	 possible, as this gives the best performance.  */
+     
+      if (GET_MODE_SIZE (mode) <= mips_section_threshold
+	  && mips_section_threshold > 0)
+	SMALL_DATA_SECTION ();
+      else
+	READONLY_DATA_SECTION ();
+    }
+}
+
+/* Choose the section to use for DECL.  RELOC is true if its value contains
+   any relocatable expression.
+
+   Some of the logic used here needs to be replicated in
+   ENCODE_SECTION_INFO in mips.h so that references to these symbols
+   are done correctly.  Specifically, at least all symbols assigned
+   here to rom (.text and/or .rodata) must not be referenced via
+   ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
+
+   If you need to make a change here, you probably should check
+   ENCODE_SECTION_INFO to see if it needs a similar change.  */
+
+void
+mips_select_section (decl, reloc)
+     tree decl;
+     int reloc;
+{
+  int size = int_size_in_bytes (TREE_TYPE (decl));
+
+  if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
+      && TREE_CODE (decl) == STRING_CST
+      && !flag_writable_strings)
+    /* For embedded position independent code, put constant strings in the
+       text section, because the data section is limited to 64K in size.
+       For mips16 code, put strings in the text section so that a PC
+       relative load instruction can be used to get their address.  */
+    text_section ();
+  else if (TARGET_EMBEDDED_DATA)
+    {
+      /* For embedded applications, always put an object in read-only data
+	 if possible, in order to reduce RAM usage.  */
+
+      if (((TREE_CODE (decl) == VAR_DECL
+	    && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
+	    && DECL_INITIAL (decl)
+	    && (DECL_INITIAL (decl) == error_mark_node
+		|| TREE_CONSTANT (DECL_INITIAL (decl))))
+	   /* Deal with calls from output_constant_def_contents.  */
+	   || (TREE_CODE (decl) != VAR_DECL
+	       && (TREE_CODE (decl) != STRING_CST
+		   || !flag_writable_strings)))
+	  && ! (flag_pic && reloc))
+	READONLY_DATA_SECTION ();
+      else if (size > 0 && size <= mips_section_threshold)
+	SMALL_DATA_SECTION ();
+      else
+	data_section ();
+    }
+  else
+    {
+      /* For hosted applications, always put an object in small data if
+	 possible, as this gives the best performance.  */
+
+      if (size > 0 && size <= mips_section_threshold)
+	SMALL_DATA_SECTION ();
+      else if (((TREE_CODE (decl) == VAR_DECL
+		 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
+		 && DECL_INITIAL (decl)
+		 && (DECL_INITIAL (decl) == error_mark_node
+		     || TREE_CONSTANT (DECL_INITIAL (decl))))
+		/* Deal with calls from output_constant_def_contents.  */
+		|| (TREE_CODE (decl) != VAR_DECL
+		    && (TREE_CODE (decl) != STRING_CST
+			|| !flag_writable_strings)))
+	       && ! (flag_pic && reloc))
+	READONLY_DATA_SECTION ();
+      else
+	data_section ();
+    }
+}
+
+#ifdef MIPS_ABI_DEFAULT
+
+/* Support functions for the 64 bit ABI.  */
+
+/* Return register to use for a function return value with VALTYPE for function
+   FUNC.  */
+
+rtx
+mips_function_value (valtype, func)
+     tree valtype;
+     tree func ATTRIBUTE_UNUSED;
+{
+  int reg = GP_RETURN;
+  enum machine_mode mode = TYPE_MODE (valtype);
+  enum mode_class mclass = GET_MODE_CLASS (mode);
+  int unsignedp = TREE_UNSIGNED (valtype);
+
+  /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
+     just as PROMOTE_MODE does.  */
+  mode = promote_mode (valtype, mode, &unsignedp, 1);
+
+  /* ??? How should we return complex float?  */
+  if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
+    {
+      if (TARGET_SINGLE_FLOAT
+	  && (mclass == MODE_FLOAT
+	      ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
+	reg = GP_RETURN;
+      else
+	reg = FP_RETURN;
+    }
+
+  else if (TREE_CODE (valtype) == RECORD_TYPE
+	   && mips_abi != ABI_32 
+	   && mips_abi != ABI_O64 
+	   && mips_abi != ABI_EABI)
+    {
+      /* A struct with only one or two floating point fields is returned in
+	 the floating point registers.  */
+      tree field, fields[2];
+      int i;
+
+      for (i = 0, field = TYPE_FIELDS (valtype); field;
+	   field = TREE_CHAIN (field))
+	{
+	  if (TREE_CODE (field) != FIELD_DECL)
+	    continue;
+
+	  if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
+	    break;
+
+	  fields[i++] = field;
+	}
+	  
+      /* Must check i, so that we reject structures with no elements.  */
+      if (! field)
+	{
+	  if (i == 1)
+	    {
+	      /* The structure has DImode, but we don't allow DImode values
+		 in FP registers, so we use a PARALLEL even though it isn't
+		 strictly necessary.  */
+	      enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
+
+	      return gen_rtx (PARALLEL, mode,
+			      gen_rtvec (1,
+					 gen_rtx (EXPR_LIST, VOIDmode,
+						  gen_rtx (REG, field_mode,
+							   FP_RETURN),
+						  const0_rtx)));
+	    }
+
+	  else if (i == 2)
+	    {
+	      enum machine_mode first_mode
+		= TYPE_MODE (TREE_TYPE (fields[0]));
+	      enum machine_mode second_mode
+		= TYPE_MODE (TREE_TYPE (fields[1]));
+	      int first_offset
+		= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0]));
+	      int second_offset
+		= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1]));
+
+	      return gen_rtx (PARALLEL, mode,
+			      gen_rtvec (2,
+					 gen_rtx (EXPR_LIST, VOIDmode,
+						  gen_rtx (REG, first_mode,
+							   FP_RETURN),
+						  GEN_INT (first_offset
+							   / BITS_PER_UNIT)),
+					 gen_rtx (EXPR_LIST, VOIDmode,
+						  gen_rtx (REG, second_mode,
+							   FP_RETURN + 2),
+						  GEN_INT (second_offset
+							   / BITS_PER_UNIT))));
+	    }
+	}
+    }
+
+  return gen_rtx (REG, mode, reg);
+}
+
+/* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE.  Return
+   nonzero when an argument must be passed by reference.  */
+
+int
+function_arg_pass_by_reference (cum, mode, type, named)
+     CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
+     enum machine_mode mode;
+     tree type;
+     int named ATTRIBUTE_UNUSED;
+{
+  int size;
+
+  if (mips_abi != ABI_EABI)
+    return 0;
+
+  /* ??? How should SCmode be handled?  */
+  if (type == NULL_TREE || mode == DImode || mode == DFmode)
+    return 0;
+
+
+  size = int_size_in_bytes (type);
+  return size == -1 || size > UNITS_PER_WORD;
+}
+#endif
+
+/* This function returns the register class required for a secondary
+   register when copying between one of the registers in CLASS, and X,
+   using MODE.  If IN_P is nonzero, the copy is going from X to the
+   register, otherwise the register is the source.  A return value of
+   NO_REGS means that no secondary register is required.  */
+
+enum reg_class
+mips_secondary_reload_class (class, mode, x, in_p)
+     enum reg_class class;
+     enum machine_mode mode;
+     rtx x;
+     int in_p;
+{
+  enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
+  int regno = -1;
+  int gp_reg_p;
+
+  if (GET_CODE (x) == SIGN_EXTEND)
+    {
+      int off = 0;
+
+      x = XEXP (x, 0);
+
+      /* We may be called with reg_renumber NULL from regclass.
+	 ??? This is probably a bug.  */
+      if (reg_renumber)
+	regno = true_regnum (x);
+      else
+	{
+	  while (GET_CODE (x) == SUBREG)
+	    {
+	      off += SUBREG_WORD (x);
+	      x = SUBREG_REG (x);
+	    }
+
+	  if (GET_CODE (x) == REG)
+	    regno = REGNO (x) + off;
+	}
+    }
+
+  else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+    regno = true_regnum (x);
+
+  gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
+
+  /* We always require a general register when copying anything to
+     HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
+     to a general register, or when copying from register 0.  */
+  if (class == HILO_REG && regno != GP_REG_FIRST + 0)
+    return ((! in_p
+	     && gp_reg_p
+	     && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
+	    ? NO_REGS : gr_regs);
+  else if (regno == HILO_REGNUM)
+    return ((in_p
+	     && class == gr_regs
+	     && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
+	    ? NO_REGS : gr_regs);
+
+  /* Copying from HI or LO to anywhere other than a general register
+     requires a general register.  */
+  if (class == HI_REG || class == LO_REG || class == MD_REGS)
+    {
+      if (TARGET_MIPS16 && in_p)
+	{
+	  /* We can't really copy to HI or LO at all in mips16 mode.  */
+	  return M16_REGS;
+	}
+      return gp_reg_p ? NO_REGS : gr_regs;
+    }
+  if (MD_REG_P (regno))
+    {
+      if (TARGET_MIPS16 && ! in_p)
+	{
+	  /* We can't really copy to HI or LO at all in mips16 mode.  */
+	  return M16_REGS;
+	}
+      return class == gr_regs ? NO_REGS : gr_regs;
+    }
+
+  /* We can only copy a value to a condition code register from a
+     floating point register, and even then we require a scratch
+     floating point register.  We can only copy a value out of a
+     condition code register into a general register.  */
+  if (class == ST_REGS)
+    {
+      if (in_p)
+	return FP_REGS;
+      return GP_REG_P (regno) ? NO_REGS : GR_REGS;
+    }
+  if (ST_REG_P (regno))
+    {
+      if (! in_p)
+	return FP_REGS;
+      return class == GR_REGS ? NO_REGS : GR_REGS;
+    }
+
+  /* In mips16 mode, going between memory and anything but M16_REGS
+     requires an M16_REG.  */
+  if (TARGET_MIPS16)
+    {
+      if (class != M16_REGS && class != M16_NA_REGS)
+	{
+	  if (gp_reg_p)
+	    return NO_REGS;
+	  return M16_REGS;
+	}
+      if (! gp_reg_p)
+	{
+	  /* The stack pointer isn't a valid operand to an add instruction,
+	     so we need to load it into M16_REGS first.  This can happen as
+	     a result of register elimination and form_sum converting
+	     (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST).  We
+	     need an extra register if the dest is the same as the other
+	     register.  In that case, we can't fix the problem by loading SP
+	     into the dest first.  */
+	  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
+	      && GET_CODE (XEXP (x, 1)) == REG
+	      && (XEXP (x, 0) == stack_pointer_rtx
+		  || XEXP (x, 1) == stack_pointer_rtx))
+	    return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
+
+	  if (class == M16_REGS || class == M16_NA_REGS)
+	    return NO_REGS;
+	  return M16_REGS;
+	}
+    }
+
+  return NO_REGS;
+}
+
+/* For each mips16 function which refers to GP relative symbols, we
+   use a pseudo register, initialized at the start of the function, to
+   hold the $gp value.  */
+
+rtx
+mips16_gp_pseudo_reg ()
+{
+  if (mips16_gp_pseudo_rtx == NULL_RTX)
+    {
+      rtx const_gp;
+      rtx insn, scan;
+
+      mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
+      RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
+
+      /* We want to initialize this to a value which gcc will believe
+         is constant.  */
+      const_gp = gen_rtx (CONST, Pmode,
+			  gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
+
+      start_sequence ();
+      emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
+      insn = gen_sequence ();
+      end_sequence ();
+
+      push_topmost_sequence ();
+      /* We need to emit the initialization after the FUNCTION_BEG
+         note, so that it will be integrated.  */
+      for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
+	if (GET_CODE (scan) == NOTE
+	    && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
+	  break;
+      if (scan == NULL_RTX)
+	scan = get_insns ();
+      insn = emit_insn_after (insn, scan);
+      pop_topmost_sequence ();
+    }
+
+  return mips16_gp_pseudo_rtx;
+}
+
+/* Return an RTX which represents the signed 16 bit offset from the
+   $gp register for the given symbol.  This is only used on the
+   mips16.  */
+
+rtx
+mips16_gp_offset (sym)
+     rtx sym;
+{
+  tree gp;
+
+  if (GET_CODE (sym) != SYMBOL_REF
+      || ! SYMBOL_REF_FLAG (sym))
+    abort ();
+
+  /* We use a special identifier to represent the value of the gp
+     register.  */
+  gp = get_identifier ("__mips16_gp_value");
+
+  return gen_rtx (CONST, Pmode,
+		  gen_rtx (MINUS, Pmode, sym,
+			   gen_rtx (SYMBOL_REF, Pmode,
+				    IDENTIFIER_POINTER (gp))));
+}
+
+/* Return nonzero if the given RTX represents a signed 16 bit offset
+   from the $gp register.  */
+
+int
+mips16_gp_offset_p (x)
+     rtx x;
+{
+  if (GET_CODE (x) == CONST)
+    x = XEXP (x, 0);
+
+  /* It's OK to add a small integer value to a gp offset.  */
+  if (GET_CODE (x) == PLUS)
+    {
+      if (GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && SMALL_INT (XEXP (x, 1)))
+	return mips16_gp_offset_p (XEXP (x, 0));
+      if (GET_CODE (XEXP (x, 0)) == CONST_INT
+	  && SMALL_INT (XEXP (x, 0)))
+	return mips16_gp_offset_p (XEXP (x, 1));
+      return 0;
+    }
+
+  /* Make sure it is in the form SYM - __mips16_gp_value.  */
+  return (GET_CODE (x) == MINUS
+	  && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+	  && SYMBOL_REF_FLAG (XEXP (x, 0))
+	  && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
+	  && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
+}
+
+/* Output a GP offset.  We don't want to print the subtraction of
+   __mips16_gp_value; it is implicitly represented by the %gprel which
+   should have been printed by the caller.  */
+
+static void
+mips16_output_gp_offset (file, x)
+     FILE *file;
+     rtx x;
+{
+  if (GET_CODE (x) == CONST)
+    x = XEXP (x, 0);
+
+  if (GET_CODE (x) == PLUS)
+    {
+      mips16_output_gp_offset (file, XEXP (x, 0));
+      fputs ("+", file);
+      mips16_output_gp_offset (file, XEXP (x, 1));
+      return;
+    }
+
+  if (GET_CODE (x) == MINUS
+      && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
+      && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
+    {
+      mips16_output_gp_offset (file, XEXP (x, 0));
+      return;
+    }
+
+  output_addr_const (file, x);
+}
+
+/* Return nonzero if a constant should not be output until after the
+   function.  This is true of most string constants, so that we can
+   use a more efficient PC relative reference.  However, a static
+   inline function may never call assemble_function_end to write out
+   the constant pool, so don't try to postpone the constant in that
+   case.
+
+   ??? It's really a bug that a static inline function can put stuff
+   in the constant pool even if the function itself is not output.
+
+   We record which string constants we've seen, so that we know which
+   ones might use the more efficient reference.  */
+
+int
+mips16_constant_after_function_p (x)
+     tree x;
+{
+  if (TREE_CODE (x) == STRING_CST
+      && ! flag_writable_strings
+      && current_function_decl != 0
+      && ! DECL_DEFER_OUTPUT (current_function_decl)
+      && ! (DECL_INLINE (current_function_decl)
+	    && ((! TREE_PUBLIC (current_function_decl)
+		 && ! TREE_ADDRESSABLE (current_function_decl)
+		 && ! flag_keep_inline_functions)
+		|| DECL_EXTERNAL (current_function_decl))))
+    {
+      struct string_constant *n;
+
+      n = (struct string_constant *) xmalloc (sizeof *n);
+      n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
+      n->next = string_constants;
+      string_constants = n;
+
+      return 1;
+    }
+
+  return 0;
+}
+
+/* Validate a constant for the mips16.  This rejects general symbolic
+   addresses, which must be loaded from memory.  If ADDR is nonzero,
+   this should reject anything which is not a legal address.  If
+   ADDEND is nonzero, this is being added to something else.  */
+
+int
+mips16_constant (x, mode, addr, addend)
+     rtx x;
+     enum machine_mode mode;
+     int addr;
+     int addend;
+{
+  while (GET_CODE (x) == CONST)
+    x = XEXP (x, 0);
+
+  switch (GET_CODE (x))
+    {
+    default:
+      return 0;
+
+    case PLUS:
+      return (mips16_constant (XEXP (x, 0), mode, addr, 1)
+	      && mips16_constant (XEXP (x, 1), mode, addr, 1));
+
+    case SYMBOL_REF:
+      if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
+	return 0;
+      if (CONSTANT_POOL_ADDRESS_P (x))
+	return 1;
+
+      /* If we aren't looking for a memory address, we can accept a GP
+         relative symbol, which will have SYMBOL_REF_FLAG set; movsi
+         knows how to handle this.  We can always accept a string
+         constant, which is the other case in which SYMBOL_REF_FLAG
+         will be set.  */
+      if (! addr && ! addend && SYMBOL_REF_FLAG (x) && mode == Pmode)
+	return 1;
+
+      /* We can accept a string constant, which will have
+         SYMBOL_REF_FLAG set but must be recognized by name to
+         distinguish from a GP accessible symbol.  The name of a
+         string constant will have been generated by
+         ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def.  */
+      if (SYMBOL_REF_FLAG (x))
+	{
+	  char *name = XSTR (x, 0);
+
+	  return (name[0] == '*'
+		  && strncmp (name + 1, LOCAL_LABEL_PREFIX,
+			      sizeof LOCAL_LABEL_PREFIX - 1) == 0);
+	}
+
+      return 0;
+
+    case LABEL_REF:
+      if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
+	return 0;
+      return 1;
+
+    case CONST_INT:
+      if (addr && ! addend)
+	return 0;
+      return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
+
+    case REG:
+      /* We need to treat $gp as a legitimate constant, because
+         mips16_gp_pseudo_reg assumes that.  */
+      return REGNO (x) == GP_REG_FIRST + 28;
+    }
+}
+
+/* Write out code to move floating point arguments in or out of
+   general registers.  Output the instructions to FILE.  FP_CODE is
+   the code describing which arguments are present (see the comment at
+   the definition of CUMULATIVE_ARGS in mips.h).  FROM_FP_P is non-zero if
+   we are copying from the floating point registers.  */
+
+static void
+mips16_fp_args (file, fp_code, from_fp_p)
+     FILE *file;
+     int fp_code;
+     int from_fp_p;
+{
+  char *s;
+  int gparg, fparg;
+  unsigned int f;
+
+  /* This code only works for the original 32 bit ABI and the O64 ABI.  */
+  if (mips_abi != ABI_32 && mips_abi != ABI_O64)
+    abort ();
+
+  if (from_fp_p)
+    s = "mfc1";
+  else
+    s = "mtc1";
+  gparg = GP_ARG_FIRST;
+  fparg = FP_ARG_FIRST;
+  for (f = (unsigned int) fp_code; f != 0; f >>= 2)
+    {
+      if ((f & 3) == 1)
+	{
+	  if ((fparg & 1) != 0)
+	    ++fparg;
+	  fprintf (file, "\t%s\t%s,%s\n", s,
+		   reg_names[gparg], reg_names[fparg]);
+	}
+      else if ((f & 3) == 2)
+	{
+	  if (TARGET_64BIT)
+	    fprintf (file, "\td%s\t%s,%s\n", s,
+		     reg_names[gparg], reg_names[fparg]);
+	  else
+	    {
+	      if ((fparg & 1) != 0)
+		++fparg;
+	      if (TARGET_BIG_ENDIAN)
+		fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
+			 reg_names[gparg], reg_names[fparg + 1], s,
+			 reg_names[gparg + 1], reg_names[fparg]);
+	      else
+		fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
+			 reg_names[gparg], reg_names[fparg], s,
+			 reg_names[gparg + 1], reg_names[fparg + 1]);
+	      ++gparg;
+	      ++fparg;
+	    }
+	}
+      else
+	abort ();
+
+      ++gparg;
+      ++fparg;
+    }
+}
+
+/* Build a mips16 function stub.  This is used for functions which
+   take aruments in the floating point registers.  It is 32 bit code
+   that moves the floating point args into the general registers, and
+   then jumps to the 16 bit code.  */
+
+static void
+build_mips16_function_stub (file)
+     FILE *file;
+{
+  char *fnname;
+  char *secname, *stubname;
+  tree stubid, stubdecl;
+  int need_comma;
+  unsigned int f;
+
+  fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
+  secname = (char *) alloca (strlen (fnname) + 20);
+  sprintf (secname, ".mips16.fn.%s", fnname);
+  stubname = (char *) alloca (strlen (fnname) + 20);
+  sprintf (stubname, "__fn_stub_%s", fnname);
+  stubid = get_identifier (stubname);
+  stubdecl = build_decl (FUNCTION_DECL, stubid,
+			 build_function_type (void_type_node, NULL_TREE));
+  DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
+
+  fprintf (file, "\t# Stub function for %s (", current_function_name);
+  need_comma = 0;
+  for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
+    {
+      fprintf (file, "%s%s",
+	       need_comma ? ", " : "",
+	       (f & 3) == 1 ? "float" : "double");
+      need_comma = 1;
+    }
+  fprintf (file, ")\n");
+
+  fprintf (file, "\t.set\tnomips16\n");
+  function_section (stubdecl);
+  ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
+
+  /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
+     within a .ent, and we can not emit another .ent.  */
+#ifndef FUNCTION_NAME_ALREADY_DECLARED
+  fputs ("\t.ent\t", file);
+  assemble_name (file, stubname);
+  fputs ("\n", file);
+#endif
+
+  assemble_name (file, stubname);
+  fputs (":\n", file);
+
+  /* We don't want the assembler to insert any nops here.  */
+  fprintf (file, "\t.set\tnoreorder\n");
+
+  mips16_fp_args (file, current_function_args_info.fp_code, 1);
+
+  fprintf (asm_out_file, "\t.set\tnoat\n");
+  fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
+  assemble_name (file, fnname);
+  fprintf (file, "\n");
+  fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
+  fprintf (asm_out_file, "\t.set\tat\n");
+
+  /* Unfortunately, we can't fill the jump delay slot.  We can't fill
+     with one of the mfc1 instructions, because the result is not
+     available for one instruction, so if the very first instruction
+     in the function refers to the register, it will see the wrong
+     value.  */
+  fprintf (file, "\tnop\n");
+
+  fprintf (file, "\t.set\treorder\n");
+
+#ifndef FUNCTION_NAME_ALREADY_DECLARED
+  fputs ("\t.end\t", file);
+  assemble_name (file, stubname);
+  fputs ("\n", file);
+#endif
+
+  fprintf (file, "\t.set\tmips16\n");
+
+  function_section (current_function_decl);
+}
+
+/* We keep a list of functions for which we have already built stubs
+   in build_mips16_call_stub.  */
+
+struct mips16_stub
+{
+  struct mips16_stub *next;
+  char *name;
+  int fpret;
+};
+
+static struct mips16_stub *mips16_stubs;
+
+/* Build a call stub for a mips16 call.  A stub is needed if we are
+   passing any floating point values which should go into the floating
+   point registers.  If we are, and the call turns out to be to a 32
+   bit function, the stub will be used to move the values into the
+   floating point registers before calling the 32 bit function.  The
+   linker will magically adjust the function call to either the 16 bit
+   function or the 32 bit stub, depending upon where the function call
+   is actually defined.
+
+   Similarly, we need a stub if the return value might come back in a
+   floating point register.
+
+   RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
+   (RETVAL is NULL if this is call rather than call_value).  FP_CODE
+   is the code built by function_arg.  This function returns a nonzero
+   value if it builds the call instruction itself.  */
+
+int
+build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
+     rtx retval;
+     rtx fnmem;
+     rtx arg_size;
+     int fp_code;
+{
+  int fpret;
+  rtx fn;
+  char *fnname, *secname, *stubname;
+  struct mips16_stub *l;
+  tree stubid, stubdecl;
+  int need_comma;
+  unsigned int f;
+
+  /* We don't need to do anything if we aren't in mips16 mode, or if
+     we were invoked with the -msoft-float option.  */
+  if (! TARGET_MIPS16 || ! mips16_hard_float)
+    return 0;
+
+  /* Figure out whether the value might come back in a floating point
+     register.  */
+  fpret = (retval != 0
+	   && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
+	   && (! TARGET_SINGLE_FLOAT
+	       || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
+
+  /* We don't need to do anything if there were no floating point
+     arguments and the value will not be returned in a floating point
+     register.  */
+  if (fp_code == 0 && ! fpret)
+    return 0;
+
+  if (GET_CODE (fnmem) != MEM)
+    abort ();
+  fn = XEXP (fnmem, 0);
+
+  /* We don't need to do anything if this is a call to a special
+     mips16 support function.  */
+  if (GET_CODE (fn) == SYMBOL_REF
+      && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
+    return 0;
+
+  /* This code will only work for o32 and o64 abis.  The other ABI's 
+     require more sophisticated support.  */
+  if (mips_abi != ABI_32 && mips_abi != ABI_O64)
+    abort ();
+
+  /* We can only handle SFmode and DFmode floating point return
+     values.  */
+  if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
+    abort ();
+
+  /* If we're calling via a function pointer, then we must always call
+     via a stub.  There are magic stubs provided in libgcc.a for each
+     of the required cases.  Each of them expects the function address
+     to arrive in register $2.  */
+
+  if (GET_CODE (fn) != SYMBOL_REF)
+    {
+      char buf[30];
+      tree id;
+      rtx stub_fn, stub_mem, insn;
+
+      /* ??? If this code is modified to support other ABI's, we need
+         to handle PARALLEL return values here.  */
+
+      sprintf (buf, "__mips16_call_stub_%s%d",
+	       (fpret
+		? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
+		: ""),
+	       fp_code);
+      id = get_identifier (buf);
+      stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
+      stub_mem = gen_rtx (MEM, Pmode, stub_fn);
+
+      emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
+
+      if (retval == NULL_RTX)
+	insn = gen_call_internal0 (stub_mem, arg_size,
+				   gen_rtx (REG, SImode,
+					    GP_REG_FIRST + 31));
+      else
+	insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
+					 gen_rtx (REG, SImode,
+						  GP_REG_FIRST + 31));
+      insn = emit_call_insn (insn);
+
+      /* Put the register usage information on the CALL.  */
+      if (GET_CODE (insn) != CALL_INSN)
+	abort ();
+      CALL_INSN_FUNCTION_USAGE (insn) =
+	gen_rtx (EXPR_LIST, VOIDmode,
+		 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
+		 CALL_INSN_FUNCTION_USAGE (insn));
+
+      /* If we are handling a floating point return value, we need to
+         save $18 in the function prologue.  Putting a note on the
+         call will mean that regs_ever_live[$18] will be true if the
+         call is not eliminated, and we can check that in the prologue
+         code.  */
+      if (fpret)
+	CALL_INSN_FUNCTION_USAGE (insn) =
+	  gen_rtx (EXPR_LIST, VOIDmode,
+		   gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
+		   CALL_INSN_FUNCTION_USAGE (insn));
+
+      /* Return 1 to tell the caller that we've generated the call
+         insn.  */
+      return 1;
+    }
+
+  /* We know the function we are going to call.  If we have already
+     built a stub, we don't need to do anything further.  */
+
+  fnname = XSTR (fn, 0);
+  for (l = mips16_stubs; l != NULL; l = l->next)
+    if (strcmp (l->name, fnname) == 0)
+      break;
+
+  if (l == NULL)
+    {
+      /* Build a special purpose stub.  When the linker sees a
+	 function call in mips16 code, it will check where the target
+	 is defined.  If the target is a 32 bit call, the linker will
+	 search for the section defined here.  It can tell which
+	 symbol this section is associated with by looking at the
+	 relocation information (the name is unreliable, since this
+	 might be a static function).  If such a section is found, the
+	 linker will redirect the call to the start of the magic
+	 section.
+
+	 If the function does not return a floating point value, the
+	 special stub section is named
+	     .mips16.call.FNNAME
+
+	 If the function does return a floating point value, the stub
+	 section is named
+	     .mips16.call.fp.FNNAME
+	 */
+
+      secname = (char *) alloca (strlen (fnname) + 40);
+      sprintf (secname, ".mips16.call.%s%s",
+	       fpret ? "fp." : "",
+	       fnname);
+      stubname = (char *) alloca (strlen (fnname) + 20);
+      sprintf (stubname, "__call_stub_%s%s",
+	       fpret ? "fp_" : "",
+	       fnname);
+      stubid = get_identifier (stubname);
+      stubdecl = build_decl (FUNCTION_DECL, stubid,
+			     build_function_type (void_type_node, NULL_TREE));
+      DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
+
+      fprintf (asm_out_file, "\t# Stub function to call %s%s (",
+	       (fpret
+		? (GET_MODE (retval) == SFmode ? "float " : "double ")
+		: ""),
+	       fnname);
+      need_comma = 0;
+      for (f = (unsigned int) fp_code; f != 0; f >>= 2)
+	{
+	  fprintf (asm_out_file, "%s%s",
+		   need_comma ? ", " : "",
+		   (f & 3) == 1 ? "float" : "double");
+	  need_comma = 1;
+	}
+      fprintf (asm_out_file, ")\n");
+
+      fprintf (asm_out_file, "\t.set\tnomips16\n");
+      assemble_start_function (stubdecl, stubname);
+
+#ifndef FUNCTION_NAME_ALREADY_DECLARED
+      fputs ("\t.ent\t", asm_out_file);
+      assemble_name (asm_out_file, stubname);
+      fputs ("\n", asm_out_file);
+
+      assemble_name (asm_out_file, stubname);
+      fputs (":\n", asm_out_file);
+#endif
+
+      /* We build the stub code by hand.  That's the only way we can
+	 do it, since we can't generate 32 bit code during a 16 bit
+	 compilation. */
+
+      /* We don't want the assembler to insert any nops here.  */
+      fprintf (asm_out_file, "\t.set\tnoreorder\n");
+
+      mips16_fp_args (asm_out_file, fp_code, 0);
+
+      if (! fpret)
+	{
+	  fprintf (asm_out_file, "\t.set\tnoat\n");
+	  fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
+		   fnname);
+	  fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
+	  fprintf (asm_out_file, "\t.set\tat\n");
+	  /* Unfortunately, we can't fill the jump delay slot.  We
+	     can't fill with one of the mtc1 instructions, because the
+	     result is not available for one instruction, so if the
+	     very first instruction in the function refers to the
+	     register, it will see the wrong value.  */
+	  fprintf (asm_out_file, "\tnop\n");
+	}
+      else
+	{
+	  fprintf (asm_out_file, "\tmove\t%s,%s\n",
+		   reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
+	  fprintf (asm_out_file, "\tjal\t%s\n", fnname);
+	  /* As above, we can't fill the delay slot.  */
+	  fprintf (asm_out_file, "\tnop\n");
+	  if (GET_MODE (retval) == SFmode)
+	    fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
+		     reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
+	  else
+	    {
+	      if (TARGET_BIG_ENDIAN)
+		{
+		  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
+			   reg_names[GP_REG_FIRST + 2],
+			   reg_names[FP_REG_FIRST + 1]);
+		  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
+			   reg_names[GP_REG_FIRST + 3],
+			   reg_names[FP_REG_FIRST + 0]);
+		}
+	      else
+		{
+		  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
+			   reg_names[GP_REG_FIRST + 2],
+			   reg_names[FP_REG_FIRST + 0]);
+		  fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
+			   reg_names[GP_REG_FIRST + 3],
+			   reg_names[FP_REG_FIRST + 1]);
+		}
+	    }
+	  fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
+	  /* As above, we can't fill the delay slot.  */
+	  fprintf (asm_out_file, "\tnop\n");
+	}
+
+      fprintf (asm_out_file, "\t.set\treorder\n");
+
+#ifdef ASM_DECLARE_FUNCTION_SIZE
+      ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
+#endif
+
+#ifndef FUNCTION_NAME_ALREADY_DECLARED
+      fputs ("\t.end\t", asm_out_file);
+      assemble_name (asm_out_file, stubname);
+      fputs ("\n", asm_out_file);
+#endif
+
+      fprintf (asm_out_file, "\t.set\tmips16\n");
+
+      /* Record this stub.  */
+      l = (struct mips16_stub *) xmalloc (sizeof *l);
+      l->name = (char *) xmalloc (strlen (fnname) + 1);
+      strcpy (l->name, fnname);
+      l->fpret = fpret;
+      l->next = mips16_stubs;
+      mips16_stubs = l;
+    }
+
+  /* If we expect a floating point return value, but we've built a
+     stub which does not expect one, then we're in trouble.  We can't
+     use the existing stub, because it won't handle the floating point
+     value.  We can't build a new stub, because the linker won't know
+     which stub to use for the various calls in this object file.
+     Fortunately, this case is illegal, since it means that a function
+     was declared in two different ways in a single compilation.  */
+  if (fpret && ! l->fpret)
+    error ("can not handle inconsistent calls to `%s'", fnname);
+
+  /* If we are calling a stub which handles a floating point return
+     value, we need to arrange to save $18 in the prologue.  We do
+     this by marking the function call as using the register.  The
+     prologue will later see that it is used, and emit code to save
+     it.  */
+
+  if (l->fpret)
+    {
+      rtx insn;
+
+      if (retval == NULL_RTX)
+	insn = gen_call_internal0 (fnmem, arg_size,
+				   gen_rtx (REG, SImode,
+					    GP_REG_FIRST + 31));
+      else
+	insn = gen_call_value_internal0 (retval, fnmem, arg_size,
+					 gen_rtx (REG, SImode,
+						  GP_REG_FIRST + 31));
+      insn = emit_call_insn (insn);
+
+      if (GET_CODE (insn) != CALL_INSN)
+	abort ();
+
+      CALL_INSN_FUNCTION_USAGE (insn) =
+	gen_rtx (EXPR_LIST, VOIDmode,
+		 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
+		 CALL_INSN_FUNCTION_USAGE (insn));
+
+      /* Return 1 to tell the caller that we've generated the call
+         insn.  */
+      return 1;
+    }
+
+  /* Return 0 to let the caller generate the call insn.  */
+  return 0;
+}
+
+/* This function looks through the code for a function, and tries to
+   optimize the usage of the $gp register.  We arrange to copy $gp
+   into a pseudo-register, and then let gcc's normal reload handling
+   deal with the pseudo-register.  Unfortunately, if reload choose to
+   put the pseudo-register into a call-clobbered register, it will
+   emit saves and restores for that register around any function
+   calls.  We don't need the saves, and it's faster to copy $gp than
+   to do an actual restore.  ??? This still means that we waste a
+   stack slot.
+
+   This is an optimization, and the code which gcc has actually
+   generated is correct, so we do not need to catch all cases.  */
+
+static void
+mips16_optimize_gp (first)
+     rtx first;
+{
+  rtx gpcopy, slot, insn;
+
+  /* Look through the instructions.  Set GPCOPY to the register which
+     holds a copy of $gp.  Set SLOT to the stack slot where it is
+     saved.  If we find an instruction which sets GPCOPY to anything
+     other than $gp or SLOT, then we can't use it.  If we find an
+     instruction which sets SLOT to anything other than GPCOPY, we
+     can't use it.  */
+
+  gpcopy = NULL_RTX;
+  slot = NULL_RTX;
+  for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
+    {
+      rtx set;
+
+      if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
+	continue;
+
+      set = PATTERN (insn);
+
+      /* We know that all references to memory will be inside a SET,
+         because there is no other way to access memory on the mips16.
+         We don't have to worry about a PARALLEL here, because the
+         mips.md file will never generate them for memory references.  */
+      if (GET_CODE (set) != SET)
+	continue;
+
+      if (gpcopy == NULL_RTX
+	  && GET_CODE (SET_SRC (set)) == CONST
+	  && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
+	  && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
+	  && GET_CODE (SET_DEST (set)) == REG
+	  && GET_MODE (SET_DEST (set)) == Pmode)
+	gpcopy = SET_DEST (set);
+      else if (slot == NULL_RTX
+	       && gpcopy != NULL_RTX
+	       && GET_CODE (SET_DEST (set)) == MEM
+	       && GET_CODE (SET_SRC (set)) == REG
+	       && REGNO (SET_SRC (set)) == REGNO (gpcopy)
+	       && GET_MODE (SET_DEST (set)) == Pmode)
+	{
+	  rtx base, offset;
+
+	  offset = const0_rtx;
+	  base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
+	  if (GET_CODE (base) == REG
+	      && (REGNO (base) == STACK_POINTER_REGNUM
+		  || REGNO (base) == FRAME_POINTER_REGNUM))
+	    slot = SET_DEST (set);
+	}
+      else if (gpcopy != NULL_RTX
+	       && (GET_CODE (SET_DEST (set)) == REG
+		   || GET_CODE (SET_DEST (set)) == SUBREG)
+	       && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
+	       && (GET_CODE (SET_DEST (set)) != REG
+		   || REGNO (SET_DEST (set)) != REGNO (gpcopy)
+		   || GET_MODE (SET_DEST (set)) != Pmode
+		   || ((GET_CODE (SET_SRC (set)) != CONST
+			|| GET_CODE (XEXP (SET_SRC (set), 0)) != REG
+			|| (REGNO (XEXP (SET_SRC (set), 0))
+			    != GP_REG_FIRST + 28))
+		       && ! rtx_equal_p (SET_SRC (set), slot))))
+	break;
+      else if (slot != NULL_RTX
+	       && GET_CODE (SET_DEST (set)) == MEM
+	       && rtx_equal_p (SET_DEST (set), slot)
+	       && (GET_CODE (SET_SRC (set)) != REG
+		   || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
+	break;
+    }
+
+  /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
+     different optimization.  Any time we find a copy of $28 into a
+     register, followed by an add of a symbol_ref to that register, we
+     convert it to load the value from the constant table instead.
+     The copy and add will take six bytes, just as the load and
+     constant table entry will take six bytes.  However, it is
+     possible that the constant table entry will be shared.
+
+     This could be a peephole optimization, but I don't know if the
+     peephole code can call force_const_mem.
+
+     Using the same register for the copy of $28 and the add of the
+     symbol_ref is actually pretty likely, since the add instruction
+     requires the destination and the first addend to be the same
+     register.  */
+
+  if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
+    {
+      rtx next;
+
+      /* This optimization is only reasonable if the constant table
+         entries are only 4 bytes.  */
+      if (Pmode != SImode)
+	return;
+
+      for (insn = first; insn != NULL_RTX; insn = next)
+	{
+	  rtx set1, set2;
+
+	  next = insn;
+	  do
+	    {
+	      next = NEXT_INSN (next);
+	    }
+	  while (next != NULL_RTX
+		 && (GET_CODE (next) == NOTE
+		     || (GET_CODE (next) == INSN
+			 && (GET_CODE (PATTERN (next)) == USE
+			     || GET_CODE (PATTERN (next)) == CLOBBER))));
+
+	  if (next == NULL_RTX)
+	    break;
+
+	  if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
+	    continue;
+
+	  if (GET_RTX_CLASS (GET_CODE (next)) != 'i')
+	    continue;
+
+	  set1 = PATTERN (insn);
+	  if (GET_CODE (set1) != SET)
+	    continue;
+	  set2 = PATTERN (next);
+	  if (GET_CODE (set2) != SET)
+	    continue;
+
+	  if (GET_CODE (SET_DEST (set1)) == REG
+	      && GET_CODE (SET_SRC (set1)) == CONST
+	      && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
+	      && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
+	      && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
+	      && GET_CODE (SET_SRC (set2)) == PLUS
+	      && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
+	      && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
+	      && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
+	    {
+	      rtx sym;
+
+	      /* We've found a case we can change to load from the
+                 constant table.  */
+
+	      sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
+	      if (GET_CODE (sym) != SYMBOL_REF)
+		abort ();
+	      emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
+					force_const_mem (Pmode, sym)),
+			       next);
+	      
+	      PUT_CODE (insn, NOTE);
+	      NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+	      NOTE_SOURCE_FILE (insn) = 0;
+
+	      PUT_CODE (next, NOTE);
+	      NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
+	      NOTE_SOURCE_FILE (next) = 0;
+	    }
+	}
+
+      return;
+    }
+
+  /* We can safely remove all assignments to SLOT from GPCOPY, and
+     replace all assignments from SLOT to GPCOPY with assignments from
+     $28.  */
+
+  for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
+    {
+      rtx set;
+
+      if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
+	continue;
+
+      set = PATTERN (insn);
+      if (GET_CODE (set) != SET
+	  || GET_MODE (SET_DEST (set)) != Pmode)
+	continue;
+
+      if (GET_CODE (SET_DEST (set)) == MEM
+	  && rtx_equal_p (SET_DEST (set), slot)
+	  && GET_CODE (SET_SRC (set)) == REG
+	  && REGNO (SET_SRC (set)) == REGNO (gpcopy))
+	{
+	  PUT_CODE (insn, NOTE);
+	  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+	  NOTE_SOURCE_FILE (insn) = 0;
+	}
+      else if (GET_CODE (SET_DEST (set)) == REG
+	       && REGNO (SET_DEST (set)) == REGNO (gpcopy)
+	       && GET_CODE (SET_SRC (set)) == MEM
+	       && rtx_equal_p (SET_SRC (set), slot))
+	{
+	  emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
+				    gen_rtx (CONST, Pmode,
+					     gen_rtx (REG, Pmode,
+						      GP_REG_FIRST + 28))),
+			   insn);
+	  PUT_CODE (insn, NOTE);
+	  NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
+	  NOTE_SOURCE_FILE (insn) = 0;
+	}
+    }
+}
+
+/* We keep a list of constants we which we have to add to internal
+   constant tables in the middle of large functions.  */
+
+struct constant
+{
+  struct constant *next;
+  rtx value;
+  rtx label;
+  enum machine_mode mode;
+};
+
+/* Add a constant to the list in *PCONSTANTS.  */
+
+static rtx
+add_constant (pconstants, val, mode)
+     struct constant **pconstants;
+     rtx val;
+     enum machine_mode mode;
+{
+  struct constant *c;
+
+  for (c = *pconstants; c != NULL; c = c->next)
+    if (mode == c->mode && rtx_equal_p (val, c->value))
+      return c->label;
+
+  c = (struct constant *) xmalloc (sizeof *c);
+  c->value = val;
+  c->mode = mode;
+  c->label = gen_label_rtx ();
+  c->next = *pconstants;
+  *pconstants = c;
+  return c->label;
+}
+
+/* Dump out the constants in CONSTANTS after INSN.  */
+
+static void
+dump_constants (constants, insn)
+     struct constant *constants;
+     rtx insn;
+{
+  struct constant *c;
+  int align;
+
+  c = constants;
+  align = 0;
+  while (c != NULL)
+    {
+      rtx r;
+      struct constant *next;
+
+      switch (GET_MODE_SIZE (c->mode))
+	{
+	case 1:
+	  align = 0;
+	  break;
+	case 2:
+	  if (align < 1)
+	    insn = emit_insn_after (gen_align_2 (), insn);
+	  align = 1;
+	  break;
+	case 4:
+	  if (align < 2)
+	    insn = emit_insn_after (gen_align_4 (), insn);
+	  align = 2;
+	  break;
+	default:
+	  if (align < 3)
+	    insn = emit_insn_after (gen_align_8 (), insn);
+	  align = 3;
+	  break;
+	}
+
+      insn = emit_label_after (c->label, insn);
+
+      switch (c->mode)
+	{
+	case QImode:
+	  r = gen_consttable_qi (c->value);
+	  break;
+	case HImode:
+	  r = gen_consttable_hi (c->value);
+	  break;
+	case SImode:
+	  r = gen_consttable_si (c->value);
+	  break;
+	case SFmode:
+	  r = gen_consttable_sf (c->value);
+	  break;
+	case DImode:
+	  r = gen_consttable_di (c->value);
+	  break;
+	case DFmode:
+	  r = gen_consttable_df (c->value);
+	  break;
+	default:
+	  abort ();
+	}
+
+      insn = emit_insn_after (r, insn);
+
+      next = c->next;
+      free (c);
+      c = next;
+    }
+
+  emit_barrier_after (insn);
+}
+
+/* Find the symbol in an address expression.  */
+
+static rtx
+mips_find_symbol (addr)
+     rtx addr;
+{
+  if (GET_CODE (addr) == MEM)
+    addr = XEXP (addr, 0);
+  while (GET_CODE (addr) == CONST)
+    addr = XEXP (addr, 0);
+  if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
+    return addr;
+  if (GET_CODE (addr) == PLUS)
+    {
+      rtx l1, l2;
+
+      l1 = mips_find_symbol (XEXP (addr, 0));
+      l2 = mips_find_symbol (XEXP (addr, 1));
+      if (l1 != NULL_RTX && l2 == NULL_RTX)
+	return l1;
+      else if (l1 == NULL_RTX && l2 != NULL_RTX)
+	return l2;
+    }
+  return NULL_RTX;
+}
+
+/* Exported to toplev.c.
+
+   Do a final pass over the function, just before delayed branch
+   scheduling.  */
+
+void
+machine_dependent_reorg (first)
+     rtx first;
+{
+  int insns_len, max_internal_pool_size, pool_size, addr;
+  rtx insn;
+  struct constant *constants;
+
+  if (! TARGET_MIPS16)
+    return;
+
+  /* If $gp is used, try to remove stores, and replace loads with
+     copies from $gp.  */
+  if (optimize)
+    mips16_optimize_gp (first);
+
+  /* Scan the function looking for PC relative loads which may be out
+     of range.  All such loads will either be from the constant table,
+     or be getting the address of a constant string.  If the size of
+     the function plus the size of the constant table is less than
+     0x8000, then all loads are in range.  */
+
+  insns_len = 0;
+  for (insn = first; insn; insn = NEXT_INSN (insn))
+    {
+      insns_len += get_attr_length (insn) * 2;
+
+      /* ??? We put switch tables in .text, but we don't define
+         JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
+         compute their lengths correctly.  */
+      if (GET_CODE (insn) == JUMP_INSN)
+	{
+	  rtx body;
+
+	  body = PATTERN (insn);
+	  if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
+	    insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
+			  * GET_MODE_SIZE (GET_MODE (body)));
+	  insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
+	}
+    }
+
+  /* Store the original value of insns_len in current_frame_info, so
+     that simple_memory_operand can look at it.  */
+  current_frame_info.insns_len = insns_len;
+
+  pool_size = get_pool_size ();
+  if (insns_len + pool_size + mips_string_length < 0x8000)
+    return;
+
+  /* Loop over the insns and figure out what the maximum internal pool
+     size could be.  */
+  max_internal_pool_size = 0;
+  for (insn = first; insn; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN
+	  && GET_CODE (PATTERN (insn)) == SET)
+	{
+	  rtx src;
+
+	  src = mips_find_symbol (SET_SRC (PATTERN (insn)));
+	  if (src == NULL_RTX)
+	    continue;
+	  if (CONSTANT_POOL_ADDRESS_P (src))
+	    max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
+	  else if (SYMBOL_REF_FLAG (src))
+	    max_internal_pool_size += GET_MODE_SIZE (Pmode);
+	}
+    }
+
+  constants = NULL;
+  addr = 0;
+
+  for (insn = first; insn; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN
+	  && GET_CODE (PATTERN (insn)) == SET)
+	{
+	  rtx val, src;
+	  enum machine_mode mode;
+
+	  val = NULL_RTX;
+	  src = mips_find_symbol (SET_SRC (PATTERN (insn)));
+	  if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
+	    {
+	      /* ??? This is very conservative, which means that we
+                 will generate too many copies of the constant table.
+                 The only solution would seem to be some form of
+                 relaxing.  */
+	      if (((insns_len - addr)
+		   + max_internal_pool_size
+		   + get_pool_offset (src))
+		  >= 0x8000)
+		{
+		  val = get_pool_constant (src);
+		  mode = get_pool_mode (src);
+		}
+	      max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
+	    }
+	  else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
+	    {
+	      /* Including all of mips_string_length is conservative,
+                 and so is including all of max_internal_pool_size.  */
+	      if (((insns_len - addr)
+		   + max_internal_pool_size
+		   + pool_size
+		   + mips_string_length)
+		  >= 0x8000)
+	      val = src;
+	      mode = Pmode;
+	      max_internal_pool_size -= Pmode;
+	    }
+
+	  if (val != NULL_RTX)
+	    {
+	      rtx lab, newsrc;
+
+	      /* This PC relative load is out of range.  ??? In the
+		 case of a string constant, we are only guessing that
+		 it is range, since we don't know the offset of a
+		 particular string constant.  */
+
+	      lab = add_constant (&constants, val, mode);
+	      newsrc = gen_rtx (MEM, mode,
+				gen_rtx (LABEL_REF, VOIDmode, lab));
+	      RTX_UNCHANGING_P (newsrc) = 1;
+	      PATTERN (insn) = gen_rtx (SET, VOIDmode,
+					SET_DEST (PATTERN (insn)),
+					newsrc);
+	      INSN_CODE (insn) = -1;
+	    }
+	}
+
+      addr += get_attr_length (insn) * 2;
+
+      /* ??? We put switch tables in .text, but we don't define
+         JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
+         compute their lengths correctly.  */
+      if (GET_CODE (insn) == JUMP_INSN)
+	{
+	  rtx body;
+
+	  body = PATTERN (insn);
+	  if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
+	    addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
+			  * GET_MODE_SIZE (GET_MODE (body)));
+	  addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
+	}
+
+      if (GET_CODE (insn) == BARRIER)
+	{
+	  /* Output any constants we have accumulated.  Note that we
+             don't need to change ADDR, since its only use is
+             subtraction from INSNS_LEN, and both would be changed by
+             the same amount.
+	     ??? If the instructions up to the next barrier reuse a
+	     constant, it would often be better to continue
+	     accumulating.  */
+	  if (constants != NULL)
+	    dump_constants (constants, insn);
+	  constants = NULL;
+	}
+
+      /* ??? If we don't find a barrier within 0x8000 bytes of
+         instructions and constants in CONSTANTS, we need to invent
+         one.  This seems sufficiently unlikely that I am not going to
+         worry about it.  */
+    }
+
+  if (constants != NULL)
+    {
+      rtx label, jump, barrier;
+
+      label = gen_label_rtx ();
+      jump = emit_jump_insn_after (gen_jump (label), get_last_insn ());
+      JUMP_LABEL (jump) = label;
+      LABEL_NUSES (label) = 1;
+      barrier = emit_barrier_after (jump);
+      emit_label_after (label, barrier);
+      dump_constants (constants, barrier);
+      constants = NULL;
+    }
+
+  /* ??? If we output all references to a constant in internal
+     constants table, we don't need to output the constant in the real
+     constant table, but we have no way to prevent that.  */
+}
+
+/* Return nonzero if X is a SIGN or ZERO extend operator.  */
+int
+extend_operator (x, mode)
+     rtx x;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  enum rtx_code code = GET_CODE (x);
+  return code == SIGN_EXTEND || code == ZERO_EXTEND;
+}
+
+/* Accept any operator that can be used to shift the high half of the
+   input value to the lower half, suitable for truncation.  The
+   remainder (the lower half of the input, and the upper half of the
+   output) will be discarded.  */
+int
+highpart_shift_operator (x, mode)
+     rtx x;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  enum rtx_code code = GET_CODE (x);
+  return (code == LSHIFTRT
+	  || code == ASHIFTRT
+	  || code == ROTATERT
+	  || code == ROTATE);
+}
+
+
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
new file mode 100755
index 0000000..df6e28d
--- /dev/null
+++ b/gcc/config/mips/mips.h
@@ -0,0 +1,4760 @@
+/* Definitions of target machine for GNU compiler.  MIPS version.
+   Copyright (C) 1989, 90-97, 1998 Free Software Foundation, Inc.
+   Contributed by A. Lichnewsky (lich@inria.inria.fr).
+   Changed by Michael Meissner	(meissner@osf.org).
+   64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
+   Brendan Eich (brendan@microunity.com).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+/* Standard GCC variables that we reference.  */
+
+extern char    *asm_file_name;
+extern char	call_used_regs[];
+extern int	current_function_calls_alloca;
+extern char    *language_string;
+extern int	may_call_alloca;
+extern char   **save_argv;
+extern int	target_flags;
+extern char    *version_string;
+
+/* MIPS external variables defined in mips.c.  */
+
+/* comparison type */
+enum cmp_type {
+  CMP_SI,				/* compare four byte integers */
+  CMP_DI,				/* compare eight byte integers */
+  CMP_SF,				/* compare single precision floats */
+  CMP_DF,				/* compare double precision floats */
+  CMP_MAX				/* max comparison type */
+};
+
+/* types of delay slot */
+enum delay_type {
+  DELAY_NONE,				/* no delay slot */
+  DELAY_LOAD,				/* load from memory delay */
+  DELAY_HILO,				/* move from/to hi/lo registers */
+  DELAY_FCMP				/* delay after doing c.<xx>.{d,s} */
+};
+
+/* Which processor to schedule for.  Since there is no difference between
+   a R2000 and R3000 in terms of the scheduler, we collapse them into
+   just an R3000.  The elements of the enumeration must match exactly
+   the cpu attribute in the mips.md machine description.  */
+
+enum processor_type {
+  PROCESSOR_DEFAULT,
+  PROCESSOR_R3000,
+  PROCESSOR_R3900,
+  PROCESSOR_R6000,
+  PROCESSOR_R4000,
+  PROCESSOR_R4100,
+  PROCESSOR_R4300,
+  PROCESSOR_R4600,
+  PROCESSOR_R4650,
+  PROCESSOR_R5000,
+  PROCESSOR_R5400,		/* CYGNUS LOCAL vr5400/raeburn */
+  PROCESSOR_R8000
+};
+
+/* Recast the cpu class to be the cpu attribute.  */
+#define mips_cpu_attr ((enum attr_cpu)mips_cpu)
+
+/* Which ABI to use.  These are constants because abi64.h must check their
+   value at preprocessing time.
+
+   ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
+   defined by SGI.  ABI_O64 is o32 extended to work on a 64 bit machine. */
+
+#define ABI_32  0
+#define ABI_N32 1
+#define ABI_64  2
+#define ABI_EABI 3
+#define ABI_O64  4
+
+#ifndef MIPS_ABI_DEFAULT
+/* We define this away so that there is no extra runtime cost if the target
+   doesn't support multiple ABIs.  */
+#define mips_abi ABI_32
+#else
+extern int mips_abi;
+#endif
+
+/* Whether to emit abicalls code sequences or not.  */
+
+enum mips_abicalls_type {
+  MIPS_ABICALLS_NO,
+  MIPS_ABICALLS_YES
+};
+
+/* Recast the abicalls class to be the abicalls attribute.  */
+#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
+
+/* Which type of block move to do (whether or not the last store is
+   split out so it can fill a branch delay slot).  */
+
+enum block_move_type {
+  BLOCK_MOVE_NORMAL,			/* generate complete block move */
+  BLOCK_MOVE_NOT_LAST,			/* generate all but last store */
+  BLOCK_MOVE_LAST			/* generate just the last store */
+};
+
+extern char mips_reg_names[][8];	/* register names (a0 vs. $4). */
+extern char mips_print_operand_punct[];	/* print_operand punctuation chars */
+extern char *current_function_file;	/* filename current function is in */
+extern int num_source_filenames;	/* current .file # */
+extern int inside_function;		/* != 0 if inside of a function */
+extern int ignore_line_number;		/* != 0 if we are to ignore next .loc */
+extern int file_in_function_warning;	/* warning given about .file in func */
+extern int sdb_label_count;		/* block start/end next label # */
+extern int sdb_begin_function_line;     /* Starting Line of current function */
+extern int mips_section_threshold;	/* # bytes of data/sdata cutoff */
+extern int g_switch_value;		/* value of the -G xx switch */
+extern int g_switch_set;		/* whether -G xx was passed.  */
+extern int sym_lineno;			/* sgi next label # for each stmt */
+extern int set_noreorder;		/* # of nested .set noreorder's  */
+extern int set_nomacro;			/* # of nested .set nomacro's  */
+extern int set_noat;			/* # of nested .set noat's  */
+extern int set_volatile;		/* # of nested .set volatile's  */
+extern int mips_branch_likely;		/* emit 'l' after br (branch likely) */
+extern int mips_dbx_regno[];		/* Map register # to debug register # */
+extern struct rtx_def *branch_cmp[2];	/* operands for compare */
+extern enum cmp_type branch_type;	/* what type of branch to use */
+extern enum processor_type mips_cpu;	/* which cpu are we scheduling for */
+extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
+extern int mips_isa;			/* architectural level */
+extern int mips16;			/* whether generating mips16 code */
+extern int mips16_hard_float;		/* mips16 without -msoft-float */
+extern int mips_entry;			/* generate entry/exit for mips16 */
+extern char *mips_cpu_string;		/* for -mcpu=<xxx> */
+extern char *mips_isa_string;		/* for -mips{1,2,3,4} */
+extern char *mips_abi_string;		/* for -mabi={32,n32,64} */
+extern char *mips_entry_string;		/* for -mentry */
+extern char *mips_no_mips16_string;	/* for -mno-mips16 */
+extern int mips_split_addresses;	/* perform high/lo_sum support */
+extern int dslots_load_total;		/* total # load related delay slots */
+extern int dslots_load_filled;		/* # filled load delay slots */
+extern int dslots_jump_total;		/* total # jump related delay slots */
+extern int dslots_jump_filled;		/* # filled jump delay slots */
+extern int dslots_number_nops;		/* # of nops needed by previous insn */
+extern int num_refs[3];			/* # 1/2/3 word references */
+extern struct rtx_def *mips_load_reg;	/* register to check for load delay */
+extern struct rtx_def *mips_load_reg2;	/* 2nd reg to check for load delay */
+extern struct rtx_def *mips_load_reg3;	/* 3rd reg to check for load delay */
+extern struct rtx_def *mips_load_reg4;	/* 4th reg to check for load delay */
+extern struct rtx_def *embedded_pic_fnaddr_rtx;	/* function address */
+extern int mips_string_length;		/* length of strings for mips16 */
+extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
+
+/* Functions within mips.c that we reference.  Some of these return  type
+   HOST_WIDE_INT, so define that here.  This is a copy of code in machmode.h.
+
+   ??? It would be good to try to put this as common code someplace.  */
+
+#ifndef HOST_BITS_PER_WIDE_INT
+
+#if HOST_BITS_PER_LONG > HOST_BITS_PER_INT
+#define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONG
+#define HOST_WIDE_INT long
+#else
+#define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_INT
+#define HOST_WIDE_INT int
+#endif
+
+#endif
+
+extern void		abort_with_insn ();
+extern int		arith32_operand ();
+extern int		arith_operand ();
+extern int		cmp_op ();
+extern HOST_WIDE_INT	compute_frame_size ();
+extern int		const_float_1_operand ();
+extern void		expand_block_move ();
+extern int		equality_op ();
+extern void		final_prescan_insn ();
+extern struct rtx_def *	function_arg ();
+extern void		function_arg_advance ();
+extern int		function_arg_partial_nregs ();
+extern int		function_arg_pass_by_reference ();
+extern void		function_epilogue ();
+extern void		function_prologue ();
+extern void		gen_conditional_branch ();
+extern void		gen_conditional_move ();
+extern struct rtx_def * gen_int_relational ();
+extern void		init_cumulative_args ();
+extern int		large_int ();
+extern void		machine_dependent_reorg ();
+extern int		mips_address_cost ();
+extern void		mips_asm_file_end ();
+extern void		mips_asm_file_start ();
+extern int		mips_can_use_return_insn ();
+extern int		mips_const_double_ok ();
+extern void		mips_count_memory_refs ();
+extern HOST_WIDE_INT	mips_debugger_offset ();
+extern void		mips_declare_object ();
+extern int		mips_epilogue_delay_slots ();
+extern void		mips_expand_epilogue ();
+extern void		mips_expand_prologue ();
+extern int		mips_check_split ();
+extern char	       *mips_fill_delay_slot ();
+extern char	       *mips_move_1word ();
+extern char	       *mips_move_2words ();
+extern void		mips_output_double ();
+extern int		mips_output_external ();
+extern void		mips_output_float ();
+extern void		mips_output_filename ();
+extern void		mips_output_lineno ();
+extern char	       *output_block_move ();
+extern void		override_options ();
+extern int		pc_or_label_operand ();
+extern void		print_operand_address ();
+extern void		print_operand ();
+extern void		print_options ();
+extern int		reg_or_0_operand ();
+extern int		true_reg_or_0_operand ();
+extern int		simple_epilogue_p ();
+extern int		simple_memory_operand ();
+extern int		double_memory_operand ();
+extern int		small_int ();
+extern void		trace ();
+extern int		uns_arith_operand ();
+extern struct rtx_def *	embedded_pic_offset ();
+extern void		mips_order_regs_for_local_alloc ();
+extern struct rtx_def *	mips16_gp_pseudo_reg ();
+extern struct rtx_def * mips16_gp_offset ();
+extern int		mips16_gp_offset_p ();
+extern int		mips16_constant ();
+extern int		mips16_constant_after_function_p ();
+extern int		build_mips16_call_stub ();
+
+/* Recognition functions that return if a condition is true.  */
+extern int		address_operand ();
+extern int		call_insn_operand ();
+extern int		const_double_operand ();
+extern int		const_int_operand ();
+extern int		consttable_operand ();
+extern int		general_operand ();
+extern int		immediate_operand ();
+extern int		memory_address_p ();
+extern int		memory_operand ();
+extern int		nonimmediate_operand ();
+extern int		nonmemory_operand ();
+extern int		pic_address_needs_scratch ();
+extern int		register_operand ();
+extern int		scratch_operand ();
+extern int		move_operand ();
+extern int		movdi_operand ();
+extern int		se_register_operand ();
+extern int		se_reg_or_0_operand ();
+extern int		se_uns_arith_operand ();
+extern int		se_arith_operand ();
+extern int		se_nonmemory_operand ();
+extern int		se_nonimmediate_operand ();
+extern int              extend_operator ();
+extern int              highpart_shift_operator ();
+extern int		m16_uimm3_b ();
+extern int		m16_simm4_1 ();
+extern int		m16_nsimm4_1 ();
+extern int		m16_simm5_1 ();
+extern int		m16_nsimm5_1 ();
+extern int		m16_uimm5_4 ();
+extern int		m16_nuimm5_4 ();
+extern int		m16_simm8_1 ();
+extern int		m16_nsimm8_1 ();
+extern int		m16_uimm8_1 ();
+extern int		m16_nuimm8_1 ();
+extern int		m16_uimm8_m1_1 ();
+extern int		m16_uimm8_4 ();
+extern int		m16_nuimm8_4 ();
+extern int		m16_simm8_8 ();
+extern int		m16_nsimm8_8 ();
+extern int		m16_usym8_4 ();
+extern int		m16_usym5_4 ();
+
+/* Functions to change what output section we are using.  */
+extern void		data_section ();
+extern void		rdata_section ();
+extern void		readonly_data_section ();
+extern void		sdata_section ();
+extern void		text_section ();
+extern void		mips_select_rtx_section ();
+extern void		mips_select_section ();
+
+/* Stubs for half-pic support if not OSF/1 reference platform.  */
+
+#ifndef HALF_PIC_P
+#define HALF_PIC_P() 0
+#define HALF_PIC_NUMBER_PTRS 0
+#define HALF_PIC_NUMBER_REFS 0
+#define HALF_PIC_ENCODE(DECL)
+#define HALF_PIC_DECLARE(NAME)
+#define HALF_PIC_INIT()	error ("half-pic init called on systems that don't support it.")
+#define HALF_PIC_ADDRESS_P(X) 0
+#define HALF_PIC_PTR(X) X
+#define HALF_PIC_FINISH(STREAM)
+#endif
+
+
+/* Run-time compilation parameters selecting different hardware subsets.  */
+
+/* Macros used in the machine description to test the flags.  */
+
+					/* Bits for real switches */
+#define MASK_INT64	0x00000001	/* ints are 64 bits */
+#define MASK_LONG64	0x00000002	/* longs and pointers are 64 bits */
+#define MASK_SPLIT_ADDR	0x00000004	/* Address splitting is enabled.  */
+#define MASK_GPOPT	0x00000008	/* Optimize for global pointer */
+#define MASK_GAS	0x00000010	/* Gas used instead of MIPS as */
+#define MASK_NAME_REGS	0x00000020	/* Use MIPS s/w reg name convention */
+#define MASK_STATS	0x00000040	/* print statistics to stderr */
+#define MASK_MEMCPY	0x00000080	/* call memcpy instead of inline code*/
+#define MASK_SOFT_FLOAT	0x00000100	/* software floating point */
+#define MASK_FLOAT64	0x00000200	/* fp registers are 64 bits */
+#define MASK_ABICALLS	0x00000400	/* emit .abicalls/.cprestore/.cpload */
+#define MASK_HALF_PIC	0x00000800	/* Emit OSF-style pic refs to externs*/
+#define MASK_LONG_CALLS	0x00001000	/* Always call through a register */
+#define MASK_64BIT	0x00002000	/* Use 64 bit GP registers and insns */
+#define MASK_EMBEDDED_PIC 0x00004000	/* Generate embedded PIC code */
+#define MASK_EMBEDDED_DATA 0x00008000	/* Reduce RAM usage, not fast code */
+#define MASK_BIG_ENDIAN	0x00010000	/* Generate big endian code */
+#define MASK_SINGLE_FLOAT 0x00020000	/* Only single precision FPU.  */
+#define MASK_MAD	0x00040000	/* Generate mad/madu as on 4650.  */
+#define MASK_4300_MUL_FIX 0x00080000    /* Work-around early Vr4300 CPU bug */
+#define MASK_MIPS3900	0x00100000	/* like -mips1 only 3900 */
+#define MASK_MIPS5400	0x00800000	/* vr5400 port */ /* CYGNUS LOCAL vr5400/raeburn */
+#define MASK_MIPS16	0x01000000	/* Generate mips16 code */
+#define MASK_NO_CHECK_ZERO_DIV 0x04000000	/* divide by zero checking */
+#define MASK_CHECK_RANGE_DIV 0x08000000	/* divide result range checking */
+
+					/* Dummy switches used only in spec's*/
+#define MASK_MIPS_TFILE	0x00000000	/* flag for mips-tfile usage */
+
+					/* Debug switches, not documented */
+#define MASK_DEBUG	0		/* Eliminate version # in .s file */
+#define MASK_DEBUG_A	0x40000000	/* don't allow <label>($reg) addrs */
+#define MASK_DEBUG_B	0x20000000	/* GO_IF_LEGITIMATE_ADDRESS debug */
+#define MASK_DEBUG_C	0x10000000	/* don't expand seq, etc. */
+#define MASK_DEBUG_D	0		/* don't do define_split's */
+#define MASK_DEBUG_E	0		/* function_arg debug */
+#define MASK_DEBUG_F	0
+#define MASK_DEBUG_G	0		/* don't support 64 bit arithmetic */
+#define MASK_DEBUG_H	0               /* allow ints in FP registers */
+#define MASK_DEBUG_I	0		/* unused */
+
+					/* r4000 64 bit sizes */
+#define TARGET_INT64		(target_flags & MASK_INT64)
+#define TARGET_LONG64		(target_flags & MASK_LONG64)
+#define TARGET_FLOAT64		(target_flags & MASK_FLOAT64)
+#define TARGET_64BIT		(target_flags & MASK_64BIT)
+
+					/* Mips vs. GNU linker */
+#define TARGET_SPLIT_ADDRESSES	(target_flags & MASK_SPLIT_ADDR)
+
+/* generate mips 3900 insns */
+#define TARGET_MIPS3900         (target_flags & MASK_MIPS3900)
+
+
+/* CYGNUS LOCAL vr5400/raeburn */
+/* Generate mips vr5400 insns.  */
+#define TARGET_MIPS5400		(target_flags & MASK_MIPS5400)
+/* END CYGNUS LOCAL vr5400/raeburn */
+
+
+
+					/* Mips vs. GNU assembler */
+#define TARGET_GAS		(target_flags & MASK_GAS)
+#define TARGET_UNIX_ASM		(!TARGET_GAS)
+#define TARGET_MIPS_AS		TARGET_UNIX_ASM
+
+					/* Debug Mode */
+#define TARGET_DEBUG_MODE	(target_flags & MASK_DEBUG)
+#define TARGET_DEBUG_A_MODE	(target_flags & MASK_DEBUG_A)
+#define TARGET_DEBUG_B_MODE	(target_flags & MASK_DEBUG_B)
+#define TARGET_DEBUG_C_MODE	(target_flags & MASK_DEBUG_C)
+#define TARGET_DEBUG_D_MODE	(target_flags & MASK_DEBUG_D)
+#define TARGET_DEBUG_E_MODE	(target_flags & MASK_DEBUG_E)
+#define TARGET_DEBUG_F_MODE	(target_flags & MASK_DEBUG_F)
+#define TARGET_DEBUG_G_MODE	(target_flags & MASK_DEBUG_G)
+#define TARGET_DEBUG_H_MODE	(target_flags & MASK_DEBUG_H)
+#define TARGET_DEBUG_I_MODE	(target_flags & MASK_DEBUG_I)
+
+					/* Reg. Naming in .s ($21 vs. $a0) */
+#define TARGET_NAME_REGS	(target_flags & MASK_NAME_REGS)
+
+					/* Optimize for Sdata/Sbss */
+#define TARGET_GP_OPT		(target_flags & MASK_GPOPT)
+
+					/* print program statistics */
+#define TARGET_STATS		(target_flags & MASK_STATS)
+
+					/* call memcpy instead of inline code */
+#define TARGET_MEMCPY		(target_flags & MASK_MEMCPY)
+
+					/* .abicalls, etc from Pyramid V.4 */
+#define TARGET_ABICALLS		(target_flags & MASK_ABICALLS)
+
+					/* OSF pic references to externs */
+#define TARGET_HALF_PIC		(target_flags & MASK_HALF_PIC)
+
+					/* software floating point */
+#define TARGET_SOFT_FLOAT	(target_flags & MASK_SOFT_FLOAT)
+#define TARGET_HARD_FLOAT	(! TARGET_SOFT_FLOAT)
+
+					/* always call through a register */
+#define TARGET_LONG_CALLS	(target_flags & MASK_LONG_CALLS)
+
+					/* generate embedded PIC code;
+					   requires gas.  */
+#define TARGET_EMBEDDED_PIC	(target_flags & MASK_EMBEDDED_PIC)
+
+					/* for embedded systems, optimize for
+					   reduced RAM space instead of for
+					   fastest code.  */
+#define TARGET_EMBEDDED_DATA	(target_flags & MASK_EMBEDDED_DATA)
+
+					/* generate big endian code.  */
+#define TARGET_BIG_ENDIAN	(target_flags & MASK_BIG_ENDIAN)
+
+#define TARGET_SINGLE_FLOAT	(target_flags & MASK_SINGLE_FLOAT)
+#define TARGET_DOUBLE_FLOAT	(! TARGET_SINGLE_FLOAT)
+
+#define TARGET_MAD		(target_flags & MASK_MAD)
+
+#define TARGET_4300_MUL_FIX     (target_flags & MASK_4300_MUL_FIX)
+
+#define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
+#define TARGET_CHECK_RANGE_DIV  (target_flags & MASK_CHECK_RANGE_DIV)
+
+/* This is true if we must enable the assembly language file switching
+   code.  */
+
+#define TARGET_FILE_SWITCHING	(TARGET_GP_OPT && ! TARGET_GAS)
+
+/* We must disable the function end stabs when doing the file switching trick,
+   because the Lscope stabs end up in the wrong place, making it impossible
+   to debug the resulting code.  */
+#define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
+
+					/* Generate mips16 code */
+#define TARGET_MIPS16		(target_flags & MASK_MIPS16)
+
+/* Macro to define tables used to set the flags.
+   This is a list in braces of pairs in braces,
+   each pair being { "NAME", VALUE }
+   where VALUE is the bits to set or minus the bits to clear.
+   An empty string NAME is used to identify the default VALUE.  */
+
+#define TARGET_SWITCHES							\
+{									\
+  {"int64",		  MASK_INT64 | MASK_LONG64},			\
+  {"long64",		  MASK_LONG64},					\
+  {"split-addresses",	  MASK_SPLIT_ADDR},				\
+  {"no-split-addresses", -MASK_SPLIT_ADDR},				\
+  {"mips-as",		 -MASK_GAS},					\
+  {"gas",		  MASK_GAS},					\
+  {"rnames",		  MASK_NAME_REGS},				\
+  {"no-rnames",		 -MASK_NAME_REGS},				\
+  {"gpOPT",		  MASK_GPOPT},					\
+  {"gpopt",		  MASK_GPOPT},					\
+  {"no-gpOPT",		 -MASK_GPOPT},					\
+  {"no-gpopt",		 -MASK_GPOPT},					\
+  {"stats",		  MASK_STATS},					\
+  {"no-stats",		 -MASK_STATS},					\
+  {"memcpy",		  MASK_MEMCPY},					\
+  {"no-memcpy",		 -MASK_MEMCPY},					\
+  {"mips-tfile",	  MASK_MIPS_TFILE},				\
+  {"no-mips-tfile",	 -MASK_MIPS_TFILE},				\
+  {"soft-float",	  MASK_SOFT_FLOAT},				\
+  {"hard-float",	 -MASK_SOFT_FLOAT},				\
+  {"fp64",		  MASK_FLOAT64},				\
+  {"fp32",		 -MASK_FLOAT64},				\
+  {"gp64",		  MASK_64BIT},					\
+  {"gp32",		 -MASK_64BIT},					\
+  {"abicalls",		  MASK_ABICALLS},				\
+  {"no-abicalls",	 -MASK_ABICALLS},				\
+  {"half-pic",		  MASK_HALF_PIC},				\
+  {"no-half-pic",	 -MASK_HALF_PIC},				\
+  {"long-calls",	  MASK_LONG_CALLS},				\
+  {"no-long-calls",	 -MASK_LONG_CALLS},				\
+  {"embedded-pic",	  MASK_EMBEDDED_PIC},				\
+  {"no-embedded-pic",	 -MASK_EMBEDDED_PIC},				\
+  {"embedded-data",	  MASK_EMBEDDED_DATA},				\
+  {"no-embedded-data",	 -MASK_EMBEDDED_DATA},				\
+  {"eb",		  MASK_BIG_ENDIAN},				\
+  {"el",		 -MASK_BIG_ENDIAN},				\
+  {"single-float",	  MASK_SINGLE_FLOAT},				\
+  {"double-float",	 -MASK_SINGLE_FLOAT},				\
+  {"mad",		  MASK_MAD},					\
+  {"no-mad",		 -MASK_MAD},					\
+  {"fix4300",             MASK_4300_MUL_FIX},				\
+  {"no-fix4300",         -MASK_4300_MUL_FIX},				\
+  {"4650",		  MASK_MAD | MASK_SINGLE_FLOAT},		\
+  {"3900",		  MASK_MIPS3900},                               \
+  {"5400",		  MASK_MIPS5400}, /* CYGNUS LOCAL vr5400/raeburn */ \
+  {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV},			\
+  {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV},			\
+  {"check-range-division",MASK_CHECK_RANGE_DIV},			\
+  {"no-check-range-division",-MASK_CHECK_RANGE_DIV},			\
+  {"debug",		  MASK_DEBUG},					\
+  {"debuga",		  MASK_DEBUG_A},				\
+  {"debugb",		  MASK_DEBUG_B},				\
+  {"debugc",		  MASK_DEBUG_C},				\
+  {"debugd",		  MASK_DEBUG_D},				\
+  {"debuge",		  MASK_DEBUG_E},				\
+  {"debugf",		  MASK_DEBUG_F},				\
+  {"debugg",		  MASK_DEBUG_G},				\
+  {"debugh",		  MASK_DEBUG_H},				\
+  {"debugi",		  MASK_DEBUG_I},				\
+  {"",			  (TARGET_DEFAULT				\
+			   | TARGET_CPU_DEFAULT				\
+			   | TARGET_ENDIAN_DEFAULT)}			\
+}
+
+/* Default target_flags if no switches are specified  */
+
+#ifndef TARGET_DEFAULT
+#define TARGET_DEFAULT 0
+#endif
+
+#ifndef TARGET_CPU_DEFAULT
+#define TARGET_CPU_DEFAULT 0
+#endif
+
+#ifndef TARGET_ENDIAN_DEFAULT
+#ifndef DECSTATION
+#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
+#else
+#define TARGET_ENDIAN_DEFAULT 0
+#endif
+#endif
+
+#ifndef MULTILIB_DEFAULTS
+#if TARGET_ENDIAN_DEFAULT == 0
+#define MULTILIB_DEFAULTS { "EL", "mips1" }
+#else
+#define MULTILIB_DEFAULTS { "EB", "mips1" }
+#endif
+#endif
+
+/* We must pass -EL to the linker by default for little endian embedded
+   targets using linker scripts with a OUTPUT_FORMAT line.  Otherwise, the
+   linker will default to using big-endian output files.  The OUTPUT_FORMAT
+   line must be in the linker script, otherwise -EB/-EL will not work.  */
+
+#ifndef LINKER_ENDIAN_SPEC
+#if TARGET_ENDIAN_DEFAULT == 0
+#define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
+#else
+#define LINKER_ENDIAN_SPEC ""
+#endif
+#endif
+
+/* This macro is similar to `TARGET_SWITCHES' but defines names of
+   command options that have values.  Its definition is an
+   initializer with a subgrouping for each command option.
+
+   Each subgrouping contains a string constant, that defines the
+   fixed part of the option name, and the address of a variable. 
+   The variable, type `char *', is set to the variable part of the
+   given option if the fixed part matches.  The actual option name
+   is made by appending `-m' to the specified name.
+
+   Here is an example which defines `-mshort-data-NUMBER'.  If the
+   given option is `-mshort-data-512', the variable `m88k_short_data'
+   will be set to the string `"512"'.
+
+	extern char *m88k_short_data;
+	#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
+
+#define TARGET_OPTIONS							\
+{									\
+  SUBTARGET_TARGET_OPTIONS						\
+  { "cpu=",	&mips_cpu_string	},				\
+  { "ips",	&mips_isa_string	},				\
+  { "entry",	&mips_entry_string	},				\
+  /* CYGNUS LOCAL law */						\
+  { "align-loops=",	&mips_align_loops_string },			\
+  { "align-jumps=",	&mips_align_jumps_string },			\
+  { "align-functions=",	&mips_align_funcs_string },			\
+  { "max-skip-loops=",	&mips_max_skip_loops_string },			\
+  { "max-skip-jumps=",	&mips_max_skip_jumps_string },			\
+  { "max-skip-functions=",	&mips_max_skip_funcs_string },		\
+  /* END CYGNUS LOCAL */						\
+  { "no-mips16", &mips_no_mips16_string	}                               \
+}
+
+/* This is meant to be redefined in the host dependent files.  */
+#define SUBTARGET_TARGET_OPTIONS
+
+#define GENERATE_BRANCHLIKELY  (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
+
+/* Generate three-operand multiply instructions for both SImode and DImode.  */
+#define GENERATE_MULT3         ((TARGET_MIPS3900                         \
+				 )					 \
+				&& !TARGET_MIPS16)
+
+/* Macros to decide whether certain features are available or not,
+   depending on the instruction set architecture level.  */
+
+#define BRANCH_LIKELY_P()	GENERATE_BRANCHLIKELY
+#define HAVE_SQRT_P()		(mips_isa >= 2)
+
+/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
+   -mips2 sets -mfp32 and -mgp32.  This can be overridden by an explicit
+   -mfp32, -mfp64, -mgp32 or -mgp64.  -mfp64 sets MASK_FLOAT64 in
+   target_flags, and -mgp64 sets MASK_64BIT.
+
+   Setting MASK_64BIT in target_flags will cause gcc to assume that
+   registers are 64 bits wide.  int, long and void * will be 32 bit;
+   this may be changed with -mint64 or -mlong64.
+
+   The gen* programs link code that refers to MASK_64BIT.  They don't
+   actually use the information in target_flags; they just refer to
+   it.  */
+
+/* Switch  Recognition by gcc.c.  Add -G xx support */
+
+#ifdef SWITCH_TAKES_ARG
+#undef SWITCH_TAKES_ARG
+#endif
+
+#define SWITCH_TAKES_ARG(CHAR)						\
+  (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
+
+/* Sometimes certain combinations of command options do not make sense
+   on a particular target machine.  You can define a macro
+   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
+   defined, is executed once just after all the command options have
+   been parsed.
+
+   On the MIPS, it is used to handle -G.  We also use it to set up all
+   of the tables referenced in the other macros.  */
+
+#define OVERRIDE_OPTIONS override_options ()
+
+/* Zero or more C statements that may conditionally modify two
+   variables `fixed_regs' and `call_used_regs' (both of type `char
+   []') after they have been initialized from the two preceding
+   macros.
+
+   This is necessary in case the fixed or call-clobbered registers
+   depend on target flags.
+
+   You need not define this macro if it has no work to do.
+
+   If the usage of an entire class of registers depends on the target
+   flags, you may indicate this to GCC by using this macro to modify
+   `fixed_regs' and `call_used_regs' to 1 for each of the registers in
+   the classes which should not be used by GCC.  Also define the macro
+   `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
+   letter for a class that shouldn't be used.
+
+   (However, if this class is not included in `GENERAL_REGS' and all
+   of the insn patterns whose constraints permit this class are
+   controlled by target switches, then GCC will automatically avoid
+   using these registers when the target switches are opposed to
+   them.)  */
+
+#define CONDITIONAL_REGISTER_USAGE					\
+do									\
+  {									\
+    if (!TARGET_HARD_FLOAT)						\
+      {									\
+	int regno;							\
+									\
+	for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)	\
+	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
+	for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)	\
+	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
+      }									\
+    else if (mips_isa < 4)						\
+      {									\
+	int regno;							\
+									\
+	/* We only have a single condition code register.  We		\
+           implement this by hiding all the condition code registers,	\
+           and generating RTL that refers directly to ST_REG_FIRST.  */	\
+	for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)	\
+	  fixed_regs[regno] = call_used_regs[regno] = 1;		\
+      }									\
+    /* In mips16 mode, we permit the $t temporary registers to be used	\
+       for reload.  We prohibit the unused $s registers, since they	\
+       are caller saved, and saving them via a mips16 register would	\
+       probably waste more time than just reloading the value.  */	\
+    if (TARGET_MIPS16)							\
+      {									\
+	fixed_regs[18] = call_used_regs[18] = 1;                        \
+	fixed_regs[19] = call_used_regs[19] = 1;                        \
+	fixed_regs[20] = call_used_regs[20] = 1;                        \
+	fixed_regs[21] = call_used_regs[21] = 1;                        \
+	fixed_regs[22] = call_used_regs[22] = 1;                        \
+	fixed_regs[23] = call_used_regs[23] = 1;                        \
+	fixed_regs[26] = call_used_regs[26] = 1;                        \
+	fixed_regs[27] = call_used_regs[27] = 1;                        \
+	fixed_regs[30] = call_used_regs[30] = 1;                        \
+      }									\
+    SUBTARGET_CONDITIONAL_REGISTER_USAGE				\
+  }									\
+while (0)
+
+/* This is meant to be redefined in the host dependent files.  */
+#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
+
+/* Show we can debug even without a frame pointer.  */
+#define CAN_DEBUG_WITHOUT_FP
+
+/* Complain about missing specs and predefines that should be defined in each
+   of the target tm files to override the defaults.  This is mostly a place-
+   holder until I can get each of the files updated [mm].  */
+
+#if defined(OSF_OS) \
+    || defined(DECSTATION) \
+    || defined(SGI_TARGET) \
+    || defined(MIPS_NEWS) \
+    || defined(MIPS_SYSV) \
+    || defined(MIPS_SVR4) \
+    || defined(MIPS_BSD43)
+
+#ifndef CPP_PREDEFINES
+	#error "Define CPP_PREDEFINES in the appropriate tm.h file"
+#endif
+
+#ifndef LIB_SPEC
+	#error "Define LIB_SPEC in the appropriate tm.h file"
+#endif
+
+#ifndef STARTFILE_SPEC
+	#error "Define STARTFILE_SPEC in the appropriate tm.h file"
+#endif
+
+#ifndef MACHINE_TYPE
+	#error "Define MACHINE_TYPE in the appropriate tm.h file"
+#endif
+#endif
+
+/* Tell collect what flags to pass to nm.  */
+#ifndef NM_FLAGS
+#define NM_FLAGS "-Bn"
+#endif
+
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#ifndef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
+-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
+-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
+#endif
+
+/* Assembler specs.  */
+
+/* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
+   than gas.  */
+
+#define MIPS_AS_ASM_SPEC "\
+%{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
+%{pipe: %e-pipe is not supported.} \
+%{K} %(subtarget_mips_as_asm_spec)"
+
+/* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
+   rather than gas.  It may be overridden by subtargets.  */
+
+#ifndef SUBTARGET_MIPS_AS_ASM_SPEC
+#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
+#endif
+
+/* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
+   assembler.  */
+
+/* CYGNUS LOCAL law; vr5400/raeburn; abi_gas_asm_spec/gavin */
+#define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{m5400}  %{v} %(abi_gas_asm_spec)" /*  */
+/* END CYGNUS LOCAL */
+
+/* CYGNUS LOCAL abi_gas_asm_spec/gavin */
+#ifndef MIPS_ABI_DEFAULT
+#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=32}"
+
+#elif MIPS_ABI_DEFAULT == ABI_32
+#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=32}"
+
+#elif MIPS_ABI_DEFAULT == ABI_N32
+#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=n32}"
+
+#elif MIPS_ABI_DEFAULT == ABI_64
+#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=64}"
+
+#elif MIPS_ABI_DEFAULT == ABI_EABI
+#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=eabi}"
+
+#elif MIPS_ABI_DEFAULT == ABI_O64
+#define ABI_GAS_ASM_SPEC "%{mabi=*} %{!mabi=*:-mabi=o64}"
+
+#else
+#error "Unhandled MIPS_ABI_DEFAULT"
+#endif
+/* END CYGNUS LOCAL abi_gas_asm_spec/gavin */
+
+
+
+
+/* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
+   GAS_ASM_SPEC as the default, depending upon the value of
+   TARGET_DEFAULT.  */
+
+#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
+/* GAS */
+
+#define TARGET_ASM_SPEC "\
+%{mmips-as: %(mips_as_asm_spec)} \
+%{!mmips-as: %(gas_asm_spec)}"
+
+#else /* not GAS */
+
+#define TARGET_ASM_SPEC "\
+%{!mgas: %(mips_as_asm_spec)} \
+%{mgas: %(gas_asm_spec)}"
+
+#endif /* not GAS */
+
+/* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
+   to the assembler.  It may be overridden by subtargets.  */
+#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
+#define SUBTARGET_ASM_OPTIMIZING_SPEC "\
+%{noasmopt:-O0} \
+%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
+#endif
+
+/* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
+   the assembler.  It may be overridden by subtargets.  */
+#ifndef SUBTARGET_ASM_DEBUGGING_SPEC
+#define SUBTARGET_ASM_DEBUGGING_SPEC "\
+%{g} %{g0} %{g1} %{g2} %{g3} \
+%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
+%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
+%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
+%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
+#endif
+
+/* SUBTARGET_ASM_SPEC is always passed to the assembler.  It may be
+   overridden by subtargets.  */
+
+#ifndef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC ""
+#endif
+
+/* ASM_SPEC is the set of arguments to pass to the assembler.  */
+
+#define ASM_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
+%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
+%(subtarget_asm_optimizing_spec) \
+%(subtarget_asm_debugging_spec) \
+%{membedded-pic} \
+%{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
+%(target_asm_spec) \
+%(subtarget_asm_spec)"
+
+/* Specify to run a post-processor, mips-tfile after the assembler
+   has run to stuff the mips debug information into the object file.
+   This is needed because the $#!%^ MIPS assembler provides no way
+   of specifying such information in the assembly file.  If we are
+   cross compiling, disable mips-tfile unless the user specifies
+   -mmips-tfile.  */
+
+#ifndef ASM_FINAL_SPEC
+#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
+/* GAS */
+#define ASM_FINAL_SPEC "\
+%{mmips-as: %{!mno-mips-tfile: \
+	\n mips-tfile %{v*: -v} \
+		%{K: -I %b.o~} \
+		%{!K: %{save-temps: -I %b.o~}} \
+		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
+		%{.s:%i} %{!.s:%g.s}}}"
+
+#else
+/* not GAS */
+#define ASM_FINAL_SPEC "\
+%{!mgas: %{!mno-mips-tfile: \
+	\n mips-tfile %{v*: -v} \
+		%{K: -I %b.o~} \
+		%{!K: %{save-temps: -I %b.o~}} \
+		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
+		%{.s:%i} %{!.s:%g.s}}}"
+
+#endif
+#endif	/* ASM_FINAL_SPEC */
+
+/* Redefinition of libraries used.  Mips doesn't support normal
+   UNIX style profiling via calling _mcount.  It does offer
+   profiling that samples the PC, so do what we can... */
+
+#ifndef LIB_SPEC
+#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
+#endif
+
+/* Extra switches sometimes passed to the linker.  */
+/* ??? The bestGnum will never be passed to the linker, because the gcc driver
+  will interpret it as a -b option.  */
+
+#ifndef LINK_SPEC
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
+%{bestGnum} %{shared} %{non_shared} \
+%(linker_endian_spec)"
+#endif	/* LINK_SPEC defined */
+
+/* Specs for the compiler proper */
+
+/* SUBTARGET_CC1_SPEC is passed to the compiler proper.  It may be
+   overridden by subtargets.  */
+#ifndef SUBTARGET_CC1_SPEC
+#define SUBTARGET_CC1_SPEC ""
+#endif
+
+/* CC1_SPEC is the set of arguments to pass to the compiler proper.  */
+
+#ifndef CC1_SPEC
+#define CC1_SPEC "\
+%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
+%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
+%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
+%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
+%{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
+%{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
+%{m4650:-mcpu=r4650} \
+%{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
+%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
+%{pic-none:   -mno-half-pic} \
+%{pic-lib:    -mhalf-pic} \
+%{pic-extern: -mhalf-pic} \
+%{pic-calls:  -mhalf-pic} \
+%{save-temps: } \
+%(subtarget_cc1_spec) "
+#endif
+
+/* Preprocessor specs.  */
+
+/* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE.  It may
+   be overridden by subtargets.  */
+
+#ifndef SUBTARGET_CPP_SIZE_SPEC
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+%{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
+#endif
+
+/* SUBTARGET_CPP_SPEC is passed to the preprocessor.  It may be
+   overridden by subtargets.  */
+#ifndef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC ""
+#endif
+
+/* If we're using 64bit longs, then we have to define __LONG_MAX__
+   correctly.  Similarly for 64bit ints and __INT_MAX__.  */
+#ifndef LONG_MAX_SPEC
+#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
+#define LONG_MAX_SPEC "%{!mno-long64:-D__LONG_MAX__=9223372036854775807L}"
+#else
+#define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
+#endif
+#endif
+
+/* CPP_SPEC is the set of arguments to pass to the preprocessor.  */
+
+#ifndef CPP_SPEC
+#define CPP_SPEC "\
+%{.cc:	-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
+%{.cxx:	-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
+%{.C:	-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
+%{.m:	-D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
+%{.S:	-D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
+%{.s:	-D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
+%{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
+%(subtarget_cpp_size_spec) \
+%{mips3:-U__mips -D__mips=3 -D__mips64} \
+%{mips4:-U__mips -D__mips=4 -D__mips64} \
+%{mgp32:-U__mips64} %{mgp64:-D__mips64} \
+%{msingle-float:%{!msoft-float:-D__mips_single_float}} \
+%{m4650:%{!msoft-float:-D__mips_single_float}} \
+%{msoft-float:-D__mips_soft_float} \
+%{mabi=eabi:-D__mips_eabi} \
+%{mips16:%{!mno-mips16:-D__mips16}} \
+%{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
+%{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
+%(long_max_spec) \
+%(subtarget_cpp_spec) "
+#endif
+
+/* This macro defines names of additional specifications to put in the specs
+   that can be used in various specifications like CC1_SPEC.  Its definition
+   is an initializer with a subgrouping for each command option.
+
+   Each subgrouping contains a string constant, that defines the
+   specification name, and a string constant that used by the GNU CC driver
+   program.
+
+   Do not define this macro if it does not need to do anything.  */
+
+#define EXTRA_SPECS							\
+  { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC },				\
+  { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },				\
+  { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC },		\
+  { "long_max_spec", LONG_MAX_SPEC },					\
+  { "mips_as_asm_spec", MIPS_AS_ASM_SPEC },				\
+  { "gas_asm_spec", GAS_ASM_SPEC },					\
+  { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, /* CYGNUS LOCAL gavin */	\
+  { "target_asm_spec", TARGET_ASM_SPEC },				\
+  { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, 	\
+  { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC },	\
+  { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC },	\
+  { "subtarget_asm_spec", SUBTARGET_ASM_SPEC },				\
+  { "linker_endian_spec", LINKER_ENDIAN_SPEC },				\
+  SUBTARGET_EXTRA_SPECS
+
+#ifndef SUBTARGET_EXTRA_SPECS
+#define SUBTARGET_EXTRA_SPECS
+#endif
+
+/* If defined, this macro is an additional prefix to try after
+   `STANDARD_EXEC_PREFIX'.  */
+
+#ifndef MD_EXEC_PREFIX
+#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
+#endif
+
+#ifndef MD_STARTFILE_PREFIX
+#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
+#endif
+
+
+/* Print subsidiary information on the compiler version in use.  */
+
+#define MIPS_VERSION "[AL 1.1, MM 40]"
+
+#ifndef MACHINE_TYPE
+#define MACHINE_TYPE "BSD Mips"
+#endif
+
+#ifndef TARGET_VERSION_INTERNAL
+#define TARGET_VERSION_INTERNAL(STREAM)					\
+  fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
+#endif
+
+#ifndef TARGET_VERSION
+#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
+#endif
+
+
+#define SDB_DEBUGGING_INFO		/* generate info for mips-tfile */
+#define DBX_DEBUGGING_INFO		/* generate stabs (OSF/rose) */
+#define MIPS_DEBUGGING_INFO		/* MIPS specific debugging info */
+
+#ifndef PREFERRED_DEBUGGING_TYPE	/* assume SDB_DEBUGGING_INFO */
+#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
+#endif
+
+/* By default, turn on GDB extensions.  */
+#define DEFAULT_GDB_EXTENSIONS 1
+
+/* If we are passing smuggling stabs through the MIPS ECOFF object
+   format, put a comment in front of the .stab<x> operation so
+   that the MIPS assembler does not choke.  The mips-tfile program
+   will correctly put the stab into the object file.  */
+
+#define ASM_STABS_OP	((TARGET_GAS) ? ".stabs" : " #.stabs")
+#define ASM_STABN_OP	((TARGET_GAS) ? ".stabn" : " #.stabn")
+#define ASM_STABD_OP	((TARGET_GAS) ? ".stabd" : " #.stabd")
+
+/* Local compiler-generated symbols must have a prefix that the assembler
+   understands.   By default, this is $, although some targets (e.g.,
+   NetBSD-ELF) need to override this. */
+
+#ifndef LOCAL_LABEL_PREFIX
+#define LOCAL_LABEL_PREFIX	"$"
+#endif
+
+/* By default on the mips, external symbols do not have an underscore
+   prepended, but some targets (e.g., NetBSD) require this. */
+
+#ifndef USER_LABEL_PREFIX
+#define USER_LABEL_PREFIX	""
+#endif
+
+/* Forward references to tags are allowed.  */
+#define SDB_ALLOW_FORWARD_REFERENCES
+
+/* Unknown tags are also allowed.  */
+#define SDB_ALLOW_UNKNOWN_REFERENCES
+
+/* On Sun 4, this limit is 2048.  We use 1500 to be safe,
+   since the length can run past this up to a continuation point.  */
+#define DBX_CONTIN_LENGTH 1500
+
+/* How to renumber registers for dbx and gdb. */
+#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
+
+/* The mapping from gcc register number to DWARF 2 CFA column number.
+   This mapping does not allow for tracking register 0, since SGI's broken
+   dwarf reader thinks column 0 is used for the frame address, but since
+   register 0 is fixed this is not a problem.  */
+#define DWARF_FRAME_REGNUM(REG)				\
+  (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
+
+/* The DWARF 2 CFA column which tracks the return address.  */
+#define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
+
+/* Before the prologue, RA lives in r31.  */
+#define INCOMING_RETURN_ADDR_RTX  gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
+
+/* Overrides for the COFF debug format.  */
+#define PUT_SDB_SCL(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.scl\t%d;", (a));	\
+} while (0)
+
+#define PUT_SDB_INT_VAL(a)				\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.val\t%d;", (a));	\
+} while (0)
+
+#define PUT_SDB_VAL(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fputs ("\t.val\t", asm_out_text_file);		\
+  output_addr_const (asm_out_text_file, (a));		\
+  fputc (';', asm_out_text_file);			\
+} while (0)
+
+#define PUT_SDB_DEF(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t%s.def\t",		\
+	   (TARGET_GAS) ? "" : "#");			\
+  ASM_OUTPUT_LABELREF (asm_out_text_file, a); 		\
+  fputc (';', asm_out_text_file);			\
+} while (0)
+
+#define PUT_SDB_PLAIN_DEF(a)				\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t%s.def\t.%s;",		\
+	   (TARGET_GAS) ? "" : "#", (a));		\
+} while (0)
+
+#define PUT_SDB_ENDEF					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.endef\n");		\
+} while (0)
+
+#define PUT_SDB_TYPE(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.type\t0x%x;", (a));	\
+} while (0)
+
+#define PUT_SDB_SIZE(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.size\t%d;", (a));	\
+} while (0)
+
+#define PUT_SDB_DIM(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.dim\t%d;", (a));	\
+} while (0)
+
+#ifndef PUT_SDB_START_DIM
+#define PUT_SDB_START_DIM				\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.dim\t");		\
+} while (0)
+#endif
+
+#ifndef PUT_SDB_NEXT_DIM
+#define PUT_SDB_NEXT_DIM(a)				\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "%d,", a);		\
+} while (0)
+#endif
+
+#ifndef PUT_SDB_LAST_DIM
+#define PUT_SDB_LAST_DIM(a)				\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "%d;", a);		\
+} while (0)
+#endif
+
+#define PUT_SDB_TAG(a)					\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file, "\t.tag\t");		\
+  ASM_OUTPUT_LABELREF (asm_out_text_file, a); 		\
+  fputc (';', asm_out_text_file);			\
+} while (0)
+
+/* For block start and end, we create labels, so that
+   later we can figure out where the correct offset is.
+   The normal .ent/.end serve well enough for functions,
+   so those are just commented out.  */
+
+#define PUT_SDB_BLOCK_START(LINE)			\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file,				\
+	   "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n",		\
+	   LOCAL_LABEL_PREFIX,				\
+	   sdb_label_count,				\
+	   (TARGET_GAS) ? "" : "#",			\
+	   LOCAL_LABEL_PREFIX,				\
+	   sdb_label_count,				\
+	   (LINE));					\
+  sdb_label_count++;					\
+} while (0)
+
+#define PUT_SDB_BLOCK_END(LINE)				\
+do {							\
+  extern FILE *asm_out_text_file;			\
+  fprintf (asm_out_text_file,				\
+	   "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n",		\
+	   LOCAL_LABEL_PREFIX,				\
+	   sdb_label_count,				\
+	   (TARGET_GAS) ? "" : "#",			\
+	   LOCAL_LABEL_PREFIX,				\
+	   sdb_label_count,				\
+	   (LINE));					\
+  sdb_label_count++;					\
+} while (0)
+
+#define PUT_SDB_FUNCTION_START(LINE)
+
+#define PUT_SDB_FUNCTION_END(LINE)            \
+do {                                                  \
+  extern FILE *asm_out_text_file;             \
+  ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
+} while (0)
+
+#define PUT_SDB_EPILOGUE_END(NAME)
+
+#define PUT_SDB_SRC_FILE(FILENAME) \
+do {							\
+  extern FILE *asm_out_text_file;			\
+  output_file_directive (asm_out_text_file, (FILENAME)); \
+} while (0)
+
+#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
+  sprintf ((BUFFER), ".%dfake", (NUMBER));
+
+/* Correct the offset of automatic variables and arguments.  Note that
+   the MIPS debug format wants all automatic variables and arguments
+   to be in terms of the virtual frame pointer (stack pointer before
+   any adjustment in the function), while the MIPS 3.0 linker wants
+   the frame pointer to be the stack pointer after the initial
+   adjustment.  */
+
+#define DEBUGGER_AUTO_OFFSET(X)  \
+  mips_debugger_offset (X, (HOST_WIDE_INT) 0)
+#define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
+  mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
+
+/* Tell collect that the object format is ECOFF */
+#ifndef OBJECT_FORMAT_ROSE
+#define OBJECT_FORMAT_COFF	/* Object file looks like COFF */
+#define EXTENDED_COFF		/* ECOFF, not normal coff */
+#endif
+
+#if 0 /* These definitions normally have no effect because
+	 MIPS systems define USE_COLLECT2, so
+	 assemble_constructor does nothing anyway.  */
+
+/* Don't use the default definitions, because we don't have gld.
+   Also, we don't want stabs when generating ECOFF output.
+   Instead we depend on collect to handle these.  */
+
+#define ASM_OUTPUT_CONSTRUCTOR(file, name)
+#define ASM_OUTPUT_DESTRUCTOR(file, name)
+
+#endif /* 0 */
+
+/* Target machine storage layout */
+
+/* Define in order to support both big and little endian float formats
+   in the same gcc binary.  */
+#define REAL_ARITHMETIC
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.
+*/
+#define BITS_BIG_ENDIAN 0
+
+/* Define this if most significant byte of a word is the lowest numbered. */
+#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
+
+/* Define this if most significant word of a multiword number is the lowest. */
+#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
+
+/* Define this to set the endianness to use in libgcc2.c, which can
+   not depend on target_flags.  */
+#if !defined(MIPSEL) && !defined(__MIPSEL__)
+#define LIBGCC2_WORDS_BIG_ENDIAN 1
+#else
+#define LIBGCC2_WORDS_BIG_ENDIAN 0
+#endif
+
+/* Number of bits in an addressable storage unit */
+#define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+   Note that this is not necessarily the width of data type `int';
+   if using 16-bit ints on a 68000, this would still be 32.
+   But on a machine with 16-bit registers, this would be 16.  */
+#define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
+#define MAX_BITS_PER_WORD 64
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
+#define MIN_UNITS_PER_WORD 4
+
+/* For MIPS, width of a floating point register.  */
+#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
+
+/* A C expression for the size in bits of the type `int' on the
+   target machine.  If you don't define this, the default is one
+   word.  */
+#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
+#define MAX_INT_TYPE_SIZE 64
+
+/* Tell the preprocessor the maximum size of wchar_t.  */
+#ifndef MAX_WCHAR_TYPE_SIZE
+#ifndef WCHAR_TYPE_SIZE
+#define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
+#endif
+#endif
+
+/* A C expression for the size in bits of the type `short' on the
+   target machine.  If you don't define this, the default is half a
+   word.  (If this would be less than one storage unit, it is
+   rounded up to one unit.)  */
+#define SHORT_TYPE_SIZE 16
+
+/* A C expression for the size in bits of the type `long' on the
+   target machine.  If you don't define this, the default is one
+   word.  */
+#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
+#define MAX_LONG_TYPE_SIZE 64
+
+/* A C expression for the size in bits of the type `long long' on the
+   target machine.  If you don't define this, the default is two
+   words.  */
+#define LONG_LONG_TYPE_SIZE 64
+
+/* A C expression for the size in bits of the type `char' on the
+   target machine.  If you don't define this, the default is one
+   quarter of a word.  (If this would be less than one storage unit,
+   it is rounded up to one unit.)  */
+#define CHAR_TYPE_SIZE BITS_PER_UNIT
+
+/* A C expression for the size in bits of the type `float' on the
+   target machine.  If you don't define this, the default is one
+   word.  */
+#define FLOAT_TYPE_SIZE 32
+
+/* A C expression for the size in bits of the type `double' on the
+   target machine.  If you don't define this, the default is two
+   words.  */
+#define DOUBLE_TYPE_SIZE 64
+
+/* A C expression for the size in bits of the type `long double' on
+   the target machine.  If you don't define this, the default is two
+   words.  */
+#define LONG_DOUBLE_TYPE_SIZE 64
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#ifndef POINTER_SIZE
+#define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
+#endif
+
+/* Allocation boundary (in *bits*) for storing pointers in memory.  */
+#define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
+
+/* CYGNUS LOCAL law */
+/* Allocation boundary (in *bits*) for the code of a function.  */
+#define FUNCTION_BOUNDARY (1 << (mips_align_funcs + 3))
+#define FUNCTION_BOUNDARY_MAX_SKIP (mips_max_skip_funcs)
+/* END CYGNUS LOCAL */
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY 32
+
+/* Every structure's size must be a multiple of this.  */
+/* 8 is observed right on a DECstation and on riscos 4.02.  */
+#define STRUCTURE_SIZE_BOUNDARY 8
+
+/* There is no point aligning anything to a rounder boundary than this.  */
+#define BIGGEST_ALIGNMENT 64
+
+/* Set this nonzero if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT 1
+
+/* CYGNUS LOCAL law */
+/* Align loop starts for optimal branching.  */
+#define LOOP_ALIGN(LABEL) (mips_align_loops)
+#define LOOP_ALIGN_MAX_SKIP (mips_max_skip_loops)
+
+/* This is how to align an instruction for optimal branching. */
+#define LABEL_ALIGN_AFTER_BARRIER(LABEL) (mips_align_jumps)
+#define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP (mips_max_skip_jumps)
+
+#ifndef DEFAULT_LOOP_ALIGN
+#define DEFAULT_LOOP_ALIGN 2
+#endif
+
+#ifndef DEFAULT_JUMP_ALIGN
+#define DEFAULT_JUMP_ALIGN 2
+#endif
+
+#ifndef DEFAULT_FUNCTION_ALIGN
+#define DEFAULT_FUNCTION_ALIGN 2
+#endif
+
+#ifndef DEFAULT_LOOP_MAX_SKIP
+#define DEFAULT_LOOP_MAX_SKIP 0
+#endif
+
+#ifndef DEFAULT_JUMP_MAX_SKIP
+#define DEFAULT_JUMP_MAX_SKIP 0
+#endif
+
+#ifndef DEFAULT_FUNCTION_MAX_SKIP
+#define DEFAULT_FUNCTION_MAX_SKIP 0
+#endif
+
+extern char *mips_align_loops_string;
+extern char *mips_align_jumps_string;
+extern char *mips_align_funcs_string;
+extern int mips_align_loops;
+extern int mips_align_jumps;
+extern int mips_align_funcs;
+extern char *mips_max_skip_loops_string;
+extern char *mips_max_skip_jumps_string;
+extern char *mips_max_skip_funcs_string;
+extern int mips_max_skip_loops;
+extern int mips_max_skip_jumps;
+extern int mips_max_skip_funcs;
+/* END CYGNUS LOCAL */
+
+/* Define this if you wish to imitate the way many other C compilers
+   handle alignment of bitfields and the structures that contain
+   them.
+
+   The behavior is that the type written for a bitfield (`int',
+   `short', or other integer type) imposes an alignment for the
+   entire structure, as if the structure really did contain an
+   ordinary field of that type.  In addition, the bitfield is placed
+   within the structure so that it would fit within such a field,
+   not crossing a boundary for it.
+
+   Thus, on most machines, a bitfield whose type is written as `int'
+   would not cross a four-byte boundary, and would force four-byte
+   alignment for the whole structure.  (The alignment used may not
+   be four bytes; it is controlled by the other alignment
+   parameters.)
+
+   If the macro is defined, its definition should be a C expression;
+   a nonzero value for the expression enables this behavior.  */
+
+#define PCC_BITFIELD_TYPE_MATTERS 1
+
+/* If defined, a C expression to compute the alignment given to a
+   constant that is being placed in memory.  CONSTANT is the constant
+   and ALIGN is the alignment that the object would ordinarily have.
+   The value of this macro is used instead of that alignment to align
+   the object.
+
+   If this macro is not defined, then ALIGN is used.
+
+   The typical use of this macro is to increase alignment for string
+   constants to be word aligned so that `strcpy' calls that copy
+   constants can be done inline.  */
+
+#define CONSTANT_ALIGNMENT(EXP, ALIGN)					\
+  ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)	\
+   && (ALIGN) < BITS_PER_WORD						\
+	? BITS_PER_WORD							\
+	: (ALIGN))
+
+/* If defined, a C expression to compute the alignment for a static
+   variable.  TYPE is the data type, and ALIGN is the alignment that
+   the object would ordinarily have.  The value of this macro is used
+   instead of that alignment to align the object.
+
+   If this macro is not defined, then ALIGN is used.
+
+   One use of this macro is to increase alignment of medium-size
+   data to make it all fit in fewer cache lines.  Another is to
+   cause character arrays to be word-aligned so that `strcpy' calls
+   that copy constants to character arrays can be done inline.  */
+
+#undef DATA_ALIGNMENT
+#define DATA_ALIGNMENT(TYPE, ALIGN)					\
+  ((((ALIGN) < BITS_PER_WORD)						\
+    && (TREE_CODE (TYPE) == ARRAY_TYPE					\
+	|| TREE_CODE (TYPE) == UNION_TYPE				\
+	|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
+
+/* Define this macro if an argument declared as `char' or `short' in a
+   prototype should actually be passed as an `int'.  In addition to
+   avoiding errors in certain cases of mismatch, it also makes for
+   better code on certain machines. */
+
+#define PROMOTE_PROTOTYPES
+
+/* Define if operations between registers always perform the operation
+   on the full register even if a narrower mode is specified.  */
+#define WORD_REGISTER_OPERATIONS
+
+/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
+   will either zero-extend or sign-extend.  The value of this macro should
+   be the code that says which one of the two operations is implicitly
+   done, NIL if none. 
+
+   When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
+   moves.  All other referces are zero extended.  */
+#define LOAD_EXTEND_OP(MODE) \
+  (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
+   ? SIGN_EXTEND : ZERO_EXTEND)
+
+/* Define this macro if it is advisable to hold scalars in registers
+   in a wider mode than that declared by the program.  In such cases, 
+   the value is constrained to be within the bounds of the declared
+   type, but kept valid in the wider mode.  The signedness of the
+   extension may differ from that of the type.
+
+   We promote any value smaller than SImode up to SImode.  We don't
+   want to promote to DImode when in 64 bit mode, because that would
+   prevent us from using the faster SImode multiply and divide
+   instructions.  */
+
+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
+  if (GET_MODE_CLASS (MODE) == MODE_INT		\
+      && GET_MODE_SIZE (MODE) < 4)		\
+    (MODE) = SImode;
+
+/* Define this if function arguments should also be promoted using the above
+   procedure.  */
+
+#define PROMOTE_FUNCTION_ARGS
+
+/* Likewise, if the function return value is promoted.  */
+
+#define PROMOTE_FUNCTION_RETURN
+
+/* Standard register usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.
+
+   On the Mips, we have 32 integer registers, 32 floating point
+   registers, 8 condition code registers, and the special registers
+   hi, lo, hilo, and rap.  The 8 condition code registers are only
+   used if mips_isa >= 4.  The hilo register is only used in 64 bit
+   mode.  It represents a 64 bit value stored as two 32 bit values in
+   the hi and lo registers; this is the result of the mult
+   instruction.  rap is a pointer to the stack where the return
+   address reg ($31) was stored.  This is needed for C++ exception
+   handling.  */
+
+#define FIRST_PSEUDO_REGISTER 76
+
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.
+
+   On the MIPS, see conventions, page D-2  */
+
+#define FIXED_REGISTERS							\
+{									\
+  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1,			\
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1					\
+}
+
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.  */
+
+#define CALL_USED_REGISTERS						\
+{									\
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
+  0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1,			\
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,			\
+  1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,			\
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1					\
+}
+
+
+/* Internal macros to classify a register number as to whether it's a
+   general purpose register, a floating point register, a
+   multiply/divide register, or a status register.  */
+
+#define GP_REG_FIRST 0
+#define GP_REG_LAST  31
+#define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
+#define GP_DBX_FIRST 0
+
+#define FP_REG_FIRST 32
+#define FP_REG_LAST  63
+#define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
+#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
+
+#define MD_REG_FIRST 64
+#define MD_REG_LAST  66
+#define MD_REG_NUM   (MD_REG_LAST - MD_REG_FIRST + 1)
+
+
+#define ST_REG_FIRST 67
+#define ST_REG_LAST  74
+#define ST_REG_NUM   (ST_REG_LAST - ST_REG_FIRST + 1)
+
+#define RAP_REG_NUM   75
+
+#define AT_REGNUM	(GP_REG_FIRST + 1)
+#define HI_REGNUM	(MD_REG_FIRST + 0)
+#define LO_REGNUM	(MD_REG_FIRST + 1)
+#define HILO_REGNUM	(MD_REG_FIRST + 2)
+
+/* FPSW_REGNUM is the single condition code used if mips_isa < 4.  If
+   mips_isa >= 4, it should not be used, and an arbitrary ST_REG
+   should be used instead.  */
+#define FPSW_REGNUM	ST_REG_FIRST
+
+#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
+#define M16_REG_P(REGNO) \
+  (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
+#define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
+#define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
+#define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.
+
+   On the MIPS, all general registers are one word long.  Except on
+   the R4000 with the FR bit set, the floating point uses register
+   pairs, with the second register not being allocable.  */
+
+#define HARD_REGNO_NREGS(REGNO, MODE)					\
+  (! FP_REG_P (REGNO)							\
+	? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
+	: ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
+
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode
+   MODE.  In 32 bit mode, require that DImode and DFmode be in even
+   registers.  For DImode, this makes some of the insns easier to
+   write, since you don't have to worry about a DImode value in
+   registers 3 & 4, producing a result in 4 & 5.
+
+   To make the code simpler HARD_REGNO_MODE_OK now just references an
+   array built in override_options.  Because machmodes.h is not yet
+   included before this file is processed, the MODE bound can't be
+   expressed here.  */
+
+extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
+
+#define HARD_REGNO_MODE_OK(REGNO, MODE)					\
+  mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
+
+/* Value is 1 if it is a good idea to tie two pseudo registers
+   when one has mode MODE1 and one has mode MODE2.
+   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
+   for any hard reg, then this must be 0 for correct output.  */
+#define MODES_TIEABLE_P(MODE1, MODE2)					\
+  ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||				\
+    GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)			\
+   == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||				\
+       GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
+
+/* MIPS pc is not overloaded on a register.	*/
+/* #define PC_REGNUM xx				*/
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
+
+/* Offset from the stack pointer to the first available location.  Use
+   the default value zero.  */
+/* #define STACK_POINTER_OFFSET 0 */
+
+/* Base register for access to local variables of the function.  We
+   pretend that the frame pointer is $1, and then eliminate it to
+   HARD_FRAME_POINTER_REGNUM.  We can get away with this because $1 is
+   a fixed register, and will not be used for anything else.  */
+#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
+
+/* $30 is not available on the mips16, so we use $17 as the frame
+   pointer.  */
+#define HARD_FRAME_POINTER_REGNUM \
+  (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
+
+/* Value should be nonzero if functions must have frame pointers.
+   Zero means the frame pointer need not be set up (and parms
+   may be accessed via the stack pointer) in functions that seem suitable.
+   This is computed in `reload', in reload1.c.  */
+#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
+
+/* Base register for access to arguments of the function.  */
+#define ARG_POINTER_REGNUM GP_REG_FIRST
+
+/* Fake register that holds the address on the stack of the
+   current function's return address.  */
+#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
+
+/* Register in which static-chain is passed to a function.  */
+#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
+
+/* If the structure value address is passed in a register, then
+   `STRUCT_VALUE_REGNUM' should be the number of that register.  */
+/* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
+
+/* If the structure value address is not passed in a register, define
+   `STRUCT_VALUE' as an expression returning an RTX for the place
+   where the address is passed.  If it returns 0, the address is
+   passed as an "invisible" first argument.  */
+#define STRUCT_VALUE 0
+
+/* Mips registers used in prologue/epilogue code when the stack frame
+   is larger than 32K bytes.  These registers must come from the
+   scratch register set, and not used for passing and returning
+   arguments and any other information used in the calling sequence
+   (such as pic).  Must start at 12, since t0/t3 are parameter passing
+   registers in the 64 bit ABI.  */
+
+#define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
+#define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
+
+/* Define this macro if it is as good or better to call a constant
+   function address than to call an address kept in a register.  */
+#define NO_FUNCTION_CSE 1
+
+/* Define this macro if it is as good or better for a function to
+   call itself with an explicit address than to call an address
+   kept in a register.  */
+#define NO_RECURSIVE_FUNCTION_CSE 1
+
+/* The register number of the register used to address a table of
+   static data addresses in memory.  In some cases this register is
+   defined by a processor's "application binary interface" (ABI). 
+   When this macro is defined, RTL is generated for this register
+   once, as with the stack pointer and frame pointer registers.  If
+   this macro is not defined, it is up to the machine-dependent
+   files to allocate such a register (if necessary).  */
+#define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
+
+#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
+
+/* Initialize embedded_pic_fnaddr_rtx before RTL generation for
+   each function.  We used to do this in FINALIZE_PIC, but FINALIZE_PIC
+   isn't always called for static inline functions.  */
+#define INIT_EXPANDERS			\
+do {					\
+  embedded_pic_fnaddr_rtx = NULL;	\
+  mips16_gp_pseudo_rtx = NULL;		\
+} while (0)
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.  */
+
+enum reg_class
+{
+  NO_REGS,			/* no registers in set */
+  M16_NA_REGS,			/* mips16 regs not used to pass args */
+  M16_REGS,			/* mips16 directly accessible registers */
+  T_REG,			/* mips16 T register ($24) */
+  M16_T_REGS,			/* mips16 registers plus T register */
+  GR_REGS,			/* integer registers */
+  FP_REGS,			/* floating point registers */
+  HI_REG,			/* hi register */
+  LO_REG,			/* lo register */
+  HILO_REG,			/* hilo register pair for 64 bit mode mult */
+  MD_REGS,			/* multiply/divide registers (hi/lo) */
+  HI_AND_GR_REGS,		/* union classes */
+  LO_AND_GR_REGS,
+  HILO_AND_GR_REGS,
+  ST_REGS,			/* status registers (fp status) */
+  ALL_REGS,			/* all registers */
+  LIM_REG_CLASSES		/* max value + 1 */
+};
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+#define GENERAL_REGS GR_REGS
+
+/* An initializer containing the names of the register classes as C
+   string constants.  These names are used in writing some of the
+   debugging dumps.  */
+
+#define REG_CLASS_NAMES							\
+{									\
+  "NO_REGS",								\
+  "M16_NA_REGS",							\
+  "M16_REGS",								\
+  "T_REG",								\
+  "M16_T_REGS",								\
+  "GR_REGS",								\
+  "FP_REGS",								\
+  "HI_REG",								\
+  "LO_REG",								\
+  "HILO_REG",								\
+  "MD_REGS",								\
+  "HI_AND_GR_REGS",							\
+  "LO_AND_GR_REGS",							\
+  "HILO_AND_GR_REGS",							\
+  "ST_REGS",								\
+  "ALL_REGS"								\
+}
+
+/* An initializer containing the contents of the register classes,
+   as integers which are bit masks.  The Nth integer specifies the
+   contents of class N.  The way the integer MASK is interpreted is
+   that register R is in the class if `MASK & (1 << R)' is 1.
+
+   When the machine has more than 32 registers, an integer does not
+   suffice.  Then the integers are replaced by sub-initializers,
+   braced groupings containing several integers.  Each
+   sub-initializer must be suitable as an initializer for the type
+   `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
+
+#define REG_CLASS_CONTENTS						\
+{									\
+  { 0x00000000, 0x00000000, 0x00000000 },	/* no registers */	\
+  { 0x0003000c, 0x00000000, 0x00000000 },	/* mips16 nonarg regs */\
+  { 0x000300fc, 0x00000000, 0x00000000 },	/* mips16 registers */	\
+  { 0x01000000, 0x00000000, 0x00000000 },	/* mips16 T register */	\
+  { 0x010300fc, 0x00000000, 0x00000000 },	/* mips16 and T regs */ \
+  { 0xffffffff, 0x00000000, 0x00000000 },	/* integer registers */	\
+  { 0x00000000, 0xffffffff, 0x00000000 },	/* floating registers*/	\
+  { 0x00000000, 0x00000000, 0x00000001 },	/* hi register */	\
+  { 0x00000000, 0x00000000, 0x00000002 },	/* lo register */	\
+  { 0x00000000, 0x00000000, 0x00000004 },	/* hilo register */	\
+  { 0x00000000, 0x00000000, 0x00000003 },	/* mul/div registers */	\
+  { 0xffffffff, 0x00000000, 0x00000001 },	/* union classes */     \
+  { 0xffffffff, 0x00000000, 0x00000002 },				\
+  { 0xffffffff, 0x00000000, 0x00000004 },				\
+  { 0x00000000, 0x00000000, 0x000007f8 },	/* status registers */	\
+  { 0xffffffff, 0xffffffff, 0x000078ff }	/* all registers */	\
+}
+
+
+/* A C expression whose value is a register class containing hard
+   register REGNO.  In general there is more that one such class;
+   choose a class which is "minimal", meaning that no smaller class
+   also contains the register.  */
+
+extern enum reg_class mips_regno_to_class[];
+
+#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
+
+/* A macro whose definition is the name of the class to which a
+   valid base register must belong.  A base register is one used in
+   an address which is the register value plus a displacement.  */
+
+#define BASE_REG_CLASS  (TARGET_MIPS16 ? M16_REGS : GR_REGS)
+
+/* A macro whose definition is the name of the class to which a
+   valid index register must belong.  An index register is one used
+   in an address where its value is either multiplied by a scale
+   factor or added to another register (as well as added to a
+   displacement).  */
+
+#define INDEX_REG_CLASS NO_REGS
+
+/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
+   registers explicitly used in the rtl to be used as spill registers
+   but prevents the compiler from extending the lifetime of these
+   registers. */
+
+#define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
+
+/* This macro is used later on in the file.  */
+#define GR_REG_CLASS_P(CLASS)						\
+  ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG	\
+   || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
+
+/* REG_ALLOC_ORDER is to order in which to allocate registers.  This
+   is the default value (allocate the registers in numeric order).  We
+   define it just so that we can override it for the mips16 target in
+   ORDER_REGS_FOR_LOCAL_ALLOC.  */
+
+#define REG_ALLOC_ORDER							\
+{  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,	\
+  16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,	\
+  32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,	\
+  48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,	\
+  64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75			\
+}
+
+/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
+   to be rearranged based on a particular function.  On the mips16, we
+   want to allocate $24 (T_REG) before other registers for
+   instructions for which it is possible.  */
+
+#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
+
+/* REGISTER AND CONSTANT CLASSES */
+
+/* Get reg_class from a letter such as appears in the machine
+   description.
+
+   DEFINED REGISTER CLASSES:
+
+   'd'  General (aka integer) registers
+        Normally this is GR_REGS, but in mips16 mode this is M16_REGS
+   'y'  General registers (in both mips16 and non mips16 mode)
+   'e'	mips16 non argument registers (M16_NA_REGS)
+   't'  mips16 temporary register ($24)
+   'f'	Floating point registers
+   'h'	Hi register
+   'l'	Lo register
+   'x'	Multiply/divide registers
+   'a'	HILO_REG
+   'z'	FP Status register
+   'b'	All registers */
+
+extern enum reg_class mips_char_to_class[];
+
+#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
+
+/* The letters I, J, K, L, M, N, O, and P in a register constraint
+   string can be used to stand for particular ranges of immediate
+   operands.  This macro defines what the ranges are.  C is the
+   letter, and VALUE is a constant value.  Return 1 if VALUE is
+   in the range specified by C.  */
+
+/* For MIPS:
+
+   `I'	is used for the range of constants an arithmetic insn can
+	actually contain (16 bits signed integers).
+
+   `J'	is used for the range which is just zero (ie, $r0).
+
+   `K'	is used for the range of constants a logical insn can actually
+	contain (16 bit zero-extended integers).
+
+   `L'	is used for the range of constants that be loaded with lui
+	(ie, the bottom 16 bits are zero).
+
+   `M'	is used for the range of constants that take two words to load
+	(ie, not matched by `I', `K', and `L').
+
+   `N'	is used for negative 16 bit constants other than -65536.
+
+   `O'	is a 15 bit signed integer.
+
+   `P'	is used for positive 16 bit constants.  */
+
+#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
+#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
+
+#define CONST_OK_FOR_LETTER_P(VALUE, C)					\
+  ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000)	\
+   : (C) == 'J' ? ((VALUE) == 0)					\
+   : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000)		\
+   : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0				\
+		   && (((VALUE) & ~2147483647) == 0			\
+		       || ((VALUE) & ~2147483647) == ~2147483647))	\
+   : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0)			\
+		   && (((VALUE) & ~0x0000ffff) != ~0x0000ffff)		\
+		   && (((VALUE) & 0x0000ffff) != 0			\
+		       || (((VALUE) & ~2147483647) != 0			\
+			   && ((VALUE) & ~2147483647) != ~2147483647)))	\
+   : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
+   : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
+   : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0))	\
+   : 0)
+
+/* Similar, but for floating constants, and defining letters G and H.
+   Here VALUE is the CONST_DOUBLE rtx itself.  */
+
+/* For Mips
+
+  'G'	: Floating point 0 */
+
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
+  ((C) == 'G'								\
+   && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
+
+/* Letters in the range `Q' through `U' may be defined in a
+   machine-dependent fashion to stand for arbitrary operand types. 
+   The machine description macro `EXTRA_CONSTRAINT' is passed the
+   operand as its first argument and the constraint letter as its
+   second operand.
+
+   `Q'	is for mips16 GP relative constants
+   `R'	is for memory references which take 1 word for the instruction.
+   `S'	is for references to extern items which are PIC for OSF/rose.
+   `T'	is for memory addresses that can be used to load two words.  */
+
+#define EXTRA_CONSTRAINT(OP,CODE)					\
+  (((CODE) == 'T')	  ? double_memory_operand (OP, GET_MODE (OP))	\
+   : ((CODE) == 'Q')	  ? (GET_CODE (OP) == CONST			\
+			     && mips16_gp_offset_p (OP))		\
+   : (GET_CODE (OP) != MEM) ? FALSE					\
+   : ((CODE) == 'R')	  ? simple_memory_operand (OP, GET_MODE (OP))	\
+   : ((CODE) == 'S')	  ? (HALF_PIC_P () && CONSTANT_P (OP)		\
+			     && HALF_PIC_ADDRESS_P (OP))		\
+   : FALSE)
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class.  */
+
+#define PREFERRED_RELOAD_CLASS(X,CLASS)					\
+  ((CLASS) != ALL_REGS							\
+   ? (! TARGET_MIPS16							\
+      ? (CLASS)								\
+      : ((CLASS) != GR_REGS						\
+	 ? (CLASS)							\
+	 : M16_REGS))							\
+   : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT			\
+       || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)		\
+      ? (TARGET_SOFT_FLOAT						\
+	 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS)				\
+	 : FP_REGS)							\
+      : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT			\
+	  || GET_MODE (X) == VOIDmode)					\
+	 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS)				\
+	 : (CLASS))))
+
+/* Certain machines have the property that some registers cannot be
+   copied to some other registers without using memory.  Define this
+   macro on those machines to be a C expression that is non-zero if
+   objects of mode MODE in registers of CLASS1 can only be copied to
+   registers of class CLASS2 by storing a register of CLASS1 into
+   memory and loading that memory location into a register of CLASS2.
+
+   Do not define this macro if its value would always be zero.  */
+
+#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)			\
+  ((!TARGET_DEBUG_H_MODE						\
+    && GET_MODE_CLASS (MODE) == MODE_INT				\
+    && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2))			\
+	|| (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS)))		\
+   || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode		\
+       && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS)		\
+	   || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
+
+/* The HI and LO registers can only be reloaded via the general
+   registers.  Condition code registers can only be loaded to the
+   general registers, and from the floating point registers.  */
+
+#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)			\
+  mips_secondary_reload_class (CLASS, MODE, X, 1)
+#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)			\
+  mips_secondary_reload_class (CLASS, MODE, X, 0)
+
+/* Not declared above, with the other functions, because enum
+   reg_class is not declared yet.  */
+extern enum reg_class	mips_secondary_reload_class ();
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.  */
+
+#define CLASS_UNITS(mode, size)						\
+  ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
+
+#define CLASS_MAX_NREGS(CLASS, MODE)					\
+  ((CLASS) == FP_REGS							\
+   ? (TARGET_FLOAT64							\
+      ? CLASS_UNITS (MODE, 8)						\
+      : 2 * CLASS_UNITS (MODE, 8))					\
+   : CLASS_UNITS (MODE, UNITS_PER_WORD))
+
+/* If defined, gives a class of registers that cannot be used as the
+   operand of a SUBREG that changes the size of the object.  */
+
+#define CLASS_CANNOT_CHANGE_SIZE                                      \
+  (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
+
+/* If defined, this is a C expression whose value should be
+   nonzero if the insn INSN has the effect of mysteriously
+   clobbering the contents of hard register number REGNO.  By
+   "mysterious" we mean that the insn's RTL expression doesn't
+   describe such an effect.
+
+   If this macro is not defined, it means that no insn clobbers
+   registers mysteriously.  This is the usual situation; all else
+   being equal, it is best for the RTL expression to show all the
+   activity.  */
+
+/* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
+
+
+/* Stack layout; function entry, exit and calling.  */
+
+/* Define this if pushing a word on the stack
+   makes the stack pointer a smaller address.  */
+#define STACK_GROWS_DOWNWARD
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset in the frame.  */
+/* #define FRAME_GROWS_DOWNWARD */
+
+/* Offset within stack frame to start allocating local variables at.
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
+   of the first local allocated.  */
+#define STARTING_FRAME_OFFSET						\
+  (current_function_outgoing_args_size					\
+   + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
+
+/* Offset from the stack pointer register to an item dynamically
+   allocated on the stack, e.g., by `alloca'.
+
+   The default value for this macro is `STACK_POINTER_OFFSET' plus the
+   length of the outgoing arguments.  The default is correct for most
+   machines.  See `function.c' for details.
+
+   The MIPS ABI states that functions which dynamically allocate the
+   stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
+   we are trying to create a second frame pointer to the function, so
+   allocate some stack space to make it happy.
+
+   However, the linker currently complains about linking any code that
+   dynamically allocates stack space, and there seems to be a bug in
+   STACK_DYNAMIC_OFFSET, so don't define this right now.  */
+
+#if 0
+#define STACK_DYNAMIC_OFFSET(FUNDECL)					\
+  ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
+	? 4*UNITS_PER_WORD						\
+	: current_function_outgoing_args_size)
+#endif
+
+/* The return address for the current frame is in r31 is this is a leaf
+   function.  Otherwise, it is on the stack.  It is at a variable offset
+   from sp/fp/ap, so we define a fake hard register rap which is a
+   poiner to the return address on the stack.  This always gets eliminated
+   during reload to be either the frame pointer or the stack pointer plus
+   an offset.  */
+
+/* ??? This definition fails for leaf functions.  There is currently no
+   general solution for this problem.  */
+
+/* ??? There appears to be no way to get the return address of any previous
+   frame except by disassembling instructions in the prologue/epilogue.
+   So currently we support only the current frame.  */
+
+#define RETURN_ADDR_RTX(count, frame)			\
+  ((count == 0)						\
+   ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
+   : (rtx) 0)
+
+/* Structure to be filled in by compute_frame_size with register
+   save masks, and offsets for the current function.  */
+
+struct mips_frame_info
+{
+  long total_size;		/* # bytes that the entire frame takes up */
+  long var_size;		/* # bytes that variables take up */
+  long args_size;		/* # bytes that outgoing arguments take up */
+  long extra_size;		/* # bytes of extra gunk */
+  int  gp_reg_size;		/* # bytes needed to store gp regs */
+  int  fp_reg_size;		/* # bytes needed to store fp regs */
+  long mask;			/* mask of saved gp registers */
+  long fmask;			/* mask of saved fp registers */
+  long gp_save_offset;		/* offset from vfp to store gp registers */
+  long fp_save_offset;		/* offset from vfp to store fp registers */
+  long gp_sp_offset;		/* offset from new sp to store gp registers */
+  long fp_sp_offset;		/* offset from new sp to store fp registers */
+  int  initialized;		/* != 0 if frame size already calculated */
+  int  num_gp;			/* number of gp registers saved */
+  int  num_fp;			/* number of fp registers saved */
+  long insns_len;		/* length of insns; mips16 only */
+};
+
+extern struct mips_frame_info current_frame_info;
+
+/* If defined, this macro specifies a table of register pairs used to
+   eliminate unneeded registers that point into the stack frame.  If
+   it is not defined, the only elimination attempted by the compiler
+   is to replace references to the frame pointer with references to
+   the stack pointer.
+
+   The definition of this macro is a list of structure
+   initializations, each of which specifies an original and
+   replacement register.
+
+   On some machines, the position of the argument pointer is not
+   known until the compilation is completed.  In such a case, a
+   separate hard register must be used for the argument pointer. 
+   This register can be eliminated by replacing it with either the
+   frame pointer or the argument pointer, depending on whether or not
+   the frame pointer has been eliminated.
+
+   In this case, you might specify:
+        #define ELIMINABLE_REGS  \
+        {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+         {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
+         {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
+
+   Note that the elimination of the argument pointer with the stack
+   pointer is specified first since that is the preferred elimination.
+
+   The eliminations to $17 are only used on the mips16.  See the
+   definition of HARD_FRAME_POINTER_REGNUM.  */
+
+#define ELIMINABLE_REGS							\
+{{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},				\
+ { ARG_POINTER_REGNUM,   GP_REG_FIRST + 30},				\
+ { ARG_POINTER_REGNUM,   GP_REG_FIRST + 17},				\
+ { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},		\
+ { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30},			\
+ { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17},			\
+ { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},			\
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},				\
+ { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30},				\
+ { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
+
+/* A C expression that returns non-zero if the compiler is allowed to
+   try to replace register number FROM-REG with register number
+   TO-REG.  This macro need only be defined if `ELIMINABLE_REGS' is
+   defined, and will usually be the constant 1, since most of the
+   cases preventing register elimination are things that the compiler
+   already knows about.
+
+   When not in mips16 and mips64, we can always eliminate to the
+   frame pointer.  We can eliminate to the stack pointer unless
+   a frame pointer is needed.  In mips16 mode, we need a frame
+   pointer for a large frame; otherwise, reload may be unable
+   to compute the address of a local variable, since there is
+   no way to add a large constant to the stack pointer
+   without using a temporary register.
+
+   In mips16, for some instructions (eg lwu), we can't eliminate the
+   frame pointer for the stack pointer.  These instructions are
+   only generated in TARGET_64BIT mode.
+   */
+
+#define CAN_ELIMINATE(FROM, TO)						\
+  (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p ()	\
+   || (TO == GP_REG_FIRST + 31 && leaf_function_p)))   			\
+  || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM				\
+   && ((TO) == HARD_FRAME_POINTER_REGNUM 				\
+   || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed		\
+       && ! (TARGET_MIPS16 && TARGET_64BIT)                             \
+       && (! TARGET_MIPS16						\
+	   || compute_frame_size (get_frame_size ()) < 32768)))))
+
+/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It
+   specifies the initial difference between the specified pair of
+   registers.  This macro must be defined if `ELIMINABLE_REGS' is
+   defined.  */
+
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			 \
+{  compute_frame_size (get_frame_size ());				 \
+  if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM			 \
+      && (TO) == HARD_FRAME_POINTER_REGNUM)				 \
+    (OFFSET) = - current_function_outgoing_args_size;			 \
+  else if ((FROM) == FRAME_POINTER_REGNUM)				 \
+    (OFFSET) = 0;							 \
+  else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM		 \
+	   && (TO) == HARD_FRAME_POINTER_REGNUM)			 \
+    (OFFSET) = (current_frame_info.total_size				 \
+		- current_function_outgoing_args_size			 \
+		- ((mips_abi != ABI_32 					 \
+		    && mips_abi != ABI_O64				 \
+		    && mips_abi != ABI_EABI)				 \
+		   ? current_function_pretend_args_size			 \
+		   : 0));						 \
+  else if ((FROM) == ARG_POINTER_REGNUM)				 \
+    (OFFSET) = (current_frame_info.total_size				 \
+		- ((mips_abi != ABI_32 					 \
+		    && mips_abi != ABI_O64				 \
+		    && mips_abi != ABI_EABI)				 \
+		   ? current_function_pretend_args_size			 \
+		   : 0));						 \
+  /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits,	 \
+     so we must add 4 bytes to the offset to get the right value.  */	 \
+  else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM)			 \
+  {									 \
+   if (leaf_function_p ()) 						 \
+      (OFFSET) = 0;				 			 \
+   else (OFFSET) = current_frame_info.gp_sp_offset			 \
+	       + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT))	 \
+		  * (BYTES_BIG_ENDIAN != 0));				 \
+  }									 \
+}
+
+/* If we generate an insn to push BYTES bytes,
+   this says how many the stack pointer really advances by.
+   On the vax, sp@- in a byte insn really pushes a word.  */
+
+/* #define PUSH_ROUNDING(BYTES) 0 */
+
+/* If defined, the maximum amount of space required for outgoing
+   arguments will be computed and placed into the variable
+   `current_function_outgoing_args_size'.  No space will be pushed
+   onto the stack for each call; instead, the function prologue
+   should increase the stack frame size by this amount.
+
+   It is not proper to define both `PUSH_ROUNDING' and
+   `ACCUMULATE_OUTGOING_ARGS'.  */
+#define ACCUMULATE_OUTGOING_ARGS
+
+/* Offset from the argument pointer register to the first argument's
+   address.  On some machines it may depend on the data type of the
+   function.
+
+   If `ARGS_GROW_DOWNWARD', this is the offset to the location above
+   the first argument's address.
+
+   On the MIPS, we must skip the first argument position if we are
+   returning a structure or a union, to account for its address being
+   passed in $4.  However, at the current time, this produces a compiler
+   that can't bootstrap, so comment it out for now.  */
+
+#if 0
+#define FIRST_PARM_OFFSET(FNDECL)					\
+  (FNDECL != 0								\
+   && TREE_TYPE (FNDECL) != 0						\
+   && TREE_TYPE (TREE_TYPE (FNDECL)) != 0				\
+   && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE	\
+       || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE)	\
+		? UNITS_PER_WORD					\
+		: 0)
+#else
+#define FIRST_PARM_OFFSET(FNDECL) 0
+#endif
+
+/* When a parameter is passed in a register, stack space is still
+   allocated for it.  For the MIPS, stack space must be allocated, cf
+   Asm Lang Prog Guide page 7-8.
+
+   BEWARE that some space is also allocated for non existing arguments
+   in register. In case an argument list is of form GF used registers
+   are a0 (a2,a3), but we should push over a1...  */
+
+#define REG_PARM_STACK_SPACE(FNDECL)	\
+  ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
+
+/* Define this if it is the responsibility of the caller to
+   allocate the area reserved for arguments passed in registers. 
+   If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
+   of this macro is to determine whether the space is included in 
+   `current_function_outgoing_args_size'.  */
+#define OUTGOING_REG_PARM_STACK_SPACE
+
+/* Align stack frames on 64 bits (Double Word ).  */
+#ifndef STACK_BOUNDARY
+#define STACK_BOUNDARY 64
+#endif
+
+/* Make sure 4 words are always allocated on the stack.  */
+
+#ifndef STACK_ARGS_ADJUST
+#define STACK_ARGS_ADJUST(SIZE)						\
+{									\
+  if (SIZE.constant < 4 * UNITS_PER_WORD)				\
+    SIZE.constant = 4 * UNITS_PER_WORD;					\
+}
+#endif
+
+
+/* A C expression that should indicate the number of bytes of its
+   own arguments that a function pops on returning, or 0
+   if the function pops no arguments and the caller must therefore
+   pop them all after the function returns.
+
+   FUNDECL is the declaration node of the function (as a tree).
+
+   FUNTYPE is a C variable whose value is a tree node that
+   describes the function in question.  Normally it is a node of
+   type `FUNCTION_TYPE' that describes the data type of the function.
+   From this it is possible to obtain the data types of the value
+   and arguments (if known).
+
+   When a call to a library function is being considered, FUNTYPE
+   will contain an identifier node for the library function.  Thus,
+   if you need to distinguish among various library functions, you
+   can do so by their names.  Note that "library function" in this
+   context means a function used to perform arithmetic, whose name
+   is known specially in the compiler and was not mentioned in the
+   C code being compiled.
+
+   STACK-SIZE is the number of bytes of arguments passed on the
+   stack.  If a variable number of bytes is passed, it is zero, and
+   argument popping will always be the responsibility of the
+   calling function.  */
+
+#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
+
+
+/* Symbolic macros for the registers used to return integer and floating
+   point values.  */
+
+#define GP_RETURN (GP_REG_FIRST + 2)
+#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
+
+/* Symbolic macros for the first/last argument registers.  */
+
+#define GP_ARG_FIRST (GP_REG_FIRST + 4)
+#define GP_ARG_LAST  (GP_REG_FIRST + 7)
+#define FP_ARG_FIRST (FP_REG_FIRST + 12)
+#define FP_ARG_LAST  (FP_REG_FIRST + 15)
+
+#define MAX_ARGS_IN_REGISTERS	4
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  Because we define
+   PROMOTE_FUNCTION_RETURN, we must promote the mode just as
+   PROMOTE_MODE does.  */
+
+#define LIBCALL_VALUE(MODE)						\
+  gen_rtx (REG,								\
+	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
+	     || GET_MODE_SIZE (MODE) >= 4)				\
+	    ? (MODE)							\
+	    : SImode),							\
+	   ((GET_MODE_CLASS (MODE) == MODE_FLOAT			\
+	     && (! TARGET_SINGLE_FLOAT					\
+		 || GET_MODE_SIZE (MODE) <= 4))				\
+	    ? FP_RETURN							\
+	    : GP_RETURN))
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.  */
+
+#define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
+
+
+/* 1 if N is a possible register number for a function value.
+   On the MIPS, R2 R3 and F0 F2 are the only register thus used.
+   Currently, R2 and F0 are only implemented  here (C has no complex type)  */
+
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
+
+/* 1 if N is a possible register number for function argument passing.
+   We have no FP argument registers when soft-float.  When FP registers
+   are 32 bits, we can't directly reference the odd numbered ones.  */
+
+#define FUNCTION_ARG_REGNO_P(N)					\
+  (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST)			\
+   || ((! TARGET_SOFT_FLOAT					\
+       && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST)		\
+       && (TARGET_FLOAT64 || (0 == (N) % 2)))			\
+       && ! fixed_regs[N]))
+
+/* A C expression which can inhibit the returning of certain function
+   values in registers, based on the type of value.  A nonzero value says
+   to return the function value in memory, just as large structures are
+   always returned.  Here TYPE will be a C expression of type
+   `tree', representing the data type of the value.
+
+   Note that values of mode `BLKmode' must be explicitly
+   handled by this macro.  Also, the option `-fpcc-struct-return'
+   takes effect regardless of this macro.  On most systems, it is
+   possible to leave the macro undefined; this causes a default
+   definition to be used, whose value is the constant 1 for BLKmode
+   values, and 0 otherwise.
+
+   GCC normally converts 1 byte structures into chars, 2 byte
+   structs into shorts, and 4 byte structs into ints, and returns
+   them this way.  Defining the following macro overrides this,
+   to give us MIPS cc compatibility.  */
+
+#define RETURN_IN_MEMORY(TYPE)	\
+  (TYPE_MODE (TYPE) == BLKmode)
+
+/* A code distinguishing the floating point format of the target
+   machine.  There are three defined values: IEEE_FLOAT_FORMAT,
+   VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT.  */
+
+#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
+
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On the mips16, we need to keep track of which floating point
+   arguments were passed in general registers, but would have been
+   passed in the FP regs if this were a 32 bit function, so that we
+   can move them to the FP regs if we wind up calling a 32 bit
+   function.  We record this information in fp_code, encoded in base
+   four.  A zero digit means no floating point argument, a one digit
+   means an SFmode argument, and a two digit means a DFmode argument,
+   and a three digit is not used.  The low order digit is the first
+   argument.  Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
+   an SFmode argument.  ??? A more sophisticated approach will be
+   needed if MIPS_ABI != ABI_32.  */
+
+typedef struct mips_args {
+  int gp_reg_found;		/* whether a gp register was found yet */
+  int arg_number;		/* argument number */
+  int arg_words;		/* # total words the arguments take */
+  int fp_arg_words;		/* # words for FP args (MIPS_EABI only) */
+  int last_arg_fp;		/* nonzero if last arg was FP (EABI only) */
+  int fp_code;			/* Mode of FP arguments (mips16) */
+  int num_adjusts;		/* number of adjustments made */
+				/* Adjustments made to args pass in regs.  */
+				/* ??? The size is doubled to work around a 
+				   bug in the code that sets the adjustments
+				   in function_arg.  */
+  struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
+} CUMULATIVE_ARGS;
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.
+
+*/
+
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)		\
+  init_cumulative_args (&CUM, FNTYPE, LIBNAME)				\
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)  */
+
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
+  function_arg_advance (&CUM, MODE, TYPE, NAMED)
+
+/* Determine where to put an argument to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).  */
+
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
+  function_arg( &CUM, MODE, TYPE, NAMED)
+
+/* For an arg passed partly in registers and partly in memory,
+   this is the number of registers used.
+   For args passed entirely in registers or entirely in memory, zero. */
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
+  function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
+
+/* If defined, a C expression that gives the alignment boundary, in
+   bits, of an argument with the specified mode and type.  If it is
+   not defined,  `PARM_BOUNDARY' is used for all arguments.  */
+
+#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)				\
+  (((TYPE) != 0)							\
+	? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY)		\
+		? PARM_BOUNDARY						\
+		: TYPE_ALIGN(TYPE))					\
+	: ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY)			\
+		? PARM_BOUNDARY						\
+		: GET_MODE_ALIGNMENT(MODE)))
+
+
+/* This macro generates the assembly code for function entry.
+   FILE is a stdio stream to output the code to.
+   SIZE is an int: how many units of temporary storage to allocate.
+   Refer to the array `regs_ever_live' to determine which registers
+   to save; `regs_ever_live[I]' is nonzero if register number I
+   is ever used in the function.  This macro is responsible for
+   knowing which registers should not be saved even if used.  */
+
+#define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
+
+/* This macro generates the assembly code for function exit,
+   on machines that need it.  If FUNCTION_EPILOGUE is not defined
+   then individual return instructions are generated for each
+   return statement.  Args are same as for FUNCTION_PROLOGUE.  */
+
+#define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
+
+
+/* Tell prologue and epilogue if register REGNO should be saved / restored.  */
+
+#define MUST_SAVE_REGISTER(regno) \
+ ((regs_ever_live[regno] && !call_used_regs[regno])			\
+  || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)	\
+  || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
+
+/* ALIGN FRAMES on double word boundaries */
+#ifndef MIPS_STACK_ALIGN
+#define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
+#endif
+
+
+/* Output assembler code to FILE to increment profiler label # LABELNO
+   for profiling a function entry.  */
+
+#define FUNCTION_PROFILER(FILE, LABELNO)				\
+{									\
+  if (TARGET_MIPS16)							\
+    sorry ("mips16 function profiling");				\
+  fprintf (FILE, "\t.set\tnoreorder\n");				\
+  fprintf (FILE, "\t.set\tnoat\n");					\
+  fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",	\
+	   reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);	\
+  fprintf (FILE, "\tjal\t_mcount\n");					\
+  fprintf (FILE,							\
+	   "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",	\
+	   TARGET_64BIT ? "dsubu" : "subu",				\
+	   reg_names[STACK_POINTER_REGNUM],				\
+	   reg_names[STACK_POINTER_REGNUM],				\
+	   Pmode == DImode ? 16 : 8);					\
+  fprintf (FILE, "\t.set\treorder\n");					\
+  fprintf (FILE, "\t.set\tat\n");					\
+}
+
+/* Define this macro if the code for function profiling should come
+   before the function prologue.  Normally, the profiling code comes
+   after.  */
+
+/* #define PROFILE_BEFORE_PROLOGUE */
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+
+#define EXIT_IGNORE_STACK 1
+
+
+/* A C statement to output, on the stream FILE, assembler code for a
+   block of data that contains the constant parts of a trampoline. 
+   This code should not include a label--the label is taken care of
+   automatically.  */
+
+#define TRAMPOLINE_TEMPLATE(STREAM)					 \
+{									 \
+  fprintf (STREAM, "\t.word\t0x03e00821\t\t# move   $1,$31\n");		\
+  fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n");		\
+  fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n");			\
+  if (Pmode == DImode)							\
+    {									\
+      fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld     $3,20($31)\n");	\
+      fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld     $2,28($31)\n");	\
+    }									\
+  else									\
+    {									\
+      fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw     $3,20($31)\n");	\
+      fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw     $2,24($31)\n");	\
+    }									\
+  fprintf (STREAM, "\t.word\t0x0060c821\t\t# move   $25,$3 (abicalls)\n"); \
+  fprintf (STREAM, "\t.word\t0x00600008\t\t# jr     $3\n");		\
+  fprintf (STREAM, "\t.word\t0x0020f821\t\t# move   $31,$1\n");		\
+  if (Pmode == DImode)							\
+    {									\
+      fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
+      fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
+    }									\
+  else									\
+    {									\
+      fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
+      fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
+    }									\
+}
+
+/* A C expression for the size in bytes of the trampoline, as an
+   integer.  */
+
+#define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
+
+/* Alignment required for trampolines, in bits.  */
+
+#define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
+
+/* INITIALIZE_TRAMPOLINE calls this library function to flush
+   program and data caches.  */
+
+#ifndef CACHE_FLUSH_FUNC
+#define CACHE_FLUSH_FUNC "_flush_cache"
+#endif
+
+/* A C statement to initialize the variable parts of a trampoline. 
+   ADDR is an RTX for the address of the trampoline; FNADDR is an
+   RTX for the address of the nested function; STATIC_CHAIN is an
+   RTX for the static chain value that should be passed to the
+   function when it is called.  */
+
+#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN)			    \
+{									    \
+  rtx addr = ADDR;							    \
+  if (Pmode == DImode)							    \
+    {									    \
+      emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
+      emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
+    }									    \
+  else									    \
+    {									    \
+      emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
+      emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
+    }									    \
+									    \
+  /* Flush both caches.  We need to flush the data cache in case	    \
+     the system has a write-back cache.  */				    \
+  /* ??? Should check the return value for errors.  */			    \
+  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC),	    \
+		     0, VOIDmode, 3, addr, Pmode,			    \
+		     GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
+		     GEN_INT (3), TYPE_MODE (integer_type_node));	    \
+}
+
+/* Addressing modes, and classification of registers for them.  */
+
+/* #define HAVE_POST_INCREMENT 0 */
+/* #define HAVE_POST_DECREMENT 0 */
+
+/* #define HAVE_PRE_DECREMENT 0 */
+/* #define HAVE_PRE_INCREMENT 0 */
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   These definitions are NOT overridden anywhere.  */
+
+#define BASE_REG_P(regno, mode)					\
+  (TARGET_MIPS16						\
+   ? (M16_REG_P (regno)						\
+      || (regno) == FRAME_POINTER_REGNUM			\
+      || (regno) == ARG_POINTER_REGNUM				\
+      || ((regno) == STACK_POINTER_REGNUM			\
+	  && (GET_MODE_SIZE (mode) == 4				\
+	      || GET_MODE_SIZE (mode) == 8)))			\
+   : GP_REG_P (regno))
+
+#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)				    \
+  BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
+	     (mode))
+
+#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
+  (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
+
+#define REGNO_OK_FOR_INDEX_P(regno)	0
+#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
+  GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects them all.
+   The symbol REG_OK_STRICT causes the latter definition to be used.
+
+   Most source files want to accept pseudo regs in the hope that
+   they will get allocated to the class that the insn wants them to be in.
+   Some source files that are used after register allocation
+   need to be strict.  */
+
+#ifndef REG_OK_STRICT
+
+#define REG_OK_STRICT_P 0
+#define REG_OK_FOR_INDEX_P(X) 0
+#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
+  GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
+
+#else
+
+#define REG_OK_STRICT_P 1
+#define REG_OK_FOR_INDEX_P(X) 0
+#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
+  REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
+
+#endif
+
+
+/* Maximum number of registers that can appear in a valid memory address.  */
+
+#define MAX_REGS_PER_ADDRESS 1
+
+/* A C compound statement with a conditional `goto LABEL;' executed
+   if X (an RTX) is a legitimate memory address on the target
+   machine for a memory operand of mode MODE.
+
+   It usually pays to define several simpler macros to serve as
+   subroutines for this one.  Otherwise it may be too complicated
+   to understand.
+
+   This macro must exist in two variants: a strict variant and a
+   non-strict one.  The strict variant is used in the reload pass. 
+   It must be defined so that any pseudo-register that has not been
+   allocated a hard register is considered a memory reference.  In
+   contexts where some kind of register is required, a
+   pseudo-register with no hard register must be rejected.
+
+   The non-strict variant is used in other passes.  It must be
+   defined to accept all pseudo-registers in every context where
+   some kind of register is required.
+
+   Compiler source files that want to use the strict variant of
+   this macro define the macro `REG_OK_STRICT'.  You should use an
+   `#ifdef REG_OK_STRICT' conditional to define the strict variant
+   in that case and the non-strict variant otherwise.
+
+   Typically among the subroutines used to define
+   `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
+   acceptable registers for various purposes (one for base
+   registers, one for index registers, and so on).  Then only these
+   subroutine macros need have two variants; the higher levels of
+   macros may be the same whether strict or not.
+
+   Normally, constant addresses which are the sum of a `symbol_ref'
+   and an integer are stored inside a `const' RTX to mark them as
+   constant.  Therefore, there is no need to recognize such sums
+   specifically as legitimate addresses.  Normally you would simply
+   recognize any `const' as legitimate.
+
+   Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
+   constant sums that are not marked with  `const'.  It assumes
+   that a naked `plus' indicates indexing.  If so, then you *must*
+   reject such naked constant sums as illegitimate addresses, so
+   that none of them will be given to `PRINT_OPERAND_ADDRESS'.
+
+   On some machines, whether a symbolic address is legitimate
+   depends on the section that the address refers to.  On these
+   machines, define the macro `ENCODE_SECTION_INFO' to store the
+   information into the `symbol_ref', and then check for it here. 
+   When you see a `const', you will have to look inside it to find
+   the `symbol_ref' in order to determine the section.  */
+
+#if 1
+#define GO_PRINTF(x)	trace(x)
+#define GO_PRINTF2(x,y)	trace(x,y)
+#define GO_DEBUG_RTX(x) debug_rtx(x)
+
+#else
+#define GO_PRINTF(x)
+#define GO_PRINTF2(x,y)
+#define GO_DEBUG_RTX(x)
+#endif
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
+{									\
+  register rtx xinsn = (X);						\
+									\
+  if (TARGET_DEBUG_B_MODE)						\
+    {									\
+      GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",	\
+		  (REG_OK_STRICT_P) ? "" : "not ");			\
+      GO_DEBUG_RTX (xinsn);						\
+    }									\
+									\
+  /* The mips16 can only use the stack pointer as a base register when	\
+     loading SImode or DImode values.  */				\
+  if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE))	\
+    goto ADDR;								\
+									\
+  if (CONSTANT_ADDRESS_P (xinsn)					\
+      && ! (mips_split_addresses && mips_check_split (xinsn, MODE))	\
+      && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0)))	\
+    goto ADDR;								\
+									\
+  if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)		\
+    {									\
+      register rtx xlow0 = XEXP (xinsn, 0);				\
+      register rtx xlow1 = XEXP (xinsn, 1);				\
+									\
+      if (GET_CODE (xlow0) == REG					\
+	  && REG_MODE_OK_FOR_BASE_P (xlow0, MODE)			\
+	  && mips_check_split (xlow1, MODE))				\
+	goto ADDR;							\
+    }									\
+									\
+  if (GET_CODE (xinsn) == PLUS)						\
+    {									\
+      register rtx xplus0 = XEXP (xinsn, 0);				\
+      register rtx xplus1 = XEXP (xinsn, 1);				\
+      register enum rtx_code code0 = GET_CODE (xplus0);			\
+      register enum rtx_code code1 = GET_CODE (xplus1);			\
+									\
+      /* The mips16 can only use the stack pointer as a base register	\
+         when loading SImode or DImode values.  */			\
+      if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE))	\
+	{								\
+	  if (code1 == CONST_INT					\
+	      && INTVAL (xplus1) >= -32768				\
+	      && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767)	\
+	    goto ADDR;							\
+									\
+	  /* On the mips16, we represent GP relative offsets in RTL.	\
+             These are 16 bit signed values, and can serve as register	\
+             offsets.  */						\
+	  if (TARGET_MIPS16						\
+	      && mips16_gp_offset_p (xplus1))				\
+	    goto ADDR;							\
+									\
+	  /* For some code sequences, you actually get better code by	\
+	     pretending that the MIPS supports an address mode of a	\
+	     constant address + a register, even though the real	\
+	     machine doesn't support it.  This is because the		\
+	     assembler can use $r1 to load just the high 16 bits, add	\
+	     in the register, and fold the low 16 bits into the memory	\
+	     reference, whereas the compiler generates a 4 instruction	\
+	     sequence.  On the other hand, CSE is not as effective.	\
+	     It would be a win to generate the lui directly, but the	\
+	     MIPS assembler does not have syntax to generate the	\
+	     appropriate relocation.  */				\
+									\
+	  /* Also accept CONST_INT addresses here, so no else.  */	\
+	  /* Reject combining an embedded PIC text segment reference	\
+	     with a register.  That requires an additional		\
+	     instruction.  */						\
+          /* ??? Reject combining an address with a register for the MIPS  \
+	     64 bit ABI, because the SGI assembler can not handle this.  */ \
+	  if (!TARGET_DEBUG_A_MODE					\
+	      && (mips_abi == ABI_32					\
+		  || mips_abi == ABI_O64				\
+		  || mips_abi == ABI_EABI)				\
+	      && CONSTANT_ADDRESS_P (xplus1)				\
+	      && ! mips_split_addresses					\
+	      && (!TARGET_EMBEDDED_PIC					\
+		  || code1 != CONST					\
+		  || GET_CODE (XEXP (xplus1, 0)) != MINUS)		\
+	      && !TARGET_MIPS16)					\
+	    goto ADDR;							\
+	}								\
+    }									\
+									\
+  if (TARGET_DEBUG_B_MODE)						\
+    GO_PRINTF ("Not a legitimate address\n");				\
+}
+
+
+/* A C expression that is 1 if the RTX X is a constant which is a
+   valid address.  This is defined to be the same as `CONSTANT_P (X)',
+   but rejecting CONST_DOUBLE.  */
+/* When pic, we must reject addresses of the form symbol+large int.
+   This is because an instruction `sw $4,s+70000' needs to be converted
+   by the assembler to `lw $at,s($gp);sw $4,70000($at)'.  Normally the
+   assembler would use $at as a temp to load in the large offset.  In this
+   case $at is already in use.  We convert such problem addresses to
+   `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS.  */
+/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.  */
+#define CONSTANT_ADDRESS_P(X)						\
+  ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
+    || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH		\
+    || (GET_CODE (X) == CONST						\
+	&& ! (flag_pic && pic_address_needs_scratch (X))		\
+	&& (mips_abi == ABI_32						\
+	    || mips_abi == ABI_O64					\
+	    || mips_abi == ABI_EABI)))					\
+   && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
+
+/* Define this, so that when PIC, reload won't try to reload invalid
+   addresses which require two reload registers.  */
+
+#define LEGITIMATE_PIC_OPERAND_P(X)  (! pic_address_needs_scratch (X))
+
+/* Nonzero if the constant value X is a legitimate general operand.
+   It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
+
+   At present, GAS doesn't understand li.[sd], so don't allow it
+   to be generated at present.  Also, the MIPS assembler does not
+   grok li.d Infinity.  */
+
+/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.  */
+#define LEGITIMATE_CONSTANT_P(X)					\
+  ((GET_CODE (X) != CONST_DOUBLE					\
+    || mips_const_double_ok (X, GET_MODE (X)))				\
+   && ! (GET_CODE (X) == CONST						\
+	 && mips_abi != ABI_32 						\
+	 && mips_abi != ABI_O64 					\
+         && mips_abi != ABI_EABI)					\
+   && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
+
+/* A C compound statement that attempts to replace X with a valid
+   memory address for an operand of mode MODE.  WIN will be a C
+   statement label elsewhere in the code; the macro definition may
+   use
+
+          GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
+
+   to avoid further processing if the address has become legitimate.
+
+   X will always be the result of a call to `break_out_memory_refs',
+   and OLDX will be the operand that was given to that function to
+   produce X.
+
+   The code generated by this macro should not alter the
+   substructure of X.  If it transforms X into a more legitimate
+   form, it should assign X (which will always be a C variable) a
+   new value.
+
+   It is not necessary for this macro to come up with a legitimate
+   address.  The compiler has standard ways of doing so in all
+   cases.  In fact, it is safe for this macro to do nothing.  But
+   often a machine-dependent strategy can generate better code.
+
+   For the MIPS, transform:
+
+	memory(X + <large int>)
+
+   into:
+
+	Y = <large int> & ~0x7fff;
+	Z = X + Y
+	memory (Z + (<large int> & 0x7fff));
+
+   This is for CSE to find several similar references, and only use one Z.
+
+   When PIC, convert addresses of the form memory (symbol+large int) to
+   memory (reg+large int).  */
+   
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)				\
+{									\
+  register rtx xinsn = (X);						\
+									\
+  if (TARGET_DEBUG_B_MODE)						\
+    {									\
+      GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n");			\
+      GO_DEBUG_RTX (xinsn);						\
+    }									\
+									\
+  if (mips_split_addresses && mips_check_split (X, MODE))		\
+    {									\
+      /* ??? Is this ever executed?  */					\
+      X = gen_rtx (LO_SUM, Pmode,					\
+		   copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
+      goto WIN;								\
+    }									\
+									\
+  if (GET_CODE (xinsn) == CONST						\
+      && ((flag_pic && pic_address_needs_scratch (xinsn))		\
+	  /* ??? SGI's Irix 6 assembler can't handle CONST.  */		\
+	  || (mips_abi != ABI_32 					\
+	      && mips_abi != ABI_O64					\
+	      && mips_abi != ABI_EABI)))				\
+    {									\
+      rtx ptr_reg = gen_reg_rtx (Pmode);				\
+      rtx constant = XEXP (XEXP (xinsn, 0), 1);				\
+									\
+      emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0));		\
+									\
+      X = gen_rtx (PLUS, Pmode, ptr_reg, constant);			\
+      if (SMALL_INT (constant))						\
+	goto WIN;							\
+      /* Otherwise we fall through so the code below will fix the	\
+	 constant.  */							\
+      xinsn = X;							\
+    }									\
+									\
+  if (GET_CODE (xinsn) == PLUS)						\
+    {									\
+      register rtx xplus0 = XEXP (xinsn, 0);				\
+      register rtx xplus1 = XEXP (xinsn, 1);				\
+      register enum rtx_code code0 = GET_CODE (xplus0);			\
+      register enum rtx_code code1 = GET_CODE (xplus1);			\
+									\
+      if (code0 != REG && code1 == REG)					\
+	{								\
+	  xplus0 = XEXP (xinsn, 1);					\
+	  xplus1 = XEXP (xinsn, 0);					\
+	  code0 = GET_CODE (xplus0);					\
+	  code1 = GET_CODE (xplus1);					\
+	}								\
+									\
+      if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)		\
+	  && code1 == CONST_INT && !SMALL_INT (xplus1))			\
+	{								\
+	  rtx int_reg = gen_reg_rtx (Pmode);				\
+	  rtx ptr_reg = gen_reg_rtx (Pmode);				\
+									\
+	  emit_move_insn (int_reg,					\
+			  GEN_INT (INTVAL (xplus1) & ~ 0x7fff));	\
+									\
+	  emit_insn (gen_rtx (SET, VOIDmode,				\
+			      ptr_reg,					\
+			      gen_rtx (PLUS, Pmode, xplus0, int_reg)));	\
+									\
+	  X = gen_rtx (PLUS, Pmode, ptr_reg,				\
+		       GEN_INT (INTVAL (xplus1) & 0x7fff));		\
+	  goto WIN;							\
+	}								\
+    }									\
+									\
+  if (TARGET_DEBUG_B_MODE)						\
+    GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n");			\
+}
+
+
+/* A C statement or compound statement with a conditional `goto
+   LABEL;' executed if memory address X (an RTX) can have different
+   meanings depending on the machine mode of the memory reference it
+   is used for.
+
+   Autoincrement and autodecrement addresses typically have
+   mode-dependent effects because the amount of the increment or
+   decrement is the size of the operand being addressed.  Some
+   machines have other mode-dependent addresses.  Many RISC machines
+   have no mode-dependent addresses.
+
+   You may assume that ADDR is a valid address for the machine.  */
+
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
+
+
+/* Define this macro if references to a symbol must be treated
+   differently depending on something about the variable or
+   function named by the symbol (such as what section it is in).
+
+   The macro definition, if any, is executed immediately after the
+   rtl for DECL has been created and stored in `DECL_RTL (DECL)'. 
+   The value of the rtl will be a `mem' whose address is a
+   `symbol_ref'.
+
+   The usual thing for this macro to do is to a flag in the
+   `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
+   name string in the `symbol_ref' (if one bit is not enough
+   information).
+
+   The best way to modify the name string is by adding text to the
+   beginning, with suitable punctuation to prevent any ambiguity. 
+   Allocate the new name in `saveable_obstack'.  You will have to
+   modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
+   and output the name accordingly.
+
+   You can also check the information stored in the `symbol_ref' in
+   the definition of `GO_IF_LEGITIMATE_ADDRESS' or
+   `PRINT_OPERAND_ADDRESS'.
+
+   When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
+   small objects.
+
+   When generating embedded PIC code, SYMBOL_REF_FLAG is set for
+   symbols which are not in the .text section.
+
+   When generating mips16 code, SYMBOL_REF_FLAG is set for string
+   constants which are put in the .text section.  We also record the
+   total length of all such strings; this total is used to decide
+   whether we need to split the constant table, and need not be
+   precisely correct. 
+
+   When not mips16 code nor embedded PIC, if a symbol is in a
+   gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
+   splitting the reference so that gas can generate a gp relative
+   reference.
+
+   When TARGET_EMBEDDED_DATA is set, we assume that all const
+   variables will be stored in ROM, which is too far from %gp to use
+   %gprel addressing.  Note that (1) we include "extern const"
+   variables in this, which mips_select_section doesn't, and (2) we
+   can't always tell if they're really const (they might be const C++
+   objects with non-const constructors), so we err on the side of
+   caution and won't use %gprel anyway (otherwise we'd have to defer
+   this decision to the linker/loader).  The handling of extern consts
+   is why the DECL_INITIAL macros differ from mips_select_section.
+
+   If you are changing this macro, you should look at
+   mips_select_section and see if it needs a similar change.  */
+
+#define ENCODE_SECTION_INFO(DECL)					\
+do									\
+  {									\
+    if (TARGET_MIPS16)							\
+      {									\
+	if (TREE_CODE (DECL) == STRING_CST				\
+	    && ! flag_writable_strings					\
+	    /* If this string is from a function, and the function will	\
+	       go in a gnu linkonce section, then we can't directly	\
+	       access the string.  This gets an assembler error		\
+	       "unsupported PC relative reference to different section".\
+	       If we modify SELECT_SECTION to put it in function_section\
+	       instead of text_section, it still fails because		\
+	       DECL_SECTION_NAME isn't set until assemble_start_function.\
+	       If we fix that, it still fails because strings are shared\
+	       among multiple functions, and we have cross section	\
+	       references again.  We force it to work by putting string	\
+	       addresses in the constant pool and indirecting.  */	\
+	    && (! current_function_decl					\
+		|| ! UNIQUE_SECTION_P (current_function_decl)))		\
+	  {								\
+	    SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1;	\
+	    mips_string_length += TREE_STRING_LENGTH (DECL);		\
+	  }								\
+      }									\
+									\
+    if (TARGET_EMBEDDED_DATA						\
+	&& (TREE_CODE (DECL) == VAR_DECL				\
+	    && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL))	\
+	    && (!DECL_INITIAL (DECL)					\
+		|| TREE_CONSTANT (DECL_INITIAL (DECL))))		\
+      {									\
+	SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0;		\
+      }									\
+									\
+    else if (TARGET_EMBEDDED_PIC)					\
+      {									\
+        if (TREE_CODE (DECL) == VAR_DECL)				\
+	  SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;		\
+        else if (TREE_CODE (DECL) == FUNCTION_DECL)			\
+	  SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0;		\
+	else if (TREE_CODE (DECL) == STRING_CST				\
+		 && ! flag_writable_strings)				\
+	  SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0;		\
+        else								\
+	  SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1;		\
+      }									\
+									\
+    else if (TREE_CODE (DECL) == VAR_DECL				\
+             && DECL_SECTION_NAME (DECL) != NULL_TREE                   \
+             && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
+                              ".sdata")                                 \
+                || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
+                              ".sbss")))                                \
+      {									\
+        SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;		\
+      }									\
+									\
+    else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL)		\
+      {									\
+	int size = int_size_in_bytes (TREE_TYPE (DECL));		\
+									\
+	if (size > 0 && size <= mips_section_threshold)			\
+	  SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;		\
+      }									\
+									\
+    else if (HALF_PIC_P ())						\
+      {									\
+        HALF_PIC_ENCODE (DECL);						\
+      }									\
+  }									\
+while (0)
+
+/* The mips16 wants the constant pool to be after the function,
+   because the PC relative load instructions use unsigned offsets.  */
+
+#define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
+
+#define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE)	\
+  mips_string_length = 0;
+
+#if 0
+/* In mips16 mode, put most string constants after the function.  */
+#define CONSTANT_AFTER_FUNCTION_P(tree)				\
+  (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
+#endif
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.
+   ??? Using HImode in mips16 mode can cause overflow.  However, the
+   overflow is no more likely than the overflow in a branch
+   instruction.  Large functions can currently break in both ways.  */
+#define CASE_VECTOR_MODE \
+  (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
+
+/* Define as C expression which evaluates to nonzero if the tablejump
+   instruction expects the table to contain offsets from the address of the
+   table.
+   Do not define this if the table should contain absolute addresses. */
+#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+
+/* Define this as 1 if `char' should by default be signed; else as 0.  */
+#ifndef DEFAULT_SIGNED_CHAR
+#define DEFAULT_SIGNED_CHAR 1
+#endif
+
+/* Max number of bytes we can move from memory to memory
+   in one reasonably fast instruction.  */
+#define MOVE_MAX (TARGET_64BIT ? 8 : 4)
+#define MAX_MOVE_MAX 8
+
+/* Define this macro as a C expression which is nonzero if
+   accessing less than a word of memory (i.e. a `char' or a
+   `short') is no faster than accessing a word of memory, i.e., if
+   such access require more than one instruction or if there is no
+   difference in cost between byte and (aligned) word loads.
+
+   On RISC machines, it tends to generate better code to define
+   this as 1, since it avoids making a QI or HI mode register.  */
+#define SLOW_BYTE_ACCESS 1
+
+/* We assume that the store-condition-codes instructions store 0 for false
+   and some other value for true.  This is the value stored for true.  */
+
+#define STORE_FLAG_VALUE 1
+
+/* Define this if zero-extension is slow (more than one real instruction).  */
+#define SLOW_ZERO_EXTEND
+
+/* Define this to be nonzero if shift instructions ignore all but the low-order
+   few bits. */
+#define SHIFT_COUNT_TRUNCATED 1
+
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+   is done just by pretending it is already truncated.  */
+/* In 64 bit mode, 32 bit instructions require that register values be properly
+   sign-extended to 64 bits.  As a result, a truncate is not a no-op if it
+   converts a value >32 bits to a value <32 bits.  */
+/* ??? This results in inefficient code for 64 bit to 32 conversions.
+   Something needs to be done about this.  Perhaps not use any 32 bit
+   instructions?  Perhaps use PROMOTE_MODE?  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
+  (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
+
+/* Specify the machine mode that pointers have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
+
+#ifndef Pmode
+#define Pmode ((enum machine_mode)(TARGET_LONG64 ? DImode : SImode))
+#endif
+
+/* A function address in a call instruction
+   is a word address (for indexing purposes)
+   so give the MEM rtx a words's mode.  */
+
+#define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
+
+/* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
+   memset, instead of the BSD functions bcopy and bzero.  */
+
+#if defined(MIPS_SYSV) || defined(OSF_OS)
+#define TARGET_MEM_FUNCTIONS
+#endif
+
+
+/* A part of a C `switch' statement that describes the relative
+   costs of constant RTL expressions.  It must contain `case'
+   labels for expression codes `const_int', `const', `symbol_ref',
+   `label_ref' and `const_double'.  Each case must ultimately reach
+   a `return' statement to return the relative cost of the use of
+   that kind of constant value in an expression.  The cost may
+   depend on the precise value of the constant, which is available
+   for examination in X.
+
+   CODE is the expression code--redundant, since it can be obtained
+   with `GET_CODE (X)'.  */
+
+#define CONST_COSTS(X,CODE,OUTER_CODE)					\
+  case CONST_INT:							\
+    if (! TARGET_MIPS16)						\
+      {									\
+	/* Always return 0, since we don't have different sized		\
+	   instructions, hence different costs according to Richard	\
+	   Kenner */							\
+	return 0;							\
+      }									\
+    if ((OUTER_CODE) == SET)						\
+      {									\
+	if (INTVAL (X) >= 0 && INTVAL (X) < 0x100)			\
+	  return 0;							\
+	else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000)		\
+		 || (INTVAL (X) < 0 && INTVAL (X) > -0x100))		\
+	  return COSTS_N_INSNS (1);					\
+	else								\
+	  return COSTS_N_INSNS (2);					\
+      }									\
+    /* A PLUS could be an address.  We don't want to force an address	\
+       to use a register, so accept any signed 16 bit value without	\
+       complaint.  */							\
+    if ((OUTER_CODE) == PLUS						\
+	&& INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000)		\
+      return 0;								\
+    /* A number between 1 and 8 inclusive is efficient for a shift.	\
+       Otherwise, we will need an extended instruction.  */		\
+    if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT		\
+	|| (OUTER_CODE) == LSHIFTRT)					\
+      {									\
+	if (INTVAL (X) >= 1 && INTVAL (X) <= 8)				\
+	  return 0;							\
+	return COSTS_N_INSNS (1);					\
+      }									\
+    /* We can use cmpi for an xor with an unsigned 16 bit value.  */	\
+    if ((OUTER_CODE) == XOR						\
+	&& INTVAL (X) >= 0 && INTVAL (X) < 0x10000)			\
+      return 0;								\
+    /* We may be able to use slt or sltu for a comparison with a	\
+       signed 16 bit value.  (The boundary conditions aren't quite	\
+       right, but this is just a heuristic anyhow.)  */			\
+    if (((OUTER_CODE) == LT || (OUTER_CODE) == LE			\
+	 || (OUTER_CODE) == GE || (OUTER_CODE) == GT			\
+	 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU			\
+	 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU)			\
+	&& INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000)		\
+      return 0;								\
+    /* Equality comparisons with 0 are cheap.  */			\
+    if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE)			\
+	&& INTVAL (X) == 0)						\
+      return 0;								\
+									\
+    /* Otherwise, work out the cost to load the value into a		\
+       register.  */							\
+    if (INTVAL (X) >= 0 && INTVAL (X) < 0x100)				\
+      return COSTS_N_INSNS (1);						\
+    else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000)			\
+	     || (INTVAL (X) < 0 && INTVAL (X) > -0x100))		\
+      return COSTS_N_INSNS (2);						\
+    else								\
+      return COSTS_N_INSNS (3);						\
+									\
+  case LABEL_REF:							\
+    return COSTS_N_INSNS (2);						\
+									\
+  case CONST:								\
+    {									\
+      rtx offset = const0_rtx;						\
+      rtx symref = eliminate_constant_term (XEXP (X, 0), &offset);	\
+									\
+      if (TARGET_MIPS16 && mips16_gp_offset_p (X))			\
+	{								\
+	  /* Treat this like a signed 16 bit CONST_INT.  */		\
+	  if ((OUTER_CODE) == PLUS)					\
+	    return 0;							\
+	  else if ((OUTER_CODE) == SET)					\
+	    return COSTS_N_INSNS (1);					\
+	  else								\
+	    return COSTS_N_INSNS (2);					\
+	}								\
+									\
+      if (GET_CODE (symref) == LABEL_REF)				\
+	return COSTS_N_INSNS (2);					\
+									\
+      if (GET_CODE (symref) != SYMBOL_REF)				\
+	return COSTS_N_INSNS (4);					\
+									\
+      /* let's be paranoid.... */					\
+      if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767)		\
+	return COSTS_N_INSNS (2);					\
+									\
+      return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2);		\
+    }									\
+									\
+  case SYMBOL_REF:							\
+    return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2);			\
+									\
+  case CONST_DOUBLE:							\
+    {									\
+      rtx high, low;							\
+      if (TARGET_MIPS16)						\
+	return COSTS_N_INSNS (4);					\
+      split_double (X, &high, &low);					\
+      return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high))	\
+			     || low == CONST0_RTX (GET_MODE (low)))	\
+			    ? 2 : 4);					\
+    }
+
+/* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
+   This can be used, for example, to indicate how costly a multiply
+   instruction is.  In writing this macro, you can use the construct
+   `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
+
+   This macro is optional; do not define it if the default cost
+   assumptions are adequate for the target machine.
+
+   If -mdebugd is used, change the multiply cost to 2, so multiply by
+   a constant isn't converted to a series of shifts.  This helps
+   strength reduction, and also makes it easier to identify what the
+   compiler is doing.  */
+
+/* ??? Fix this to be right for the R8000.  */
+#define RTX_COSTS(X,CODE,OUTER_CODE)					\
+  case MEM:								\
+    {									\
+      int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
+      if (simple_memory_operand (X, GET_MODE (X)))			\
+	return COSTS_N_INSNS (num_words);				\
+									\
+      return COSTS_N_INSNS (2*num_words);				\
+    }									\
+									\
+  case FFS:								\
+    return COSTS_N_INSNS (6);						\
+									\
+  case NOT:								\
+    return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
+									\
+  case AND:								\
+  case IOR:								\
+  case XOR:								\
+    if (GET_MODE (X) == DImode && !TARGET_64BIT)			\
+      return COSTS_N_INSNS (2);						\
+									\
+    break;								\
+									\
+  case ASHIFT:								\
+  case ASHIFTRT:							\
+  case LSHIFTRT:							\
+    if (GET_MODE (X) == DImode && !TARGET_64BIT)			\
+      return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
+									\
+    break;								\
+									\
+  case ABS:								\
+    {									\
+      enum machine_mode xmode = GET_MODE (X);				\
+      if (xmode == SFmode || xmode == DFmode)				\
+	return COSTS_N_INSNS (1);					\
+									\
+      return COSTS_N_INSNS (4);						\
+    }									\
+									\
+  case PLUS:								\
+  case MINUS:								\
+    {									\
+      enum machine_mode xmode = GET_MODE (X);				\
+      if (xmode == SFmode || xmode == DFmode)				\
+	{								\
+	  if (mips_cpu == PROCESSOR_R3000				\
+              || mips_cpu == PROCESSOR_R3900)				\
+	    return COSTS_N_INSNS (2);					\
+	  else if (mips_cpu == PROCESSOR_R6000)				\
+	    return COSTS_N_INSNS (3);					\
+	  else								\
+	    return COSTS_N_INSNS (6);					\
+	}								\
+									\
+      if (xmode == DImode && !TARGET_64BIT)				\
+	return COSTS_N_INSNS (4);					\
+									\
+      break;								\
+    }									\
+									\
+  case NEG:								\
+    if (GET_MODE (X) == DImode && !TARGET_64BIT)			\
+      return 4;								\
+									\
+    break;								\
+									\
+  case MULT:								\
+    {									\
+      enum machine_mode xmode = GET_MODE (X);				\
+      if (xmode == SFmode)						\
+	{								\
+	  if (mips_cpu == PROCESSOR_R3000				\
+	      || mips_cpu == PROCESSOR_R3900				\
+	      || mips_cpu == PROCESSOR_R5000)				\
+	    return COSTS_N_INSNS (4);					\
+	  else if (mips_cpu == PROCESSOR_R6000)				\
+	    return COSTS_N_INSNS (5);					\
+	  else								\
+	    return COSTS_N_INSNS (7);					\
+	}								\
+									\
+      if (xmode == DFmode)						\
+	{								\
+	  if (mips_cpu == PROCESSOR_R3000				\
+	      || mips_cpu == PROCESSOR_R3900				\
+	      || mips_cpu == PROCESSOR_R5000)				\
+	    return COSTS_N_INSNS (5);					\
+	  else if (mips_cpu == PROCESSOR_R6000)				\
+	    return COSTS_N_INSNS (6);					\
+	  else								\
+	    return COSTS_N_INSNS (8);					\
+	}								\
+									\
+      if (mips_cpu == PROCESSOR_R3000)					\
+	return COSTS_N_INSNS (12);					\
+      else if (mips_cpu == PROCESSOR_R3900)				\
+	return COSTS_N_INSNS (2);					\
+      else if (mips_cpu == PROCESSOR_R6000)				\
+	return COSTS_N_INSNS (17);					\
+      else if (mips_cpu == PROCESSOR_R5000)				\
+	return COSTS_N_INSNS (5);					\
+      else								\
+	return COSTS_N_INSNS (10);					\
+    }									\
+									\
+  case DIV:								\
+  case MOD:								\
+    {									\
+      enum machine_mode xmode = GET_MODE (X);				\
+      if (xmode == SFmode)						\
+	{								\
+	  if (mips_cpu == PROCESSOR_R3000				\
+              || mips_cpu == PROCESSOR_R3900)				\
+	    return COSTS_N_INSNS (12);					\
+	  else if (mips_cpu == PROCESSOR_R6000)				\
+	    return COSTS_N_INSNS (15);					\
+	  else								\
+	    return COSTS_N_INSNS (23);					\
+	}								\
+									\
+      if (xmode == DFmode)						\
+	{								\
+	  if (mips_cpu == PROCESSOR_R3000				\
+              || mips_cpu == PROCESSOR_R3900)				\
+	    return COSTS_N_INSNS (19);					\
+	  else if (mips_cpu == PROCESSOR_R6000)				\
+	    return COSTS_N_INSNS (16);					\
+	  else								\
+	    return COSTS_N_INSNS (36);					\
+	}								\
+    }									\
+    /* fall through */							\
+									\
+  case UDIV:								\
+  case UMOD:								\
+    if (mips_cpu == PROCESSOR_R3000					\
+        || mips_cpu == PROCESSOR_R3900)					\
+      return COSTS_N_INSNS (35);					\
+    else if (mips_cpu == PROCESSOR_R6000)				\
+      return COSTS_N_INSNS (38);					\
+    else if (mips_cpu == PROCESSOR_R5000)				\
+      return COSTS_N_INSNS (36);					\
+    else								\
+      return COSTS_N_INSNS (69);					\
+									\
+  case SIGN_EXTEND:							\
+    /* A sign extend from SImode to DImode in 64 bit mode is often	\
+       zero instructions, because the result can often be used		\
+       directly by another instruction; we'll call it one.  */		\
+    if (TARGET_64BIT && GET_MODE (X) == DImode				\
+	&& GET_MODE (XEXP (X, 0)) == SImode)				\
+      return COSTS_N_INSNS (1);						\
+    else								\
+      return COSTS_N_INSNS (2);						\
+									\
+  case ZERO_EXTEND:							\
+    if (TARGET_64BIT && GET_MODE (X) == DImode				\
+	&& GET_MODE (XEXP (X, 0)) == SImode)				\
+      return COSTS_N_INSNS (2);						\
+    else								\
+      return COSTS_N_INSNS (1);
+
+/* An expression giving the cost of an addressing mode that
+   contains ADDRESS.  If not defined, the cost is computed from the
+   form of the ADDRESS expression and the `CONST_COSTS' values.
+
+   For most CISC machines, the default cost is a good approximation
+   of the true cost of the addressing mode.  However, on RISC
+   machines, all instructions normally have the same length and
+   execution time.  Hence all addresses will have equal costs.
+
+   In cases where more than one form of an address is known, the
+   form with the lowest cost will be used.  If multiple forms have
+   the same, lowest, cost, the one that is the most complex will be
+   used.
+
+   For example, suppose an address that is equal to the sum of a
+   register and a constant is used twice in the same basic block. 
+   When this macro is not defined, the address will be computed in
+   a register and memory references will be indirect through that
+   register.  On machines where the cost of the addressing mode
+   containing the sum is no higher than that of a simple indirect
+   reference, this will produce an additional instruction and
+   possibly require an additional register.  Proper specification
+   of this macro eliminates this overhead for such machines.
+
+   Similar use of this macro is made in strength reduction of loops.
+
+   ADDRESS need not be valid as an address.  In such a case, the
+   cost is not relevant and can be any value; invalid addresses
+   need not be assigned a different cost.
+
+   On machines where an address involving more than one register is
+   as cheap as an address computation involving only one register,
+   defining `ADDRESS_COST' to reflect this can cause two registers
+   to be live over a region of code where only one would have been
+   if `ADDRESS_COST' were not defined in that manner.  This effect
+   should be considered in the definition of this macro. 
+   Equivalent costs should probably only be given to addresses with
+   different numbers of registers on machines with lots of registers.
+
+   This macro will normally either not be defined or be defined as
+   a constant. */
+
+#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
+
+/* A C expression for the cost of moving data from a register in
+   class FROM to one in class TO.  The classes are expressed using
+   the enumeration values such as `GENERAL_REGS'.  A value of 2 is
+   the default; other values are interpreted relative to that.
+
+   It is not required that the cost always equal 2 when FROM is the
+   same as TO; on some machines it is expensive to move between
+   registers if they are not general registers.
+
+   If reload sees an insn consisting of a single `set' between two
+   hard registers, and if `REGISTER_MOVE_COST' applied to their
+   classes returns a value of 2, reload does not check to ensure
+   that the constraints of the insn are met.  Setting a cost of
+   other than 2 will allow reload to verify that the constraints are
+   met.  You should do this if the `movM' pattern's constraints do
+   not allow such copying.  */
+
+#define REGISTER_MOVE_COST(FROM, TO)	\
+  ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2			\
+   : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2			\
+   : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2			\
+   : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2			\
+   : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
+   : (FROM) == FP_REGS && (TO) == FP_REGS ? 2				\
+   : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4			\
+   : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4			\
+   : (((FROM) == HI_REG || (FROM) == LO_REG				\
+       || (FROM) == MD_REGS || (FROM) == HILO_REG)			\
+      && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 12		\
+   : (((FROM) == HI_REG || (FROM) == LO_REG				\
+       || (FROM) == MD_REGS || (FROM) == HILO_REG)			\
+      && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6)		\
+   : (((TO) == HI_REG || (TO) == LO_REG					\
+       || (TO) == MD_REGS || (TO) == HILO_REG)				\
+      && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6)		\
+   : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4			\
+   : (FROM) == FP_REGS && (TO) == ST_REGS ? 8				\
+   : 12)
+
+/* ??? Fix this to be right for the R8000.  */
+#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
+  (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
+   + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
+
+/* Define if copies to/from condition code registers should be avoided.
+
+   This is needed for the MIPS because reload_outcc is not complete;
+   it needs to handle cases where the source is a general or another
+   condition code register.  */
+#define AVOID_CCMODE_COPIES
+
+/* A C expression for the cost of a branch instruction.  A value of
+   1 is the default; other values are interpreted relative to that.  */
+
+/* ??? Fix this to be right for the R8000.  */
+#define BRANCH_COST							\
+  ((! TARGET_MIPS16							\
+    && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000))	\
+   ? 2 : 1)
+
+/* A C statement (sans semicolon) to update the integer variable COST
+   based on the relationship between INSN that is dependent on
+   DEP_INSN through the dependence LINK.  The default is to make no
+   adjustment to COST.  On the MIPS, ignore the cost of anti- and
+   output-dependencies.  */
+
+#define ADJUST_COST(INSN,LINK,DEP_INSN,COST)				\
+  if (REG_NOTE_KIND (LINK) != 0)					\
+    (COST) = 0; /* Anti or output dependence.  */
+
+#define ISSUE_RATE (TARGET_MIPS5400 ? 2 : 1) /* CYGNUS LOCAL vr5400/raeburn */
+
+/* Optionally define this if you have added predicates to
+   `MACHINE.c'.  This macro is called within an initializer of an
+   array of structures.  The first field in the structure is the
+   name of a predicate and the second field is an array of rtl
+   codes.  For each predicate, list all rtl codes that can be in
+   expressions matched by the predicate.  The list should have a
+   trailing comma.  Here is an example of two entries in the list
+   for a typical RISC machine:
+
+   #define PREDICATE_CODES \
+     {"gen_reg_rtx_operand", {SUBREG, REG}},  \
+     {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
+
+   Defining this macro does not affect the generated code (however,
+   incorrect definitions that omit an rtl code that may be matched
+   by the predicate can cause the compiler to malfunction). 
+   Instead, it allows the table built by `genrecog' to be more
+   compact and efficient, thus speeding up the compiler.  The most
+   important predicates to include in the list specified by this
+   macro are thoses used in the most insn patterns.  */
+
+#define PREDICATE_CODES							\
+  {"uns_arith_operand",		{ REG, CONST_INT, SUBREG }},		\
+  {"arith_operand",		{ REG, CONST_INT, SUBREG }},		\
+  {"arith32_operand",		{ REG, CONST_INT, SUBREG }},		\
+  {"reg_or_0_operand",		{ REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
+  {"true_reg_or_0_operand",	{ REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
+  {"small_int",			{ CONST_INT }},				\
+  {"large_int",			{ CONST_INT }},				\
+  {"mips_const_double_ok",	{ CONST_DOUBLE }},			\
+  {"const_float_1_operand",	{ CONST_DOUBLE }},			\
+  {"simple_memory_operand",	{ MEM, SUBREG }},			\
+  {"equality_op",		{ EQ, NE }},				\
+  {"cmp_op",			{ EQ, NE, GT, GE, GTU, GEU, LT, LE,	\
+				  LTU, LEU }},				\
+  {"pc_or_label_operand",	{ PC, LABEL_REF }},			\
+  {"call_insn_operand",		{ CONST_INT, CONST, SYMBOL_REF, REG}},	\
+  {"move_operand", 		{ CONST_INT, CONST_DOUBLE, CONST,	\
+				  SYMBOL_REF, LABEL_REF, SUBREG,	\
+				  REG, MEM}},				\
+  {"movdi_operand",		{ CONST_INT, CONST_DOUBLE, CONST,	\
+				  SYMBOL_REF, LABEL_REF, SUBREG, REG,	\
+				  MEM, SIGN_EXTEND }},			\
+  {"se_register_operand",	{ SUBREG, REG, SIGN_EXTEND }},		\
+  {"se_reg_or_0_operand",	{ REG, CONST_INT, CONST_DOUBLE, SUBREG,	\
+				  SIGN_EXTEND }},			\
+  {"se_uns_arith_operand",	{ REG, CONST_INT, SUBREG,		\
+				  SIGN_EXTEND }},			\
+  {"se_arith_operand",		{ REG, CONST_INT, SUBREG,		\
+				  SIGN_EXTEND }},			\
+  {"se_nonmemory_operand",	{ CONST_INT, CONST_DOUBLE, CONST,	\
+				  SYMBOL_REF, LABEL_REF, SUBREG,	\
+				  REG, SIGN_EXTEND }},			\
+  {"se_nonimmediate_operand",   { SUBREG, REG, MEM, SIGN_EXTEND }},	\
+  {"consttable_operand",	{ LABEL_REF, SYMBOL_REF, CONST_INT,	\
+				  CONST_DOUBLE, CONST }},		\
+  {"extend_operator",           { SIGN_EXTEND, ZERO_EXTEND }},          \
+  {"highpart_shift_operator",   { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
+
+
+
+/* If defined, a C statement to be executed just prior to the
+   output of assembler code for INSN, to modify the extracted
+   operands so they will be output differently.
+
+   Here the argument OPVEC is the vector containing the operands
+   extracted from INSN, and NOPERANDS is the number of elements of
+   the vector which contain meaningful data for this insn.  The
+   contents of this vector are what will be used to convert the
+   insn template into assembler code, so you can change the
+   assembler output by changing the contents of the vector.
+
+   We use it to check if the current insn needs a nop in front of it
+   because of load delays, and also to update the delay slot
+   statistics.  */
+
+#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)			\
+  final_prescan_insn (INSN, OPVEC, NOPERANDS)
+
+
+/* Control the assembler format that we output.  */
+
+/* Output at beginning of assembler file.
+   If we are optimizing to use the global pointer, create a temporary
+   file to hold all of the text stuff, and write it out to the end.
+   This is needed because the MIPS assembler is evidently one pass,
+   and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
+   declaration when the code is processed, it generates a two
+   instruction sequence.  */
+
+#define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
+
+/* Output to assembler file text saying following lines
+   may contain character constants, extra white space, comments, etc.  */
+
+#define ASM_APP_ON " #APP\n"
+
+/* Output to assembler file text saying following lines
+   no longer contain unusual constructs.  */
+
+#define ASM_APP_OFF " #NO_APP\n"
+
+/* How to refer to registers in assembler output.
+   This sequence is indexed by compiler's hard-register-number (see above).
+
+   In order to support the two different conventions for register names,
+   we use the name of a table set up in mips.c, which is overwritten
+   if -mrnames is used.  */
+
+#define REGISTER_NAMES							\
+{									\
+  &mips_reg_names[ 0][0],						\
+  &mips_reg_names[ 1][0],						\
+  &mips_reg_names[ 2][0],						\
+  &mips_reg_names[ 3][0],						\
+  &mips_reg_names[ 4][0],						\
+  &mips_reg_names[ 5][0],						\
+  &mips_reg_names[ 6][0],						\
+  &mips_reg_names[ 7][0],						\
+  &mips_reg_names[ 8][0],						\
+  &mips_reg_names[ 9][0],						\
+  &mips_reg_names[10][0],						\
+  &mips_reg_names[11][0],						\
+  &mips_reg_names[12][0],						\
+  &mips_reg_names[13][0],						\
+  &mips_reg_names[14][0],						\
+  &mips_reg_names[15][0],						\
+  &mips_reg_names[16][0],						\
+  &mips_reg_names[17][0],						\
+  &mips_reg_names[18][0],						\
+  &mips_reg_names[19][0],						\
+  &mips_reg_names[20][0],						\
+  &mips_reg_names[21][0],						\
+  &mips_reg_names[22][0],						\
+  &mips_reg_names[23][0],						\
+  &mips_reg_names[24][0],						\
+  &mips_reg_names[25][0],						\
+  &mips_reg_names[26][0],						\
+  &mips_reg_names[27][0],						\
+  &mips_reg_names[28][0],						\
+  &mips_reg_names[29][0],						\
+  &mips_reg_names[30][0],						\
+  &mips_reg_names[31][0],						\
+  &mips_reg_names[32][0],						\
+  &mips_reg_names[33][0],						\
+  &mips_reg_names[34][0],						\
+  &mips_reg_names[35][0],						\
+  &mips_reg_names[36][0],						\
+  &mips_reg_names[37][0],						\
+  &mips_reg_names[38][0],						\
+  &mips_reg_names[39][0],						\
+  &mips_reg_names[40][0],						\
+  &mips_reg_names[41][0],						\
+  &mips_reg_names[42][0],						\
+  &mips_reg_names[43][0],						\
+  &mips_reg_names[44][0],						\
+  &mips_reg_names[45][0],						\
+  &mips_reg_names[46][0],						\
+  &mips_reg_names[47][0],						\
+  &mips_reg_names[48][0],						\
+  &mips_reg_names[49][0],						\
+  &mips_reg_names[50][0],						\
+  &mips_reg_names[51][0],						\
+  &mips_reg_names[52][0],						\
+  &mips_reg_names[53][0],						\
+  &mips_reg_names[54][0],						\
+  &mips_reg_names[55][0],						\
+  &mips_reg_names[56][0],						\
+  &mips_reg_names[57][0],						\
+  &mips_reg_names[58][0],						\
+  &mips_reg_names[59][0],						\
+  &mips_reg_names[60][0],						\
+  &mips_reg_names[61][0],						\
+  &mips_reg_names[62][0],						\
+  &mips_reg_names[63][0],						\
+  &mips_reg_names[64][0],						\
+  &mips_reg_names[65][0],						\
+  &mips_reg_names[66][0],						\
+  &mips_reg_names[67][0],						\
+  &mips_reg_names[68][0],						\
+  &mips_reg_names[69][0],						\
+  &mips_reg_names[70][0],						\
+  &mips_reg_names[71][0],						\
+  &mips_reg_names[72][0],						\
+  &mips_reg_names[73][0],						\
+  &mips_reg_names[74][0],						\
+  &mips_reg_names[75][0],						\
+}
+
+/* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
+   So define this for it.  */
+#define DEBUG_REGISTER_NAMES						\
+{									\
+  "$0",   "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",		\
+  "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",		\
+  "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",		\
+  "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "$fp",   "ra",	\
+  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",	\
+  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",	\
+  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",	\
+  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",	\
+  "hi",   "lo",   "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",	\
+  "$fcc5","$fcc6","$fcc7","$rap"					\
+}
+
+/* If defined, a C initializer for an array of structures
+   containing a name and a register number.  This macro defines
+   additional names for hard registers, thus allowing the `asm'
+   option in declarations to refer to registers using alternate
+   names.
+
+   We define both names for the integer registers here.  */
+
+#define ADDITIONAL_REGISTER_NAMES					\
+{									\
+  { "$0",	 0 + GP_REG_FIRST },					\
+  { "$1",	 1 + GP_REG_FIRST },					\
+  { "$2",	 2 + GP_REG_FIRST },					\
+  { "$3",	 3 + GP_REG_FIRST },					\
+  { "$4",	 4 + GP_REG_FIRST },					\
+  { "$5",	 5 + GP_REG_FIRST },					\
+  { "$6",	 6 + GP_REG_FIRST },					\
+  { "$7",	 7 + GP_REG_FIRST },					\
+  { "$8",	 8 + GP_REG_FIRST },					\
+  { "$9",	 9 + GP_REG_FIRST },					\
+  { "$10",	10 + GP_REG_FIRST },					\
+  { "$11",	11 + GP_REG_FIRST },					\
+  { "$12",	12 + GP_REG_FIRST },					\
+  { "$13",	13 + GP_REG_FIRST },					\
+  { "$14",	14 + GP_REG_FIRST },					\
+  { "$15",	15 + GP_REG_FIRST },					\
+  { "$16",	16 + GP_REG_FIRST },					\
+  { "$17",	17 + GP_REG_FIRST },					\
+  { "$18",	18 + GP_REG_FIRST },					\
+  { "$19",	19 + GP_REG_FIRST },					\
+  { "$20",	20 + GP_REG_FIRST },					\
+  { "$21",	21 + GP_REG_FIRST },					\
+  { "$22",	22 + GP_REG_FIRST },					\
+  { "$23",	23 + GP_REG_FIRST },					\
+  { "$24",	24 + GP_REG_FIRST },					\
+  { "$25",	25 + GP_REG_FIRST },					\
+  { "$26",	26 + GP_REG_FIRST },					\
+  { "$27",	27 + GP_REG_FIRST },					\
+  { "$28",	28 + GP_REG_FIRST },					\
+  { "$29",	29 + GP_REG_FIRST },					\
+  { "$30",	30 + GP_REG_FIRST },					\
+  { "$31",	31 + GP_REG_FIRST },					\
+  { "$sp",	29 + GP_REG_FIRST },					\
+  { "$fp",	30 + GP_REG_FIRST },					\
+  { "at",	 1 + GP_REG_FIRST },					\
+  { "v0",	 2 + GP_REG_FIRST },					\
+  { "v1",	 3 + GP_REG_FIRST },					\
+  { "a0",	 4 + GP_REG_FIRST },					\
+  { "a1",	 5 + GP_REG_FIRST },					\
+  { "a2",	 6 + GP_REG_FIRST },					\
+  { "a3",	 7 + GP_REG_FIRST },					\
+  { "t0",	 8 + GP_REG_FIRST },					\
+  { "t1",	 9 + GP_REG_FIRST },					\
+  { "t2",	10 + GP_REG_FIRST },					\
+  { "t3",	11 + GP_REG_FIRST },					\
+  { "t4",	12 + GP_REG_FIRST },					\
+  { "t5",	13 + GP_REG_FIRST },					\
+  { "t6",	14 + GP_REG_FIRST },					\
+  { "t7",	15 + GP_REG_FIRST },					\
+  { "s0",	16 + GP_REG_FIRST },					\
+  { "s1",	17 + GP_REG_FIRST },					\
+  { "s2",	18 + GP_REG_FIRST },					\
+  { "s3",	19 + GP_REG_FIRST },					\
+  { "s4",	20 + GP_REG_FIRST },					\
+  { "s5",	21 + GP_REG_FIRST },					\
+  { "s6",	22 + GP_REG_FIRST },					\
+  { "s7",	23 + GP_REG_FIRST },					\
+  { "t8",	24 + GP_REG_FIRST },					\
+  { "t9",	25 + GP_REG_FIRST },					\
+  { "k0",	26 + GP_REG_FIRST },					\
+  { "k1",	27 + GP_REG_FIRST },					\
+  { "gp",	28 + GP_REG_FIRST },					\
+  { "sp",	29 + GP_REG_FIRST },					\
+  { "fp",	30 + GP_REG_FIRST },					\
+  { "ra",	31 + GP_REG_FIRST },					\
+  { "$sp",	29 + GP_REG_FIRST },					\
+  { "$fp",	30 + GP_REG_FIRST }					\
+}
+
+/* Define results of standard character escape sequences.  */
+#define TARGET_BELL	007
+#define TARGET_BS	010
+#define TARGET_TAB	011
+#define TARGET_NEWLINE	012
+#define TARGET_VT	013
+#define TARGET_FF	014
+#define TARGET_CR	015
+
+/* A C compound statement to output to stdio stream STREAM the
+   assembler syntax for an instruction operand X.  X is an RTL
+   expression.
+
+   CODE is a value that can be used to specify one of several ways
+   of printing the operand.  It is used when identical operands
+   must be printed differently depending on the context.  CODE
+   comes from the `%' specification that was used to request
+   printing of the operand.  If the specification was just `%DIGIT'
+   then CODE is 0; if the specification was `%LTR DIGIT' then CODE
+   is the ASCII code for LTR.
+
+   If X is a register, this macro should print the register's name.
+   The names can be found in an array `reg_names' whose type is
+   `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
+
+   When the machine description has a specification `%PUNCT' (a `%'
+   followed by a punctuation character), this macro is called with
+   a null pointer for X and the punctuation character for CODE.
+
+   See mips.c for the MIPS specific codes.  */
+
+#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
+
+/* A C expression which evaluates to true if CODE is a valid
+   punctuation character for use in the `PRINT_OPERAND' macro.  If
+   `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
+   punctuation characters (except for the standard one, `%') are
+   used in this way.  */
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
+
+/* A C compound statement to output to stdio stream STREAM the
+   assembler syntax for an instruction operand that is a memory
+   reference whose address is ADDR.  ADDR is an RTL expression.
+
+   On some machines, the syntax for a symbolic address depends on
+   the section that the address refers to.  On these machines,
+   define the macro `ENCODE_SECTION_INFO' to store the information
+   into the `symbol_ref', and then check for it here.  */
+
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
+
+
+/* A C statement, to be executed after all slot-filler instructions
+   have been output.  If necessary, call `dbr_sequence_length' to
+   determine the number of slots filled in a sequence (zero if not
+   currently outputting a sequence), to decide how many no-ops to
+   output, or whatever.
+
+   Don't define this macro if it has nothing to do, but it is
+   helpful in reading assembly output if the extent of the delay
+   sequence is made explicit (e.g. with white space).
+
+   Note that output routines for instructions with delay slots must
+   be prepared to deal with not being output as part of a sequence
+   (i.e.  when the scheduling pass is not run, or when no slot
+   fillers could be found.)  The variable `final_sequence' is null
+   when not processing a sequence, otherwise it contains the
+   `sequence' rtx being output.  */
+
+#define DBR_OUTPUT_SEQEND(STREAM)					\
+do									\
+  {									\
+    if (set_nomacro > 0 && --set_nomacro == 0)				\
+      fputs ("\t.set\tmacro\n", STREAM);				\
+									\
+    if (set_noreorder > 0 && --set_noreorder == 0)			\
+      fputs ("\t.set\treorder\n", STREAM);				\
+									\
+    dslots_jump_filled++;						\
+    fputs ("\n", STREAM);						\
+  }									\
+while (0)
+
+
+/* How to tell the debugger about changes of source files.  Note, the
+   mips ECOFF format cannot deal with changes of files inside of
+   functions, which means the output of parser generators like bison
+   is generally not debuggable without using the -l switch.  Lose,
+   lose, lose.  Silicon graphics seems to want all .file's hardwired
+   to 1.  */
+
+#ifndef SET_FILE_NUMBER
+#define SET_FILE_NUMBER() ++num_source_filenames
+#endif
+
+#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME)			\
+  mips_output_filename (STREAM, NAME)
+
+/* This is defined so that it can be overridden in iris6.h.  */
+#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
+do								\
+  {								\
+    fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES);	\
+    output_quoted_string (STREAM, NAME);			\
+    fputs ("\n", STREAM);					\
+  }								\
+while (0)
+
+/* This is how to output a note the debugger telling it the line number
+   to which the following sequence of instructions corresponds.
+   Silicon graphics puts a label after each .loc.  */
+
+#ifndef LABEL_AFTER_LOC
+#define LABEL_AFTER_LOC(STREAM)
+#endif
+
+#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE)				\
+  mips_output_lineno (STREAM, LINE)
+
+/* The MIPS implementation uses some labels for its own purpose.  The
+   following lists what labels are created, and are all formed by the
+   pattern $L[a-z].*.  The machine independent portion of GCC creates
+   labels matching:  $L[A-Z][0-9]+ and $L[0-9]+.
+
+	LM[0-9]+	Silicon Graphics/ECOFF stabs label before each stmt.
+	$Lb[0-9]+	Begin blocks for MIPS debug support
+	$Lc[0-9]+	Label for use in s<xx> operation.
+	$Le[0-9]+	End blocks for MIPS debug support
+	$Lp\..+		Half-pic labels. */
+
+/* This is how to output the definition of a user-level label named NAME,
+   such as the label on a static function or variable NAME.
+
+   If we are optimizing the gp, remember that this label has been put
+   out, so we know not to emit an .extern for it in mips_asm_file_end.
+   We use one of the common bits in the IDENTIFIER tree node for this,
+   since those bits seem to be unused, and we don't have any method
+   of getting the decl nodes from the name.  */
+
+#define ASM_OUTPUT_LABEL(STREAM,NAME)					\
+do {									\
+  assemble_name (STREAM, NAME);						\
+  fputs (":\n", STREAM);						\
+} while (0)
+
+
+/* A C statement (sans semicolon) to output to the stdio stream
+   STREAM any text necessary for declaring the name NAME of an
+   initialized variable which is being defined.  This macro must
+   output the label definition (perhaps using `ASM_OUTPUT_LABEL'). 
+   The argument DECL is the `VAR_DECL' tree node representing the
+   variable.
+
+   If this macro is not defined, then the variable name is defined
+   in the usual manner as a label (by means of `ASM_OUTPUT_LABEL').  */
+
+#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL)			\
+do									\
+ {									\
+   mips_declare_object (STREAM, NAME, "", ":\n", 0);			\
+   HALF_PIC_DECLARE (NAME);						\
+ }									\
+while (0)
+
+
+/* This is how to output a command to make the user-level label named NAME
+   defined for reference from other files.  */
+
+#define ASM_GLOBALIZE_LABEL(STREAM,NAME)				\
+  do {									\
+    fputs ("\t.globl\t", STREAM);					\
+    assemble_name (STREAM, NAME);					\
+    fputs ("\n", STREAM);						\
+  } while (0)
+
+/* This says how to define a global common symbol.  */
+
+#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED)			\
+  mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
+
+/* This says how to define a local common symbol (ie, not visible to
+   linker).  */
+
+#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED)			\
+  mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
+
+
+/* This says how to output an external.  It would be possible not to
+   output anything and let undefined symbol become external. However
+   the assembler uses length information on externals to allocate in
+   data/sdata bss/sbss, thereby saving exec time.  */
+
+#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
+  mips_output_external(STREAM,DECL,NAME)
+
+/* This says what to print at the end of the assembly file */
+#define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
+
+
+/* This is how to declare a function name.  The actual work of
+   emitting the label is moved to function_prologue, so that we can
+   get the line number correctly emitted before the .ent directive,
+   and after any .file directives.
+
+   Also, switch files if we are optimizing the global pointer.  */
+
+#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)			\
+{									\
+  extern FILE *asm_out_text_file;					\
+  if (TARGET_GP_OPT && ! TARGET_MIPS16)					\
+    {									\
+      STREAM = asm_out_text_file;					\
+      /* ??? text_section gets called too soon.  If the previous	\
+	 function is in a special section and we're not, we have	\
+	 to switch back to the text section.  We can't call		\
+	 text_section again as gcc thinks we're already there.  */	\
+      /* ??? See varasm.c.  There are other things that get output	\
+	 too early, like alignment (before we've switched STREAM).  */	\
+      if (DECL_SECTION_NAME (DECL) == NULL_TREE)			\
+	fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP);			\
+    }									\
+									\
+  HALF_PIC_DECLARE (NAME);						\
+}
+
+/* This is how to output an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.  */
+
+#define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM)			\
+  fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
+
+/* This is how to store into the string LABEL
+   the symbol_ref name of an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.
+   This is suitable for output with `assemble_name'.  */
+
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)			\
+  sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
+
+/* This is how to output an assembler line defining a `double' constant.  */
+
+#define ASM_OUTPUT_DOUBLE(STREAM,VALUE)					\
+  mips_output_double (STREAM, VALUE)
+
+
+/* This is how to output an assembler line defining a `float' constant.  */
+
+#define ASM_OUTPUT_FLOAT(STREAM,VALUE)					\
+  mips_output_float (STREAM, VALUE)
+
+
+/* This is how to output an assembler line defining an `int' constant.  */
+
+#define ASM_OUTPUT_INT(STREAM,VALUE)					\
+do {									\
+  fprintf (STREAM, "\t.word\t");					\
+  output_addr_const (STREAM, (VALUE));					\
+  fprintf (STREAM, "\n");						\
+} while (0)
+
+/* Likewise for 64 bit, `char' and `short' constants.  */
+
+#define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE)				\
+do {									\
+  if (TARGET_64BIT)							\
+    {									\
+      fprintf (STREAM, "\t.dword\t");					\
+      if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT)	\
+	/* We can't use 'X' for negative numbers, because then we won't	\
+	   get the right value for the upper 32 bits.  */		\
+        output_addr_const (STREAM, VALUE);				\
+      else								\
+	/* We must use 'X', because otherwise LONG_MIN will print as	\
+	   a number that the Irix 6 assembler won't accept.  */		\
+        print_operand (STREAM, VALUE, 'X');				\
+      fprintf (STREAM, "\n");						\
+    }									\
+  else									\
+    {									\
+      assemble_integer (operand_subword ((VALUE), 0, 0, DImode),	\
+			UNITS_PER_WORD, 1);				\
+      assemble_integer (operand_subword ((VALUE), 1, 0, DImode),	\
+			UNITS_PER_WORD, 1);				\
+    }									\
+} while (0)
+
+#define ASM_OUTPUT_SHORT(STREAM,VALUE)					\
+{									\
+  fprintf (STREAM, "\t.half\t");					\
+  output_addr_const (STREAM, (VALUE));					\
+  fprintf (STREAM, "\n");						\
+}
+
+#define ASM_OUTPUT_CHAR(STREAM,VALUE)					\
+{									\
+  fprintf (STREAM, "\t.byte\t");					\
+  output_addr_const (STREAM, (VALUE));					\
+  fprintf (STREAM, "\n");						\
+}
+
+/* This is how to output an assembler line for a numeric constant byte.  */
+
+#define ASM_OUTPUT_BYTE(STREAM,VALUE)					\
+  fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
+
+/* This is how to output an element of a case-vector that is absolute.  */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)				\
+  fprintf (STREAM, "\t%s\t%sL%d\n",					\
+	   Pmode == DImode ? ".dword" : ".word",			\
+	   LOCAL_LABEL_PREFIX,						\
+	   VALUE)
+
+/* This is how to output an element of a case-vector that is relative.
+   This is used for pc-relative code (e.g. when TARGET_ABICALLS or
+   TARGET_EMBEDDED_PIC).  */
+
+#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)		\
+do {									\
+  if (TARGET_MIPS16)							\
+    fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n",				\
+	     LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL);	\
+  else if (TARGET_EMBEDDED_PIC)						\
+    fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n",				\
+	     Pmode == DImode ? ".dword" : ".word",			\
+	     LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL);	\
+  else if (mips_abi == ABI_32 || mips_abi == ABI_O64)			\
+    fprintf (STREAM, "\t%s\t%sL%d\n",					\
+	     Pmode == DImode ? ".gpdword" : ".gpword",			\
+	     LOCAL_LABEL_PREFIX, VALUE);				\
+  else									\
+    fprintf (STREAM, "\t%s\t%sL%d\n",					\
+	     Pmode == DImode ? ".dword" : ".word",			\
+	     LOCAL_LABEL_PREFIX, VALUE);				\
+} while (0)
+
+/* When generating embedded PIC or mips16 code we want to put the jump
+   table in the .text section.  In all other cases, we want to put the
+   jump table in the .rdata section.  Unfortunately, we can't use
+   JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
+   Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
+   section if appropriate.  */
+#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN)			\
+do {									\
+  if (TARGET_EMBEDDED_PIC || TARGET_MIPS16)				\
+    function_section (current_function_decl);				\
+  ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM);			\
+} while (0)
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+
+#define ASM_OUTPUT_ALIGN(STREAM,LOG)					\
+  fprintf (STREAM, "\t.align\t%d\n", (LOG))
+
+/* CYGNUS LOCAL law */
+#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
+#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
+  if ((LOG)!=0) \
+    if ((MAX_SKIP)==0) fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
+    else fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP))
+#endif
+/* END CYGNUS LOCAL */
+
+
+/* This is how to output an assembler line to advance the location
+   counter by SIZE bytes.  */
+
+#define ASM_OUTPUT_SKIP(STREAM,SIZE)					\
+  fprintf (STREAM, "\t.space\t%u\n", (SIZE))
+
+/* This is how to output a string.  */
+#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN)				\
+do {									\
+  register int i, c, len = (LEN), cur_pos = 17;				\
+  register unsigned char *string = (unsigned char *)(STRING);		\
+  fprintf ((STREAM), "\t.ascii\t\"");					\
+  for (i = 0; i < len; i++)						\
+    {									\
+      register int c = string[i];					\
+									\
+      switch (c)							\
+	{								\
+	case '\"':							\
+	case '\\':							\
+	  putc ('\\', (STREAM));					\
+	  putc (c, (STREAM));						\
+	  cur_pos += 2;							\
+	  break;							\
+									\
+	case TARGET_NEWLINE:						\
+	  fputs ("\\n", (STREAM));					\
+	  if (i+1 < len							\
+	      && (((c = string[i+1]) >= '\040' && c <= '~')		\
+		  || c == TARGET_TAB))					\
+	    cur_pos = 32767;		/* break right here */		\
+	  else								\
+	    cur_pos += 2;						\
+	  break;							\
+									\
+	case TARGET_TAB:						\
+	  fputs ("\\t", (STREAM));					\
+	  cur_pos += 2;							\
+	  break;							\
+									\
+	case TARGET_FF:							\
+	  fputs ("\\f", (STREAM));					\
+	  cur_pos += 2;							\
+	  break;							\
+									\
+	case TARGET_BS:							\
+	  fputs ("\\b", (STREAM));					\
+	  cur_pos += 2;							\
+	  break;							\
+									\
+	case TARGET_CR:							\
+	  fputs ("\\r", (STREAM));					\
+	  cur_pos += 2;							\
+	  break;							\
+									\
+	default:							\
+	  if (c >= ' ' && c < 0177)					\
+	    {								\
+	      putc (c, (STREAM));					\
+	      cur_pos++;						\
+	    }								\
+	  else								\
+	    {								\
+	      fprintf ((STREAM), "\\%03o", c);				\
+	      cur_pos += 4;						\
+	    }								\
+	}								\
+									\
+      if (cur_pos > 72 && i+1 < len)					\
+	{								\
+	  cur_pos = 17;							\
+	  fprintf ((STREAM), "\"\n\t.ascii\t\"");			\
+	}								\
+    }									\
+  fprintf ((STREAM), "\"\n");						\
+} while (0)
+
+/* Handle certain cpp directives used in header files on sysV.  */
+#define SCCS_DIRECTIVE
+
+/* Output #ident as a in the read-only data section.  */
+#define ASM_OUTPUT_IDENT(FILE, STRING)					\
+{									\
+  char *p = STRING;							\
+  int size = strlen (p) + 1;						\
+  rdata_section ();							\
+  assemble_string (p, size);						\
+}
+
+/* Default to -G 8 */
+#ifndef MIPS_DEFAULT_GVALUE
+#define MIPS_DEFAULT_GVALUE 8
+#endif
+
+/* Define the strings to put out for each section in the object file.  */
+#define TEXT_SECTION_ASM_OP	"\t.text"	/* instructions */
+#define DATA_SECTION_ASM_OP	"\t.data"	/* large data */
+#define SDATA_SECTION_ASM_OP	"\t.sdata"	/* small data */
+#define RDATA_SECTION_ASM_OP	"\t.rdata"	/* read-only data */
+#define READONLY_DATA_SECTION	rdata_section
+#define SMALL_DATA_SECTION	sdata_section
+
+/* What other sections we support other than the normal .data/.text.  */
+
+#define EXTRA_SECTIONS in_sdata, in_rdata
+
+/* Define the additional functions to select our additional sections.  */
+
+/* on the MIPS it is not a good idea to put constants in the text
+   section, since this defeats the sdata/data mechanism. This is
+   especially true when -O is used. In this case an effort is made to
+   address with faster (gp) register relative addressing, which can
+   only get at sdata and sbss items (there is no stext !!)  However,
+   if the constant is too large for sdata, and it's readonly, it
+   will go into the .rdata section. */
+
+#define EXTRA_SECTION_FUNCTIONS						\
+void									\
+sdata_section ()							\
+{									\
+  if (in_section != in_sdata)						\
+    {									\
+      fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);		\
+      in_section = in_sdata;						\
+    }									\
+}									\
+									\
+void									\
+rdata_section ()							\
+{									\
+  if (in_section != in_rdata)						\
+    {									\
+      fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP);		\
+      in_section = in_rdata;						\
+    }									\
+}
+
+/* Given a decl node or constant node, choose the section to output it in
+   and select that section.  */
+
+#define SELECT_RTX_SECTION(MODE,RTX)	mips_select_rtx_section (MODE, RTX)
+
+#define SELECT_SECTION(DECL, RELOC)	mips_select_section (DECL, RELOC)
+
+
+/* Store in OUTPUT a string (made with alloca) containing
+   an assembler-name for a local static variable named NAME.
+   LABELNO is an integer which is different for each call.  */
+
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)			\
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),			\
+  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
+
+#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)				\
+do									\
+  {									\
+    fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n",			\
+	     TARGET_64BIT ? "dsubu" : "subu",				\
+	     reg_names[STACK_POINTER_REGNUM],				\
+	     reg_names[STACK_POINTER_REGNUM],				\
+	     TARGET_64BIT ? "sd" : "sw",				\
+	     reg_names[REGNO],						\
+	     reg_names[STACK_POINTER_REGNUM]);				\
+  }									\
+while (0)
+
+#define ASM_OUTPUT_REG_POP(STREAM,REGNO)				\
+do									\
+  {									\
+    if (! set_noreorder)						\
+      fprintf (STREAM, "\t.set\tnoreorder\n");				\
+									\
+    dslots_load_total++;						\
+    dslots_load_filled++;						\
+    fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n",			\
+	     TARGET_64BIT ? "ld" : "lw",				\
+	     reg_names[REGNO],						\
+	     reg_names[STACK_POINTER_REGNUM],				\
+	     TARGET_64BIT ? "daddu" : "addu",				\
+	     reg_names[STACK_POINTER_REGNUM],				\
+	     reg_names[STACK_POINTER_REGNUM]);				\
+									\
+    if (! set_noreorder)						\
+      fprintf (STREAM, "\t.set\treorder\n");				\
+  }									\
+while (0)
+
+/* Define the parentheses used to group arithmetic operations
+   in assembler code.  */
+
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* How to start an assembler comment.
+   The leading space is important (the mips native assembler requires it).  */
+#ifndef ASM_COMMENT_START
+#define ASM_COMMENT_START " #"
+#endif
+
+
+/* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
+   and mips-tdump.c to print them out.
+
+   These must match the corresponding definitions in gdb/mipsread.c.
+   Unfortunately, gcc and gdb do not currently share any directories. */
+
+#define CODE_MASK 0x8F300
+#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
+#define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
+#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
+
+
+/* Default definitions for size_t and ptrdiff_t.  */
+
+#ifndef SIZE_TYPE
+#define NO_BUILTIN_SIZE_TYPE
+#define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
+#endif
+
+#ifndef PTRDIFF_TYPE
+#define NO_BUILTIN_PTRDIFF_TYPE
+#define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
+#endif
+
+/* See mips_expand_prologue's use of loadgp for when this should be
+   true.  */
+
+#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS 		\
+					 && mips_abi != ABI_32		\
+					 && mips_abi != ABI_O64)
+
+/* In mips16 mode, we need to look through the function to check for
+   PC relative loads that are out of range.  */
+#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
+
+/* We need to use a special set of functions to handle hard floating
+   point code in mips16 mode.  */
+
+#ifndef INIT_SUBTARGET_OPTABS
+#define INIT_SUBTARGET_OPTABS
+#endif
+
+#define INIT_TARGET_OPTABS						\
+do									\
+  {									\
+    if (! TARGET_MIPS16 || ! mips16_hard_float)				\
+      INIT_SUBTARGET_OPTABS;						\
+    else								\
+      {									\
+	add_optab->handlers[(int) SFmode].libfunc =			\
+	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3");		\
+	sub_optab->handlers[(int) SFmode].libfunc =			\
+	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3");		\
+	smul_optab->handlers[(int) SFmode].libfunc =			\
+	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3");		\
+	flodiv_optab->handlers[(int) SFmode].libfunc =			\
+	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3");		\
+									\
+	eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2");	\
+	nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2");	\
+	gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2");	\
+	gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2");	\
+	ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2");	\
+	lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2");	\
+									\
+	floatsisf_libfunc =						\
+	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf");		\
+	fixsfsi_libfunc =						\
+	  gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi");		\
+									\
+	if (TARGET_DOUBLE_FLOAT)					\
+	  {								\
+	    add_optab->handlers[(int) DFmode].libfunc =			\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3");		\
+	    sub_optab->handlers[(int) DFmode].libfunc =			\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3");		\
+	    smul_optab->handlers[(int) DFmode].libfunc =		\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3");		\
+	    flodiv_optab->handlers[(int) DFmode].libfunc =		\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3");		\
+									\
+	    extendsfdf2_libfunc =					\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2");	\
+	    truncdfsf2_libfunc =					\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2");	\
+									\
+	    eqdf2_libfunc =						\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2");		\
+	    nedf2_libfunc =						\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2");		\
+	    gtdf2_libfunc =						\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2");		\
+	    gedf2_libfunc =						\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2");		\
+	    ltdf2_libfunc =						\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2");		\
+	    ledf2_libfunc =						\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2");		\
+									\
+	    floatsidf_libfunc =						\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf");	\
+	    fixdfsi_libfunc =						\
+	      gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi");		\
+	  }								\
+      }									\
+  }									\
+while (0)
+
+
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
new file mode 100755
index 0000000..7e18299
--- /dev/null
+++ b/gcc/config/mips/mips.md
@@ -0,0 +1,10710 @@
+;;  Mips.md	     Machine Description for MIPS based processors
+;;  Contributed by   A. Lichnewsky, lich@inria.inria.fr
+;;  Changes by       Michael Meissner, meissner@osf.org
+;;  64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+;;  Brendan Eich, brendan@microunity.com.
+;;  Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; ??? Currently does not have define_function_unit support for the R8000.
+;; Must include new entries for fmadd in addition to existing entries.
+
+
+
+;; ....................
+;;	Attributes
+;; ....................
+
+;; Classification of each insn.
+;; branch	conditional branch
+;; jump		unconditional jump
+;; call		unconditional call
+;; load		load instruction(s)
+;; store	store instruction(s)
+;; move		data movement within same register set
+;; xfer		transfer to/from coprocessor
+;; hilo		transfer of hi/lo registers
+;; arith	integer arithmetic instruction
+;; darith	double precision integer arithmetic instructions
+;; imul		integer multiply
+;; idiv		integer divide
+;; icmp		integer compare
+;; fadd		floating point add/subtract
+;; fmul		floating point multiply
+;; fmadd	floating point multiply-add
+;; fdiv		floating point divide
+;; fabs		floating point absolute value
+;; fneg		floating point negation
+;; fcmp		floating point compare
+;; fcvt		floating point convert
+;; fsqrt	floating point square root
+;; frsqrt	floating point reciprocal square root CYGNUS LOCAL vr5400/raeburn
+;; multi	multiword sequence (or user asm statements)
+;; nop		no operation
+
+(define_attr "type"
+  "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop" ; CYGNUS LOCAL vr5400/raeburn
+  (const_string "unknown"))
+
+;; Main data type used by the insn
+(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
+
+;; # instructions (4 bytes each)
+(define_attr "length" "" (const_int 1))
+
+;; Attribute describing the processor.  This attribute must match exactly
+;; with the processor_type enumeration in mips.h.
+
+;; Attribute describing the processor
+;; (define_attr "cpu" "default,r3000,r6000,r4000"
+;;   (const
+;;    (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000"))   (const_string "r3000")
+;;           (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000"))   (const_string "r4000")
+;;           (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000"))   (const_string "r6000")]
+;;          (const_string "default"))))
+
+;; ??? Fix everything that tests this attribute.
+(define_attr "cpu"
+  "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r5400,r8000" ;   CYGNUS LOCAL vr5400/raeburn
+  (const (symbol_ref "mips_cpu_attr")))
+
+;; Does the instruction have a mandatory delay slot?
+;;   The 3900, is (mostly) mips1, but does not have a manditory load delay
+;;   slot. 
+(define_attr "dslot" "no,yes"
+  (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp")
+		     (and (eq_attr "type" "load")
+			  (and (eq (symbol_ref "mips_isa") (const_int 1))
+			       (and (eq (symbol_ref "mips16") (const_int 0))
+                                    (eq_attr "cpu" "!r3900")))))
+		(const_string "yes")
+		(const_string "no")))
+
+;; Attribute defining whether or not we can use the branch-likely instructions
+
+(define_attr "branch_likely" "no,yes"
+  (const
+   (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
+		 (const_string "yes")
+		 (const_string "no"))))
+
+
+;; Describe a user's asm statement.
+(define_asm_attributes
+  [(set_attr "type" "multi")])
+
+;; whether or not generating calls to position independent functions
+(define_attr "abicalls" "no,yes"
+  (const (symbol_ref "mips_abicalls_attr")))
+
+
+
+;; .........................
+;;	Delay slots, can't describe load/fcmp/xfer delay slots here
+;; .........................
+
+(define_delay (and (eq_attr "type" "branch")
+		   (eq (symbol_ref "mips16") (const_int 0)))
+  [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
+   (nil)
+   (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "1")))])
+
+(define_delay (eq_attr "type" "jump")
+  [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
+   (nil)
+   (nil)])
+
+(define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no"))
+  [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
+   (nil)
+   (nil)])
+
+
+
+;; .........................
+;;	Functional units
+;; .........................
+
+; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
+;			TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
+
+;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
+
+(define_function_unit "memory" 1 0
+  (and (eq_attr "type" "load")
+       (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
+  3 0)
+
+(define_function_unit "memory" 1 0
+  (and (eq_attr "type" "load")
+       (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000,r5400")) ;  CYGNUS LOCAL vr5400/raeburn
+  2 0)
+
+;; CYGNUS LOCAL law
+(define_function_unit "memory"   1 0
+  (and (eq_attr "type" "store") (const_int 1)) 1 0) ; 
+
+(define_function_unit "memory"   1 0
+  (and (eq_attr "type" "xfer") (const_int 1)) 2 0) ; 
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "hilo")
+       (const_int 1)) ; 
+  1 3)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "imul")
+       (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
+  17 17)
+;; END CYGNUS LOCAL
+
+;; On them mips16, we want to stronly discourage a mult from appearing
+;; after an mflo, since that requires explicit nop instructions.  We
+;; do this by pretending that mflo ties up the function unit for long
+;; enough that the scheduler will ignore load stalls and the like when
+;; selecting instructions to between the two instructions.
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "hilo") (ne (symbol_ref "mips16") (const_int 0)))
+  1 5)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000,r3900"))
+  12 12)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000,r4600"))
+  10 10)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650"))
+  4 4)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "imul")
+       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
+  1 1)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "imul")
+       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
+  4 4)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "imul")
+       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000"))) ; 
+  5 5)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "imul")
+       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300"))) ; 
+  8 8)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "imul")
+       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
+  9 9)
+
+;; CYGNUS LOCAL vr5400/raeburn
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "imul")
+       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5400")))
+  3 1)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "imul")
+       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5400")))
+  4 2)
+;; END CYGNUS LOCAL
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "idiv")
+       (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
+  38 38)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900"))
+  35 35)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
+  42 42)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
+  36 36)
+
+(define_function_unit "imuldiv"  1 0
+  (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
+  69 69)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
+  35 35)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
+  67 67)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300"))) ; 
+  37 37)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300"))) ; 
+  69 69)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
+  36 36)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
+  68 68)
+
+;; CYGNUS LOCAL vr5400/raeburn
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5400")))
+  34 34)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "idiv")
+       (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5400")))
+  66 66)
+;; END CYGNUS LOCAL
+
+;; The R4300 does *NOT* have a separate Floating Point Unit, instead
+;; the FP hardware is part of the normal ALU circuitry.  This means FP
+;; instructions affect the pipe-line, and no functional unit
+;; parallelism can occur on R4300 processors.  To force GCC into coding
+;; for only a single functional unit, we force the R4300 FP
+;; instructions to be processed in the "imuldiv" unit.
+
+(define_function_unit "adder" 1 1
+  (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
+  3 0)
+
+(define_function_unit "adder" 1 1
+  (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
+  2 0)
+
+(define_function_unit "adder" 1 1
+  (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
+  1 0)
+
+(define_function_unit "adder" 1 1
+  (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
+  4 0)
+
+(define_function_unit "adder" 1 1
+  (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900"))
+  2 0)
+
+(define_function_unit "adder" 1 1
+  (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
+  3 0)
+
+(define_function_unit "adder" 1 1
+  (and (eq_attr "type" "fabs,fneg")
+       (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000,r5400")) ;   CYGNUS LOCAL vr5400/raeburn
+  2 0)
+
+(define_function_unit "adder" 1 1
+  (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
+  1 0)
+
+(define_function_unit "mult" 1 1
+  (and (eq_attr "type" "fmul")
+       (and (eq_attr "mode" "SF")
+	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000,r5400"))) ;   CYGNUS LOCAL vr5400/raeburn
+  7 0)
+
+(define_function_unit "mult" 1 1
+  (and (eq_attr "type" "fmul")
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000")))
+  4 0)
+
+(define_function_unit "mult" 1 1
+  (and (eq_attr "type" "fmul")
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
+  5 0)
+
+(define_function_unit "mult" 1 1
+  (and (eq_attr "type" "fmul")
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
+  8 0)
+
+(define_function_unit "mult" 1 1
+  (and (eq_attr "type" "fmul")
+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000,r5400"))) ;  CYGNUS LOCAL vr5400/raeburn
+  8 0)
+
+(define_function_unit "mult" 1 1
+  (and (eq_attr "type" "fmul")
+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000")))
+  5 0)
+
+(define_function_unit "mult" 1 1
+  (and (eq_attr "type" "fmul")
+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
+  6 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fdiv")
+       (and (eq_attr "mode" "SF")
+	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000,r5400"))) ;   CYGNUS LOCAL vr5400/raeburn
+  23 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fdiv")
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900")))
+  12 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fdiv")
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
+  15 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fdiv")
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
+  32 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fdiv")
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
+  21 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fdiv")
+       (and (eq_attr "mode" "DF")
+	    (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5400"))) ;  CYGNUS LOCAL vr5400/raeburn
+  36 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fdiv")
+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900")))
+  19 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fdiv")
+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
+  16 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fdiv")
+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
+  61 0)
+
+;;; ??? Is this number right?
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000,r5400"))) ;   CYGNUS LOCAL vr5400/raeburn
+  54 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
+  31 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
+  21 0)
+
+;;; ??? Is this number right?
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000,r5400"))) ;  CYGNUS LOCAL vr5400/raeburn
+  112 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
+  60 0)
+
+(define_function_unit "divide" 1 1
+  (and (eq_attr "type" "fsqrt,frsqrt") ; CYGNUS LOCAL vr5400/raeburn
+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
+  36 0)
+
+;; R4300 FP instruction classes treated as part of the "imuldiv"
+;; functional unit:
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300")) ; 
+  3 3)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300")) ; 
+  1 1)
+
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300"))) ; 
+  5 5)
+(define_function_unit "imuldiv" 1 0
+  (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300"))) ; 
+  8 8)
+
+(define_function_unit "imuldiv" 1 0
+  (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt")) ; CYGNUS LOCAL vr5400/raeburn
+       (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300"))) ; 
+  29 29)
+(define_function_unit "imuldiv" 1 0
+  (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt")) ; CYGNUS LOCAL vr5400/raeburn
+       (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300"))) ;  
+  58 58)
+
+;; CYGNUS LOCAL vr5400/raeburn
+(define_function_unit "alu_5400" 2 0
+  (and (eq_attr "type" "move,arith,darith,icmp,nop")
+       (eq_attr "cpu" "r5400"))
+  1 0)
+
+(define_function_unit "alu_5400" 2 0
+  (and (eq_attr "type" "fadd")
+       (eq_attr "cpu" "r5400"))
+  4 3)
+
+(define_function_unit "alu_5400" 2 0
+  (and (eq_attr "type" "fcmp,fabs,fneg")
+       (eq_attr "cpu" "r5400"))
+  2 1)
+
+(define_function_unit "alu_5400" 2 0
+  (and (and (eq_attr "type" "fmul")
+	    (eq_attr "mode" "SF"))
+       (eq_attr "cpu" "r5400"))
+  5 4)
+
+(define_function_unit "alu_5400" 2 0
+  (and (and (eq_attr "type" "fmul")
+	    (eq_attr "mode" "DF"))
+       (eq_attr "cpu" "r5400"))
+  6 5)
+
+(define_function_unit "alu_5400" 2 0
+  (and (and (eq_attr "type" "fdiv,fsqrt")
+	    (eq_attr "mode" "SF"))
+       (eq_attr "cpu" "r5400"))
+  31 30)
+
+(define_function_unit "alu_5400" 2 0
+  (and (and (eq_attr "type" "fdiv,fsqrt")
+	    (eq_attr "mode" "DF"))
+       (eq_attr "cpu" "r5400"))
+  59 58)
+
+(define_function_unit "alu_5400" 2 0
+  (and (and (eq_attr "type" "frsqrt")
+	    (eq_attr "mode" "SF"))
+       (eq_attr "cpu" "r5400"))
+  61 60)
+
+(define_function_unit "alu_5400" 2 0
+  (and (and (eq_attr "type" "frsqrt")
+	    (eq_attr "mode" "DF"))
+       (eq_attr "cpu" "r5400"))
+  121 120)
+
+(define_function_unit "alu_5400" 2 0
+  (and (and (eq_attr "type" "fmadd")
+	    (eq_attr "mode" "SF"))
+       (eq_attr "cpu" "r5400"))
+  9 8)
+
+(define_function_unit "alu_5400" 2 0
+  (and (and (eq_attr "type" "fmadd")
+	    (eq_attr "mode" "DF"))
+       (eq_attr "cpu" "r5400"))
+  10 9)
+
+(define_function_unit "alu_5400" 2 0
+  (and (eq_attr "type" "fcvt")
+       (eq_attr "cpu" "r5400"))
+  6 5)
+;; END CYGNUS LOCAL
+
+
+
+;; The following functional units do not use the cpu type, and use
+;; much less memory in genattrtab.c.
+
+;; (define_function_unit "memory"   1 0 (eq_attr "type" "load")                                3 0)
+;; (define_function_unit "memory"   1 0 (eq_attr "type" "store")                               1 0)
+;; (define_function_unit "fp_comp"  1 0 (eq_attr "type" "fcmp")                                2 0)
+;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer")                                2 0)
+;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo")                                3 0)
+;; (define_function_unit "imuldiv"  1 1 (eq_attr "type" "imul")                               17 0)
+;; (define_function_unit "imuldiv"  1 1 (eq_attr "type" "idiv")                               38 0)
+;; (define_function_unit "adder"    1 1 (eq_attr "type" "fadd")                                4 0)
+;; (define_function_unit "adder"    1 1 (eq_attr "type" "fabs,fneg")                           2 0)
+;; (define_function_unit "mult"     1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF"))    7 0)
+;; (define_function_unit "mult"     1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF"))    8 0)
+;; (define_function_unit "divide"   1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF"))   23 0)
+;; (define_function_unit "divide"   1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF"))   36 0)
+;; (define_function_unit "sqrt"     1 1 (and (eq_attr "type" "fsqrt,frsqrt") (eq_attr "mode" "SF"))  54 0) CYGNUS LOCAL vr5400/raeburn
+;; (define_function_unit "sqrt"     1 1 (and (eq_attr "type" "fsqrt,frsqrt") (eq_attr "mode" "DF")) 112 0) CYGNUS LOCAL vr5400/raeburn
+
+
+;;  ....................
+;;	ADDITION
+;;  ....................
+
+(define_insn "adddf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(plus:DF (match_operand:DF 1 "register_operand" "f")
+		 (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "add.d\\t%0,%1,%2"
+  [(set_attr "type"	"fadd")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn "addsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(plus:SF (match_operand:SF 1 "register_operand" "f")
+		 (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "add.s\\t%0,%1,%2"
+  [(set_attr "type"	"fadd")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_expand "addsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
+		 (match_operand:SI 2 "arith_operand" "dI")))]
+  ""
+  "
+{
+  /* The mips16 assembler handles -32768 correctly, and so does gas,
+     but some other MIPS assemblers think that -32768 needs to be
+     loaded into a register before it can be added in.  */
+  if (! TARGET_MIPS16
+      && ! TARGET_GAS
+      && GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) == -32768)
+    operands[2] = force_reg (SImode, operands[2]);
+}")
+
+(define_insn "addsi3_internal"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
+		 (match_operand:SI 2 "arith_operand" "dI")))]
+  "! TARGET_MIPS16
+   && (TARGET_GAS
+       || GET_CODE (operands[2]) != CONST_INT
+       || INTVAL (operands[2]) != -32768)"
+  "addu\\t%0,%z1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+;; For the mips16, we need to recognize stack pointer additions
+;; explicitly, since we don't have a constraint for $sp.  These insns
+;; will be generated by the save_restore_insns functions.
+
+(define_insn ""
+  [(set (reg:SI 29)
+	(plus:SI (reg:SI 29)
+		 (match_operand:SI 0 "small_int" "I")))]
+  "TARGET_MIPS16"
+  "addu\\t%$,%$,%0"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(plus:SI (reg:SI 29)
+		 (match_operand:SI 1 "small_int" "I")))]
+  "TARGET_MIPS16"
+  "addu\\t%0,%$,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set (attr "length")	(if_then_else (match_operand:VOID 1 "m16_uimm8_4" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+	(plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
+		 (match_operand:SI 2 "arith_operand" "IQ,O,d")))]
+  "TARGET_MIPS16
+   && (GET_CODE (operands[1]) != REG
+       || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
+       || M16_REG_P (REGNO (operands[1]))
+       || REGNO (operands[1]) == ARG_POINTER_REGNUM
+       || REGNO (operands[1]) == FRAME_POINTER_REGNUM
+       || REGNO (operands[1]) == STACK_POINTER_REGNUM)
+   && (GET_CODE (operands[2]) != REG
+       || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
+       || M16_REG_P (REGNO (operands[2]))
+       || REGNO (operands[2]) == ARG_POINTER_REGNUM
+       || REGNO (operands[2]) == FRAME_POINTER_REGNUM
+       || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
+  "*
+{
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    return \"addu\\t%0,%2\";
+  return \"addu\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (const_int 1)])])
+
+
+;; On the mips16, we can sometimes split an add of a constant which is
+;; a 4 byte instruction into two adds which are both 2 byte
+;; instructions.  There are two cases: one where we are adding a
+;; constant plus a register to another register, and one where we are
+;; simply adding a constant to a register.
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(plus:SI (match_dup 0)
+		 (match_operand:SI 1 "const_int_operand" "")))]
+  "TARGET_MIPS16 && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == CONST_INT
+   && ((INTVAL (operands[1]) > 0x7f
+	&& INTVAL (operands[1]) <= 0x7f + 0x7f)
+       || (INTVAL (operands[1]) < - 0x80
+	   && INTVAL (operands[1]) >= - 0x80 - 0x80))"
+  [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
+   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[1]);
+
+  if (val >= 0)
+    {
+      operands[1] = GEN_INT (0x7f);
+      operands[2] = GEN_INT (val - 0x7f);
+    }
+  else
+    {
+      operands[1] = GEN_INT (- 0x80);
+      operands[2] = GEN_INT (val + 0x80);
+    }
+}")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(plus:SI (match_operand:SI 1 "register_operand" "")
+		 (match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_MIPS16 && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG
+   && M16_REG_P (REGNO (operands[1]))
+   && REGNO (operands[0]) != REGNO (operands[1])
+   && GET_CODE (operands[2]) == CONST_INT
+   && ((INTVAL (operands[2]) > 0x7
+	&& INTVAL (operands[2]) <= 0x7 + 0x7f)
+       || (INTVAL (operands[2]) < - 0x8
+	   && INTVAL (operands[2]) >= - 0x8 - 0x80))"
+  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
+   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[2]);
+
+  if (val >= 0)
+    {
+      operands[2] = GEN_INT (0x7);
+      operands[3] = GEN_INT (val - 0x7);
+    }
+  else
+    {
+      operands[2] = GEN_INT (- 0x8);
+      operands[3] = GEN_INT (val + 0x8);
+    }
+}")
+
+(define_expand "adddi3"
+  [(parallel [(set (match_operand:DI 0 "register_operand" "")
+		   (plus:DI (match_operand:DI 1 "se_register_operand" "")
+			    (match_operand:DI 2 "se_arith_operand" "")))
+	      (clobber (match_dup 3))])]
+  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+  "
+{
+  /* The mips16 assembler handles -32768 correctly, and so does gas,
+     but some other MIPS assemblers think that -32768 needs to be
+     loaded into a register before it can be added in.  */
+  if (! TARGET_MIPS16
+      && ! TARGET_GAS
+      && GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) == -32768)
+    operands[2] = force_reg (DImode, operands[2]);
+
+  if (TARGET_64BIT)
+    {
+      emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
+					operands[2]));
+      DONE;
+    }
+
+  operands[3] = gen_reg_rtx (SImode);
+}")
+
+(define_insn "adddi3_internal_1"
+  [(set (match_operand:DI 0 "register_operand" "=d,&d")
+	(plus:DI (match_operand:DI 1 "register_operand" "0,d")
+		 (match_operand:DI 2 "register_operand" "d,d")))
+   (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
+  "*
+{
+  return (REGNO (operands[0]) == REGNO (operands[1])
+	  && REGNO (operands[0]) == REGNO (operands[2]))
+    ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
+    : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(plus:DI (match_operand:DI 1 "register_operand" "")
+		 (match_operand:DI 2 "register_operand" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
+   && (REGNO (operands[0]) != REGNO (operands[1])
+       || REGNO (operands[0]) != REGNO (operands[2]))"
+
+  [(set (subreg:SI (match_dup 0) 0)
+	(plus:SI (subreg:SI (match_dup 1) 0)
+		 (subreg:SI (match_dup 2) 0)))
+
+   (set (match_dup 3)
+	(ltu:SI (subreg:SI (match_dup 0) 0)
+		(subreg:SI (match_dup 2) 0)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(plus:SI (subreg:SI (match_dup 1) 1)
+		 (subreg:SI (match_dup 2) 1)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(plus:SI (subreg:SI (match_dup 0) 1)
+		 (match_dup 3)))]
+  "")
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(plus:DI (match_operand:DI 1 "register_operand" "")
+		 (match_operand:DI 2 "register_operand" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
+   && (REGNO (operands[0]) != REGNO (operands[1])
+       || REGNO (operands[0]) != REGNO (operands[2]))"
+
+  [(set (subreg:SI (match_dup 0) 1)
+	(plus:SI (subreg:SI (match_dup 1) 1)
+		 (subreg:SI (match_dup 2) 1)))
+
+   (set (match_dup 3)
+	(ltu:SI (subreg:SI (match_dup 0) 1)
+		(subreg:SI (match_dup 2) 1)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(plus:SI (subreg:SI (match_dup 1) 0)
+		 (subreg:SI (match_dup 2) 0)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(plus:SI (subreg:SI (match_dup 0) 0)
+		 (match_dup 3)))]
+  "")
+
+(define_insn "adddi3_internal_2"
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+	(plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
+		 (match_operand:DI 2 "small_int" "P,J,N")))
+   (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && (TARGET_GAS
+       || GET_CODE (operands[2]) != CONST_INT
+       || INTVAL (operands[2]) != -32768)"
+  "@
+   addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
+   move\\t%L0,%L1\;move\\t%M0,%M1
+   subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"3,2,4")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(plus:DI (match_operand:DI 1 "register_operand" "")
+		 (match_operand:DI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && INTVAL (operands[2]) > 0"
+
+  [(set (subreg:SI (match_dup 0) 0)
+	(plus:SI (subreg:SI (match_dup 1) 0)
+		 (match_dup 2)))
+
+   (set (match_dup 3)
+	(ltu:SI (subreg:SI (match_dup 0) 0)
+		(match_dup 2)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(plus:SI (subreg:SI (match_dup 1) 1)
+		 (match_dup 3)))]
+  "")
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(plus:DI (match_operand:DI 1 "register_operand" "")
+		 (match_operand:DI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && INTVAL (operands[2]) > 0"
+
+  [(set (subreg:SI (match_dup 0) 1)
+	(plus:SI (subreg:SI (match_dup 1) 1)
+		 (match_dup 2)))
+
+   (set (match_dup 3)
+	(ltu:SI (subreg:SI (match_dup 0) 1)
+		(match_dup 2)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(plus:SI (subreg:SI (match_dup 1) 0)
+		 (match_dup 3)))]
+  "")
+
+(define_insn "adddi3_internal_3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(plus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
+		 (match_operand:DI 2 "se_arith_operand" "dI")))]
+  "TARGET_64BIT
+   && !TARGET_MIPS16
+   && (TARGET_GAS
+       || GET_CODE (operands[2]) != CONST_INT
+       || INTVAL (operands[2]) != -32768)"
+  "*
+{
+  return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+    ? \"dsubu\\t%0,%z1,%n2\"
+    : \"daddu\\t%0,%z1,%2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+;; For the mips16, we need to recognize stack pointer additions
+;; explicitly, since we don't have a constraint for $sp.  These insns
+;; will be generated by the save_restore_insns functions.
+
+(define_insn ""
+  [(set (reg:DI 29)
+	(plus:DI (reg:DI 29)
+		 (match_operand:DI 0 "small_int" "I")))]
+  "TARGET_MIPS16 && TARGET_64BIT"
+  "daddu\\t%$,%$,%0"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(plus:DI (reg:DI 29)
+		 (match_operand:DI 1 "small_int" "I")))]
+  "TARGET_MIPS16 && TARGET_64BIT"
+  "daddu\\t%0,%$,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_uimm5_4" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+	(plus:DI (match_operand:DI 1 "register_operand" "0,d,d")
+		 (match_operand:DI 2 "arith_operand" "IQ,O,d")))]
+  "TARGET_MIPS16 && TARGET_64BIT
+   && (GET_CODE (operands[1]) != REG
+       || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
+       || M16_REG_P (REGNO (operands[1]))
+       || REGNO (operands[1]) == ARG_POINTER_REGNUM
+       || REGNO (operands[1]) == FRAME_POINTER_REGNUM
+       || REGNO (operands[1]) == STACK_POINTER_REGNUM)
+   && (GET_CODE (operands[2]) != REG
+       || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
+       || M16_REG_P (REGNO (operands[2]))
+       || REGNO (operands[2]) == ARG_POINTER_REGNUM
+       || REGNO (operands[2]) == FRAME_POINTER_REGNUM
+       || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
+  "*
+{
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    return \"daddu\\t%0,%2\";
+  return \"daddu\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr_alternative "length"
+		[(if_then_else (match_operand:VOID 2 "m16_simm5_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (const_int 1)])])
+
+
+;; On the mips16, we can sometimes split an add of a constant which is
+;; a 4 byte instruction into two adds which are both 2 byte
+;; instructions.  There are two cases: one where we are adding a
+;; constant plus a register to another register, and one where we are
+;; simply adding a constant to a register.
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(plus:DI (match_dup 0)
+		 (match_operand:DI 1 "const_int_operand" "")))]
+  "TARGET_MIPS16 && TARGET_64BIT && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == CONST_INT
+   && ((INTVAL (operands[1]) > 0xf
+	&& INTVAL (operands[1]) <= 0xf + 0xf)
+       || (INTVAL (operands[1]) < - 0x10
+	   && INTVAL (operands[1]) >= - 0x10 - 0x10))"
+  [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
+   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[1]);
+
+  if (val >= 0)
+    {
+      operands[1] = GEN_INT (0xf);
+      operands[2] = GEN_INT (val - 0xf);
+    }
+  else
+    {
+      operands[1] = GEN_INT (- 0x10);
+      operands[2] = GEN_INT (val + 0x10);
+    }
+}")
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(plus:DI (match_operand:DI 1 "register_operand" "")
+		 (match_operand:DI 2 "const_int_operand" "")))]
+  "TARGET_MIPS16 && TARGET_64BIT && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG
+   && M16_REG_P (REGNO (operands[1]))
+   && REGNO (operands[0]) != REGNO (operands[1])
+   && GET_CODE (operands[2]) == CONST_INT
+   && ((INTVAL (operands[2]) > 0x7
+	&& INTVAL (operands[2]) <= 0x7 + 0xf)
+       || (INTVAL (operands[2]) < - 0x8
+	   && INTVAL (operands[2]) >= - 0x8 - 0x10))"
+  [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
+   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[2]);
+
+  if (val >= 0)
+    {
+      operands[2] = GEN_INT (0x7);
+      operands[3] = GEN_INT (val - 0x7);
+    }
+  else
+    {
+      operands[2] = GEN_INT (- 0x8);
+      operands[3] = GEN_INT (val + 0x8);
+    }
+}")
+
+(define_insn "addsi3_internal_2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
+				 (match_operand:SI 2 "arith_operand" "dI"))))]
+  "TARGET_64BIT
+   && !TARGET_MIPS16
+   && (TARGET_GAS
+       || GET_CODE (operands[2]) != CONST_INT
+       || INTVAL (operands[2]) != -32768)"
+  "*
+{
+  return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+    ? \"subu\\t%0,%z1,%n2\"
+    : \"addu\\t%0,%z1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+	(sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
+				 (match_operand:SI 2 "arith_operand" "I,O,d"))))]
+  "TARGET_MIPS16 && TARGET_64BIT"
+  "*
+{
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    return \"addu\\t%0,%2\";
+  return \"addu\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (const_int 1)])])
+
+
+;;  ....................
+;;	SUBTRACTION
+;;  ....................
+
+(define_insn "subdf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(minus:DF (match_operand:DF 1 "register_operand" "f")
+		  (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "sub.d\\t%0,%1,%2"
+  [(set_attr "type"	"fadd")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn "subsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(minus:SF (match_operand:SF 1 "register_operand" "f")
+		  (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "sub.s\\t%0,%1,%2"
+  [(set_attr "type"	"fadd")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_expand "subsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
+		  (match_operand:SI 2 "arith_operand" "dI")))]
+  ""
+  "
+{
+  if (GET_CODE (operands[2]) == CONST_INT
+      && (INTVAL (operands[2]) == -32768
+	  || (TARGET_MIPS16
+	      && INTVAL (operands[2]) == -0x4000)))
+    operands[2] = force_reg (SImode, operands[2]);
+}")
+
+(define_insn "subsi3_internal"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
+		  (match_operand:SI 2 "arith_operand" "dI")))]
+  "!TARGET_MIPS16
+   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
+  "subu\\t%0,%z1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+;; For the mips16, we need to recognize stack pointer subtractions
+;; explicitly, since we don't have a constraint for $sp.  These insns
+;; will be generated by the save_restore_insns functions.
+
+(define_insn ""
+  [(set (reg:SI 29)
+	(minus:SI (reg:SI 29)
+		  (match_operand:SI 0 "small_int" "I")))]
+  "TARGET_MIPS16
+   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
+  "addu\\t%$,%$,%n0"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(minus:SI (reg:SI 29)
+		  (match_operand:SI 1 "small_int" "I")))]
+  "TARGET_MIPS16
+   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
+  "addu\\t%0,%$,%n1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set (attr "length")	(if_then_else (match_operand:VOID 1 "m16_nuimm8_4" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+	(minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
+		  (match_operand:SI 2 "arith_operand" "I,O,d")))]
+  "TARGET_MIPS16
+   && (GET_CODE (operands[2]) != CONST_INT
+       || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
+  "*
+{
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    return \"subu\\t%0,%2\";
+  return \"subu\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (const_int 1)])])
+
+;; On the mips16, we can sometimes split an subtract of a constant
+;; which is a 4 byte instruction into two adds which are both 2 byte
+;; instructions.  There are two cases: one where we are setting a
+;; register to a register minus a constant, and one where we are
+;; simply subtracting a constant from a register.
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_dup 0)
+		  (match_operand:SI 1 "const_int_operand" "")))]
+  "TARGET_MIPS16 && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == CONST_INT
+   && ((INTVAL (operands[1]) > 0x80
+	&& INTVAL (operands[1]) <= 0x80 + 0x80)
+       || (INTVAL (operands[1]) < - 0x7f
+	   && INTVAL (operands[1]) >= - 0x7f - 0x7f))"
+  [(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 1)))
+   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[1]);
+
+  if (val >= 0)
+    {
+      operands[1] = GEN_INT (0x80);
+      operands[2] = GEN_INT (val - 0x80);
+    }
+  else
+    {
+      operands[1] = GEN_INT (- 0x7f);
+      operands[2] = GEN_INT (val + 0x7f);
+    }
+}")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_operand:SI 1 "register_operand" "")
+		  (match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_MIPS16 && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG
+   && M16_REG_P (REGNO (operands[1]))
+   && REGNO (operands[0]) != REGNO (operands[1])
+   && GET_CODE (operands[2]) == CONST_INT
+   && ((INTVAL (operands[2]) > 0x8
+	&& INTVAL (operands[2]) <= 0x8 + 0x80)
+       || (INTVAL (operands[2]) < - 0x7
+	   && INTVAL (operands[2]) >= - 0x7 - 0x7f))"
+  [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
+   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 3)))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[2]);
+
+  if (val >= 0)
+    {
+      operands[2] = GEN_INT (0x8);
+      operands[3] = GEN_INT (val - 0x8);
+    }
+  else
+    {
+      operands[2] = GEN_INT (- 0x7);
+      operands[3] = GEN_INT (val + 0x7);
+    }
+}")
+
+(define_expand "subdi3"
+  [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
+		   (minus:DI (match_operand:DI 1 "se_register_operand" "d")
+			     (match_operand:DI 2 "se_register_operand" "d")))
+	      (clobber (match_dup 3))])]
+  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+  "
+{
+  if (TARGET_64BIT)
+    {
+      emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
+					operands[2]));
+      DONE;
+    }
+
+  operands[3] = gen_reg_rtx (SImode);
+}")
+
+(define_insn "subdi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(minus:DI (match_operand:DI 1 "register_operand" "d")
+		  (match_operand:DI 2 "register_operand" "d")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
+  "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(minus:DI (match_operand:DI 1 "register_operand" "")
+		  (match_operand:DI 2 "register_operand" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
+
+  [(set (match_dup 3)
+	(ltu:SI (subreg:SI (match_dup 1) 0)
+		(subreg:SI (match_dup 2) 0)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(minus:SI (subreg:SI (match_dup 1) 0)
+		  (subreg:SI (match_dup 2) 0)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(minus:SI (subreg:SI (match_dup 1) 1)
+		  (subreg:SI (match_dup 2) 1)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(minus:SI (subreg:SI (match_dup 0) 1)
+		  (match_dup 3)))]
+  "")
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(minus:DI (match_operand:DI 1 "register_operand" "")
+		  (match_operand:DI 2 "register_operand" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
+
+  [(set (match_dup 3)
+	(ltu:SI (subreg:SI (match_dup 1) 1)
+	        (subreg:SI (match_dup 2) 1)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(minus:SI (subreg:SI (match_dup 1) 1)
+		  (subreg:SI (match_dup 2) 1)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(minus:SI (subreg:SI (match_dup 1) 0)
+		  (subreg:SI (match_dup 2) 0)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(minus:SI (subreg:SI (match_dup 0) 0)
+		  (match_dup 3)))]
+  "")
+
+(define_insn "subdi3_internal_2"
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
+		  (match_operand:DI 2 "small_int" "P,J,N")))
+   (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && INTVAL (operands[2]) != -32768"
+  "@
+   sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
+   move\\t%L0,%L1\;move\\t%M0,%M1
+   sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"3,2,4")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(minus:DI (match_operand:DI 1 "register_operand" "")
+		  (match_operand:DI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && INTVAL (operands[2]) > 0"
+
+  [(set (match_dup 3)
+	(ltu:SI (subreg:SI (match_dup 1) 0)
+		(match_dup 2)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(minus:SI (subreg:SI (match_dup 1) 0)
+		  (match_dup 2)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(minus:SI (subreg:SI (match_dup 1) 1)
+		  (match_dup 3)))]
+  "")
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(minus:DI (match_operand:DI 1 "register_operand" "")
+		  (match_operand:DI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && INTVAL (operands[2]) > 0"
+
+  [(set (match_dup 3)
+	(ltu:SI (subreg:SI (match_dup 1) 1)
+		(match_dup 2)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(minus:SI (subreg:SI (match_dup 1) 1)
+		  (match_dup 2)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(minus:SI (subreg:SI (match_dup 1) 0)
+		  (match_dup 3)))]
+  "")
+
+(define_insn "subdi3_internal_3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(minus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
+		  (match_operand:DI 2 "se_arith_operand" "dI")))]
+  "TARGET_64BIT && !TARGET_MIPS16
+   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
+  "*
+{
+  return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+    ? \"daddu\\t%0,%z1,%n2\"
+    : \"dsubu\\t%0,%z1,%2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+;; For the mips16, we need to recognize stack pointer subtractions
+;; explicitly, since we don't have a constraint for $sp.  These insns
+;; will be generated by the save_restore_insns functions.
+
+(define_insn ""
+  [(set (reg:DI 29)
+	(minus:DI (reg:DI 29)
+		  (match_operand:DI 0 "small_int" "I")))]
+  "TARGET_MIPS16
+   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
+  "daddu\\t%$,%$,%n0"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(minus:DI (reg:DI 29)
+		  (match_operand:DI 1 "small_int" "I")))]
+  "TARGET_MIPS16
+   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
+  "daddu\\t%0,%$,%n1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_nuimm5_4" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+	(minus:DI (match_operand:DI 1 "register_operand" "0,d,d")
+		  (match_operand:DI 2 "arith_operand" "I,O,d")))]
+  "TARGET_MIPS16
+   && (GET_CODE (operands[2]) != CONST_INT
+       || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
+  "*
+{
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    return \"dsubu\\t%0,%2\";
+  return \"dsubu\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr_alternative "length"
+		[(if_then_else (match_operand:VOID 2 "m16_nsimm5_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (const_int 1)])])
+
+;; On the mips16, we can sometimes split an add of a constant which is
+;; a 4 byte instruction into two adds which are both 2 byte
+;; instructions.  There are two cases: one where we are adding a
+;; constant plus a register to another register, and one where we are
+;; simply adding a constant to a register.
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(minus:DI (match_dup 0)
+		  (match_operand:DI 1 "const_int_operand" "")))]
+  "TARGET_MIPS16 && TARGET_64BIT && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == CONST_INT
+   && ((INTVAL (operands[1]) > 0x10
+	&& INTVAL (operands[1]) <= 0x10 + 0x10)
+       || (INTVAL (operands[1]) < - 0xf
+	   && INTVAL (operands[1]) >= - 0xf - 0xf))"
+  [(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 1)))
+   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[1]);
+
+  if (val >= 0)
+    {
+      operands[1] = GEN_INT (0xf);
+      operands[2] = GEN_INT (val - 0xf);
+    }
+  else
+    {
+      operands[1] = GEN_INT (- 0x10);
+      operands[2] = GEN_INT (val + 0x10);
+    }
+}")
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(minus:DI (match_operand:DI 1 "register_operand" "")
+		  (match_operand:DI 2 "const_int_operand" "")))]
+  "TARGET_MIPS16 && TARGET_64BIT && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG
+   && M16_REG_P (REGNO (operands[1]))
+   && REGNO (operands[0]) != REGNO (operands[1])
+   && GET_CODE (operands[2]) == CONST_INT
+   && ((INTVAL (operands[2]) > 0x8
+	&& INTVAL (operands[2]) <= 0x8 + 0x10)
+       || (INTVAL (operands[2]) < - 0x7
+	   && INTVAL (operands[2]) >= - 0x7 - 0xf))"
+  [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
+   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[2]);
+
+  if (val >= 0)
+    {
+      operands[2] = GEN_INT (0x8);
+      operands[3] = GEN_INT (val - 0x8);
+    }
+  else
+    {
+      operands[2] = GEN_INT (- 0x7);
+      operands[3] = GEN_INT (val + 0x7);
+    }
+}")
+
+(define_insn "subsi3_internal_2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
+				  (match_operand:SI 2 "arith_operand" "dI"))))]
+  "TARGET_64BIT && !TARGET_MIPS16
+   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
+  "*
+{
+  return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+    ? \"addu\\t%0,%z1,%n2\"
+    : \"subu\\t%0,%z1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+	(sign_extend:DI (minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
+				  (match_operand:SI 2 "arith_operand" "I,O,d"))))]
+  "TARGET_64BIT && TARGET_MIPS16
+   && (GET_CODE (operands[2]) != CONST_INT
+       || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
+  "*
+{
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    return \"subu\\t%0,%2\";
+  return \"subu\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (const_int 1)])])
+  
+
+
+;;  ....................
+;;	MULTIPLICATION
+;;  ....................
+
+;; Early Vr4300 silicon has a CPU bug where multiplies with certain
+;; operands may corrupt immediately following multiplies. This is a
+;; simple fix to insert NOPs.
+
+(define_expand "muldf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(mult:DF (match_operand:DF 1 "register_operand" "f")
+		 (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "
+{
+  if (mips_cpu != PROCESSOR_R4300)
+    emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
+  else
+    emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
+  DONE;
+}")
+
+(define_insn "muldf3_internal"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(mult:DF (match_operand:DF 1 "register_operand" "f")
+		 (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300"
+  "mul.d\\t%0,%1,%2"
+  [(set_attr "type"	"fmul")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn "muldf3_r4300"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(mult:DF (match_operand:DF 1 "register_operand" "f")
+		 (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu == PROCESSOR_R4300"
+  "*
+{
+  output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
+  if (TARGET_4300_MUL_FIX)
+    output_asm_insn (\"nop\", operands);
+  return \"\";
+}"
+  [(set_attr "type"	"fmul")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"2")])	;; mul.d + nop
+
+(define_expand "mulsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(mult:SF (match_operand:SF 1 "register_operand" "f")
+		 (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "
+{
+  if (mips_cpu != PROCESSOR_R4300)
+    emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
+  else
+    emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
+  DONE;
+}")
+
+(define_insn "mulsf3_internal"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(mult:SF (match_operand:SF 1 "register_operand" "f")
+		 (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300"
+  "mul.s\\t%0,%1,%2"
+  [(set_attr "type"	"fmul")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn "mulsf3_r4300"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(mult:SF (match_operand:SF 1 "register_operand" "f")
+		 (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && mips_cpu == PROCESSOR_R4300"
+  "*
+{
+  output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
+  if (TARGET_4300_MUL_FIX)
+    output_asm_insn (\"nop\", operands);
+  return \"\";
+}"
+  [(set_attr "type"	"fmul")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"2")])	;; mul.s + nop
+
+
+;; ??? The R4000 (only) has a cpu bug.  If a double-word shift executes while
+;; a multiply is in progress, it may give an incorrect result.  Avoid
+;; this by keeping the mflo with the mult on the R4000.
+
+(define_expand "mulsi3"
+  [(set (match_operand:SI 0 "register_operand" "=l")
+	(mult:SI (match_operand:SI 1 "register_operand" "d")
+		 (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_scratch:SI 3 "=h"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  ""
+  "
+{
+  if (HAVE_mulsi3_mult3)
+    emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
+  else if (mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16)
+    emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
+  else
+    emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
+  DONE;
+}")
+
+
+(define_insn "mulsi3_mult3"
+  [(set (match_operand:SI 0 "register_operand" "=d,l")
+	(mult:SI (match_operand:SI 1 "register_operand" "d,d")
+		 (match_operand:SI 2 "register_operand" "d,d")))
+   (clobber (match_scratch:SI 3 "=h,h"))
+   (clobber (match_scratch:SI 4 "=l,X"))
+   (clobber (match_scratch:SI 5 "=a,a"))]
+  "(GENERATE_MULT3
+    || TARGET_MIPS5400 /* CYGNUS LOCAL vr5400/raeburn */
+    || TARGET_MAD)
+   && !0" ;;  CYGNUS LOCAL law
+  "*
+{
+  if (which_alternative == 1)
+    return \"mult\\t%1,%2\";
+  if (TARGET_MIPS5400			/* CYGNUS LOCAL vr5400/raeburn */
+      || TARGET_MAD)
+    return \"mul\\t%0,%1,%2\";
+  return \"mult\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "mulsi3_internal"
+  [(set (match_operand:SI 0 "register_operand" "=l")
+	(mult:SI (match_operand:SI 1 "register_operand" "d")
+		 (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_scratch:SI 3 "=h"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16"
+  "mult\\t%1,%2"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "mulsi3_r4000"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(mult:SI (match_operand:SI 1 "register_operand" "d")
+		 (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_scratch:SI 3 "=h"))
+   (clobber (match_scratch:SI 4 "=l"))
+   (clobber (match_scratch:SI 5 "=a"))]
+  "mips_cpu == PROCESSOR_R4000 && !TARGET_MIPS16"
+  "*
+{
+  rtx xoperands[10];
+
+  xoperands[0] = operands[0];
+  xoperands[1] = gen_rtx (REG, SImode, LO_REGNUM);
+
+  output_asm_insn (\"mult\\t%1,%2\", operands);
+  output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
+  return \"\";
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"3")])		;; mult + mflo + delay
+
+;; Multiply-accumulate patterns
+
+;; For processors that can copy the output to a general register:
+;; The all-d alternative is needed because the combiner will find this
+;; pattern and then register alloc/reload will move registers around to
+;; make them fit, and we don't want to trigger unnecessary loads to LO.
+;; The last alternative should be made slightly less desirable, but adding
+;; "?" to the constraint is too strong, and causes values to be loaded into
+;; LO even when that's more costly.  For now, using "*d" mostly does the
+;; trick.
+
+(define_insn "*mul_acc_si"
+  [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
+	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
+			  (match_operand:SI 2 "register_operand" "d,d,d"))
+		 (match_operand:SI 3 "register_operand" "0,l,*d")))
+   (clobber (match_scratch:SI 4 "=h,h,h"))
+   (clobber (match_scratch:SI 5 "=X,3,l"))
+   (clobber (match_scratch:SI 6 "=a,a,a"))
+   (clobber (match_scratch:SI 7 "=X,X,d"))]
+  "(TARGET_MIPS3900
+    || TARGET_MIPS5400)			/* CYGNUS LOCAL vr5400/raeburn */
+   && !TARGET_MIPS16"
+  "*
+{
+  static char *const madd[] = { \"madd\\t%1,%2\",    \"madd\\t%0,%1,%2\" };
+  static char *const macc[] = { \"macc\\t$0,%1,%2\", \"macc\\t%0,%1,%2\" }; /* CYGNUS LOCAL vr5400/raeburn */
+  if (which_alternative == 2)
+    return \"#\";
+  /* CYGNUS LOCAL vr5400/raeburn */
+  if (TARGET_MIPS5400)
+    return macc[which_alternative];
+  /* END CYGNUS LOCAL */
+  return madd[which_alternative];
+}"
+  [(set_attr "type"	"imul,imul,multi")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,1,2")])
+
+;; Split the above insn if we failed to get LO allocated.
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
+			  (match_operand:SI 2 "register_operand" ""))
+		 (match_operand:SI 3 "register_operand" "")))
+   (clobber (match_scratch:SI 4 ""))
+   (clobber (match_scratch:SI 5 ""))
+   (clobber (match_scratch:SI 6 ""))
+   (clobber (match_scratch:SI 7 ""))]
+  "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[3]))"
+  [(parallel [(set (match_dup 7)
+		   (mult:SI (match_dup 1) (match_dup 2)))
+	      (clobber (match_dup 4))
+	      (clobber (match_dup 5))
+	      (clobber (match_dup 6))])
+   (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 3)))]
+  "")
+
+;; CYGNUS LOCAL vr5400/raeburn
+(define_insn "*muls_r5400"
+  [(set (match_operand:SI 0 "register_operand" "=l,d")
+	(neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
+			 (match_operand:SI 2 "register_operand" "d,d"))))
+   (clobber (match_scratch:SI 3 "=h,h"))
+   (clobber (match_scratch:SI 4 "=a,a"))
+   (clobber (match_scratch:SI 5 "=X,l"))]
+  "TARGET_MIPS5400"
+  "@
+   muls\\t$0,%1,%2
+   muls\\t%0,%1,%2"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")])
+
+;; See comments above for mul_acc_si.
+(define_insn "*msac_r5400"
+  [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
+	(minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
+		  (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
+			   (match_operand:SI 3 "register_operand" "d,d,d"))))
+   (clobber (match_scratch:SI 4 "=h,h,h"))
+   (clobber (match_scratch:SI 5 "=X,1,l"))
+   (clobber (match_scratch:SI 6 "=a,a,a"))
+   (clobber (match_scratch:SI 7 "=X,X,d"))]
+  "TARGET_MIPS5400"
+  "@
+   msac\\t$0,%2,%3
+   msac\\t%0,%2,%3
+   #"
+  [(set_attr "type"	"imul,imul,multi")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,1,2")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_operand:SI 1 "register_operand" "")
+		  (mult:SI (match_operand:SI 2 "register_operand" "")
+			   (match_operand:SI 3 "register_operand" ""))))
+   (clobber (match_scratch:SI 4 ""))
+   (clobber (match_scratch:SI 5 ""))
+   (clobber (match_scratch:SI 6 ""))
+   (clobber (match_scratch:SI 7 ""))]
+  "reload_completed && GP_REG_P (true_regnum (operands[0])) && GP_REG_P (true_regnum (operands[1]))"
+  [(parallel [(set (match_dup 7)
+		   (mult:SI (match_dup 2) (match_dup 3)))
+	      (clobber (match_dup 4))
+	      (clobber (match_dup 5))
+	      (clobber (match_dup 6))])
+   (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 7)))]
+  "")
+;; END CYGNUS LOCAL
+
+(define_expand "muldi3"
+  [(set (match_operand:DI 0 "register_operand" "=l")
+	(mult:DI (match_operand:DI 1 "se_register_operand" "d")
+		 (match_operand:DI 2 "register_operand" "d")))
+   (clobber (match_scratch:DI 3 "=h"))
+   (clobber (match_scratch:DI 4 "=a"))]
+  "TARGET_64BIT && !0" ;;  CYGNUS LOCAL law
+
+  "
+{
+  if (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)
+    emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
+  else
+    emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
+  DONE;
+}")
+
+;; Don't accept both operands using se_register_operand, because if
+;; both operands are sign extended we would prefer to use mult in the
+;; mulsidi3 pattern.  Commutativity should permit either operand to be
+;; sign extended.
+
+(define_insn "muldi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=l")
+	(mult:DI (match_operand:DI 1 "se_register_operand" "d")
+		 (match_operand:DI 2 "register_operand" "d")))
+   (clobber (match_scratch:DI 3 "=h"))
+   (clobber (match_scratch:DI 4 "=a"))]
+  "TARGET_64BIT && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16 && !0" ;;  CYGNUS LOCAL law
+  "dmult\\t%1,%2"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn "muldi3_internal2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(mult:DI (match_operand:DI 1 "se_register_operand" "d")
+		 (match_operand:DI 2 "register_operand" "d")))
+   (clobber (match_scratch:DI 3 "=h"))
+   (clobber (match_scratch:DI 4 "=l"))
+   (clobber (match_scratch:DI 5 "=a"))]
+  "TARGET_64BIT && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16) && !0" ;;  CYGNUS LOCAL law
+  "*
+{
+  if (GENERATE_MULT3)
+    output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
+  else 
+    {
+    rtx xoperands[10];
+
+    xoperands[0] = operands[0];
+    xoperands[1] = gen_rtx (REG, DImode, LO_REGNUM);
+
+    output_asm_insn (\"dmult\\t%1,%2\", operands);
+    output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
+    }
+  return \"\";
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"DI")
+   (set (attr "length")
+	(if_then_else (ne (symbol_ref "GENERATE_MULT3") (const_int 0))
+		       (const_int 1)
+		       (const_int 3)))]) 	;; mult + mflo + delay
+
+;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
+
+(define_expand "mulsidi3"
+  [(set (match_operand:DI 0 "register_operand" "=x")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
+		 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
+  ""
+  "
+{
+  rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
+  if (TARGET_64BIT)
+    emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
+				   dummy, dummy));
+  else
+    emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
+				      dummy, dummy));
+  DONE;
+}")
+
+(define_expand "umulsidi3"
+  [(set (match_operand:DI 0 "register_operand" "=x")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
+		 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
+  ""
+  "
+{
+  rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
+  if (TARGET_64BIT)
+    emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
+				   dummy, dummy));
+  else
+    emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
+				      dummy, dummy));
+  DONE;
+}")
+
+(define_insn "mulsidi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=x")
+	(mult:DI (match_operator:DI 3 "extend_operator"
+				    [(match_operand:SI 1 "register_operand" "d")])
+		 (match_operator:DI 4 "extend_operator"
+				    [(match_operand:SI 2 "register_operand" "d")])))
+   (clobber (match_scratch:SI 5 "=a"))]
+  "!TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])"
+  "*
+{
+  if (GET_CODE (operands[3]) == SIGN_EXTEND)
+    return \"mult\\t%1,%2\";
+  return \"multu\\t%1,%2\";
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+
+(define_insn "mulsidi3_64bit"
+  [(set (match_operand:DI 0 "register_operand" "=a")
+	(mult:DI (match_operator:DI 3 "extend_operator"
+				    [(match_operand:SI 1 "register_operand" "d")])
+		 (match_operator:DI 4 "extend_operator"
+				    [(match_operand:SI 2 "register_operand" "d")])))
+   (clobber (match_scratch:DI 5 "=l"))
+   (clobber (match_scratch:DI 6 "=h"))]
+  "TARGET_64BIT && !0 && GET_CODE (operands[3]) == GET_CODE (operands[4])" ;;  CYGNUS LOCAL law
+  "*
+{
+  if (GET_CODE (operands[3]) == SIGN_EXTEND)
+    return \"mult\\t%1,%2\";
+  return \"multu\\t%1,%2\";
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+;; CYGNUS LOCAL vr5400/raeburn
+
+;; widening multiply with accumulator and/or negation
+;; These don't match yet for zero-extending; too complex for combine?
+;; Possible additions we should have:
+;;  "=x" variants for when !TARGET_64BIT ?
+;;  all-d alternatives with splits like pure SImode versions
+(define_insn "*muls_r5400_di"
+  [(set (match_operand:DI 0 "register_operand" "=a")
+	(neg:DI
+	 (mult:DI (match_operator:DI 3 "extend_operator"
+				     [(match_operand:SI 1 "register_operand" "d")])
+		  (match_operator:DI 4 "extend_operator"
+				     [(match_operand:SI 2 "register_operand" "d")]))))
+   (clobber (match_scratch:SI 5 "=h"))
+   (clobber (match_scratch:SI 6 "=l"))]
+  "TARGET_64BIT && TARGET_MIPS5400 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
+  "*
+{
+  if (GET_CODE (operands[3]) == SIGN_EXTEND)
+    return \"muls\\t$0,%1,%2\";
+  else
+    return \"mulsu\\t$0,%1,%2\";
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")])
+
+(define_insn "*msac_r5400_di"
+  [(set (match_operand:DI 0 "register_operand" "=a")
+	(minus:DI (match_operand:DI 3 "register_operand" "0")
+		  (mult:DI (match_operator:DI 4 "extend_operator"
+					      [(match_operand:SI 1 "register_operand" "d")])
+			   (match_operator:DI 5 "extend_operator"
+					      [(match_operand:SI 2 "register_operand" "d")]))))
+   (clobber (match_scratch:SI 6 "=h"))
+   (clobber (match_scratch:SI 7 "=l"))]
+  "TARGET_64BIT && TARGET_MIPS5400 && GET_CODE (operands[4]) == GET_CODE (operands[5])"
+  "*
+{
+  if (GET_CODE (operands[4]) == SIGN_EXTEND)
+    return \"msac\\t$0,%1,%2\";
+  else
+    return \"msacu\\t$0,%1,%2\";
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")])
+;; END CYGNUS LOCAL
+
+;; _highpart patterns
+(define_expand "smulsi3_highpart"
+  [(set (match_operand:SI 0 "register_operand" "=h")
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
+			       (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
+		      (const_int 32))))]
+  ""
+  "
+{
+  rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
+  rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
+#ifndef NO_MD_PROTOTYPES
+  rtx (*genfn) PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
+#else
+  rtx (*genfn) ();
+#endif
+  genfn = gen_xmulsi3_highpart_internal;
+  /* CYGNUS LOCAL vr5400/raeburn */
+  if (TARGET_MIPS5400)
+    genfn = gen_xmulsi3_highpart_5400;
+  /* END CYGNUS LOCAL */
+  emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
+		       dummy, dummy2));
+  DONE;
+}")
+
+(define_expand "umulsi3_highpart"
+  [(set (match_operand:SI 0 "register_operand" "=h")
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
+			       (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
+		      (const_int 32))))]
+  ""
+  "
+{
+  rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
+  rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
+#ifndef NO_MD_PROTOTYPES
+  rtx (*genfn) PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
+#else
+  rtx (*genfn) ();
+#endif
+  genfn = gen_xmulsi3_highpart_internal;
+  /* CYGNUS LOCAL vr5400/raeburn */
+  if (TARGET_MIPS5400)
+    genfn = gen_xmulsi3_highpart_5400;
+  /* END CYGNUS LOCAL */
+  emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
+		       dummy, dummy2));
+  DONE;
+}")
+
+
+(define_insn "xmulsi3_highpart_internal"
+  [(set (match_operand:SI 0 "register_operand" "=h")
+	(truncate:SI
+	 (match_operator:DI 5 "highpart_shift_operator"
+			    [(mult:DI (match_operator:DI 3 "extend_operator"
+							 [(match_operand:SI 1 "register_operand" "d")])
+				      (match_operator:DI 4 "extend_operator"
+							 [(match_operand:SI 2 "register_operand" "d")]))
+			     (const_int 32)])))
+   (clobber (match_scratch:SI 6 "=l"))
+   (clobber (match_scratch:SI 7 "=a"))]
+  "! TARGET_MIPS5400 && !0 && GET_CODE (operands[3]) == GET_CODE (operands[4])" ;; CYGNUS LOCAL vr5400/raeburn ;;  CYGNUS LOCAL law
+  "*
+{
+  if (GET_CODE (operands[3]) == SIGN_EXTEND)
+    return \"mult\\t%1,%2\";
+  else
+    return \"multu\\t%1,%2\";
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+;; CYGNUS LOCAL vr5400/raeburn
+(define_insn "xmulsi3_highpart_5400"
+  [(set (match_operand:SI 0 "register_operand" "=h,d")
+	(truncate:SI
+	 (match_operator:DI 5 "highpart_shift_operator"
+			    [(mult:DI (match_operator:DI 3 "extend_operator"
+							 [(match_operand:SI 1 "register_operand" "d,d")])
+				      (match_operator:DI 4 "extend_operator"
+							 [(match_operand:SI 2 "register_operand" "d,d")]))
+			     (const_int 32)])))
+   (clobber (match_scratch:SI 6 "=l,l"))
+   (clobber (match_scratch:SI 7 "=a,a"))
+   (clobber (match_scratch:SI 8 "=X,h"))]
+  "TARGET_MIPS5400 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
+  "*
+{
+  char *const sign[] = { \"mult\\t%1,%2\",  \"mulhi\\t%0,%1,%2\"  };
+  char *const zero[] = { \"multu\\t%1,%2\", \"mulhiu\\t%0,%1,%2\" };
+  if (GET_CODE (operands[3]) == SIGN_EXTEND)
+    return sign[which_alternative];
+  else
+    return zero[which_alternative];
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "*xmulsi3_neg_highpart_5400"
+  [(set (match_operand:SI 0 "register_operand" "=h,d")
+	(truncate:SI
+	 (match_operator:DI 5 "highpart_shift_operator"
+			    [(neg:DI
+			      (mult:DI (match_operator:DI 3 "extend_operator"
+							  [(match_operand:SI 1 "register_operand" "d,d")])
+				       (match_operator:DI 4 "extend_operator"
+							  [(match_operand:SI 2 "register_operand" "d,d")])))
+			     (const_int 32)])))
+   (clobber (match_scratch:SI 6 "=l,l"))
+   (clobber (match_scratch:SI 7 "=a,a"))
+   (clobber (match_scratch:SI 8 "=X,h"))]
+  "TARGET_MIPS5400 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
+  "*
+{
+  char *const sign[] = { \"mulshi\\t$0,%1,%2\",  \"mulshi\\t%0,%1,%2\"  };
+  char *const zero[] = { \"mulshiu\\t$0,%1,%2\", \"mulshiu\\t%0,%1,%2\" };
+  if (GET_CODE (operands[3]) == SIGN_EXTEND)
+    return sign[which_alternative];
+  else
+    return zero[which_alternative];
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+;; END CYGNUS LOCAL
+
+(define_insn "smuldi3_highpart"
+  [(set (match_operand:DI 0 "register_operand" "=h")
+	(truncate:DI
+	 (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
+			       (sign_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
+		      (const_int 64))))
+   (clobber (match_scratch:DI 3 "=l"))
+   (clobber (match_scratch:DI 4 "=a"))]
+  "TARGET_64BIT && !0" ;;  CYGNUS LOCAL law
+  "dmult\\t%1,%2"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn "umuldi3_highpart"
+  [(set (match_operand:DI 0 "register_operand" "=h")
+	(truncate:DI
+	 (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
+			       (zero_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
+		      (const_int 64))))
+   (clobber (match_scratch:DI 3 "=l"))
+   (clobber (match_scratch:DI 4 "=a"))]
+  "TARGET_64BIT && !0" ;;  CYGNUS LOCAL law
+  "dmultu\\t%1,%2"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
+;; instruction.  The HI/LO registers are used as a 64 bit accumulator.
+
+(define_insn "madsi"
+  [(set (match_operand:SI 0 "register_operand" "+l")
+	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+			  (match_operand:SI 2 "register_operand" "d"))
+		 (match_dup 0)))
+   (clobber (match_scratch:SI 3 "=h"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "TARGET_MAD"
+  "mad\\t%1,%2"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"   "1")])
+
+(define_insn "*mul_acc_di"
+  [(set (match_operand:DI 0 "register_operand" "+x")
+	(plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
+			   [(match_operand:SI 1 "register_operand" "d")])
+			  (match_operator:DI 4 "extend_operator"
+			   [(match_operand:SI 2 "register_operand" "d")]))
+		 (match_dup 0)))
+   (clobber (match_scratch:SI 5 "=a"))]
+  "TARGET_MAD
+   && ! TARGET_64BIT
+   && GET_CODE (operands[3]) == GET_CODE (operands[4])"
+  "*
+{
+  if (GET_CODE (operands[3]) == SIGN_EXTEND)
+    return \"mad\\t%1,%2\";
+  else
+    return \"madu\\t%1,%2\";
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"   "1")])
+
+(define_insn "*mul_acc_64bit_di"
+  [(set (match_operand:DI 0 "register_operand" "+a")
+	(plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
+			   [(match_operand:SI 1 "register_operand" "d")])
+			  (match_operator:DI 4 "extend_operator"
+			   [(match_operand:SI 2 "register_operand" "d")]))
+		 (match_dup 0)))
+   (clobber (match_scratch:SI 5 "=h"))
+   (clobber (match_scratch:SI 6 "=l"))]
+  "(TARGET_MAD || TARGET_MIPS5400) /* CYGNUS LOCAL vr5400/raeburn */
+   && TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])"
+  "*
+{
+  if (TARGET_MAD)
+    {
+      if (GET_CODE (operands[3]) == SIGN_EXTEND)
+	return \"mad\\t%1,%2\";
+      else
+	return \"madu\\t%1,%2\";
+    }
+  /* CYGNUS LOCAL vr5400/raeburn */
+  else if (TARGET_MIPS5400)
+    {
+      if (GET_CODE (operands[3]) == SIGN_EXTEND)
+	return \"macc\\t$0,%1,%2\";
+      else
+	return \"maccu\\t$0,%1,%2\";
+    }
+  /* END CYGNUS LOCAL */
+  else
+    abort ();
+}"
+  [(set_attr "type"	"imul")
+   (set_attr "mode"	"SI")
+   (set_attr "length"   "1")])
+
+;; Floating point multiply accumulate instructions.
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
+			  (match_operand:DF 2 "register_operand" "f"))
+		 (match_operand:DF 3 "register_operand" "f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "madd.d\\t%0,%3,%1,%2"
+  [(set_attr "type"	"fmadd")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
+			  (match_operand:SF 2 "register_operand" "f"))
+		 (match_operand:SF 3 "register_operand" "f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "madd.s\\t%0,%3,%1,%2"
+  [(set_attr "type"	"fmadd")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
+			   (match_operand:DF 2 "register_operand" "f"))
+		  (match_operand:DF 3 "register_operand" "f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "msub.d\\t%0,%3,%1,%2"
+  [(set_attr "type"	"fmadd")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
+			   (match_operand:SF 2 "register_operand" "f"))
+		  (match_operand:SF 3 "register_operand" "f")))]
+		  
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "msub.s\\t%0,%3,%1,%2"
+  [(set_attr "type"	"fmadd")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
+				  (match_operand:DF 2 "register_operand" "f"))
+			 (match_operand:DF 3 "register_operand" "f"))))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "nmadd.d\\t%0,%3,%1,%2"
+  [(set_attr "type"	"fmadd")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
+				  (match_operand:SF 2 "register_operand" "f"))
+			 (match_operand:SF 3 "register_operand" "f"))))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "nmadd.s\\t%0,%3,%1,%2"
+  [(set_attr "type"	"fmadd")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(minus:DF (match_operand:DF 1 "register_operand" "f")
+		  (mult:DF (match_operand:DF 2 "register_operand" "f")
+			   (match_operand:DF 3 "register_operand" "f"))))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "nmsub.d\\t%0,%1,%2,%3"
+  [(set_attr "type"	"fmadd")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(minus:SF (match_operand:SF 1 "register_operand" "f")
+		  (mult:SF (match_operand:SF 2 "register_operand" "f")
+			   (match_operand:SF 3 "register_operand" "f"))))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "nmsub.s\\t%0,%1,%2,%3"
+  [(set_attr "type"	"fmadd")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+;;  ....................
+;;	DIVISION and REMAINDER
+;;  ....................
+
+(define_insn "divdf3"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(div:DF (match_operand:DF 1 "register_operand" "f")
+		(match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "div.d\\t%0,%1,%2"
+  [(set_attr "type"	"fdiv")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn "divsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(div:SF (match_operand:SF 1 "register_operand" "f")
+		(match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "div.s\\t%0,%1,%2"
+  [(set_attr "type"	"fdiv")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(div:DF (match_operand:DF 1 "const_float_1_operand" "")
+		(match_operand:DF 2 "register_operand" "f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
+  "recip.d\\t%0,%2"
+  [(set_attr "type"	"fdiv")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(div:SF (match_operand:SF 1 "const_float_1_operand" "")
+		(match_operand:SF 2 "register_operand" "f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
+  "recip.s\\t%0,%2"
+  [(set_attr "type"	"fdiv")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+;; If optimizing, prefer the divmod functions over separate div and
+;; mod functions, since this will allow using one instruction for both
+;; the quotient and remainder.  At present, the divmod is not moved out
+;; of loops if it is constant within the loop, so allow -mdebugc to
+;; use the old method of doing things.
+
+;; 64 is the multiply/divide hi register
+;; 65 is the multiply/divide lo register
+
+;; ??? We can't accept constants here, because the MIPS assembler will replace
+;; a divide by power of 2 with a shift, and then the remainder is no longer
+;; available.
+
+(define_expand "divmodsi4"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(div:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "register_operand" "d")))
+   (set (match_operand:SI 3 "register_operand" "=d")
+	(mod:SI (match_dup 1)
+		(match_dup 2)))
+   (clobber (match_scratch:SI 4 "=l"))
+   (clobber (match_scratch:SI 5 "=h"))
+   (clobber (match_scratch:SI 6 "=a"))]
+  "optimize"
+  "
+{
+  rtx label;
+
+
+  emit_insn (gen_divmodsi4_internal (operands[0], operands[1], operands[2],
+	     operands[3]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  if (TARGET_CHECK_RANGE_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (SImode, GEN_INT (-1)),
+			       GEN_INT (0x6)));
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
+			       GEN_INT (0x6)));
+    }
+  
+  DONE;
+}")
+
+
+(define_insn "divmodsi4_internal"
+  [(set (match_operand:SI 0 "register_operand" "=l")
+	(div:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "register_operand" "d")))
+   (set (match_operand:SI 3 "register_operand" "=h")
+	(mod:SI (match_dup 1)
+		(match_dup 2)))
+   (clobber (match_scratch:SI 6 "=a"))]
+  "optimize && !0" ;;  CYGNUS LOCAL law
+  "div\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_expand "divmoddi4"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(div:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))
+   (set (match_operand:DI 3 "register_operand" "=d")
+	(mod:DI (match_dup 1)
+		(match_dup 2)))
+   (clobber (match_scratch:DI 4 "=l"))
+   (clobber (match_scratch:DI 5 "=h"))
+   (clobber (match_scratch:DI 6 "=a"))]
+  "TARGET_64BIT && optimize && !0" ;;  CYGNUS LOCAL law
+  "
+{
+  rtx label;
+
+  emit_insn (gen_divmoddi4_internal (operands[0], operands[1], operands[2],
+             operands[3]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  if (TARGET_CHECK_RANGE_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (DImode, GEN_INT (-1)),
+			       GEN_INT (0x6)));
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
+			       GEN_INT (0x6)));
+    }
+  
+  DONE;
+}")
+
+(define_insn "divmoddi4_internal"
+  [(set (match_operand:DI 0 "register_operand" "=l")
+	(div:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))
+   (set (match_operand:DI 3 "register_operand" "=h")
+	(mod:DI (match_dup 1)
+		(match_dup 2)))
+   (clobber (match_scratch:DI 6 "=a"))]
+  "TARGET_64BIT && optimize && !0" ;;  CYGNUS LOCAL law
+  "ddiv\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_expand "udivmodsi4"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(udiv:SI (match_operand:SI 1 "register_operand" "d")
+		 (match_operand:SI 2 "register_operand" "d")))
+   (set (match_operand:SI 3 "register_operand" "=d")
+	(umod:SI (match_dup 1)
+		 (match_dup 2)))
+   (clobber (match_scratch:SI 4 "=l"))
+   (clobber (match_scratch:SI 5 "=h"))
+   (clobber (match_scratch:SI 6 "=a"))]
+  "optimize"
+  "
+{
+  rtx label;
+
+  emit_insn (gen_udivmodsi4_internal (operands[0], operands[1], operands[2],
+                                      operands[3]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  
+  DONE;
+}")
+
+
+(define_insn "udivmodsi4_internal"
+  [(set (match_operand:SI 0 "register_operand" "=l")
+	(udiv:SI (match_operand:SI 1 "register_operand" "d")
+		 (match_operand:SI 2 "register_operand" "d")))
+   (set (match_operand:SI 3 "register_operand" "=h")
+	(umod:SI (match_dup 1)
+		 (match_dup 2)))
+   (clobber (match_scratch:SI 6 "=a"))]
+  "optimize && !0" ;;  CYGNUS LOCAL law
+  "divu\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_expand "udivmoddi4"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(udiv:DI (match_operand:DI 1 "se_register_operand" "d")
+		 (match_operand:DI 2 "se_register_operand" "d")))
+   (set (match_operand:DI 3 "register_operand" "=d")
+	(umod:DI (match_dup 1)
+		 (match_dup 2)))
+   (clobber (match_scratch:DI 4 "=l"))
+   (clobber (match_scratch:DI 5 "=h"))
+   (clobber (match_scratch:DI 6 "=a"))]
+  "TARGET_64BIT && optimize && !0" ;;  CYGNUS LOCAL law
+  "
+{
+  rtx label;
+
+  emit_insn (gen_udivmoddi4_internal (operands[0], operands[1], operands[2],
+                                      operands[3]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  
+  DONE;
+}")
+
+(define_insn "udivmoddi4_internal"
+  [(set (match_operand:DI 0 "register_operand" "=l")
+	(udiv:DI (match_operand:DI 1 "se_register_operand" "d")
+		 (match_operand:DI 2 "se_register_operand" "d")))
+   (set (match_operand:DI 3 "register_operand" "=h")
+	(umod:DI (match_dup 1)
+		 (match_dup 2)))
+   (clobber (match_scratch:DI 6 "=a"))]
+  "TARGET_64BIT && optimize && !0" ;;  CYGNUS LOCAL law
+  "ddivu\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+;; Division trap
+
+ ;; Division trap
+ 
+(define_expand "div_trap"
+   [(trap_if (eq (match_operand 0 "register_operand" "d")
+		(match_operand 1 "true_reg_or_0_operand" "dJ"))
+             (match_operand 2 "immediate_operand" ""))]
+   ""
+  "
+{
+  if (TARGET_MIPS16)
+    emit_insn (gen_div_trap_mips16 (operands[0],operands[1],operands[2]));
+  else
+    emit_insn (gen_div_trap_normal (operands[0],operands[1],operands[2]));
+  DONE;
+}")
+
+(define_insn "div_trap_normal"
+  [(trap_if (eq (match_operand 0 "register_operand" "d")
+		(match_operand 1 "true_reg_or_0_operand" "dJ"))
+            (match_operand 2 "immediate_operand" ""))]
+  "!TARGET_MIPS16"
+  "*
+{
+  rtx link;
+  int have_dep_anti = 0;
+
+  /* For divmod if one division is not needed then we don't need an extra
+     divide by zero trap, which is anti dependent on previous trap */
+  for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
+
+    if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
+        && GET_CODE (XEXP (link, 0)) == INSN
+        && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
+	&& REGNO (operands[1]) == 0)
+      have_dep_anti = 1;
+  if (! have_dep_anti)
+    {
+      if (GENERATE_BRANCHLIKELY)
+	{
+          if (GET_CODE (operands[1]) == CONST_INT)
+	    return \"%(beql\\t%0,$0,1f\\n\\tbreak\\t%2\\n1:%)\";
+	  else
+	    return \"%(beql\\t%0,%1,1f\\n\\tbreak\\t%2\\n1:%)\";
+	}
+      else
+	{
+          if (GET_CODE (operands[1]) == CONST_INT)
+	    return \"%(bne\\t%0,$0,1f\\n\\tnop\\n\\tbreak\\t%2\\n1:%)\";
+	  else
+	    return \"%(bne\\t%0,%1,1f\\n\\tnop\\n\\tbreak\\t%2\\n1:%)\";
+	}
+    }
+  return \"\";
+}"
+  [(set_attr "type" "unknown")
+   (set_attr "length" "3")])
+
+
+;; The mips16 bne insns is a macro which uses reg 24 as an intermediate.
+
+(define_insn "div_trap_mips16"
+  [(trap_if (eq (match_operand 0 "register_operand" "d")
+		(match_operand 1 "true_reg_or_0_operand" "dJ"))
+            (match_operand 2 "immediate_operand" ""))
+   (clobber (reg:SI 24))]
+  "TARGET_MIPS16"
+  "*
+{
+  rtx link;
+  int have_dep_anti = 0;
+
+  /* For divmod if one division is not needed then we don't need an extra
+     divide by zero trap, which is anti dependent on previous trap */
+  for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
+
+    if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
+        && GET_CODE (XEXP (link, 0)) == INSN
+        && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
+	&& REGNO (operands[1]) == 0)
+      have_dep_anti = 1;
+  if (! have_dep_anti)
+    {
+      /* No branch delay slots on mips16. */ 
+      if (GET_CODE (operands[1]) == CONST_INT)
+        return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n1:%)\";
+      else
+        return \"%(bne\\t%0,%1,1f\\n\\tbreak\\t%2\\n1:%)\";
+    }
+  return \"\";
+}"
+  [(set_attr "type" "unknown")
+   (set_attr "length" "3")])
+
+(define_expand "divsi3"
+  [(set (match_operand:SI 0 "register_operand" "=l")
+	(div:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_scratch:SI 3 "=h"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "!optimize"
+  "
+{
+  rtx label;
+
+  emit_insn (gen_divsi3_internal (operands[0], operands[1], operands[2]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  if (TARGET_CHECK_RANGE_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (SImode, GEN_INT (-1)),
+			       GEN_INT (0x6)));
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
+			       GEN_INT (0x6)));
+    }
+  
+  DONE;
+}")
+
+(define_insn "divsi3_internal"
+  [(set (match_operand:SI 0 "register_operand" "=l")
+	(div:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "nonmemory_operand" "di")))
+   (clobber (match_scratch:SI 3 "=h"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "!optimize"
+  "div\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_expand "divdi3"
+  [(set (match_operand:DI 0 "register_operand" "=l")
+	(div:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d"))) 
+   (clobber (match_scratch:DI 3 "=h"))
+   (clobber (match_scratch:DI 4 "=a"))]
+  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
+  "
+{
+  rtx label;
+
+  emit_insn (gen_divdi3_internal (operands[0], operands[1], operands[2]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  if (TARGET_CHECK_RANGE_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (DImode, GEN_INT (-1)),
+			       GEN_INT (0x6)));
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
+			       GEN_INT (0x6)));
+    }
+  
+  DONE;
+}")
+
+(define_insn "divdi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=l")
+	(div:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_nonmemory_operand" "di")))
+   (clobber (match_scratch:SI 3 "=h"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
+  "ddiv\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_expand "modsi3"
+  [(set (match_operand:SI 0 "register_operand" "=h")
+	(mod:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_scratch:SI 3 "=l"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "!optimize"
+  "
+{
+  rtx label;
+
+  emit_insn (gen_modsi3_internal (operands[0], operands[1], operands[2]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  if (TARGET_CHECK_RANGE_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (SImode, GEN_INT (-1)),
+			       GEN_INT (0x6)));
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
+			       GEN_INT (0x6)));
+    }
+  
+  DONE;
+}")
+
+(define_insn "modsi3_internal"
+  [(set (match_operand:SI 0 "register_operand" "=h")
+	(mod:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "nonmemory_operand" "di")))
+   (clobber (match_scratch:SI 3 "=l"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "!optimize"
+  "div\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_expand "moddi3"
+  [(set (match_operand:DI 0 "register_operand" "=h")
+	(mod:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))
+   (clobber (match_scratch:DI 3 "=l"))
+   (clobber (match_scratch:DI 4 "=a"))]
+  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
+  "
+{
+  rtx label;
+
+  emit_insn (gen_moddi3_internal (operands[0], operands[1], operands[2]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  if (TARGET_CHECK_RANGE_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (DImode, GEN_INT (-1)),
+			       GEN_INT (0x6)));
+      emit_insn (gen_div_trap (operands[2],
+			       copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
+			       GEN_INT (0x6)));
+    }
+  
+  DONE;
+}")
+
+(define_insn "moddi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=h")
+	(mod:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_nonmemory_operand" "di")))
+   (clobber (match_scratch:SI 3 "=l"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
+  "ddiv\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_expand "udivsi3"
+  [(set (match_operand:SI 0 "register_operand" "=l")
+	(udiv:SI (match_operand:SI 1 "register_operand" "d")
+		 (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_scratch:SI 3 "=h"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "!optimize"
+  "
+{
+  rtx label;
+
+  emit_insn (gen_udivsi3_internal (operands[0], operands[1], operands[2]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  
+  DONE;
+}")
+
+(define_insn "udivsi3_internal"
+  [(set (match_operand:SI 0 "register_operand" "=l")
+	(udiv:SI (match_operand:SI 1 "register_operand" "d")
+		 (match_operand:SI 2 "nonmemory_operand" "di")))
+   (clobber (match_scratch:SI 3 "=h"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "!optimize"
+  "divu\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_expand "udivdi3"
+  [(set (match_operand:DI 0 "register_operand" "=l")
+	(udiv:DI (match_operand:DI 1 "se_register_operand" "d")
+		 (match_operand:DI 2 "se_register_operand" "di")))
+   (clobber (match_scratch:DI 3 "=h"))
+   (clobber (match_scratch:DI 4 "=a"))]
+  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
+  "
+{
+  rtx label;
+
+  emit_insn (gen_udivdi3_internal (operands[0], operands[1], operands[2]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  
+  DONE;
+}")
+
+(define_insn "udivdi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=l")
+	(udiv:DI (match_operand:DI 1 "se_register_operand" "d")
+		 (match_operand:DI 2 "se_nonmemory_operand" "di")))
+   (clobber (match_scratch:SI 3 "=h"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
+  "ddivu\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_expand "umodsi3"
+  [(set (match_operand:SI 0 "register_operand" "=h")
+	(umod:SI (match_operand:SI 1 "register_operand" "d")
+		 (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_scratch:SI 3 "=l"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "!optimize"
+  "
+{
+  rtx label;
+
+  emit_insn (gen_umodsi3_internal (operands[0], operands[1], operands[2]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  
+  DONE;
+}")
+
+(define_insn "umodsi3_internal"
+  [(set (match_operand:SI 0 "register_operand" "=h")
+	(umod:SI (match_operand:SI 1 "register_operand" "d")
+		 (match_operand:SI 2 "nonmemory_operand" "di")))
+   (clobber (match_scratch:SI 3 "=l"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "!optimize"
+  "divu\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_expand "umoddi3"
+  [(set (match_operand:DI 0 "register_operand" "=h")
+	(umod:DI (match_operand:DI 1 "se_register_operand" "d")
+		 (match_operand:DI 2 "se_register_operand" "di")))
+   (clobber (match_scratch:DI 3 "=l"))
+   (clobber (match_scratch:DI 4 "=a"))]
+  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
+  "
+{
+  rtx label;
+
+  emit_insn (gen_umoddi3_internal (operands[0], operands[1], operands[2]));
+  if (!TARGET_NO_CHECK_ZERO_DIV)
+    {
+      emit_insn (gen_div_trap (operands[2],
+			       GEN_INT (0),
+			       GEN_INT (0x7)));
+    }
+  
+  DONE;
+}")
+
+(define_insn "umoddi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=h")
+	(umod:DI (match_operand:DI 1 "se_register_operand" "d")
+		 (match_operand:DI 2 "se_nonmemory_operand" "di")))
+   (clobber (match_scratch:SI 3 "=l"))
+   (clobber (match_scratch:SI 4 "=a"))]
+  "TARGET_64BIT && !optimize && !0" ;;  CYGNUS LOCAL law
+  "ddivu\\t$0,%1,%2"
+  [(set_attr "type"	"idiv")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+;;  ....................
+;;	SQUARE ROOT
+;;  ....................
+
+(define_insn "sqrtdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
+  "sqrt.d\\t%0,%1"
+  [(set_attr "type"	"fsqrt")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn "sqrtsf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
+  "sqrt.s\\t%0,%1"
+  [(set_attr "type"	"fsqrt")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(div:DF (match_operand:DF 1 "const_float_1_operand" "")
+		(sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
+  "rsqrt.d\\t%0,%2"
+  [(set_attr "type"	"frsqrt") ; CYGNUS LOCAL vr5400/raeburn
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(div:SF (match_operand:SF 1 "const_float_1_operand" "")
+		(sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
+  "rsqrt.s\\t%0,%2"
+  [(set_attr "type"	"frsqrt") ; CYGNUS LOCAL vr5400/raeburn
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+
+;;  ....................
+;;	ABSOLUTE VALUE
+;;  ....................
+
+;; Do not use the integer abs macro instruction, since that signals an
+;; exception on -2147483648 (sigh).
+
+(define_insn "abssi2"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(abs:SI (match_operand:SI 1 "register_operand" "d")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  dslots_jump_total++;
+  dslots_jump_filled++;
+  operands[2] = const0_rtx;
+
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    {
+      if (GENERATE_BRANCHLIKELY)
+	return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
+      else
+	return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n1:\";
+    }	  
+  else
+    return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
+}"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"3")])
+
+(define_insn "absdi2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(abs:DI (match_operand:DI 1 "se_register_operand" "d")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "*
+{
+  dslots_jump_total++;
+  dslots_jump_filled++;
+  operands[2] = const0_rtx;
+
+  if (REGNO (operands[0]) == REGNO (operands[1]))
+    return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\";
+  else
+    return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\";
+}"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"3")])
+
+(define_insn "absdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(abs:DF (match_operand:DF 1 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "abs.d\\t%0,%1"
+  [(set_attr "type"	"fabs")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn "abssf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(abs:SF (match_operand:SF 1 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "abs.s\\t%0,%1"
+  [(set_attr "type"	"fabs")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+
+;;  ....................
+;;	FIND FIRST BIT INSTRUCTION
+;;  ....................
+
+(define_insn "ffssi2"
+  [(set (match_operand:SI 0 "register_operand" "=&d")
+	(ffs:SI (match_operand:SI 1 "register_operand" "d")))
+   (clobber (match_scratch:SI 2 "=&d"))
+   (clobber (match_scratch:SI 3 "=&d"))]
+  "!TARGET_MIPS16"
+  "*
+{
+  dslots_jump_total += 2;
+  dslots_jump_filled += 2;
+  operands[4] = const0_rtx;
+
+  if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
+    return \"%(\\
+move\\t%0,%z4\\n\\
+\\tbeq\\t%1,%z4,2f\\n\\
+1:\\tand\\t%2,%1,0x0001\\n\\
+\\taddu\\t%0,%0,1\\n\\
+\\tbeq\\t%2,%z4,1b\\n\\
+\\tsrl\\t%1,%1,1\\n\\
+2:%)\";
+
+  return \"%(\\
+move\\t%0,%z4\\n\\
+\\tmove\\t%3,%1\\n\\
+\\tbeq\\t%3,%z4,2f\\n\\
+1:\\tand\\t%2,%3,0x0001\\n\\
+\\taddu\\t%0,%0,1\\n\\
+\\tbeq\\t%2,%z4,1b\\n\\
+\\tsrl\\t%3,%3,1\\n\\
+2:%)\";
+}"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"6")])
+
+(define_insn "ffsdi2"
+  [(set (match_operand:DI 0 "register_operand" "=&d")
+	(ffs:DI (match_operand:DI 1 "se_register_operand" "d")))
+   (clobber (match_scratch:DI 2 "=&d"))
+   (clobber (match_scratch:DI 3 "=&d"))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "*
+{
+  dslots_jump_total += 2;
+  dslots_jump_filled += 2;
+  operands[4] = const0_rtx;
+
+  if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
+    return \"%(\\
+move\\t%0,%z4\\n\\
+\\tbeq\\t%1,%z4,2f\\n\\
+1:\\tand\\t%2,%1,0x0001\\n\\
+\\tdaddu\\t%0,%0,1\\n\\
+\\tbeq\\t%2,%z4,1b\\n\\
+\\tdsrl\\t%1,%1,1\\n\\
+2:%)\";
+
+  return \"%(\\
+move\\t%0,%z4\\n\\
+\\tmove\\t%3,%1\\n\\
+\\tbeq\\t%3,%z4,2f\\n\\
+1:\\tand\\t%2,%3,0x0001\\n\\
+\\tdaddu\\t%0,%0,1\\n\\
+\\tbeq\\t%2,%z4,1b\\n\\
+\\tdsrl\\t%3,%3,1\\n\\
+2:%)\";
+}"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"6")])
+
+
+;;  ....................
+;;	NEGATION and ONE'S COMPLEMENT
+;;  ....................
+
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(neg:SI (match_operand:SI 1 "register_operand" "d")))]
+  ""
+  "*
+{
+  if (TARGET_MIPS16)
+    return \"neg\\t%0,%1\";
+  operands[2] = const0_rtx;
+  return \"subu\\t%0,%z2,%1\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_expand "negdi2"
+  [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
+		   (neg:DI (match_operand:DI 1 "se_register_operand" "d")))
+	      (clobber (match_dup 2))])]
+  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
+  "
+{
+  if (TARGET_64BIT)
+    {
+      emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
+      DONE;
+    }
+
+  operands[2] = gen_reg_rtx (SImode);
+}")
+
+(define_insn "negdi2_internal"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(neg:DI (match_operand:DI 1 "register_operand" "d")))
+   (clobber (match_operand:SI 2 "register_operand" "=d"))]
+  "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
+  "*
+{
+  operands[3] = const0_rtx;
+  return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+
+(define_insn "negdi2_internal_2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(neg:DI (match_operand:DI 1 "se_register_operand" "d")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "*
+{
+  operands[2] = const0_rtx;
+  return \"dsubu\\t%0,%z2,%1\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn "negdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(neg:DF (match_operand:DF 1 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "neg.d\\t%0,%1"
+  [(set_attr "type"	"fneg")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn "negsf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "neg.s\\t%0,%1"
+  [(set_attr "type"	"fneg")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(not:SI (match_operand:SI 1 "register_operand" "d")))]
+  ""
+  "*
+{
+  if (TARGET_MIPS16)
+    return \"not\\t%0,%1\";
+  operands[2] = const0_rtx;
+  return \"nor\\t%0,%z2,%1\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "one_cmpldi2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(not:DI (match_operand:DI 1 "se_register_operand" "d")))]
+  ""
+  "*
+{
+  if (TARGET_MIPS16)
+    {
+      if (TARGET_64BIT)
+	return \"not\\t%0,%1\";
+      return \"not\\t%M0,%M1\;not\\t%L0,%L1\";
+    }
+  operands[2] = const0_rtx;
+  if (TARGET_64BIT)
+    return \"nor\\t%0,%z2,%1\";
+  return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")
+	(if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
+		       (const_int 1)
+		       (const_int 2)))])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(not:DI (match_operand:DI 1 "register_operand" "")))]
+  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
+
+  [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
+   (set (subreg:SI (match_dup 0) 1) (not:SI (subreg:SI (match_dup 1) 1)))]
+  "")
+
+
+;;  ....................
+;;	LOGICAL
+;;  ....................
+
+;; Many of these instructions uses trivial define_expands, because we
+;; want to use a different set of constraints when TARGET_MIPS16.
+
+(define_expand "andsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
+		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
+  ""
+  "
+{
+  if (TARGET_MIPS16)
+    operands[2] = force_reg (SImode, operands[2]);
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
+		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
+  "!TARGET_MIPS16"
+  "@
+   and\\t%0,%1,%2
+   andi\\t%0,%1,%x2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(and:SI (match_operand:SI 1 "register_operand" "%0")
+		(match_operand:SI 2 "register_operand" "d")))]
+  "TARGET_MIPS16"
+  "and\\t%0,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_expand "anddi3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(and:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
+  "
+{
+  if (TARGET_MIPS16)
+    operands[2] = force_reg (DImode, operands[2]);
+}")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(and:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
+  "*
+{
+  if (TARGET_64BIT)
+    return \"and\\t%0,%1,%2\";
+  return \"and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")
+	(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+		       (const_int 1)
+		       (const_int 2)))])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(and:DI (match_operand:DI 1 "se_register_operand" "0")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16"
+  "*
+{
+  if (TARGET_64BIT)
+    return \"and\\t%0,%2\";
+  return \"and\\t%M0,%M2\;and\\t%L0,%L2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")
+	(if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
+		       (const_int 1)
+		       (const_int 2)))])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(and:DI (match_operand:DI 1 "register_operand" "")
+		(match_operand:DI 2 "register_operand" "")))]
+  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
+
+  [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
+   (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
+  "")
+
+(define_insn "anddi3_internal1"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(and:DI (match_operand:DI 1 "se_register_operand" "%d,d")
+		(match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "@
+   and\\t%0,%1,%2
+   andi\\t%0,%1,%x2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_expand "iorsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
+		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
+  ""
+  "
+{
+  if (TARGET_MIPS16)
+    operands[2] = force_reg (SImode, operands[2]);
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
+		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
+  "!TARGET_MIPS16"
+  "@
+   or\\t%0,%1,%2
+   ori\\t%0,%1,%x2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ior:SI (match_operand:SI 1 "register_operand" "%0")
+		(match_operand:SI 2 "register_operand" "d")))]
+  "TARGET_MIPS16"
+  "or\\t%0,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+;;; ??? There is no iordi3 pattern which accepts 'K' constants when
+;;; TARGET_64BIT
+
+(define_expand "iordi3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ior:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
+  "")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ior:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
+  "*
+{
+  if (TARGET_64BIT)
+    return \"or\\t%0,%1,%2\";
+  return \"or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")
+	(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+		       (const_int 1)
+		       (const_int 2)))])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ior:DI (match_operand:DI 1 "se_register_operand" "0")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16"
+  "*
+{
+  if (TARGET_64BIT)
+    return \"or\\t%0,%2\";
+  return \"or\\t%M0,%M2\;or\\t%L0,%L2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")
+	(if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
+		       (const_int 1)
+		       (const_int 2)))])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ior:DI (match_operand:DI 1 "register_operand" "")
+		(match_operand:DI 2 "register_operand" "")))]
+  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
+
+  [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
+   (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
+  "")
+
+(define_expand "xorsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
+		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
+		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
+  "!TARGET_MIPS16"
+  "@
+   xor\\t%0,%1,%2
+   xori\\t%0,%1,%x2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,t,t")
+	(xor:SI (match_operand:SI 1 "uns_arith_operand" "%0,d,d")
+		(match_operand:SI 2 "uns_arith_operand" "d,K,d")))]
+  "TARGET_MIPS16"
+  "@
+   xor\\t%0,%2
+   cmpi\\t%1,%2
+   cmp\\t%1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (const_int 1)])])
+
+;; ??? If delete the 32-bit long long patterns, then could merge this with
+;; the following xordi3_internal pattern.
+(define_expand "xordi3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(xor:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
+  "")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(xor:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
+  "*
+{
+  if (TARGET_64BIT)
+    return \"xor\\t%0,%1,%2\";
+  return \"xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")
+	(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+		       (const_int 1)
+		       (const_int 2)))])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(xor:DI (match_operand:DI 1 "se_register_operand" "0")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "!TARGET_64BIT && TARGET_MIPS16"
+  "xor\\t%M0,%M2\;xor\\t%L0,%L2"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,t,t")
+	(xor:DI (match_operand:DI 1 "se_register_operand" "%0,d,d")
+		(match_operand:DI 2 "se_uns_arith_operand" "d,K,d")))]
+  "TARGET_64BIT && TARGET_MIPS16"
+  "@
+   xor\\t%0,%2
+   cmpi\\t%1,%2
+   cmp\\t%1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (const_int 1)])])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(xor:DI (match_operand:DI 1 "register_operand" "")
+		(match_operand:DI 2 "register_operand" "")))]
+  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
+
+  [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
+   (set (subreg:SI (match_dup 0) 1) (xor:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
+  "")
+
+(define_insn "xordi3_immed"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(xor:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_uns_arith_operand" "K")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "xori\\t%0,%1,%x2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn "*norsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
+		(not:SI (match_operand:SI 2 "register_operand" "d"))))]
+  "!TARGET_MIPS16"
+  "nor\\t%0,%z1,%z2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "*nordi3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(and:DI (not:DI (match_operand:DI 1 "se_register_operand" "d"))
+		(not:DI (match_operand:DI 2 "se_register_operand" "d"))))]
+  "!TARGET_MIPS16"
+  "*
+{
+  if (TARGET_64BIT)
+    return \"nor\\t%0,%z1,%z2\";
+  return \"nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set (attr "length")
+	(if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+		       (const_int 1)
+		       (const_int 2)))])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(and:DI (not:DI (match_operand:DI 1 "register_operand" ""))
+		(not:DI (match_operand:DI 2 "register_operand" ""))))]
+  "reload_completed && !TARGET_MIPS16 && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+   && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
+
+  [(set (subreg:SI (match_dup 0) 0) (and:SI (not:SI (subreg:SI (match_dup 1) 0)) (not:SI (subreg:SI (match_dup 2) 0))))
+   (set (subreg:SI (match_dup 0) 1) (and:SI (not:SI (subreg:SI (match_dup 1) 1)) (not:SI (subreg:SI (match_dup 2) 1))))]
+  "")
+
+;;  ....................
+;;	TRUNCATION
+;;  ....................
+
+(define_insn "truncdfsf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "cvt.s.d\\t%0,%1"
+  [(set_attr "type"	"fcvt")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn "truncdisi2"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(truncate:SI (match_operand:DI 1 "se_register_operand" "d")))]
+  "TARGET_64BIT"
+  "*
+{
+  if (TARGET_MIPS16)
+    return \"dsll\\t%0,%1,32\;dsra\\t%0,32\";
+  return \"dsll\\t%0,%1,32\;dsra\\t%0,%0,32\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"SI")
+   (set (attr "length")	(if_then_else (eq (symbol_ref "mips16") (const_int 0))
+				      (const_int 2)
+				      (const_int 4)))])
+
+(define_insn "truncdihi2"
+  [(set (match_operand:HI 0 "register_operand" "=d")
+	(truncate:HI (match_operand:DI 1 "se_register_operand" "d")))]
+  "TARGET_64BIT"
+  "*
+{
+  if (TARGET_MIPS16)
+    return \"dsll\\t%0,%1,48\;dsra\\t%0,48\";
+  return \"andi\\t%0,%1,0xffff\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"HI")
+   (set (attr "length")	(if_then_else (eq (symbol_ref "mips16") (const_int 0))
+				      (const_int 1)
+				      (const_int 4)))])
+(define_insn "truncdiqi2"
+  [(set (match_operand:QI 0 "register_operand" "=d")
+	(truncate:QI (match_operand:DI 1 "se_register_operand" "d")))]
+  "TARGET_64BIT"
+  "*
+{
+  if (TARGET_MIPS16)
+    return \"dsll\\t%0,%1,56\;dsra\\t%0,56\";
+  return \"andi\\t%0,%1,0x00ff\"; 
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"QI")
+   (set (attr "length")	(if_then_else (eq (symbol_ref "mips16") (const_int 0))
+				      (const_int 1)
+				      (const_int 4)))])
+
+;; Combiner patterns to optimize shift/truncate combinations.
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(truncate:SI (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
+				  (match_operand:DI 2 "small_int" "I"))))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "*
+{
+  int shift_amt = INTVAL (operands[2]) & 0x3f;
+
+  if (shift_amt < 32)
+    {
+      operands[2] = GEN_INT (32 - shift_amt);
+      return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
+    }
+  else
+    {
+      operands[2] = GEN_INT (shift_amt);
+      return \"dsra\\t%0,%1,%2\";
+    }
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+	
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(truncate:SI (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
+				  (match_operand:DI 2 "small_int" "I"))))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "*
+{
+  int shift_amt = INTVAL (operands[2]) & 0x3f;
+
+  if (shift_amt < 32)
+    {
+      operands[2] = GEN_INT (32 - shift_amt);
+      return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
+    }
+  else if (shift_amt == 32)
+    return \"dsra\\t%0,%1,32\";
+  else
+    {
+      operands[2] = GEN_INT (shift_amt);
+      return \"dsrl\\t%0,%1,%2\";
+    }
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(truncate:SI (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
+				(match_operand:DI 2 "small_int" "I"))))]
+  "TARGET_64BIT"
+  "*
+{
+  int shift_amt = INTVAL (operands[2]) & 0x3f;
+
+  if (shift_amt < 32)
+    {
+      operands[2] = GEN_INT (32 + shift_amt);
+      if (TARGET_MIPS16)
+	return \"dsll\\t%0,%1,%2\;dsra\\t%0,32\";
+      return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
+    }
+  else
+    return \"move\\t%0,%.\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
+;; Combiner patterns to optimize truncate/zero_extend combinations.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(zero_extend:SI (truncate:HI
+			 (match_operand:DI 1 "se_register_operand" "d"))))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "andi\\t%0,%1,0xffff"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(zero_extend:SI (truncate:QI
+			 (match_operand:DI 1 "se_register_operand" "d"))))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "andi\\t%0,%1,0xff"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=d")
+	(zero_extend:HI (truncate:QI
+			 (match_operand:DI 1 "se_register_operand" "d"))))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "andi\\t%0,%1,0xff"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"HI")
+   (set_attr "length"	"1")])
+
+;;  ....................
+;;	ZERO EXTENSION
+;;  ....................
+
+;; Extension insns.
+;; Those for integer source operand are ordered widest source type first.
+
+(define_expand "zero_extendsidi2"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
+  "TARGET_64BIT"
+  "
+{
+  if (optimize && GET_CODE (operands[1]) == MEM)
+    operands[1] = force_not_mem (operands[1]);
+
+  if (GET_CODE (operands[1]) != MEM)
+    {
+      rtx op1   = gen_lowpart (DImode, operands[1]);
+      rtx temp  = gen_reg_rtx (DImode);
+      rtx shift = GEN_INT (32);
+
+      emit_insn (gen_ashldi3 (temp, op1, shift));
+      emit_insn (gen_lshrdi3 (operands[0], temp, shift));
+      DONE;
+    }
+}")
+
+(define_insn "zero_extendsidi2_internal"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
+  "TARGET_64BIT"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,2")])
+
+(define_expand "zero_extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
+  ""
+  "
+{
+  if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
+    {
+      rtx op = gen_lowpart (SImode, operands[1]);
+      rtx temp = force_reg (SImode, GEN_INT (0xffff));
+
+      emit_insn (gen_andsi3 (operands[0], op, temp));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  if (which_alternative == 0)
+    return \"andi\\t%0,%1,0xffff\";
+  else
+    return mips_move_1word (operands, insn, TRUE);
+}"
+  [(set_attr "type"	"arith,load,load")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,1,2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(zero_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
+  "TARGET_MIPS16"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"load,load")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,2")])
+
+(define_expand "zero_extendhidi2"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
+  "TARGET_64BIT"
+  "
+{
+  if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
+    {
+      rtx op = gen_lowpart (DImode, operands[1]);
+      rtx temp = force_reg (DImode, GEN_INT (0xffff));
+
+      emit_insn (gen_anddi3 (operands[0], op, temp));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "*
+{
+  if (which_alternative == 0)
+    return \"andi\\t%0,%1,0xffff\";
+  else
+    return mips_move_1word (operands, insn, TRUE);
+}"
+  [(set_attr "type"	"arith,load,load")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,1,2")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(zero_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
+  "TARGET_64BIT && TARGET_MIPS16"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"load,load")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,2")])
+
+(define_expand "zero_extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "")
+	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
+  ""
+  "
+{
+  if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
+    {
+      rtx op0 = gen_lowpart (SImode, operands[0]);
+      rtx op1 = gen_lowpart (SImode, operands[1]);
+      rtx temp = force_reg (SImode, GEN_INT (0xff));
+
+      emit_insn (gen_andsi3 (op0, op1, temp));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=d,d,d")
+	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  if (which_alternative == 0)
+    return \"andi\\t%0,%1,0x00ff\";
+  else
+    return mips_move_1word (operands, insn, TRUE);
+}"
+  [(set_attr "type"	"arith,load,load")
+   (set_attr "mode"	"HI")
+   (set_attr "length"	"1,1,2")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=d,d")
+	(zero_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
+  "TARGET_MIPS16"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"load,load")
+   (set_attr "mode"	"HI")
+   (set_attr "length"	"1,2")])
+
+(define_expand "zero_extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
+  ""
+  "
+{
+  if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
+    {
+      rtx op = gen_lowpart (SImode, operands[1]);
+      rtx temp = force_reg (SImode, GEN_INT (0xff));
+
+      emit_insn (gen_andsi3 (operands[0], op, temp));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  if (which_alternative == 0)
+    return \"andi\\t%0,%1,0x00ff\";
+  else
+    return mips_move_1word (operands, insn, TRUE);
+}"
+  [(set_attr "type"	"arith,load,load")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,1,2")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(zero_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
+  "TARGET_MIPS16"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"load,load")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,2")])
+
+(define_expand "zero_extendqidi2"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
+  "TARGET_64BIT"
+  "
+{
+  if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
+    {
+      rtx op = gen_lowpart (DImode, operands[1]);
+      rtx temp = force_reg (DImode, GEN_INT (0xff));
+
+      emit_insn (gen_anddi3 (operands[0], op, temp));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "*
+{
+  if (which_alternative == 0)
+    return \"andi\\t%0,%1,0x00ff\";
+  else
+    return mips_move_1word (operands, insn, TRUE);
+}"
+  [(set_attr "type"	"arith,load,load")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,1,2")])
+
+;; These can be created when a paradoxical subreg operand with an implicit
+;; sign_extend operator is reloaded.  Because of the subreg, this is really
+;; a zero extend.
+;; ??? It might be possible to eliminate the need for these patterns by adding
+;; more support to reload for implicit sign_extend operators.
+(define_insn "*paradoxical_extendhidi2"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(sign_extend:DI
+	 (subreg:SI (match_operand:HI 1 "memory_operand" "R,m") 0)))]
+  "TARGET_64BIT"
+  "*
+{
+  return mips_move_1word (operands, insn, TRUE);
+}"
+  [(set_attr "type"	"load,load")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,2")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(zero_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
+  "TARGET_64BIT && TARGET_MIPS16"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"load,load")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,2")])
+
+;;  ....................
+;;	SIGN EXTENSION
+;;  ....................
+
+;; Extension insns.
+;; Those for integer source operand are ordered widest source type first.
+
+;; In 64 bit mode, 32 bit values in general registers are always
+;; correctly sign extended.  That means that if the target is a
+;; general register, we can sign extend from SImode to DImode just by
+;; doing a move.
+
+;; CYGNUS LOCAL law
+(define_insn "extendsidi2"
+  [(set (match_operand:DI 0 "register_operand" "=d,y,d,*d,d,d")
+	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,d,y,*x*w,R,m")))]
+  "TARGET_64BIT"
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"move,move,move,hilo,load,load")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,1,1,1,1,2")])
+
+;; These patterns originally accepted general_operands, however, slightly
+;; better code is generated by only accepting register_operands, and then
+;; letting combine generate the lh and lb insns.
+
+(define_expand "extendhidi2"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
+  "TARGET_64BIT"
+  "
+{
+  if (optimize && GET_CODE (operands[1]) == MEM)
+    operands[1] = force_not_mem (operands[1]);
+
+  if (GET_CODE (operands[1]) != MEM)
+    {
+      rtx op1   = gen_lowpart (DImode, operands[1]);
+      rtx temp  = gen_reg_rtx (DImode);
+      rtx shift = GEN_INT (48);
+
+      emit_insn (gen_ashldi3 (temp, op1, shift));
+      emit_insn (gen_ashrdi3 (operands[0], temp, shift));
+      DONE;
+    }
+}")
+
+(define_insn "extendhidi2_internal"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
+  "TARGET_64BIT"
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,2")])
+
+(define_expand "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
+  ""
+  "
+{
+  if (optimize && GET_CODE (operands[1]) == MEM)
+    operands[1] = force_not_mem (operands[1]);
+
+  if (GET_CODE (operands[1]) != MEM)
+    {
+      rtx op1   = gen_lowpart (SImode, operands[1]);
+      rtx temp  = gen_reg_rtx (SImode);
+      rtx shift = GEN_INT (16);
+
+      emit_insn (gen_ashlsi3 (temp, op1, shift));
+      emit_insn (gen_ashrsi3 (operands[0], temp, shift));
+      DONE;
+    }
+}")
+
+(define_insn "extendhisi2_internal"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
+  ""
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,2")])
+
+(define_expand "extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "")
+	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
+  ""
+  "
+{
+  if (optimize && GET_CODE (operands[1]) == MEM)
+    operands[1] = force_not_mem (operands[1]);
+
+  if (GET_CODE (operands[1]) != MEM)
+    {
+      rtx op0   = gen_lowpart (SImode, operands[0]);
+      rtx op1   = gen_lowpart (SImode, operands[1]);
+      rtx temp  = gen_reg_rtx (SImode);
+      rtx shift = GEN_INT (24);
+
+      emit_insn (gen_ashlsi3 (temp, op1, shift));
+      emit_insn (gen_ashrsi3 (op0, temp, shift));
+      DONE;
+    }
+}")
+
+(define_insn "extendqihi2_internal"
+  [(set (match_operand:HI 0 "register_operand" "=d,d")
+	(sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
+  ""
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,2")])
+
+
+(define_expand "extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
+  ""
+  "
+{
+  if (optimize && GET_CODE (operands[1]) == MEM)
+    operands[1] = force_not_mem (operands[1]);
+
+  if (GET_CODE (operands[1]) != MEM)
+    {
+      rtx op1   = gen_lowpart (SImode, operands[1]);
+      rtx temp  = gen_reg_rtx (SImode);
+      rtx shift = GEN_INT (24);
+
+      emit_insn (gen_ashlsi3 (temp, op1, shift));
+      emit_insn (gen_ashrsi3 (operands[0], temp, shift));
+      DONE;
+    }
+}")
+
+(define_insn "extendqisi2_insn"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
+  ""
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,2")])
+
+(define_expand "extendqidi2"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
+  "TARGET_64BIT"
+  "
+{
+  if (optimize && GET_CODE (operands[1]) == MEM)
+    operands[1] = force_not_mem (operands[1]);
+
+  if (GET_CODE (operands[1]) != MEM)
+    {
+      rtx op1   = gen_lowpart (DImode, operands[1]);
+      rtx temp  = gen_reg_rtx (DImode);
+      rtx shift = GEN_INT (56);
+
+      emit_insn (gen_ashldi3 (temp, op1, shift));
+      emit_insn (gen_ashrdi3 (operands[0], temp, shift));
+      DONE;
+    }
+}")
+
+(define_insn "extendqidi2_insn"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
+  "TARGET_64BIT"
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,2")])
+
+
+(define_insn "extendsfdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "cvt.d.s\\t%0,%1"
+  [(set_attr "type"	"fcvt")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+
+
+;;  ....................
+;;	CONVERSIONS
+;;  ....................
+
+;; The SImode scratch register can not be shared with address regs used for
+;; operand zero, because then the address in the move instruction will be
+;; clobbered.  We mark the scratch register as early clobbered to prevent this.
+
+;; We need the ?X in alternative 1 so that it will be choosen only if the
+;; destination is a floating point register.  Otherwise, alternative 1 can
+;; have lower cost than alternative 0 (because there is one less loser), and
+;; can be choosen when it won't work (because integral reloads into FP
+;; registers are not supported).
+
+(define_insn "fix_truncdfsi2"
+  [(set (match_operand:SI 0 "general_operand" "=d,*f,R,To")
+	(fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
+   (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
+   (clobber (match_scratch:DF 3 "=f,?*X,f,f"))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  rtx xoperands[10];
+
+  if (which_alternative == 1)
+    return \"trunc.w.d %0,%1,%2\";
+
+  output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
+
+  xoperands[0] = operands[0];
+  xoperands[1] = operands[3];
+  output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
+  return \"\";
+}"
+  [(set_attr "type"	"fcvt")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"11,9,10,11")])
+
+
+(define_insn "fix_truncsfsi2"
+  [(set (match_operand:SI 0 "general_operand" "=d,*f,R,To")
+	(fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
+   (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
+   (clobber (match_scratch:SF 3 "=f,?*X,f,f"))]
+  "TARGET_HARD_FLOAT && !0" ;;  CYGNUS LOCAL law
+  "*
+{
+  rtx xoperands[10];
+
+  if (which_alternative == 1)
+    return \"trunc.w.s %0,%1,%2\";
+
+  output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
+
+  xoperands[0] = operands[0];
+  xoperands[1] = operands[3];
+  output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
+  return \"\";
+}"
+  [(set_attr "type"	"fcvt")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"11,9,10,11")])
+
+
+;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
+;;; but not in the chapter that describes the FPU.  It is not mentioned at all
+;;; in the 1991 manuals.  The r4000 at Cygnus does not have this instruction.
+
+;;; Deleting this means that we now need two libgcc2.a libraries.  One for
+;;; the 32 bit calling convention and one for the 64 bit calling convention.
+
+;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
+
+(define_insn "fix_truncdfdi2"
+  [(set (match_operand:DI 0 "general_operand" "=d,*f,R,To")
+	(fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
+   (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
+  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  rtx xoperands[10];
+
+  if (which_alternative == 1)
+    return \"trunc.l.d %0,%1\";
+
+  output_asm_insn (\"trunc.l.d %2,%1\", operands);
+
+  xoperands[0] = operands[0];
+  xoperands[1] = operands[2];
+  output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands);
+  return \"\";
+}"
+  [(set_attr "type"	"fcvt")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"2,1,2,3")])
+
+
+;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
+;;; but not in the chapter that describes the FPU.  It is not mentioned at all
+;;; in the 1991 manuals.  The r4000 at Cygnus does not have this instruction.
+(define_insn "fix_truncsfdi2"
+  [(set (match_operand:DI 0 "general_operand" "=d,*f,R,To")
+	(fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
+   (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
+  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  rtx xoperands[10];
+
+  if (which_alternative == 1)
+    return \"trunc.l.s %0,%1\";
+
+  output_asm_insn (\"trunc.l.s %2,%1\", operands);
+
+  xoperands[0] = operands[0];
+  xoperands[1] = operands[2];
+  output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands);
+  return \"\";
+}"
+  [(set_attr "type"	"fcvt")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"2,1,2,3")])
+
+
+(define_insn "floatsidf2"
+  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
+	(float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  dslots_load_total++;
+  if (GET_CODE (operands[1]) == MEM)
+    return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
+
+  return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
+}"
+  [(set_attr "type"	"fcvt")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"3,4,3")])
+
+
+(define_insn "floatdidf2"
+  [(set (match_operand:DF 0 "register_operand" "=f,f,f")
+	(float:DF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
+  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  dslots_load_total++;
+  if (GET_CODE (operands[1]) == MEM)
+    return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\";
+
+  return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\";
+}"
+  [(set_attr "type"	"fcvt")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"3,4,3")])
+
+
+(define_insn "floatsisf2"
+  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
+	(float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
+  "TARGET_HARD_FLOAT"
+  "*
+{
+  dslots_load_total++;
+  if (GET_CODE (operands[1]) == MEM)
+    return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
+
+  return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
+}"
+  [(set_attr "type"	"fcvt")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"3,4,3")])
+
+
+(define_insn "floatdisf2"
+  [(set (match_operand:SF 0 "register_operand" "=f,f,f")
+	(float:SF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
+  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  dslots_load_total++;
+  if (GET_CODE (operands[1]) == MEM)
+    return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\";
+
+  return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\";
+}"
+  [(set_attr "type"	"fcvt")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"3,4,3")])
+
+
+(define_expand "fixuns_truncdfsi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "
+{
+  rtx reg1 = gen_reg_rtx (DFmode);
+  rtx reg2 = gen_reg_rtx (DFmode);
+  rtx reg3 = gen_reg_rtx (SImode);
+  rtx label1 = gen_label_rtx ();
+  rtx label2 = gen_label_rtx ();
+  REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
+
+  if (reg1)			/* turn off complaints about unreached code */
+    {
+      emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
+      do_pending_stack_adjust ();
+
+      emit_insn (gen_cmpdf (operands[1], reg1));
+      emit_jump_insn (gen_bge (label1));
+
+      emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
+      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
+			       gen_rtx (LABEL_REF, VOIDmode, label2)));
+      emit_barrier ();
+
+      emit_label (label1);
+      emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
+      emit_move_insn (reg3, GEN_INT (0x80000000));
+
+      emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
+      emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
+
+      emit_label (label2);
+
+      /* allow REG_NOTES to be set on last insn (labels don't have enough
+	 fields, and can't be used for REG_NOTES anyway).  */
+      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
+      DONE;
+    }
+}")
+
+
+(define_expand "fixuns_truncdfdi2"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
+  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
+  "
+{
+  rtx reg1 = gen_reg_rtx (DFmode);
+  rtx reg2 = gen_reg_rtx (DFmode);
+  rtx reg3 = gen_reg_rtx (DImode);
+  rtx label1 = gen_label_rtx ();
+  rtx label2 = gen_label_rtx ();
+  REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
+
+  if (reg1)			/* turn off complaints about unreached code */
+    {
+      emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
+      do_pending_stack_adjust ();
+
+      emit_insn (gen_cmpdf (operands[1], reg1));
+      emit_jump_insn (gen_bge (label1));
+
+      emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
+      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
+			       gen_rtx (LABEL_REF, VOIDmode, label2)));
+      emit_barrier ();
+
+      emit_label (label1);
+      emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
+      emit_move_insn (reg3, GEN_INT (0x80000000));
+      emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
+
+      emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
+      emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
+
+      emit_label (label2);
+
+      /* allow REG_NOTES to be set on last insn (labels don't have enough
+	 fields, and can't be used for REG_NOTES anyway).  */
+      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
+      DONE;
+    }
+}")
+
+
+(define_expand "fixuns_truncsfsi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
+  "TARGET_HARD_FLOAT && !0" ;;  CYGNUS LOCAL law
+  "
+{
+  rtx reg1 = gen_reg_rtx (SFmode);
+  rtx reg2 = gen_reg_rtx (SFmode);
+  rtx reg3 = gen_reg_rtx (SImode);
+  rtx label1 = gen_label_rtx ();
+  rtx label2 = gen_label_rtx ();
+  REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
+
+  if (reg1)			/* turn off complaints about unreached code */
+    {
+      emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
+      do_pending_stack_adjust ();
+
+      emit_insn (gen_cmpsf (operands[1], reg1));
+      emit_jump_insn (gen_bge (label1));
+
+      emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
+      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
+			       gen_rtx (LABEL_REF, VOIDmode, label2)));
+      emit_barrier ();
+
+      emit_label (label1);
+      emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
+      emit_move_insn (reg3, GEN_INT (0x80000000));
+
+      emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
+      emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
+
+      emit_label (label2);
+
+      /* allow REG_NOTES to be set on last insn (labels don't have enough
+	 fields, and can't be used for REG_NOTES anyway).  */
+      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
+      DONE;
+    }
+}")
+
+
+(define_expand "fixuns_truncsfdi2"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
+  "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
+  "
+{
+  rtx reg1 = gen_reg_rtx (SFmode);
+  rtx reg2 = gen_reg_rtx (SFmode);
+  rtx reg3 = gen_reg_rtx (DImode);
+  rtx label1 = gen_label_rtx ();
+  rtx label2 = gen_label_rtx ();
+  REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
+
+  if (reg1)			/* turn off complaints about unreached code */
+    {
+      emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
+      do_pending_stack_adjust ();
+
+      emit_insn (gen_cmpsf (operands[1], reg1));
+      emit_jump_insn (gen_bge (label1));
+
+      emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
+      emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
+			       gen_rtx (LABEL_REF, VOIDmode, label2)));
+      emit_barrier ();
+
+      emit_label (label1);
+      emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
+      emit_move_insn (reg3, GEN_INT (0x80000000));
+      emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
+
+      emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
+      emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
+
+      emit_label (label2);
+
+      /* allow REG_NOTES to be set on last insn (labels don't have enough
+	 fields, and can't be used for REG_NOTES anyway).  */
+      emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
+      DONE;
+    }
+}")
+
+
+;;  ....................
+;;	DATA MOVEMENT
+;;  ....................
+
+;; Bit field extract patterns which use lwl/lwr.
+
+;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
+;; It isn't clear whether this will give better code.
+
+;; Only specify the mode operand 1, the rest are assumed to be word_mode.
+(define_expand "extv"
+  [(set (match_operand 0 "register_operand" "")
+	(sign_extract (match_operand:QI 1 "memory_operand" "")
+		      (match_operand 2 "immediate_operand" "")
+		      (match_operand 3 "immediate_operand" "")))]
+  "!TARGET_MIPS16"
+  "
+{
+  /* If the field does not start on a byte boundary, then fail.  */
+  if (INTVAL (operands[3]) % 8 != 0) 
+    FAIL;
+
+  /* MIPS I and MIPS II can only handle a 32bit field.  */
+  if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
+    FAIL;
+
+  /* MIPS III and MIPS IV can handle both 32bit and 64bit fields.  */
+  if (TARGET_64BIT
+      && INTVAL (operands[2]) != 64
+      && INTVAL (operands[2]) != 32)
+    FAIL;
+
+  /* This can happen for a 64 bit target, when extracting a value from
+     a 64 bit union member.  extract_bit_field doesn't verify that our
+     source matches the predicate, so we force it to be a MEM here.  */
+  if (GET_CODE (operands[1]) != MEM)
+    FAIL;
+
+  /* Change the mode to BLKmode for aliasing purposes.  */
+  operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0));
+
+  /* Otherwise, emit a l[wd]l/l[wd]r pair to load the value.  */
+  if (INTVAL (operands[2]) == 64)
+    emit_insn (gen_movdi_uld (operands[0], operands[1]));
+  else
+    {
+      if (TARGET_64BIT)
+	{
+	  operands[0] = gen_lowpart (SImode, operands[0]);
+	  if (operands[0] == NULL_RTX)
+	    FAIL;
+	}
+      emit_insn (gen_movsi_ulw (operands[0], operands[1]));
+    }
+  DONE;
+}")
+
+;; Only specify the mode operand 1, the rest are assumed to be word_mode.
+(define_expand "extzv"
+  [(set (match_operand 0 "register_operand" "")
+	(zero_extract (match_operand:QI 1 "memory_operand" "")
+		      (match_operand 2 "immediate_operand" "")
+		      (match_operand 3 "immediate_operand" "")))]
+  "!TARGET_MIPS16"
+  "
+{
+  /* If the field does not start on a byte boundary, then fail.  */
+  if (INTVAL (operands[3]) % 8 != 0) 
+    FAIL;
+
+  /* MIPS I and MIPS II can only handle a 32bit field.  */
+  if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
+    FAIL;
+
+  /* MIPS III and MIPS IV can handle both 32bit and 64bit fields.  */
+  if (TARGET_64BIT
+      && INTVAL (operands[2]) != 64
+      && INTVAL (operands[2]) != 32)
+    FAIL;
+
+  /* This can happen for a 64 bit target, when extracting a value from
+     a 64 bit union member.  extract_bit_field doesn't verify that our
+     source matches the predicate, so we force it to be a MEM here.  */
+  if (GET_CODE (operands[1]) != MEM)
+    FAIL;
+
+  /* Change the mode to BLKmode for aliasing purposes.  */
+  operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0));
+
+  /* Otherwise, emit a lwl/lwr pair to load the value.  */
+  if (INTVAL (operands[2]) == 64)
+    emit_insn (gen_movdi_uld (operands[0], operands[1]));
+  else
+    {
+      if (TARGET_64BIT)
+	{
+	  operands[0] = gen_lowpart (SImode, operands[0]);
+	  if (operands[0] == NULL_RTX)
+	    FAIL;
+	}
+      emit_insn (gen_movsi_ulw (operands[0], operands[1]));
+    }
+  DONE;
+}")
+
+;; Only specify the mode operands 0, the rest are assumed to be word_mode.
+(define_expand "insv"
+  [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
+		      (match_operand 1 "immediate_operand" "")
+		      (match_operand 2 "immediate_operand" ""))
+	(match_operand 3 "register_operand" ""))]
+  "!TARGET_MIPS16"
+  "
+{
+  /* If the field does not start on a byte boundary, then fail.  */
+  if (INTVAL (operands[2]) % 8 != 0) 
+    FAIL;
+
+  /* MIPS I and MIPS II can only handle a 32bit field.  */
+  if (!TARGET_64BIT && INTVAL (operands[1]) != 32)
+    FAIL;
+
+  /* MIPS III and MIPS IV can handle both 32bit and 64bit fields.  */
+  if (TARGET_64BIT
+      && INTVAL (operands[1]) != 64
+      && INTVAL (operands[1]) != 32)
+    FAIL;
+
+  /* This can happen for a 64 bit target, when storing into a 32 bit union
+     member.  store_bit_field doesn't verify that our target matches the
+     predicate, so we force it to be a MEM here.  */
+  if (GET_CODE (operands[0]) != MEM)
+    FAIL;
+
+  /* Change the mode to BLKmode for aliasing purposes.  */
+  operands[0] = change_address (operands[0], BLKmode, XEXP (operands[0], 0));
+
+  /* Otherwise, emit a s[wd]l/s[wd]r pair to load the value.  */
+  if (INTVAL (operands[1]) == 64)
+    emit_insn (gen_movdi_usd (operands[0], operands[3]));
+  else
+    {
+      if (TARGET_64BIT)
+	{
+	  operands[3] = gen_lowpart (SImode, operands[3]);
+	  if (operands[3] == NULL_RTX)
+	    FAIL;
+	}
+      emit_insn (gen_movsi_usw (operands[0], operands[3]));
+    }
+  DONE;
+}")
+
+;; unaligned word moves generated by the bit field patterns
+
+(define_insn "movsi_ulw"
+  [(set (match_operand:SI 0 "register_operand" "=&d,&d")
+	(unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
+  "!TARGET_MIPS16"
+  "*
+{
+  rtx offset = const0_rtx;
+  rtx addr = XEXP (operands[1], 0);
+  rtx mem_addr = eliminate_constant_term (addr, &offset);
+  char *ret;
+
+  if (TARGET_STATS)
+    mips_count_memory_refs (operands[1], 2);
+
+  /* The stack/frame pointers are always aligned, so we can convert
+     to the faster lw if we are referencing an aligned stack location.  */
+
+  if ((INTVAL (offset) & 3) == 0
+      && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
+    ret = \"lw\\t%0,%1\";
+  else
+    ret = \"ulw\\t%0,%1\";
+
+  return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
+}"
+  [(set_attr "type"	"load,load")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2,4")])
+
+(define_insn "movsi_usw"
+  [(set (match_operand:BLK 0 "memory_operand" "=R,o")
+	(unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
+  "!TARGET_MIPS16"
+  "*
+{
+  rtx offset = const0_rtx;
+  rtx addr = XEXP (operands[0], 0);
+  rtx mem_addr = eliminate_constant_term (addr, &offset);
+
+  if (TARGET_STATS)
+    mips_count_memory_refs (operands[0], 2);
+
+  /* The stack/frame pointers are always aligned, so we can convert
+     to the faster sw if we are referencing an aligned stack location.  */
+
+  if ((INTVAL (offset) & 3) == 0
+      && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
+    return \"sw\\t%1,%0\";
+
+  return \"usw\\t%z1,%0\";
+}"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2,4")])
+
+;; Bit field extract patterns which use ldl/ldr.
+
+;; unaligned double word moves generated by the bit field patterns
+
+(define_insn "movdi_uld"
+  [(set (match_operand:DI 0 "register_operand" "=&d,&d")
+	(unspec:DI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
+  ""
+  "*
+{
+  rtx offset = const0_rtx;
+  rtx addr = XEXP (operands[1], 0);
+  rtx mem_addr = eliminate_constant_term (addr, &offset);
+  char *ret;
+
+  if (TARGET_STATS)
+    mips_count_memory_refs (operands[1], 2);
+
+  /* The stack/frame pointers are always aligned, so we can convert
+     to the faster lw if we are referencing an aligned stack location.  */
+
+  if ((INTVAL (offset) & 7) == 0
+      && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
+    ret = \"ld\\t%0,%1\";
+  else
+    ret = \"uld\\t%0,%1\";
+
+  return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
+}"
+  [(set_attr "type"	"load,load")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2,4")])
+
+(define_insn "movdi_usd"
+  [(set (match_operand:BLK 0 "memory_operand" "=R,o")
+	(unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
+  ""
+  "*
+{
+  rtx offset = const0_rtx;
+  rtx addr = XEXP (operands[0], 0);
+  rtx mem_addr = eliminate_constant_term (addr, &offset);
+
+  if (TARGET_STATS)
+    mips_count_memory_refs (operands[0], 2);
+
+  /* The stack/frame pointers are always aligned, so we can convert
+     to the faster sw if we are referencing an aligned stack location.  */
+
+  if ((INTVAL (offset) & 7) == 0
+      && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
+    return \"sd\\t%1,%0\";
+
+  return \"usd\\t%z1,%0\";
+}"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2,4")])
+
+;; These two patterns support loading addresses with two instructions instead
+;; of using the macro instruction la.
+
+;; ??? mips_move_1word has support for HIGH, so this pattern may be
+;; unnecessary.
+
+(define_insn "high"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(high:SI (match_operand:SI 1 "immediate_operand" "")))]
+  "mips_split_addresses && !TARGET_MIPS16"
+  "lui\\t%0,%%hi(%1) # high"
+  [(set_attr "type"	"move")
+   (set_attr "length"	"1")])
+
+(define_insn "low"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+		   (match_operand:SI 2 "immediate_operand" "")))]
+  "mips_split_addresses && !TARGET_MIPS16"
+  "addiu\\t%0,%1,%%lo(%2) # low"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+
+;; 64-bit integer moves
+
+;; Unlike most other insns, the move insns can't be split with
+;; different predicates, because register spilling and other parts of
+;; the compiler, have memoized the insn number already.
+
+(define_expand "movdi"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "")
+	(match_operand:DI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if (mips_split_addresses && mips_check_split (operands[1], DImode))
+    {
+      enum machine_mode mode = GET_MODE (operands[0]);
+      rtx tem = ((reload_in_progress | reload_completed)
+		 ? operands[0] : gen_reg_rtx (mode));
+
+      emit_insn (gen_rtx (SET, VOIDmode, tem,
+			  gen_rtx (HIGH, mode, operands[1])));
+
+      operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]);
+    }
+
+  /* If we are generating embedded PIC code, and we are referring to a
+     symbol in the .text section, we must use an offset from the start
+     of the function.  */
+  if (TARGET_EMBEDDED_PIC
+      && (GET_CODE (operands[1]) == LABEL_REF
+	  || (GET_CODE (operands[1]) == SYMBOL_REF
+	      && ! SYMBOL_REF_FLAG (operands[1]))))
+    {
+      rtx temp;
+
+      temp = embedded_pic_offset (operands[1]);
+      temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx,
+		      force_reg (DImode, temp));
+      emit_move_insn (operands[0], force_reg (DImode, temp));
+      DONE;
+    }
+
+  /* If operands[1] is a constant address illegal for pic, then we need to
+     handle it just like LEGITIMIZE_ADDRESS does.  */
+  if (flag_pic && pic_address_needs_scratch (operands[1]))
+    {
+      rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
+      rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
+
+      if (! SMALL_INT (temp2))
+	temp2 = force_reg (DImode, temp2);
+
+      emit_move_insn (operands[0], gen_rtx (PLUS, DImode, temp, temp2));
+      DONE;
+    }
+
+  /* On the mips16, we can handle a GP relative reference by adding in
+     $gp.  We need to check the name to see whether this is a string
+     constant.  */
+  if (TARGET_MIPS16
+      && register_operand (operands[0], DImode)
+      && GET_CODE (operands[1]) == SYMBOL_REF
+      && SYMBOL_REF_FLAG (operands[1]))
+    {
+      char *name = XSTR (operands[1], 0);
+
+      if (name[0] != '*'
+	  || strncmp (name + 1, LOCAL_LABEL_PREFIX,
+		      sizeof LOCAL_LABEL_PREFIX - 1) != 0)
+	{
+	  rtx base_reg;
+
+	  if (reload_in_progress || reload_completed)
+	    {
+	      /* In movsi we use the constant table here.  However, in
+                 this case, we're better off copying $28 into a
+                 register and adding, because the constant table entry
+                 would be 8 bytes.  */
+	      base_reg = operands[0];
+	      emit_move_insn (base_reg,
+			      gen_rtx (CONST, DImode,
+				       gen_rtx (REG, DImode,
+						GP_REG_FIRST + 28)));
+	    }
+	  else
+	    {
+	      base_reg = gen_reg_rtx (Pmode);
+	      emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
+	    }
+
+	  emit_move_insn (operands[0],
+			  gen_rtx (PLUS, Pmode, base_reg,
+				   mips16_gp_offset (operands[1])));
+	  DONE;
+	}
+    }
+
+  if ((reload_in_progress | reload_completed) == 0
+      && !register_operand (operands[0], DImode)
+      && !register_operand (operands[1], DImode)
+      && (TARGET_MIPS16
+	  || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+	       && operands[1] != CONST0_RTX (DImode))))
+    {
+      rtx temp = force_reg (DImode, operands[1]);
+      emit_move_insn (operands[0], temp);
+      DONE;
+    }
+}")
+
+;; For mips16, we need a special case to handle storing $31 into
+;; memory, since we don't have a constraint to match $31.  This
+;; instruction can be generated by save_restore_insns.
+
+(define_insn ""
+  [(set (match_operand:DI 0 "memory_operand" "R,m")
+	(reg:DI 31))]
+  "TARGET_MIPS16 && TARGET_64BIT"
+  "*
+{
+  operands[1] = gen_rtx (REG, DImode, 31);
+  return mips_move_2words (operands, insn);
+}"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,2")])
+
+;; CYGNUS LOCAL law
+(define_insn "movdi_internal"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x*w,*d,*x*w")
+	(match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d"))]
+  "!TARGET_64BIT && !TARGET_MIPS16
+   && (register_operand (operands[0], DImode)
+       || register_operand (operands[1], DImode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
+       || operands[1] == CONST0_RTX (DImode))"
+  "* return mips_move_2words (operands, insn); "
+  [(set_attr "type"	"move,arith,load,load,store,store,hilo,hilo,hilo")
+   (set_attr "mode"	"DI")
+   (set_attr "length"   "2,4,2,4,2,4,2,2,2")])
+
+;; CYGNUS LOCAL law
+(define_insn ""
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,To,*d")
+	(match_operand:DI 1 "general_operand" "d,d,y,K,N,R,To,d,d,*x*w"))]
+  "!TARGET_64BIT && TARGET_MIPS16
+   && (register_operand (operands[0], DImode)
+       || register_operand (operands[1], DImode))"
+  "* return mips_move_2words (operands, insn);"
+  [(set_attr "type"	"move,move,move,arith,arith,load,load,store,store,hilo")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2,2,2,2,3,2,4,2,4,2")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(match_operand:DI 1 "register_operand" ""))]
+  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
+
+  [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
+   (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
+  "")
+
+;; CYGNUS LOCAL law
+(define_insn "movdi_internal2"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x*w,*d,*x*w,*a*q")
+	(match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x*w,*d,*J"))]
+  "TARGET_64BIT && !TARGET_MIPS16
+   && (register_operand (operands[0], DImode)
+       || se_register_operand (operands[1], DImode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
+       || operands[1] == CONST0_RTX (DImode))"
+  "* return mips_move_2words (operands, insn); "
+  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1,2,1,2,1,2,1,2,1,1,1,2")])
+
+;; CYGNUS LOCAL law
+(define_insn ""
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d")
+	(match_operand:DI 1 "movdi_operand" "d,d,y,K,N,s,R,m,d,d,*x*w"))]
+  "TARGET_64BIT && TARGET_MIPS16
+   && (register_operand (operands[0], DImode)
+       || se_register_operand (operands[1], DImode))"
+  "* return mips_move_2words (operands, insn);"
+  [(set_attr "type"	"move,move,move,arith,arith,arith,load,load,store,store,hilo")
+   (set_attr "mode"	"DI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (const_int 1)
+		 (const_int 1)
+		 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
+			       (const_int 2)
+			       (const_int 3))
+		 (if_then_else (match_operand:VOID 1 "m16_usym5_4" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (const_int 1)
+		 (const_int 2)
+		 (const_int 1)
+		 (const_int 2)
+		 (const_int 1)])])
+
+;; On the mips16, we can split ld $r,N($r) into an add and a load,
+;; when the original load is a 4 byte instruction but the add and the
+;; load are 2 2 byte instructions.
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(mem:DI (plus:DI (match_dup 0)
+			 (match_operand:DI 1 "const_int_operand" ""))))]
+  "TARGET_64BIT && TARGET_MIPS16 && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == CONST_INT
+   && ((INTVAL (operands[1]) < 0
+	&& INTVAL (operands[1]) >= -0x10)
+       || (INTVAL (operands[1]) >= 32 * 8
+	   && INTVAL (operands[1]) <= 31 * 8 + 0x8)
+       || (INTVAL (operands[1]) >= 0
+	   && INTVAL (operands[1]) < 32 * 8
+	   && (INTVAL (operands[1]) & 7) != 0))"
+  [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
+   (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[1]);
+
+  if (val < 0)
+    operands[2] = GEN_INT (0);
+  else if (val >= 32 * 8)
+    {
+      int off = val & 7;
+
+      operands[1] = GEN_INT (0x8 + off);
+      operands[2] = GEN_INT (val - off - 0x8);
+    }
+  else
+    {
+      int off = val & 7;
+
+      operands[1] = GEN_INT (off);
+      operands[2] = GEN_INT (val - off);
+    }
+}")
+
+;; Handle input reloads in DImode.
+;; This is mainly to handle reloading HILO_REGNUM.  Note that we may
+;; see it as the source or the destination, depending upon which way
+;; reload handles the instruction.
+;; Making the second operand TImode is a trick.  The compiler may
+;; reuse the same register for operand 0 and operand 2.  Using TImode
+;; gives us two registers, so we can always use the one which is not
+;; used.
+
+(define_expand "reload_indi"
+  [(set (match_operand:DI 0 "register_operand" "=b")
+	(match_operand:DI 1 "" "b"))
+   (clobber (match_operand:TI 2 "register_operand" "=&d"))]
+  "TARGET_64BIT"
+  "
+{
+  rtx scratch = gen_rtx (REG, DImode,
+			 (REGNO (operands[0]) == REGNO (operands[2]) 
+			  ? REGNO (operands[2]) + 1
+			  : REGNO (operands[2])));
+
+  if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
+    {
+      if (GET_CODE (operands[1]) == MEM)
+	{
+	  rtx memword, offword, hiword, loword;
+	  rtx addr = find_replacement (&XEXP (operands[1], 0));
+	  rtx op1 = change_address (operands[1], VOIDmode, addr);
+
+	  scratch = gen_rtx (REG, SImode, REGNO (scratch));
+	  memword = change_address (op1, SImode, NULL_RTX);
+	  offword = change_address (adj_offsettable_operand (op1, 4),
+				    SImode, NULL_RTX);
+	  if (BYTES_BIG_ENDIAN)
+	    {
+	      hiword = memword;
+	      loword = offword;
+	    }
+	  else
+	    {
+	      hiword = offword;
+	      loword = memword;
+	    }
+	  emit_move_insn (scratch, hiword);
+	  emit_move_insn (gen_rtx (REG, SImode, 64), scratch);
+	  emit_move_insn (scratch, loword);
+	  emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
+          emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
+	}
+      else
+	{
+	  emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
+	  emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
+	  emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
+	  emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
+	  emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
+          emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
+	}
+      DONE;
+    }
+  if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
+    {
+      emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
+      emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
+      emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
+      emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
+      emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
+      emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
+      emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
+      DONE;
+    }
+  /* This handles moves between a float register and HI/LO.  */
+  emit_move_insn (scratch, operands[1]);
+  emit_move_insn (operands[0], scratch);
+  DONE;
+}")
+
+;; Handle output reloads in DImode.
+
+;; Reloading HILO_REG in MIPS16 mode requires two scratch registers, so we
+;; use a TImode scratch reg.
+
+(define_expand "reload_outdi"
+  [(set (match_operand:DI 0 "" "=b")
+	(match_operand:DI 1 "se_register_operand" "b"))
+   (clobber (match_operand:TI 2 "register_operand" "=&d"))]
+  "TARGET_64BIT"
+  "
+{
+  rtx scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
+
+  if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
+    {
+      emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
+      emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
+      emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
+      emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
+      emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
+      emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
+      DONE;
+    }
+  if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
+    {
+      if (GET_CODE (operands[0]) == MEM)
+	{
+	  rtx scratch, memword, offword, hiword, loword;
+	  rtx addr = find_replacement (&XEXP (operands[0], 0));
+	  rtx op0 = change_address (operands[0], VOIDmode, addr);
+
+	  scratch = gen_rtx (REG, SImode, REGNO (operands[2]));
+	  memword = change_address (op0, SImode, NULL_RTX);
+	  offword = change_address (adj_offsettable_operand (op0, 4),
+				    SImode, NULL_RTX);
+	  if (BYTES_BIG_ENDIAN)
+	    {
+	      hiword = memword;
+	      loword = offword;
+	    }
+	  else
+	    {
+	      hiword = offword;
+	      loword = memword;
+	    }
+	  emit_move_insn (scratch, gen_rtx (REG, SImode, 64));
+	  emit_move_insn (hiword, scratch);
+	  emit_move_insn (scratch, gen_rtx (REG, SImode, 65));
+	  emit_move_insn (loword, scratch);
+	  emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
+	}
+      else if (TARGET_MIPS16 && ! M16_REG_P (REGNO (operands[0])))
+	{
+	  /* Handle the case where operand[0] is not a 'd' register,
+	     and hence we can not directly move from the HILO register
+	     into it.  */
+	  rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
+	  emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
+	  emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
+	  emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
+	  emit_insn (gen_movdi (scratch2, gen_rtx (REG, DImode, 64)));
+	  emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32)));
+	  emit_insn (gen_iordi3 (scratch, scratch, scratch2));
+	  emit_insn (gen_movdi (operands[0], scratch));
+	  emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
+	}
+      else
+	{
+	  emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
+	  emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
+	  emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
+	  emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
+	  emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
+	  emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
+	  emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
+	}
+      DONE;
+    }
+  /* This handles moves between a float register and HI/LO.  */
+  emit_move_insn (scratch, operands[1]);
+  emit_move_insn (operands[0], scratch);
+  DONE;
+}")
+
+;; 32-bit Integer moves
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_operand:SI 1 "large_int" ""))]
+  "!TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
+  [(set (match_dup 0)
+	(match_dup 2))
+   (set (match_dup 0)
+     	(ior:SI (match_dup 0)
+		(match_dup 3)))]
+  "
+{
+  operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
+  operands[3] = GEN_INT (INTVAL (operands[1]) & 0x0000ffff);
+}")
+
+;; Unlike most other insns, the move insns can't be split with
+;; different predicates, because register spilling and other parts of
+;; the compiler, have memoized the insn number already.
+
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "")
+	(match_operand:SI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if (mips_split_addresses && mips_check_split (operands[1], SImode))
+    {
+      enum machine_mode mode = GET_MODE (operands[0]);
+      rtx tem = ((reload_in_progress | reload_completed)
+		 ? operands[0] : gen_reg_rtx (mode));
+
+      emit_insn (gen_rtx (SET, VOIDmode, tem,
+			  gen_rtx (HIGH, mode, operands[1])));
+
+      operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]);
+    }
+
+  /* If we are generating embedded PIC code, and we are referring to a
+     symbol in the .text section, we must use an offset from the start
+     of the function.  */
+  if (TARGET_EMBEDDED_PIC
+      && (GET_CODE (operands[1]) == LABEL_REF
+	  || (GET_CODE (operands[1]) == SYMBOL_REF
+	      && ! SYMBOL_REF_FLAG (operands[1]))))
+    {
+      rtx temp;
+
+      temp = embedded_pic_offset (operands[1]);
+      temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx,
+		      force_reg (SImode, temp));
+      emit_move_insn (operands[0], force_reg (SImode, temp));
+      DONE;
+    }
+
+  /* If operands[1] is a constant address invalid for pic, then we need to
+     handle it just like LEGITIMIZE_ADDRESS does.  */
+  if (flag_pic && pic_address_needs_scratch (operands[1]))
+    {
+      rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0));
+      rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
+
+      if (! SMALL_INT (temp2))
+	temp2 = force_reg (SImode, temp2);
+
+      emit_move_insn (operands[0], gen_rtx (PLUS, SImode, temp, temp2));
+      DONE;
+    }
+
+  /* On the mips16, we can handle a GP relative reference by adding in
+     $gp.  We need to check the name to see whether this is a string
+     constant.  */
+  if (TARGET_MIPS16
+      && register_operand (operands[0], SImode)
+      && GET_CODE (operands[1]) == SYMBOL_REF
+      && SYMBOL_REF_FLAG (operands[1]))
+    {
+      char *name = XSTR (operands[1], 0);
+
+      if (name[0] != '*'
+	  || strncmp (name + 1, LOCAL_LABEL_PREFIX,
+		      sizeof LOCAL_LABEL_PREFIX - 1) != 0)
+	{
+	  rtx base_reg;
+
+	  if (reload_in_progress || reload_completed)
+	    {
+	      /* We need to reload this address.  In this case we
+                 aren't going to have a chance to combine loading the
+                 address with the load or store.  That means that we
+                 can either generate a 2 byte move followed by a 4
+                 byte addition, or a 2 byte load with a 4 byte entry
+                 in the constant table.  Since the entry in the
+                 constant table might be shared, we're better off, on
+                 average, loading the address from the constant table.  */
+	      emit_move_insn (operands[0],
+			      force_const_mem (SImode, operands[1]));
+	      DONE;
+	    }
+
+	  base_reg = gen_reg_rtx (Pmode);
+	  emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
+
+	  emit_move_insn (operands[0],
+			  gen_rtx (PLUS, Pmode, base_reg,
+				   mips16_gp_offset (operands[1])));
+	  DONE;
+	}
+    }
+
+  if ((reload_in_progress | reload_completed) == 0
+      && !register_operand (operands[0], SImode)
+      && !register_operand (operands[1], SImode)
+      && (TARGET_MIPS16
+	  || GET_CODE (operands[1]) != CONST_INT
+	  || INTVAL (operands[1]) != 0))
+    {
+      rtx temp = force_reg (SImode, operands[1]);
+      emit_move_insn (operands[0], temp);
+      DONE;
+    }
+}")
+
+;; For mips16, we need a special case to handle storing $31 into
+;; memory, since we don't have a constraint to match $31.  This
+;; instruction can be generated by save_restore_insns.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "memory_operand" "R,m")
+	(reg:SI 31))]
+  "TARGET_MIPS16"
+  "*
+{
+  operands[1] = gen_rtx (REG, SImode, 31);
+  return mips_move_1word (operands, insn, FALSE);
+}"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,2")])
+
+;; The difference between these two is whether or not ints are allowed
+;; in FP registers (off by default, use -mdebugh to enable).
+
+;; CYGNUS LOCAL law
+(define_insn "movsi_internal1"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x*w,*x*w,*d,*d")
+	(match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x*w,*a*q"))]
+  "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
+   && (register_operand (operands[0], SImode)
+       || register_operand (operands[1], SImode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,2,1,2,1,2,1,2,1,1,1,1,2,1,2,1,1,1,1")])
+
+;; CYGNUS LOCAL law
+(define_insn "movsi_internal2"
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x*w,*d,*x*w,*d")
+	(match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x*w,*d,*a*q"))]
+  "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
+   && (register_operand (operands[0], SImode)
+       || register_operand (operands[1], SImode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1,2,1,2,1,2,1,2,1,1,1,1,1,1")])
+
+;; This is the mips16 movsi instruction.  We accept a small integer as
+;; the source if the destination is a GP memory reference.  This is
+;; because we want the combine pass to turn adding a GP reference to a
+;; register into a direct GP reference, but the combine pass will pass
+;; in the source as a constant if it finds an equivalent one.  If the
+;; instruction is recognized, reload will force the constant back out
+;; into a register.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,d,R,m,*d,*d")
+	(match_operand:SI 1 "move_operand" "d,d,y,S,K,N,s,R,m,d,d,*x,*a"))]
+  "TARGET_MIPS16
+   && (register_operand (operands[0], SImode)
+       || register_operand (operands[1], SImode)
+       || (GET_CODE (operands[0]) == MEM
+	   && GET_CODE (XEXP (operands[0], 0)) == PLUS
+	   && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST
+	   && mips16_gp_offset_p (XEXP (XEXP (operands[0], 0), 1))
+	   && GET_CODE (operands[1]) == CONST_INT
+	   && (SMALL_INT (operands[1])
+	       || SMALL_INT_UNSIGNED (operands[1]))))"
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"move,move,move,load,arith,arith,arith,load,load,store,store,hilo,hilo")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (const_int 1)
+		 (const_int 1)
+		 (const_int 2)
+		 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
+			       (const_int 2)
+			       (const_int 3))
+		 (if_then_else (match_operand:VOID 1 "m16_usym8_4" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (const_int 1)
+		 (const_int 2)
+		 (const_int 1)
+		 (const_int 2)
+		 (const_int 1)
+		 (const_int 1)])])
+
+;; On the mips16, we can split lw $r,N($r) into an add and a load,
+;; when the original load is a 4 byte instruction but the add and the
+;; load are 2 2 byte instructions.
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(mem:SI (plus:SI (match_dup 0)
+			 (match_operand:SI 1 "const_int_operand" ""))))]
+  "TARGET_MIPS16 && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == CONST_INT
+   && ((INTVAL (operands[1]) < 0
+	&& INTVAL (operands[1]) >= -0x80)
+       || (INTVAL (operands[1]) >= 32 * 4
+	   && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
+       || (INTVAL (operands[1]) >= 0
+	   && INTVAL (operands[1]) < 32 * 4
+	   && (INTVAL (operands[1]) & 3) != 0))"
+  [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
+   (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[1]);
+
+  if (val < 0)
+    operands[2] = GEN_INT (0);
+  else if (val >= 32 * 4)
+    {
+      int off = val & 3;
+
+      operands[1] = GEN_INT (0x7c + off);
+      operands[2] = GEN_INT (val - off - 0x7c);
+    }
+  else
+    {
+      int off = val & 3;
+
+      operands[1] = GEN_INT (off);
+      operands[2] = GEN_INT (val - off);
+    }
+}")
+
+;; On the mips16, we can split a load of certain constants into a load
+;; and an add.  This turns a 4 byte instruction into 2 2 byte
+;; instructions.
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_operand:SI 1 "const_int_operand" ""))]
+  "TARGET_MIPS16 && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == CONST_INT
+   && INTVAL (operands[1]) >= 0x100
+   && INTVAL (operands[1]) <= 0xff + 0x7f"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
+  "
+{
+  int val = INTVAL (operands[1]);
+
+  operands[1] = GEN_INT (0xff);
+  operands[2] = GEN_INT (val - 0xff);
+}")
+
+;; On the mips16, we can split a load of a negative constant into a
+;; load and a neg.  That's what mips_move_1word will generate anyhow.
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(match_operand:SI 1 "const_int_operand" ""))]
+  "TARGET_MIPS16 && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == CONST_INT
+   && INTVAL (operands[1]) < 0
+   && INTVAL (operands[1]) > - 0x8000"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 0) (neg:SI (match_dup 0)))]
+  "
+{
+  operands[1] = GEN_INT (- INTVAL (operands[1]));
+}")
+
+;; Reload HILO_REGNUM in SI mode.  This needs a scratch register in
+;; order to set the sign bit correctly in the HI register.
+
+(define_expand "reload_outsi"
+  [(set (match_operand:SI 0 "general_operand" "=b")
+	(match_operand:SI 1 "register_operand" "b"))
+   (clobber (match_operand:SI 2 "register_operand" "=&d"))]
+  "TARGET_64BIT || TARGET_MIPS16"
+  "
+{
+  if (TARGET_64BIT
+      && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
+    {
+      emit_insn (gen_movsi (gen_rtx (REG, SImode, 65), operands[1]));
+      emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31)));
+      emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2]));
+      emit_insn (gen_rtx_USE (VOIDmode, operands[0]));
+      DONE;
+    }
+  /* Use a mult to reload LO on mips16.  ??? This is hideous.  */
+  if (TARGET_MIPS16
+      && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
+    {
+      emit_insn (gen_movsi (operands[2], GEN_INT (1)));
+      /* This is gen_mulsi3_internal, but we need to fill in the
+	 scratch registers.  */
+      emit_insn (gen_rtx (PARALLEL, VOIDmode,
+			  gen_rtvec (3,
+				     gen_rtx (SET, VOIDmode,
+					      operands[0],
+					      gen_rtx (MULT, SImode,
+						       operands[1],
+						       operands[2])),
+				     gen_rtx (CLOBBER, VOIDmode,
+					      gen_rtx (REG, SImode, 64)),
+				     gen_rtx (CLOBBER, VOIDmode,
+					      gen_rtx (REG, SImode, 66)))));
+      DONE;
+    }
+  /* FIXME: I don't know how to get a value into the HI register.  */
+  if (GET_CODE (operands[0]) == REG
+      && (TARGET_MIPS16 ? M16_REG_P (REGNO (operands[0]))
+	  : GP_REG_P (REGNO (operands[0]))))
+    {
+      emit_move_insn (operands[0], operands[1]);
+      DONE;
+    }
+  /* This handles moves between a float register and HI/LO.  */
+  emit_move_insn (operands[2], operands[1]);
+  emit_move_insn (operands[0], operands[2]);
+  DONE;
+}")
+
+;; Reload a value into HI or LO.  There is no mthi or mtlo on mips16,
+;; so we use a mult.  ??? This is hideous, and we ought to figure out
+;; something better.
+
+;; We use no predicate for operand1, because it may be a PLUS, and there
+;; is no convenient predicate for that.
+
+(define_expand "reload_insi"
+  [(set (match_operand:SI 0 "register_operand" "=b")
+	(match_operand:SI 1 "" "b"))
+   (clobber (match_operand:SI 2 "register_operand" "=&d"))]
+  "TARGET_MIPS16"
+  "
+{
+  if (TARGET_MIPS16
+      && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
+    {
+      emit_insn (gen_movsi (operands[2], GEN_INT (1)));
+      /* This is gen_mulsi3_internal, but we need to fill in the
+	 scratch registers.  */
+      emit_insn (gen_rtx (PARALLEL, VOIDmode,
+			  gen_rtvec (3,
+				     gen_rtx (SET, VOIDmode,
+					      operands[0],
+					      gen_rtx (MULT, SImode,
+						       operands[1],
+						       operands[2])),
+				     gen_rtx (CLOBBER, VOIDmode,
+					      gen_rtx (REG, SImode, 64)),
+				     gen_rtx (CLOBBER, VOIDmode,
+					      gen_rtx (REG, SImode, 66)))));
+      DONE;
+    }
+
+  /* If this is a plus, then this must be an add of the stack pointer against
+     either a hard register or a pseudo.  */
+  if (TARGET_MIPS16 && GET_CODE (operands[1]) == PLUS)
+    {
+      rtx plus_op;
+
+      if (XEXP (operands[1], 0) == stack_pointer_rtx)
+	plus_op = XEXP (operands[1], 1);
+      else if (XEXP (operands[1], 1) == stack_pointer_rtx)
+	plus_op = XEXP (operands[1], 0);
+      else
+	abort ();
+
+      /* We should have a register now.  */
+      if (GET_CODE (plus_op) != REG)
+	abort ();
+
+      if (REGNO (plus_op) < FIRST_PSEUDO_REGISTER)
+	{
+	  /* We have to have at least one temporary register which is not
+	     overlapping plus_op.  */
+	  if (! rtx_equal_p (plus_op, operands[0]))
+	    {
+	      emit_move_insn (operands[0], stack_pointer_rtx);
+	      emit_insn (gen_addsi3 (operands[0], operands[0], plus_op));
+	    }
+	  else if (! rtx_equal_p (plus_op, operands[2]))
+	    {
+	      emit_move_insn (operands[2], stack_pointer_rtx);
+	      emit_insn (gen_addsi3 (operands[0], plus_op, operands[2]));
+	    }
+	  else
+	    abort ();
+	}
+      else
+	{
+	  /* We need two registers in this case.  */
+	  if (! rtx_equal_p (operands[0], operands[2]))
+	    {
+	      emit_move_insn (operands[0], stack_pointer_rtx);
+	      emit_move_insn (operands[2], plus_op);
+	      emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
+	    }
+	  else
+	    abort ();
+	}
+      DONE;
+    }
+
+  /* FIXME: I don't know how to get a value into the HI register.  */
+  emit_move_insn (operands[0], operands[1]);
+  DONE;
+}")
+
+;; This insn handles moving CCmode values.  It's really just a
+;; slightly simplified copy of movsi_internal2, with additional cases
+;; to move a condition register to a general register and to move
+;; between the general registers and the floating point registers.
+
+(define_insn "movcc"
+  [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
+	(match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2,1,1,2,1,2,1,1,1,1,2,1,2")])
+
+;; Reload condition code registers.  These need scratch registers.
+
+(define_expand "reload_incc"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(match_operand:CC 1 "general_operand" "z"))
+   (clobber (match_operand:TF 2 "register_operand" "=&f"))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "
+{
+  rtx source;
+  rtx fp1, fp2;
+
+  /* This is called when are copying some value into a condition code
+     register.  Operand 0 is the condition code register.  Operand 1
+     is the source.  Operand 2 is a scratch register; we use TFmode
+     because we actually need two floating point registers.  */
+  if (! ST_REG_P (true_regnum (operands[0]))
+      || ! FP_REG_P (true_regnum (operands[2])))
+    abort ();
+
+  /* We need to get the source in SFmode so that the insn is
+     recognized.  */
+  if (GET_CODE (operands[1]) == MEM)
+    source = change_address (operands[1], SFmode, NULL_RTX);
+  else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
+    source = gen_rtx (REG, SFmode, true_regnum (operands[1]));
+  else
+    source = operands[1];
+
+  fp1 = gen_rtx (REG, SFmode, REGNO (operands[2]));
+  fp2 = gen_rtx (REG, SFmode, REGNO (operands[2]) + 1);
+
+  emit_insn (gen_move_insn (fp1, source));
+  emit_insn (gen_move_insn (fp2, gen_rtx (REG, SFmode, 0)));
+  emit_insn (gen_rtx (SET, VOIDmode, operands[0],
+		      gen_rtx (LT, CCmode, fp2, fp1)));
+
+  DONE;
+}")
+
+(define_expand "reload_outcc"
+  [(set (match_operand:CC 0 "general_operand" "=z")
+	(match_operand:CC 1 "register_operand" "z"))
+   (clobber (match_operand:CC 2 "register_operand" "=&d"))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "
+{
+  /* This is called when we are copying a condition code register out
+     to save it somewhere.  Operand 0 should be the location we are
+     going to save it to.  Operand 1 should be the condition code
+     register.  Operand 2 should be a scratch general purpose register
+     created for us by reload.  The mips_secondary_reload_class
+     function should have told reload that we don't need a scratch
+     register if the destination is a general purpose register anyhow.  */
+  if (ST_REG_P (true_regnum (operands[0]))
+      || GP_REG_P (true_regnum (operands[0]))
+      || ! ST_REG_P (true_regnum (operands[1]))
+      || ! GP_REG_P (true_regnum (operands[2])))
+    abort ();
+
+  /* All we have to do is copy the value from the condition code to
+     the data register, which movcc can handle, and then store the
+     value into the real final destination.  */
+  emit_insn (gen_move_insn (operands[2], operands[1]));
+  emit_insn (gen_move_insn (operands[0], operands[2]));
+
+  DONE;
+}")
+
+;; MIPS4 supports loading and storing a floating point register from
+;; the sum of two general registers.  We use two versions for each of
+;; these four instructions: one where the two general registers are
+;; SImode, and one where they are DImode.  This is because general
+;; registers will be in SImode when they hold 32 bit values, but,
+;; since the 32 bit values are always sign extended, the [ls][wd]xc1
+;; instructions will still work correctly.
+
+;; ??? Perhaps it would be better to support these instructions by
+;; modifying GO_IF_LEGITIMATE_ADDRESS and friends.  However, since
+;; these instructions can only be used to load and store floating
+;; point registers, that would probably cause trouble in reload.
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
+			 (match_operand:SI 2 "register_operand" "d"))))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "lwxc1\\t%0,%1(%2)"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
+			 (match_operand:DI 2 "se_register_operand" "d"))))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "lwxc1\\t%0,%1(%2)"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
+			 (match_operand:SI 2 "register_operand" "d"))))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "ldxc1\\t%0,%1(%2)"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
+			 (match_operand:DI 2 "se_register_operand" "d"))))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "ldxc1\\t%0,%1(%2)"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
+			 (match_operand:SI 2 "register_operand" "d")))
+	(match_operand:SF 0 "register_operand" "=f"))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "swxc1\\t%0,%1(%2)"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
+			 (match_operand:DI 2 "se_register_operand" "d")))
+	(match_operand:SF 0 "register_operand" "=f"))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "swxc1\\t%0,%1(%2)"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
+			 (match_operand:SI 2 "register_operand" "d")))
+	(match_operand:DF 0 "register_operand" "=f"))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "sdxc1\\t%0,%1(%2)"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
+			 (match_operand:DI 2 "se_register_operand" "d")))
+	(match_operand:DF 0 "register_operand" "=f"))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "sdxc1\\t%0,%1(%2)"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1")])
+
+;; 16-bit Integer moves
+
+;; Unlike most other insns, the move insns can't be split with
+;; different predicates, because register spilling and other parts of
+;; the compiler, have memoized the insn number already.
+;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "")
+	(match_operand:HI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if ((reload_in_progress | reload_completed) == 0
+      && !register_operand (operands[0], HImode)
+      && !register_operand (operands[1], HImode)
+      && (TARGET_MIPS16
+	  || (GET_CODE (operands[1]) != CONST_INT
+	  || INTVAL (operands[1]) != 0)))
+    {
+      rtx temp = force_reg (HImode, operands[1]);
+      emit_move_insn (operands[0], temp);
+      DONE;
+    }
+}")
+
+;; The difference between these two is whether or not ints are allowed
+;; in FP registers (off by default, use -mdebugh to enable).
+
+(define_insn "movhi_internal1"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
+	(match_operand:HI 1 "general_operand"       "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
+  "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
+   && (register_operand (operands[0], HImode)
+       || register_operand (operands[1], HImode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
+   (set_attr "mode"	"HI")
+   (set_attr "length"	"1,1,1,2,1,2,1,1,1,1,1")])
+
+(define_insn "movhi_internal2"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
+	(match_operand:HI 1 "general_operand"       "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
+  "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
+   && (register_operand (operands[0], HImode)
+       || register_operand (operands[1], HImode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
+   (set_attr "mode"	"HI")
+   (set_attr "length"	"1,1,1,2,1,2,1,1,1,1")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
+	(match_operand:HI 1 "general_operand"      "d,d,y,K,N,R,m,d,d,*x"))]
+  "TARGET_MIPS16
+   && (register_operand (operands[0], HImode)
+       || register_operand (operands[1], HImode))"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"move,move,move,arith,arith,load,load,store,store,hilo")
+   (set_attr "mode"	"HI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (const_int 1)
+		 (const_int 1)
+		 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
+			       (const_int 2)
+			       (const_int 3))
+		 (const_int 1)
+		 (const_int 2)
+		 (const_int 1)
+		 (const_int 2)
+		 (const_int 1)])])
+
+
+;; On the mips16, we can split lh $r,N($r) into an add and a load,
+;; when the original load is a 4 byte instruction but the add and the
+;; load are 2 2 byte instructions.
+
+(define_split
+  [(set (match_operand:HI 0 "register_operand" "")
+	(mem:HI (plus:SI (match_dup 0)
+			 (match_operand:SI 1 "const_int_operand" ""))))]
+  "TARGET_MIPS16 && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == CONST_INT
+   && ((INTVAL (operands[1]) < 0
+	&& INTVAL (operands[1]) >= -0x80)
+       || (INTVAL (operands[1]) >= 32 * 2
+	   && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
+       || (INTVAL (operands[1]) >= 0
+	   && INTVAL (operands[1]) < 32 * 2
+	   && (INTVAL (operands[1]) & 1) != 0))"
+  [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
+   (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[1]);
+
+  if (val < 0)
+    operands[2] = GEN_INT (0);
+  else if (val >= 32 * 2)
+    {
+      int off = val & 1;
+
+      operands[1] = GEN_INT (0x7e + off);
+      operands[2] = GEN_INT (val - off - 0x7e);
+    }
+  else
+    {
+      int off = val & 1;
+
+      operands[1] = GEN_INT (off);
+      operands[2] = GEN_INT (val - off);
+    }
+}")
+
+;; 8-bit Integer moves
+
+;; Unlike most other insns, the move insns can't be split with
+;; different predicates, because register spilling and other parts of
+;; the compiler, have memoized the insn number already.
+;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "")
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+  "
+{
+  if ((reload_in_progress | reload_completed) == 0
+      && !register_operand (operands[0], QImode)
+      && !register_operand (operands[1], QImode)
+      && (TARGET_MIPS16
+	  || (GET_CODE (operands[1]) != CONST_INT
+	  || INTVAL (operands[1]) != 0)))
+    {
+      rtx temp = force_reg (QImode, operands[1]);
+      emit_move_insn (operands[0], temp);
+      DONE;
+    }
+}")
+
+;; The difference between these two is whether or not ints are allowed
+;; in FP registers (off by default, use -mdebugh to enable).
+
+(define_insn "movqi_internal1"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
+	(match_operand:QI 1 "general_operand"       "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
+  "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
+   && (register_operand (operands[0], QImode)
+       || register_operand (operands[1], QImode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
+   (set_attr "mode"	"QI")
+   (set_attr "length"	"1,1,1,2,1,2,1,1,1,1,1")])
+
+(define_insn "movqi_internal2"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
+	(match_operand:QI 1 "general_operand"       "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
+  "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
+   && (register_operand (operands[0], QImode)
+       || register_operand (operands[1], QImode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
+   (set_attr "mode"	"QI")
+   (set_attr "length"	"1,1,1,2,1,2,1,1,1,1")])
+
+(define_insn ""
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
+	(match_operand:QI 1 "general_operand"      "d,d,y,K,N,R,m,d,d,*x"))]
+  "TARGET_MIPS16
+   && (register_operand (operands[0], QImode)
+       || register_operand (operands[1], QImode))"
+  "* return mips_move_1word (operands, insn, TRUE);"
+  [(set_attr "type"	"move,move,move,arith,arith,load,load,store,store,hilo")
+   (set_attr "mode"	"QI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (const_int 1)
+		 (const_int 1)
+		 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))
+		 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
+			       (const_int 2)
+			       (const_int 3))
+		 (const_int 1)
+		 (const_int 2)
+		 (const_int 1)
+		 (const_int 2)
+		 (const_int 1)])])
+
+
+;; On the mips16, we can split lb $r,N($r) into an add and a load,
+;; when the original load is a 4 byte instruction but the add and the
+;; load are 2 2 byte instructions.
+
+(define_split
+  [(set (match_operand:QI 0 "register_operand" "")
+	(mem:QI (plus:SI (match_dup 0)
+			 (match_operand:SI 1 "const_int_operand" ""))))]
+  "TARGET_MIPS16 && reload_completed
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == CONST_INT
+   && ((INTVAL (operands[1]) < 0
+	&& INTVAL (operands[1]) >= -0x80)
+       || (INTVAL (operands[1]) >= 32
+	   && INTVAL (operands[1]) <= 31 + 0x7f))"
+  [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
+   (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
+  "
+{
+  HOST_WIDE_INT val = INTVAL (operands[1]);
+
+  if (val < 0)
+    operands[2] = GEN_INT (0);
+  else
+    {
+      operands[1] = GEN_INT (0x7f);
+      operands[2] = GEN_INT (val - 0x7f);
+    }
+}")
+
+;; 32-bit floating point moves
+
+(define_expand "movsf"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "")
+	(match_operand:SF 1 "general_operand" ""))]
+  ""
+  "
+{
+  if ((reload_in_progress | reload_completed) == 0
+      && !register_operand (operands[0], SFmode)
+      && !register_operand (operands[1], SFmode)
+      && (TARGET_MIPS16
+	  || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+	       && operands[1] != CONST0_RTX (SFmode))))
+    {
+      rtx temp = force_reg (SFmode, operands[1]);
+      emit_move_insn (operands[0], temp);
+      DONE;
+    }
+}")
+
+(define_insn "movsf_internal1"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
+	(match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))]
+  "TARGET_HARD_FLOAT
+   && (register_operand (operands[0], SFmode)
+       || register_operand (operands[1], SFmode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
+       || operands[1] == CONST0_RTX (SFmode))"
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1,1,1,2,1,2,1,1,1,1,2,1,2")])
+
+
+(define_insn "movsf_internal2"
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m")
+	(match_operand:SF 1 "general_operand" "      Gd,R,Fm,d,d"))]
+  "TARGET_SOFT_FLOAT && !TARGET_MIPS16
+   && (register_operand (operands[0], SFmode)
+       || register_operand (operands[1], SFmode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
+       || operands[1] == CONST0_RTX (SFmode))"
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"move,load,load,store,store")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1,1,2,1,2")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,d,R,m")
+	(match_operand:SF 1 "general_operand"      "d,d,y,R,Fm,d,d"))]
+  "TARGET_MIPS16
+   && (register_operand (operands[0], SFmode)
+       || register_operand (operands[1], SFmode))"
+  "* return mips_move_1word (operands, insn, FALSE);"
+  [(set_attr "type"	"move,move,move,load,load,store,store")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"1,1,1,1,2,1,2")])
+
+
+;; 64-bit floating point moves
+
+(define_expand "movdf"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "")
+	(match_operand:DF 1 "general_operand" ""))]
+  ""
+  "
+{
+  if ((reload_in_progress | reload_completed) == 0
+      && !register_operand (operands[0], DFmode)
+      && !register_operand (operands[1], DFmode)
+      && (TARGET_MIPS16
+	  || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+	       && operands[1] != CONST0_RTX (DFmode))))
+    {
+      rtx temp = force_reg (DFmode, operands[1]);
+      emit_move_insn (operands[0], temp);
+      DONE;
+    }
+}")
+
+(define_insn "movdf_internal1"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,To,f,*f,*d,*d,*d,*d,*R,*T")
+	(match_operand:DF 1 "general_operand" "f,R,To,fG,fG,F,*d,*f,*d*G,*R,*T*F,*d,*d"))]
+  "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT)
+   && TARGET_DOUBLE_FLOAT
+   && (register_operand (operands[0], DFmode)
+       || register_operand (operands[1], DFmode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
+       || operands[1] == CONST0_RTX (DFmode))"
+  "* return mips_move_2words (operands, insn); "
+  [(set_attr "type"	"move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1,2,4,2,4,4,2,2,2,2,4,2,4")])
+
+(define_insn "movdf_internal1a"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,To,To,f,*d,*d,*d,*To,*R")
+	(match_operand:DF 1 "general_operand"      " f,To,f,G,f,G,F,*F,*To,*R,*d,*d"))]
+  "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT)
+   && TARGET_DOUBLE_FLOAT
+   && (register_operand (operands[0], DFmode)
+       || register_operand (operands[1], DFmode)
+       || (GET_CODE (operands [0]) == MEM
+	   && ((GET_CODE (operands[1]) == CONST_INT
+		&& INTVAL (operands[1]) == 0)
+	       || operands[1] == CONST0_RTX (DFmode))))"
+  "* return mips_move_2words (operands, insn); "
+  [(set_attr "type"	"move,load,store,store,store,store,load,load,load,load,store,store")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"1,2,1,1,2,2,2,2,2,1,2,1")])
+
+(define_insn "movdf_internal2"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,To")
+	(match_operand:DF 1 "general_operand" "dG,R,ToF,d,d"))]
+  "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
+   && (register_operand (operands[0], DFmode)
+       || register_operand (operands[1], DFmode)
+       || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
+       || operands[1] == CONST0_RTX (DFmode))"
+  "* return mips_move_2words (operands, insn); "
+  [(set_attr "type"	"move,load,load,store,store")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"2,2,4,2,4")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,d,R,To")
+	(match_operand:DF 1 "general_operand" "d,d,y,R,ToF,d,d"))]
+  "TARGET_MIPS16
+   && (register_operand (operands[0], DFmode)
+       || register_operand (operands[1], DFmode))"
+  "* return mips_move_2words (operands, insn);"
+  [(set_attr "type"	"move,move,move,load,load,store,store")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"2,2,2,2,4,2,4")])
+
+(define_split
+  [(set (match_operand:DF 0 "register_operand" "")
+	(match_operand:DF 1 "register_operand" ""))]
+  "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
+   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
+  [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
+   (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
+  "")
+
+;; Instructions to load the global pointer register.
+;; This is volatile to make sure that the scheduler won't move any symbol_ref
+;; uses in front of it.  All symbol_refs implicitly use the gp reg.
+
+(define_insn "loadgp"
+  [(set (reg:DI 28)
+	(unspec_volatile:DI [(match_operand:DI 0 "address_operand" "")
+			     (match_operand:DI 1 "register_operand" "")] 2))
+   (clobber (reg:DI 1))]
+  ""
+  "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,%1%]"
+  [(set_attr "type"	"move")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"3")])
+
+;; Block moves, see mips.c for more details.
+;; Argument 0 is the destination
+;; Argument 1 is the source
+;; Argument 2 is the length
+;; Argument 3 is the alignment
+
+(define_expand "movstrsi"
+  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
+		   (match_operand:BLK 1 "general_operand" ""))
+	      (use (match_operand:SI 2 "arith32_operand" ""))
+	      (use (match_operand:SI 3 "immediate_operand" ""))])]
+  "!TARGET_MIPS16"
+  "
+{
+  if (operands[0])		/* avoid unused code messages */
+    {
+      expand_block_move (operands);
+      DONE;
+    }
+}")
+
+;; Insn generated by block moves
+
+(define_insn "movstrsi_internal"
+  [(set (match_operand:BLK 0 "memory_operand" "=o")	;; destination
+	(match_operand:BLK 1 "memory_operand" "o"))	;; source
+   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
+   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
+   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
+   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
+   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
+   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
+   (use (const_int 0))]					;; normal block move
+  ""
+  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"20")])
+
+;; We need mips16 versions, because an offset from the stack pointer
+;; is not offsettable, since the stack pointer can only handle 4 and 8
+;; byte loads.
+
+(define_insn ""
+  [(set (match_operand:BLK 0 "memory_operand" "=d")	;; destination
+	(match_operand:BLK 1 "memory_operand" "d"))	;; source
+   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
+   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
+   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
+   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
+   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
+   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
+   (use (const_int 0))]					;; normal block move
+  "TARGET_MIPS16"
+  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"20")])
+
+(define_insn ""
+  [(set (match_operand:BLK 0 "memory_operand" "=d")	;; destination
+	(match_operand:BLK 1 "memory_operand" "o"))	;; source
+   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
+   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
+   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
+   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
+   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
+   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
+   (use (const_int 0))]					;; normal block move
+  "TARGET_MIPS16"
+  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"20")])
+
+(define_insn ""
+  [(set (match_operand:BLK 0 "memory_operand" "=o")	;; destination
+	(match_operand:BLK 1 "memory_operand" "d"))	;; source
+   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
+   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
+   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
+   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
+   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
+   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
+   (use (const_int 0))]					;; normal block move
+  "TARGET_MIPS16"
+  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"20")])
+
+;; Split a block move into 2 parts, the first part is everything
+;; except for the last move, and the second part is just the last
+;; store, which is exactly 1 instruction (ie, not a usw), so it can
+;; fill a delay slot.  This also prevents a bug in delayed branches
+;; from showing up, which reuses one of the registers in our clobbers.
+
+(define_split
+  [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
+	(mem:BLK (match_operand:SI 1 "register_operand" "")))
+   (clobber (match_operand:SI 4 "register_operand" ""))
+   (clobber (match_operand:SI 5 "register_operand" ""))
+   (clobber (match_operand:SI 6 "register_operand" ""))
+   (clobber (match_operand:SI 7 "register_operand" ""))
+   (use (match_operand:SI 2 "small_int" ""))
+   (use (match_operand:SI 3 "small_int" ""))
+   (use (const_int 0))]
+
+  "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
+
+  ;; All but the last move
+  [(parallel [(set (mem:BLK (match_dup 0))
+		   (mem:BLK (match_dup 1)))
+	      (clobber (match_dup 4))
+	      (clobber (match_dup 5))
+	      (clobber (match_dup 6))
+	      (clobber (match_dup 7))
+	      (use (match_dup 2))
+	      (use (match_dup 3))
+	      (use (const_int 1))])
+
+   ;; The last store, so it can fill a delay slot
+   (parallel [(set (mem:BLK (match_dup 0))
+		   (mem:BLK (match_dup 1)))
+	      (clobber (match_dup 4))
+	      (clobber (match_dup 5))
+	      (clobber (match_dup 6))
+	      (clobber (match_dup 7))
+	      (use (match_dup 2))
+	      (use (match_dup 3))
+	      (use (const_int 2))])]
+
+  "")
+
+(define_insn "movstrsi_internal2"
+  [(set (match_operand:BLK 0 "memory_operand" "=o")	;; destination
+	(match_operand:BLK 1 "memory_operand" "o"))	;; source
+   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
+   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
+   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
+   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
+   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
+   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
+   (use (const_int 1))]					;; all but last store
+  ""
+  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"20")])
+
+(define_insn ""
+  [(set (match_operand:BLK 0 "memory_operand" "=d")	;; destination
+	(match_operand:BLK 1 "memory_operand" "d"))	;; source
+   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
+   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
+   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
+   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
+   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
+   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
+   (use (const_int 1))]					;; all but last store
+  "TARGET_MIPS16"
+  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
+  [(set_attr "type"	"multi")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"20")])
+
+(define_insn "movstrsi_internal3"
+  [(set (match_operand:BLK 0 "memory_operand" "=Ro")	;; destination
+	(match_operand:BLK 1 "memory_operand" "Ro"))	;; source
+   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
+   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
+   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
+   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
+   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
+   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
+   (use (const_int 2))]					;; just last store of block move
+  ""
+  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:BLK 0 "memory_operand" "=d")	;; destination
+	(match_operand:BLK 1 "memory_operand" "d"))	;; source
+   (clobber (match_scratch:SI 4 "=&d"))			;; temp 1
+   (clobber (match_scratch:SI 5 "=&d"))			;; temp 2
+   (clobber (match_scratch:SI 6 "=&d"))			;; temp 3
+   (clobber (match_scratch:SI 7 "=&d"))			;; temp 4
+   (use (match_operand:SI 2 "small_int" "I"))		;; # bytes to move
+   (use (match_operand:SI 3 "small_int" "I"))		;; alignment
+   (use (const_int 2))]					;; just last store of block move
+  "TARGET_MIPS16"
+  "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
+  [(set_attr "type"	"store")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+
+;;  ....................
+;;	SHIFTS
+;;  ....................
+
+;; Many of these instructions uses trivial define_expands, because we
+;; want to use a different set of constraints when TARGET_MIPS16.
+
+(define_expand "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ashift:SI (match_operand:SI 1 "register_operand" "d")
+		   (match_operand:SI 2 "arith_operand" "dI")))]
+  ""
+  "
+{
+  /* On the mips16, a shift of more than 8 is a four byte instruction,
+     so, for a shift between 8 and 16, it is just as fast to do two
+     shifts of 8 or less.  If there is a lot of shifting going on, we
+     may win in CSE.  Otherwise combine will put the shifts back
+     together again.  This can be called by function_arg, so we must
+     be careful not to allocate a new register if we've reached the
+     reload pass.  */
+  if (TARGET_MIPS16
+      && optimize
+      && GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) > 8
+      && INTVAL (operands[2]) <= 16
+      && ! reload_in_progress
+      && ! reload_completed)
+    {
+      rtx temp = gen_reg_rtx (SImode);
+
+      emit_insn (gen_ashlsi3_internal2 (temp, operands[1], GEN_INT (8)));
+      emit_insn (gen_ashlsi3_internal2 (operands[0], temp,
+					GEN_INT (INTVAL (operands[2]) - 8)));
+      DONE;
+    }
+}")
+
+(define_insn "ashlsi3_internal1"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ashift:SI (match_operand:SI 1 "register_operand" "d")
+		   (match_operand:SI 2 "arith_operand" "dI")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+
+  return \"sll\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "ashlsi3_internal2"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(ashift:SI (match_operand:SI 1 "register_operand" "0,d")
+		   (match_operand:SI 2 "arith_operand" "d,I")))]
+  "TARGET_MIPS16"
+  "*
+{
+  if (which_alternative == 0)
+    return \"sll\\t%0,%2\";
+
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+
+  return \"sll\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+			       (const_int 1)
+			       (const_int 2))])])
+
+;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ashift:SI (match_operand:SI 1 "register_operand" "")
+		   (match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_MIPS16
+   && reload_completed
+   && GET_CODE (operands[2]) == CONST_INT
+   && INTVAL (operands[2]) > 8
+   && INTVAL (operands[2]) <= 16"
+  [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8)))
+   (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
+"
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
+}")
+
+(define_expand "ashldi3"
+  [(parallel [(set (match_operand:DI 0 "register_operand" "")
+		   (ashift:DI (match_operand:DI 1 "se_register_operand" "")
+			      (match_operand:SI 2 "arith_operand" "")))
+	      (clobber (match_dup  3))])]
+  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+  "
+{
+  if (TARGET_64BIT)
+    {
+      /* On the mips16, a shift of more than 8 is a four byte
+	 instruction, so, for a shift between 8 and 16, it is just as
+	 fast to do two shifts of 8 or less.  If there is a lot of
+	 shifting going on, we may win in CSE.  Otherwise combine will
+	 put the shifts back together again.  This can be called by
+	 function_arg, so we must be careful not to allocate a new
+	 register if we've reached the reload pass.  */
+      if (TARGET_MIPS16
+	  && optimize
+	  && GET_CODE (operands[2]) == CONST_INT
+	  && INTVAL (operands[2]) > 8
+	  && INTVAL (operands[2]) <= 16
+	  && ! reload_in_progress
+	  && ! reload_completed)
+	{
+	  rtx temp = gen_reg_rtx (DImode);
+
+	  emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
+	  emit_insn (gen_ashldi3_internal4 (operands[0], temp,
+					    GEN_INT (INTVAL (operands[2]) - 8)));
+	  DONE;
+	}
+
+      emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
+					operands[2]));
+      DONE;
+    }
+
+  operands[3] = gen_reg_rtx (SImode);
+}")
+
+
+(define_insn "ashldi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=&d")
+	(ashift:DI (match_operand:DI 1 "register_operand" "d")
+		   (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
+  "* 
+{
+  operands[4] = const0_rtx;
+  dslots_jump_total += 3;
+  dslots_jump_filled += 2;
+
+  return \"sll\\t%3,%2,26\\n\\
+\\tbgez\\t%3,1f\\n\\
+\\tsll\\t%M0,%L1,%2\\n\\
+\\t%(b\\t3f\\n\\
+\\tmove\\t%L0,%z4%)\\n\\
+\\n\\
+1:\\n\\
+\\t%(beq\\t%3,%z4,2f\\n\\
+\\tsll\\t%M0,%M1,%2%)\\n\\
+\\n\\
+\\tsubu\\t%3,%z4,%2\\n\\
+\\tsrl\\t%3,%L1,%3\\n\\
+\\tor\\t%M0,%M0,%3\\n\\
+2:\\n\\
+\\tsll\\t%L0,%L1,%2\\n\\
+3:\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"12")])
+
+
+(define_insn "ashldi3_internal2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashift:DI (match_operand:DI 1 "register_operand" "d")
+		   (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && (INTVAL (operands[2]) & 32) != 0"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+  operands[4] = const0_rtx;
+  return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ashift:DI (match_operand:DI 1 "register_operand" "")
+		   (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 1) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 0) (const_int 0))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ashift:DI (match_operand:DI 1 "register_operand" "")
+		   (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 1) (const_int 0))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_insn "ashldi3_internal3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashift:DI (match_operand:DI 1 "register_operand" "d")
+		   (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+  "*
+{
+  int amount = INTVAL (operands[2]);
+
+  operands[2] = GEN_INT ((amount & 31));
+  operands[4] = const0_rtx;
+  operands[5] = GEN_INT (((-amount) & 31));
+
+  return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ashift:DI (match_operand:DI 1 "register_operand" "")
+		   (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 1)
+	(ashift:SI (subreg:SI (match_dup 1) 1)
+		   (match_dup 2)))
+
+   (set (match_dup 3)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
+		     (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(ior:SI (subreg:SI (match_dup 0) 1)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(ashift:SI (subreg:SI (match_dup 1) 0)
+		   (match_dup 2)))]
+  "
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT ((amount & 31));
+  operands[4] = GEN_INT (((-amount) & 31));
+}")
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ashift:DI (match_operand:DI 1 "register_operand" "")
+		   (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0)
+	(ashift:SI (subreg:SI (match_dup 1) 0)
+		   (match_dup 2)))
+
+   (set (match_dup 3)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 1)
+		     (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(ior:SI (subreg:SI (match_dup 0) 0)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(ashift:SI (subreg:SI (match_dup 1) 1)
+		   (match_dup 2)))]
+  "
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT ((amount & 31));
+  operands[4] = GEN_INT (((-amount) & 31));
+}")
+
+
+(define_insn "ashldi3_internal4"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashift:DI (match_operand:DI 1 "se_register_operand" "d")
+		   (match_operand:SI 2 "arith_operand" "dI")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+
+  return \"dsll\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(ashift:DI (match_operand:DI 1 "se_register_operand" "0,d")
+		   (match_operand:SI 2 "arith_operand" "d,I")))]
+  "TARGET_64BIT && TARGET_MIPS16"
+  "*
+{
+  if (which_alternative == 0)
+    return \"dsll\\t%0,%2\";
+
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+
+  return \"dsll\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+			       (const_int 1)
+			       (const_int 2))])])
+
+
+;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ashift:DI (match_operand:DI 1 "register_operand" "")
+		   (match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_MIPS16 && TARGET_64BIT
+   && reload_completed
+   && GET_CODE (operands[2]) == CONST_INT
+   && INTVAL (operands[2]) > 8
+   && INTVAL (operands[2]) <= 16"
+  [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8)))
+   (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
+"
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
+}")
+
+(define_expand "ashrsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
+		     (match_operand:SI 2 "arith_operand" "dI")))]
+  ""
+  "
+{
+  /* On the mips16, a shift of more than 8 is a four byte instruction,
+     so, for a shift between 8 and 16, it is just as fast to do two
+     shifts of 8 or less.  If there is a lot of shifting going on, we
+     may win in CSE.  Otherwise combine will put the shifts back
+     together again.  */
+  if (TARGET_MIPS16
+      && optimize
+      && GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) > 8
+      && INTVAL (operands[2]) <= 16)
+    {
+      rtx temp = gen_reg_rtx (SImode);
+
+      emit_insn (gen_ashrsi3_internal2 (temp, operands[1], GEN_INT (8)));
+      emit_insn (gen_ashrsi3_internal2 (operands[0], temp,
+					GEN_INT (INTVAL (operands[2]) - 8)));
+      DONE;
+    }
+}")
+
+(define_insn "ashrsi3_internal1"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
+		     (match_operand:SI 2 "arith_operand" "dI")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+
+  return \"sra\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "ashrsi3_internal2"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
+		     (match_operand:SI 2 "arith_operand" "d,I")))]
+  "TARGET_MIPS16"
+  "*
+{
+  if (which_alternative == 0)
+    return \"sra\\t%0,%2\";
+
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+
+  return \"sra\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+			       (const_int 1)
+			       (const_int 2))])])
+
+
+;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")
+		     (match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_MIPS16
+   && reload_completed
+   && GET_CODE (operands[2]) == CONST_INT
+   && INTVAL (operands[2]) > 8
+   && INTVAL (operands[2]) <= 16"
+  [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8)))
+   (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
+"
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
+}")
+
+(define_expand "ashrdi3"
+  [(parallel [(set (match_operand:DI 0 "register_operand" "")
+		   (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "")
+				(match_operand:SI 2 "arith_operand" "")))
+	      (clobber (match_dup  3))])]
+  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+  "
+{
+  if (TARGET_64BIT)
+    {
+      /* On the mips16, a shift of more than 8 is a four byte
+	 instruction, so, for a shift between 8 and 16, it is just as
+	 fast to do two shifts of 8 or less.  If there is a lot of
+	 shifting going on, we may win in CSE.  Otherwise combine will
+	 put the shifts back together again.  */
+      if (TARGET_MIPS16
+	  && optimize
+	  && GET_CODE (operands[2]) == CONST_INT
+	  && INTVAL (operands[2]) > 8
+	  && INTVAL (operands[2]) <= 16)
+	{
+	  rtx temp = gen_reg_rtx (DImode);
+
+	  emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
+	  emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
+					    GEN_INT (INTVAL (operands[2]) - 8)));
+	  DONE;
+	}
+
+      emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
+					operands[2]));
+      DONE;
+    }
+
+  operands[3] = gen_reg_rtx (SImode);
+}")
+
+
+(define_insn "ashrdi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=&d")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
+  "* 
+{
+  operands[4] = const0_rtx;
+  dslots_jump_total += 3;
+  dslots_jump_filled += 2;
+
+  return \"sll\\t%3,%2,26\\n\\
+\\tbgez\\t%3,1f\\n\\
+\\tsra\\t%L0,%M1,%2\\n\\
+\\t%(b\\t3f\\n\\
+\\tsra\\t%M0,%M1,31%)\\n\\
+\\n\\
+1:\\n\\
+\\t%(beq\\t%3,%z4,2f\\n\\
+\\tsrl\\t%L0,%L1,%2%)\\n\\
+\\n\\
+\\tsubu\\t%3,%z4,%2\\n\\
+\\tsll\\t%3,%M1,%3\\n\\
+\\tor\\t%L0,%L0,%3\\n\\
+2:\\n\\
+\\tsra\\t%M0,%M1,%2\\n\\
+3:\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"12")])
+
+
+(define_insn "ashrdi3_internal2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+  return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+		     (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (const_int 31)))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+		     (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_insn "ashrdi3_internal3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+  "*
+{
+  int amount = INTVAL (operands[2]);
+
+  operands[2] = GEN_INT ((amount & 31));
+  operands[4] = GEN_INT (((-amount) & 31));
+
+  return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+		     (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
+		     (match_dup 2)))
+
+   (set (match_dup 3)
+	(ashift:SI (subreg:SI (match_dup 1) 1)
+		   (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(ior:SI (subreg:SI (match_dup 0) 0)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(ashiftrt:SI (subreg:SI (match_dup 1) 1)
+		     (match_dup 2)))]
+  "
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT ((amount & 31));
+  operands[4] = GEN_INT (((-amount) & 31));
+}")
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+		     (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 1)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 1)
+		     (match_dup 2)))
+
+   (set (match_dup 3)
+	(ashift:SI (subreg:SI (match_dup 1) 0)
+		   (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(ior:SI (subreg:SI (match_dup 0) 1)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(ashiftrt:SI (subreg:SI (match_dup 1) 0)
+		     (match_dup 2)))]
+  "
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT ((amount & 31));
+  operands[4] = GEN_INT (((-amount) & 31));
+}")
+
+
+(define_insn "ashrdi3_internal4"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
+		     (match_operand:SI 2 "arith_operand" "dI")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+
+  return \"dsra\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(ashiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
+		     (match_operand:SI 2 "arith_operand" "d,I")))]
+  "TARGET_64BIT && TARGET_MIPS16"
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+
+  return \"dsra\\t%0,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+			       (const_int 1)
+			       (const_int 2))])])
+
+;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "")
+		     (match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_MIPS16 && TARGET_64BIT
+   && reload_completed
+   && GET_CODE (operands[2]) == CONST_INT
+   && INTVAL (operands[2]) > 8
+   && INTVAL (operands[2]) <= 16"
+  [(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8)))
+   (set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))]
+"
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
+}")
+
+(define_expand "lshrsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
+		     (match_operand:SI 2 "arith_operand" "dI")))]
+  ""
+  "
+{
+  /* On the mips16, a shift of more than 8 is a four byte instruction,
+     so, for a shift between 8 and 16, it is just as fast to do two
+     shifts of 8 or less.  If there is a lot of shifting going on, we
+     may win in CSE.  Otherwise combine will put the shifts back
+     together again.  */
+  if (TARGET_MIPS16
+      && optimize
+      && GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) > 8
+      && INTVAL (operands[2]) <= 16)
+    {
+      rtx temp = gen_reg_rtx (SImode);
+
+      emit_insn (gen_lshrsi3_internal2 (temp, operands[1], GEN_INT (8)));
+      emit_insn (gen_lshrsi3_internal2 (operands[0], temp,
+					GEN_INT (INTVAL (operands[2]) - 8)));
+      DONE;
+    }
+}")
+
+(define_insn "lshrsi3_internal1"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
+		     (match_operand:SI 2 "arith_operand" "dI")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+
+  return \"srl\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "lshrsi3_internal2"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
+		     (match_operand:SI 2 "arith_operand" "d,I")))]
+  "TARGET_MIPS16"
+  "*
+{
+  if (which_alternative == 0)
+    return \"srl\\t%0,%2\";
+
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+
+  return \"srl\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+			       (const_int 1)
+			       (const_int 2))])])
+
+
+;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")
+		     (match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_MIPS16
+   && reload_completed
+   && GET_CODE (operands[2]) == CONST_INT
+   && INTVAL (operands[2]) > 8
+   && INTVAL (operands[2]) <= 16"
+  [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8)))
+   (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
+"
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
+}")
+
+;; If we load a byte on the mips16 as a bitfield, the resulting
+;; sequence of instructions is too complicated for combine, because it
+;; involves four instructions: a load, a shift, a constant load into a
+;; register, and an and (the key problem here is that the mips16 does
+;; not have and immediate).  We recognize a shift of a load in order
+;; to make it simple enough for combine to understand.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "R,m")
+		     (match_operand:SI 2 "immediate_operand" "I,I")))]
+  "TARGET_MIPS16"
+  "lw\\t%0,%1\;srl\\t%0,%2"
+  [(set_attr "type"	"load")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+			       (const_int 2)
+			       (const_int 3))
+		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+			       (const_int 3)
+			       (const_int 4))])])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "")
+		     (match_operand:SI 2 "immediate_operand" "")))]
+  "TARGET_MIPS16"
+  [(set (match_dup 0) (match_dup 1))
+   (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
+  "")
+
+(define_expand "lshrdi3"
+  [(parallel [(set (match_operand:DI 0 "register_operand" "")
+		   (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "")
+				(match_operand:SI 2 "arith_operand" "")))
+	      (clobber (match_dup  3))])]
+  "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+  "
+{
+  if (TARGET_64BIT)
+    {
+      /* On the mips16, a shift of more than 8 is a four byte
+	 instruction, so, for a shift between 8 and 16, it is just as
+	 fast to do two shifts of 8 or less.  If there is a lot of
+	 shifting going on, we may win in CSE.  Otherwise combine will
+	 put the shifts back together again.  */
+      if (TARGET_MIPS16
+	  && optimize
+	  && GET_CODE (operands[2]) == CONST_INT
+	  && INTVAL (operands[2]) > 8
+	  && INTVAL (operands[2]) <= 16)
+	{
+	  rtx temp = gen_reg_rtx (DImode);
+
+	  emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
+	  emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
+					    GEN_INT (INTVAL (operands[2]) - 8)));
+	  DONE;
+	}
+
+      emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
+					operands[2]));
+      DONE;
+    }
+
+  operands[3] = gen_reg_rtx (SImode);
+}")
+
+
+(define_insn "lshrdi3_internal"
+  [(set (match_operand:DI 0 "register_operand" "=&d")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:SI 2 "register_operand" "d")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
+  "* 
+{
+  operands[4] = const0_rtx;
+  dslots_jump_total += 3;
+  dslots_jump_filled += 2;
+
+  return \"sll\\t%3,%2,26\\n\\
+\\tbgez\\t%3,1f\\n\\
+\\tsrl\\t%L0,%M1,%2\\n\\
+\\t%(b\\t3f\\n\\
+\\tmove\\t%M0,%z4%)\\n\\
+\\n\\
+1:\\n\\
+\\t%(beq\\t%3,%z4,2f\\n\\
+\\tsrl\\t%L0,%L1,%2%)\\n\\
+\\n\\
+\\tsubu\\t%3,%z4,%2\\n\\
+\\tsll\\t%3,%M1,%3\\n\\
+\\tor\\t%L0,%L0,%3\\n\\
+2:\\n\\
+\\tsrl\\t%M0,%M1,%2\\n\\
+3:\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"12")])
+
+
+(define_insn "lshrdi3_internal2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && (INTVAL (operands[2]) & 32) != 0"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+  operands[4] = const0_rtx;
+  return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+		     (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 1) (const_int 0))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+		     (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 32) != 0"
+
+  [(set (subreg:SI (match_dup 0) 1) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
+   (set (subreg:SI (match_dup 0) 0) (const_int 0))]
+
+  "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
+
+
+(define_insn "lshrdi3_internal3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
+		   (match_operand:SI 2 "small_int" "IJK")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+  "*
+{
+  int amount = INTVAL (operands[2]);
+
+  operands[2] = GEN_INT ((amount & 31));
+  operands[4] = GEN_INT (((-amount) & 31));
+
+  return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
+}"
+  [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+		     (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 0)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
+		     (match_dup 2)))
+
+   (set (match_dup 3)
+	(ashift:SI (subreg:SI (match_dup 1) 1)
+		   (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(ior:SI (subreg:SI (match_dup 0) 0)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 1)
+		     (match_dup 2)))]
+  "
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT ((amount & 31));
+  operands[4] = GEN_INT (((-amount) & 31));
+}")
+
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+		     (match_operand:SI 2 "small_int" "")))
+   (clobber (match_operand:SI 3 "register_operand" ""))]
+  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
+   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
+   && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+   && (INTVAL (operands[2]) & 63) < 32
+   && (INTVAL (operands[2]) & 63) != 0"
+
+  [(set (subreg:SI (match_dup 0) 1)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 1)
+		     (match_dup 2)))
+
+   (set (match_dup 3)
+	(ashift:SI (subreg:SI (match_dup 1) 0)
+		   (match_dup 4)))
+
+   (set (subreg:SI (match_dup 0) 1)
+	(ior:SI (subreg:SI (match_dup 0) 1)
+		(match_dup 3)))
+
+   (set (subreg:SI (match_dup 0) 0)
+	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
+		     (match_dup 2)))]
+  "
+{
+  int amount = INTVAL (operands[2]);
+  operands[2] = GEN_INT ((amount & 31));
+  operands[4] = GEN_INT (((-amount) & 31));
+}")
+
+
+(define_insn "lshrdi3_internal4"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
+		     (match_operand:SI 2 "arith_operand" "dI")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+
+  return \"dsrl\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+;; CYGNUS LOCAL vr5400/raeburn
+(define_insn "rotrsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(rotatert:SI (match_operand:SI 1 "register_operand" "d")
+		     (match_operand:SI 2 "arith_operand" "dn")))]
+  "TARGET_MIPS5400"
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+
+  return \"ror\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")])
+
+(define_insn "rotrdi3"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(rotatert:DI (match_operand:DI 1 "register_operand" "d")
+		     (match_operand:DI 2 "arith_operand" "dn")))]
+  "TARGET_MIPS5400 && TARGET_64BIT"
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+
+  return \"dror\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")])
+;; END CYGNUS LOCAL
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(lshiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
+		     (match_operand:SI 2 "arith_operand" "d,I")))]
+  "TARGET_64BIT && TARGET_MIPS16"
+  "*
+{
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+
+  return \"dsrl\\t%0,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+			       (const_int 1)
+			       (const_int 2))])])
+
+;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
+		     (match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_MIPS16
+   && reload_completed
+   && GET_CODE (operands[2]) == CONST_INT
+   && INTVAL (operands[2]) > 8
+   && INTVAL (operands[2]) <= 16"
+  [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8)))
+   (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))]
+"
+{
+  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
+}")
+
+
+;;  ....................
+;;	COMPARISONS
+;;  ....................
+
+;; Flow here is rather complex:
+;;  1)	The cmp{si,di,sf,df} routine is called.  It deposits the
+;;	arguments into the branch_cmp array, and the type into
+;;	branch_type.  No RTL is generated.
+;;  2)	The appropriate branch define_expand is called, which then
+;;	creates the appropriate RTL for the comparison and branch.
+;;	Different CC modes are used, based on what type of branch is
+;;	done, so that we can constrain things appropriately.  There
+;;	are assumptions in the rest of GCC that break if we fold the
+;;	operands into the branchs for integer operations, and use cc0
+;;	for floating point, so we use the fp status register instead.
+;;	If needed, an appropriate temporary is created to hold the
+;;	of the integer compare.
+
+(define_expand "cmpsi"
+  [(set (cc0)
+	(compare:CC (match_operand:SI 0 "register_operand" "")
+		    (match_operand:SI 1 "arith_operand" "")))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code message */
+    {
+      branch_cmp[0] = operands[0];
+      branch_cmp[1] = operands[1];
+      branch_type = CMP_SI;
+      DONE;
+    }
+}")
+
+(define_expand "tstsi"
+  [(set (cc0)
+	(match_operand:SI 0 "register_operand" ""))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code message */
+    {
+      branch_cmp[0] = operands[0];
+      branch_cmp[1] = const0_rtx;
+      branch_type = CMP_SI;
+      DONE;
+    }
+}")
+
+(define_expand "cmpdi"
+  [(set (cc0)
+	(compare:CC (match_operand:DI 0 "se_register_operand" "")
+		    (match_operand:DI 1 "se_arith_operand" "")))]
+  "TARGET_64BIT"
+  "
+{
+  if (operands[0])		/* avoid unused code message */
+    {
+      branch_cmp[0] = operands[0];
+      branch_cmp[1] = operands[1];
+      branch_type = CMP_DI;
+      DONE;
+    }
+}")
+
+(define_expand "tstdi"
+  [(set (cc0)
+	(match_operand:DI 0 "se_register_operand" ""))]
+  "TARGET_64BIT"
+  "
+{
+  if (operands[0])		/* avoid unused code message */
+    {
+      branch_cmp[0] = operands[0];
+      branch_cmp[1] = const0_rtx;
+      branch_type = CMP_DI;
+      DONE;
+    }
+}")
+
+(define_expand "cmpdf"
+  [(set (cc0)
+	(compare:CC (match_operand:DF 0 "register_operand" "")
+		    (match_operand:DF 1 "register_operand" "")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "
+{
+  if (operands[0])		/* avoid unused code message */
+    {
+      branch_cmp[0] = operands[0];
+      branch_cmp[1] = operands[1];
+      branch_type = CMP_DF;
+      DONE;
+    }
+}")
+
+(define_expand "cmpsf"
+  [(set (cc0)
+	(compare:CC (match_operand:SF 0 "register_operand" "")
+		    (match_operand:SF 1 "register_operand" "")))]
+  "TARGET_HARD_FLOAT"
+  "
+{
+  if (operands[0])		/* avoid unused code message */
+    {
+      branch_cmp[0] = operands[0];
+      branch_cmp[1] = operands[1];
+      branch_type = CMP_SF;
+      DONE;
+    }
+}")
+
+
+;;  ....................
+;;	CONDITIONAL BRANCHES
+;;  ....................
+
+(define_insn "branch_fp_ne"
+  [(set (pc)
+	(if_then_else (ne:CC (match_operand:CC 0 "register_operand" "z")
+			     (const_int 0))
+		      (match_operand 1 "pc_or_label_operand" "")
+		      (match_operand 2 "pc_or_label_operand" "")))]
+  "TARGET_HARD_FLOAT"
+  "*
+{
+  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
+  return (operands[1] != pc_rtx) ? \"%*bc1t%?\\t%Z0%1\" : \"%*bc1f%?\\t%Z0%2\";
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "branch_fp_eq"
+  [(set (pc)
+	(if_then_else (eq:CC (match_operand:CC 0 "register_operand" "z")
+			     (const_int 0))
+		      (match_operand 1 "pc_or_label_operand" "")
+		      (match_operand 2 "pc_or_label_operand" "")))]
+  "TARGET_HARD_FLOAT"
+  "*
+{
+  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
+  return (operands[1] != pc_rtx) ? \"%*bc1f%?\\t%Z0%1\" : \"%*bc1t%?\\t%Z0%2\";
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "branch_zero"
+  [(set (pc)
+	(if_then_else (match_operator:SI 0 "cmp_op"
+					 [(match_operand:SI 1 "register_operand" "d")
+					  (const_int 0)])
+	(match_operand 2 "pc_or_label_operand" "")
+	(match_operand 3 "pc_or_label_operand" "")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
+  if (operands[2] != pc_rtx)
+    {				/* normal jump */
+      switch (GET_CODE (operands[0]))
+	{
+	case EQ:  return \"%*beq%?\\t%z1,%.,%2\";
+	case NE:  return \"%*bne%?\\t%z1,%.,%2\";
+	case GTU: return \"%*bne%?\\t%z1,%.,%2\";
+	case LEU: return \"%*beq%?\\t%z1,%.,%2\";
+	case GEU: return \"%*j\\t%2\";
+	case LTU: return \"%*bne%?\\t%.,%.,%2\";
+	default:
+	  break;
+	}
+
+      return \"%*b%C0z%?\\t%z1,%2\";
+    }
+  else
+    {				/* inverted jump */
+      switch (GET_CODE (operands[0]))
+	{
+	case EQ:  return \"%*bne%?\\t%z1,%.,%3\";
+	case NE:  return \"%*beq%?\\t%z1,%.,%3\";
+	case GTU: return \"%*beq%?\\t%z1,%.,%3\";
+	case LEU: return \"%*bne%?\\t%z1,%.,%3\";
+	case GEU: return \"%*beq%?\\t%.,%.,%3\";
+	case LTU: return \"%*j\\t%3\";
+	default:
+	  break;
+	}
+
+      return \"%*b%N0z%?\\t%z1,%3\";
+    }
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator:SI 0 "equality_op"
+					 [(match_operand:SI 1 "register_operand" "d,t")
+					  (const_int 0)])
+	(match_operand 2 "pc_or_label_operand" "")
+	(match_operand 3 "pc_or_label_operand" "")))]
+  "TARGET_MIPS16"
+  "*
+{
+  if (operands[2] != pc_rtx)
+    {
+      if (which_alternative == 0)
+	return \"%*b%C0z\\t%1,%2\";
+      else
+	return \"%*bt%C0z\\t%2\";
+    }
+  else
+    {
+      if (which_alternative == 0)
+	return \"%*b%N0z\\t%1,%3\";
+      else
+	return \"%*bt%N0z\\t%3\";
+    }
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_insn "branch_zero_di"
+  [(set (pc)
+	(if_then_else (match_operator:DI 0 "cmp_op"
+					 [(match_operand:DI 1 "se_register_operand" "d")
+					  (const_int 0)])
+	(match_operand 2 "pc_or_label_operand" "")
+	(match_operand 3 "pc_or_label_operand" "")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
+  if (operands[2] != pc_rtx)
+    {				/* normal jump */
+      switch (GET_CODE (operands[0]))
+	{
+	case EQ:  return \"%*beq%?\\t%z1,%.,%2\";
+	case NE:  return \"%*bne%?\\t%z1,%.,%2\";
+	case GTU: return \"%*bne%?\\t%z1,%.,%2\";
+	case LEU: return \"%*beq%?\\t%z1,%.,%2\";
+	case GEU: return \"%*j\\t%2\";
+	case LTU: return \"%*bne%?\\t%.,%.,%2\";
+	default:
+	  break;
+	}
+
+      return \"%*b%C0z%?\\t%z1,%2\";
+    }
+  else
+    {				/* inverted jump */
+      switch (GET_CODE (operands[0]))
+	{
+	case EQ:  return \"%*bne%?\\t%z1,%.,%3\";
+	case NE:  return \"%*beq%?\\t%z1,%.,%3\";
+	case GTU: return \"%*beq%?\\t%z1,%.,%3\";
+	case LEU: return \"%*bne%?\\t%z1,%.,%3\";
+	case GEU: return \"%*beq%?\\t%.,%.,%3\";
+	case LTU: return \"%*j\\t%3\";
+	default:
+	  break;
+	}
+
+      return \"%*b%N0z%?\\t%z1,%3\";
+    }
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else (match_operator:DI 0 "equality_op"
+					 [(match_operand:DI 1 "se_register_operand" "d,t")
+					  (const_int 0)])
+	(match_operand 2 "pc_or_label_operand" "")
+	(match_operand 3 "pc_or_label_operand" "")))]
+  "TARGET_MIPS16"
+  "*
+{
+  if (operands[2] != pc_rtx)
+    {
+      if (which_alternative == 0)
+	return \"%*b%C0z\\t%1,%2\";
+      else
+	return \"%*bt%C0z\\t%2\";
+    }
+  else
+    {
+      if (which_alternative == 0)
+	return \"%*b%N0z\\t%1,%3\";
+      else
+	return \"%*bt%N0z\\t%3\";
+    }
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+
+(define_insn "branch_equality"
+  [(set (pc)
+	(if_then_else (match_operator:SI 0 "equality_op"
+					 [(match_operand:SI 1 "register_operand" "d")
+					  (match_operand:SI 2 "register_operand" "d")])
+	(match_operand 3 "pc_or_label_operand" "")
+	(match_operand 4 "pc_or_label_operand" "")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
+  return (operands[3] != pc_rtx)
+	? \"%*b%C0%?\\t%z1,%z2,%3\"
+	: \"%*b%N0%?\\t%z1,%z2,%4\";
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+
+(define_insn "branch_equality_di"
+  [(set (pc)
+	(if_then_else (match_operator:DI 0 "equality_op"
+					 [(match_operand:DI 1 "se_register_operand" "d")
+					  (match_operand:DI 2 "se_register_operand" "d")])
+	(match_operand 3 "pc_or_label_operand" "")
+	(match_operand 4 "pc_or_label_operand" "")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
+  return (operands[3] != pc_rtx)
+	? \"%*b%C0%?\\t%z1,%z2,%3\"
+	: \"%*b%N0%?\\t%z1,%z2,%4\";
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+
+(define_expand "beq"
+  [(set (pc)
+	(if_then_else (eq:CC (cc0)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code warning */
+    {
+      gen_conditional_branch (operands, EQ);
+      DONE;
+    }
+}")
+
+(define_expand "bne"
+  [(set (pc)
+	(if_then_else (ne:CC (cc0)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code warning */
+    {
+      gen_conditional_branch (operands, NE);
+      DONE;
+    }
+}")
+
+(define_expand "bgt"
+  [(set (pc)
+	(if_then_else (gt:CC (cc0)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code warning */
+    {
+      gen_conditional_branch (operands, GT);
+      DONE;
+    }
+}")
+
+(define_expand "bge"
+  [(set (pc)
+	(if_then_else (ge:CC (cc0)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code warning */
+    {
+      gen_conditional_branch (operands, GE);
+      DONE;
+    }
+}")
+
+(define_expand "blt"
+  [(set (pc)
+	(if_then_else (lt:CC (cc0)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code warning */
+    {
+      gen_conditional_branch (operands, LT);
+      DONE;
+    }
+}")
+
+(define_expand "ble"
+  [(set (pc)
+	(if_then_else (le:CC (cc0)
+			     (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code warning */
+    {
+      gen_conditional_branch (operands, LE);
+      DONE;
+    }
+}")
+
+(define_expand "bgtu"
+  [(set (pc)
+	(if_then_else (gtu:CC (cc0)
+			      (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code warning */
+    {
+      gen_conditional_branch (operands, GTU);
+      DONE;
+    }
+}")
+
+(define_expand "bgeu"
+  [(set (pc)
+	(if_then_else (geu:CC (cc0)
+			      (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code warning */
+    {
+      gen_conditional_branch (operands, GEU);
+      DONE;
+    }
+}")
+
+
+(define_expand "bltu"
+  [(set (pc)
+	(if_then_else (ltu:CC (cc0)
+			      (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code warning */
+    {
+      gen_conditional_branch (operands, LTU);
+      DONE;
+    }
+}")
+
+(define_expand "bleu"
+  [(set (pc)
+	(if_then_else (leu:CC (cc0)
+			      (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  if (operands[0])		/* avoid unused code warning */
+    {
+      gen_conditional_branch (operands, LEU);
+      DONE;
+    }
+}")
+
+
+;;  ....................
+;;	SETTING A REGISTER FROM A COMPARISON
+;;  ....................
+
+(define_expand "seq"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(eq:SI (match_dup 1)
+	       (match_dup 2)))]
+  ""
+  "
+{
+  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+    FAIL;
+
+  /* set up operands from compare.  */
+  operands[1] = branch_cmp[0];
+  operands[2] = branch_cmp[1];
+
+  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+    {
+      gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
+      DONE;
+    }
+
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+    operands[2] = force_reg (SImode, operands[2]);
+
+  /* fall through and generate default code */
+}")
+
+
+(define_insn "seq_si_zero"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(eq:SI (match_operand:SI 1 "register_operand" "d")
+	       (const_int 0)))]
+  "!TARGET_MIPS16"
+  "sltu\\t%0,%1,1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=t")
+	(eq:SI (match_operand:SI 1 "register_operand" "d")
+	       (const_int 0)))]
+  "TARGET_MIPS16"
+  "sltu\\t%1,1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "seq_di_zero"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(eq:DI (match_operand:DI 1 "se_register_operand" "d")
+	       (const_int 0)))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "sltu\\t%0,%1,1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=t")
+	(eq:DI (match_operand:DI 1 "se_register_operand" "d")
+	       (const_int 0)))]
+  "TARGET_64BIT && TARGET_MIPS16"
+  "sltu\\t%1,1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn "seq_si"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(eq:SI (match_operand:SI 1 "register_operand" "%d,d")
+	       (match_operand:SI 2 "uns_arith_operand" "d,K")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "@
+   xor\\t%0,%1,%2\;sltu\\t%0,%0,1
+   xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(eq:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "uns_arith_operand" "")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
+  [(set (match_dup 0)
+	(xor:SI (match_dup 1)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(ltu:SI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+(define_insn "seq_di"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(eq:DI (match_operand:DI 1 "se_register_operand" "%d,d")
+	       (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "@
+   xor\\t%0,%1,%2\;sltu\\t%0,%0,1
+   xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(eq:DI (match_operand:DI 1 "se_register_operand" "")
+	       (match_operand:DI 2 "se_uns_arith_operand" "")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
+    && !TARGET_MIPS16
+    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
+  [(set (match_dup 0)
+	(xor:DI (match_dup 1)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(ltu:DI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+;; On the mips16 the default code is better than using sltu.
+
+(define_expand "sne"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ne:SI (match_dup 1)
+	       (match_dup 2)))]
+  "!TARGET_MIPS16"
+  "
+{
+  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+    FAIL;
+
+  /* set up operands from compare.  */
+  operands[1] = branch_cmp[0];
+  operands[2] = branch_cmp[1];
+
+  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
+    {
+      gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
+      DONE;
+    }
+
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+    operands[2] = force_reg (SImode, operands[2]);
+
+  /* fall through and generate default code */
+}")
+
+(define_insn "sne_si_zero"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ne:SI (match_operand:SI 1 "register_operand" "d")
+	       (const_int 0)))]
+  "!TARGET_MIPS16"
+  "sltu\\t%0,%.,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "sne_di_zero"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ne:DI (match_operand:DI 1 "se_register_operand" "d")
+	       (const_int 0)))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "sltu\\t%0,%.,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn "sne_si"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(ne:SI (match_operand:SI 1 "register_operand" "%d,d")
+	       (match_operand:SI 2 "uns_arith_operand" "d,K")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "@
+    xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
+    xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ne:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "uns_arith_operand" "")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
+    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
+  [(set (match_dup 0)
+	(xor:SI (match_dup 1)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(gtu:SI (match_dup 0)
+		(const_int 0)))]
+  "")
+
+(define_insn "sne_di"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(ne:DI (match_operand:DI 1 "se_register_operand" "%d,d")
+	       (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "@
+    xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
+    xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ne:DI (match_operand:DI 1 "se_register_operand" "")
+	       (match_operand:DI 2 "se_uns_arith_operand" "")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
+    && !TARGET_MIPS16
+    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
+  [(set (match_dup 0)
+	(xor:DI (match_dup 1)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(gtu:DI (match_dup 0)
+		(const_int 0)))]
+  "")
+
+(define_expand "sgt"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(gt:SI (match_dup 1)
+	       (match_dup 2)))]
+  ""
+  "
+{
+  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+    FAIL;
+
+  /* set up operands from compare.  */
+  operands[1] = branch_cmp[0];
+  operands[2] = branch_cmp[1];
+
+  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+    {
+      gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
+      DONE;
+    }
+
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
+    operands[2] = force_reg (SImode, operands[2]);
+
+  /* fall through and generate default code */
+}")
+
+(define_insn "sgt_si"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(gt:SI (match_operand:SI 1 "register_operand" "d")
+	       (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
+  "!TARGET_MIPS16"
+  "slt\\t%0,%z2,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=t")
+	(gt:SI (match_operand:SI 1 "register_operand" "d")
+	       (match_operand:SI 2 "register_operand" "d")))]
+  "TARGET_MIPS16"
+  "slt\\t%2,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "sgt_di"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(gt:DI (match_operand:DI 1 "se_register_operand" "d")
+	       (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "slt\\t%0,%z2,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(gt:DI (match_operand:DI 1 "se_register_operand" "d")
+	       (match_operand:DI 2 "se_register_operand" "d")))]
+  "TARGET_64BIT && TARGET_MIPS16"
+  "slt\\t%2,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_expand "sge"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ge:SI (match_dup 1)
+	       (match_dup 2)))]
+  ""
+  "
+{
+  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+    FAIL;
+
+  /* set up operands from compare.  */
+  operands[1] = branch_cmp[0];
+  operands[2] = branch_cmp[1];
+
+  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+    {
+      gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
+      DONE;
+    }
+
+  /* fall through and generate default code */
+}")
+
+(define_insn "sge_si"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ge:SI (match_operand:SI 1 "register_operand" "d")
+	       (match_operand:SI 2 "arith_operand" "dI")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ge:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "arith_operand" "")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
+  [(set (match_dup 0)
+	(lt:SI (match_dup 1)
+	       (match_dup 2)))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+(define_insn "sge_di"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ge:DI (match_operand:DI 1 "se_register_operand" "d")
+	       (match_operand:DI 2 "se_arith_operand" "dI")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(ge:DI (match_operand:DI 1 "se_register_operand" "")
+	       (match_operand:DI 2 "se_arith_operand" "")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
+   && !TARGET_MIPS16"
+  [(set (match_dup 0)
+	(lt:DI (match_dup 1)
+	       (match_dup 2)))
+   (set (match_dup 0)
+	(xor:DI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+(define_expand "slt"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(lt:SI (match_dup 1)
+	       (match_dup 2)))]
+  ""
+  "
+{
+  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+    FAIL;
+
+  /* set up operands from compare.  */
+  operands[1] = branch_cmp[0];
+  operands[2] = branch_cmp[1];
+
+  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+    {
+      gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
+      DONE;
+    }
+
+  /* fall through and generate default code */
+}")
+
+(define_insn "slt_si"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(lt:SI (match_operand:SI 1 "register_operand" "d")
+	       (match_operand:SI 2 "arith_operand" "dI")))]
+  "!TARGET_MIPS16"
+  "slt\\t%0,%1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=t,t")
+	(lt:SI (match_operand:SI 1 "register_operand" "d,d")
+	       (match_operand:SI 2 "arith_operand" "d,I")))]
+  "TARGET_MIPS16"
+  "slt\\t%1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))])])
+
+(define_insn "slt_di"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(lt:DI (match_operand:DI 1 "se_register_operand" "d")
+	       (match_operand:DI 2 "se_arith_operand" "dI")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "slt\\t%0,%1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=t,t")
+	(lt:DI (match_operand:DI 1 "se_register_operand" "d,d")
+	       (match_operand:DI 2 "se_arith_operand" "d,I")))]
+  "TARGET_64BIT && TARGET_MIPS16"
+  "slt\\t%1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))])])
+
+(define_expand "sle"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(le:SI (match_dup 1)
+	       (match_dup 2)))]
+  ""
+  "
+{
+  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+    FAIL;
+
+  /* set up operands from compare.  */
+  operands[1] = branch_cmp[0];
+  operands[2] = branch_cmp[1];
+
+  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+    {
+      gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
+      DONE;
+    }
+
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
+    operands[2] = force_reg (SImode, operands[2]);
+
+  /* fall through and generate default code */
+}")
+
+(define_insn "sle_si_const"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(le:SI (match_operand:SI 1 "register_operand" "d")
+	       (match_operand:SI 2 "small_int" "I")))]
+  "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2])+1);
+  return \"slt\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=t")
+	(le:SI (match_operand:SI 1 "register_operand" "d")
+	       (match_operand:SI 2 "small_int" "I")))]
+  "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2])+1);
+  return \"slt\\t%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn "sle_di_const"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(le:DI (match_operand:DI 1 "se_register_operand" "d")
+	       (match_operand:DI 2 "small_int" "I")))]
+  "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2])+1);
+  return \"slt\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=t")
+	(le:DI (match_operand:DI 1 "se_register_operand" "d")
+	       (match_operand:DI 2 "small_int" "I")))]
+  "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2])+1);
+  return \"slt\\t%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn "sle_si_reg"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(le:SI (match_operand:SI 1 "register_operand" "d")
+	       (match_operand:SI 2 "register_operand" "d")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(le:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "register_operand" "")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
+  [(set (match_dup 0)
+	(lt:SI (match_dup 2)
+	       (match_dup 1)))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+(define_insn "sle_di_reg"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(le:DI (match_operand:DI 1 "se_register_operand" "d")
+	       (match_operand:DI 2 "se_register_operand" "d")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(le:DI (match_operand:DI 1 "se_register_operand" "")
+	       (match_operand:DI 2 "se_register_operand" "")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
+   && !TARGET_MIPS16"
+  [(set (match_dup 0)
+	(lt:DI (match_dup 2)
+	       (match_dup 1)))
+   (set (match_dup 0)
+	(xor:DI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+(define_expand "sgtu"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(gtu:SI (match_dup 1)
+		(match_dup 2)))]
+  ""
+  "
+{
+  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+    FAIL;
+
+  /* set up operands from compare.  */
+  operands[1] = branch_cmp[0];
+  operands[2] = branch_cmp[1];
+
+  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+    {
+      gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
+      DONE;
+    }
+
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
+    operands[2] = force_reg (SImode, operands[2]);
+
+  /* fall through and generate default code */
+}")
+
+(define_insn "sgtu_si"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(gtu:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "reg_or_0_operand" "dJ")))]
+  ""
+  "sltu\\t%0,%z2,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=t")
+	(gtu:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "register_operand" "d")))]
+  ""
+  "sltu\\t%2,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn "sgtu_di"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(gtu:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
+  "TARGET_64BIT"
+  "sltu\\t%0,%z2,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=t")
+	(gtu:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "TARGET_64BIT"
+  "sltu\\t%2,%1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_expand "sgeu"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (geu:SI (match_dup 1)
+                (match_dup 2)))]
+  ""
+  "
+{
+  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+    FAIL;
+
+  /* set up operands from compare.  */
+  operands[1] = branch_cmp[0];
+  operands[2] = branch_cmp[1];
+
+  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+    {
+      gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
+      DONE;
+    }
+
+  /* fall through and generate default code */
+}")
+
+(define_insn "sgeu_si"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(geu:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "arith_operand" "dI")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(geu:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "arith_operand" "")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
+  [(set (match_dup 0)
+	(ltu:SI (match_dup 1)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+(define_insn "sgeu_di"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(geu:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_arith_operand" "dI")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(geu:DI (match_operand:DI 1 "se_register_operand" "")
+		(match_operand:DI 2 "se_arith_operand" "")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
+   && !TARGET_MIPS16"
+  [(set (match_dup 0)
+	(ltu:DI (match_dup 1)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(xor:DI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+(define_expand "sltu"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ltu:SI (match_dup 1)
+		(match_dup 2)))]
+  ""
+  "
+{
+  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+    FAIL;
+
+  /* set up operands from compare.  */
+  operands[1] = branch_cmp[0];
+  operands[2] = branch_cmp[1];
+
+  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+    {
+      gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
+      DONE;
+    }
+
+  /* fall through and generate default code */
+}")
+
+(define_insn "sltu_si"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(ltu:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "arith_operand" "dI")))]
+  "!TARGET_MIPS16"
+  "sltu\\t%0,%1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=t,t")
+	(ltu:SI (match_operand:SI 1 "register_operand" "d,d")
+		(match_operand:SI 2 "arith_operand" "d,I")))]
+  "TARGET_MIPS16"
+  "sltu\\t%1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))])])
+
+(define_insn "sltu_di"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ltu:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_arith_operand" "dI")))]
+  "TARGET_64BIT && !TARGET_MIPS16"
+  "sltu\\t%0,%1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=t,t")
+	(ltu:DI (match_operand:DI 1 "se_register_operand" "d,d")
+		(match_operand:DI 2 "se_arith_operand" "d,I")))]
+  "TARGET_64BIT && TARGET_MIPS16"
+  "sltu\\t%1,%2"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr_alternative "length"
+		[(const_int 1)
+		 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+			       (const_int 1)
+			       (const_int 2))])])
+
+(define_expand "sleu"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(leu:SI (match_dup 1)
+		(match_dup 2)))]
+  ""
+  "
+{
+  if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
+    FAIL;
+
+  /* set up operands from compare.  */
+  operands[1] = branch_cmp[0];
+  operands[2] = branch_cmp[1];
+
+  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
+    {
+      gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
+      DONE;
+    }
+
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
+    operands[2] = force_reg (SImode, operands[2]);
+
+  /* fall through and generate default code */
+}")
+
+(define_insn "sleu_si_const"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(leu:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "small_int" "I")))]
+  "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2])+1);
+  return \"sltu\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=t")
+	(leu:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "small_int" "I")))]
+  "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2])+1);
+  return \"sltu\\t%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn "sleu_di_const"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(leu:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "small_int" "I")))]
+  "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2])+1);
+  return \"sltu\\t%0,%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"1")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=t")
+	(leu:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "small_int" "I")))]
+  "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
+  "*
+{
+  operands[2] = GEN_INT (INTVAL (operands[2])+1);
+  return \"sltu\\t%1,%2\";
+}"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
+				      (const_int 1)
+				      (const_int 2)))])
+
+(define_insn "sleu_si_reg"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(leu:SI (match_operand:SI 1 "register_operand" "d")
+		(match_operand:SI 2 "register_operand" "d")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(leu:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "register_operand" "")))]
+  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
+  [(set (match_dup 0)
+	(ltu:SI (match_dup 2)
+		(match_dup 1)))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+(define_insn "sleu_di_reg"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(leu:DI (match_operand:DI 1 "se_register_operand" "d")
+		(match_operand:DI 2 "se_register_operand" "d")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
+  "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"2")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(leu:DI (match_operand:DI 1 "se_register_operand" "")
+		(match_operand:DI 2 "se_register_operand" "")))]
+  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
+   && !TARGET_MIPS16"
+  [(set (match_dup 0)
+	(ltu:DI (match_dup 2)
+		(match_dup 1)))
+   (set (match_dup 0)
+	(xor:DI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+
+;;  ....................
+;;	FLOATING POINT COMPARISONS
+;;  ....................
+
+(define_insn "seq_df"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(eq:CC (match_operand:DF 1 "register_operand" "f")
+	       (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
+}"
+ [(set_attr "type"	"fcmp")
+  (set_attr "mode"	"FPSW")
+  (set_attr "length"	"1")])
+
+(define_insn "slt_df"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(lt:CC (match_operand:DF 1 "register_operand" "f")
+	       (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
+}"
+ [(set_attr "type"	"fcmp")
+  (set_attr "mode"	"FPSW")
+  (set_attr "length"	"1")])
+
+(define_insn "sle_df"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(le:CC (match_operand:DF 1 "register_operand" "f")
+	       (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
+}"
+ [(set_attr "type"	"fcmp")
+  (set_attr "mode"	"FPSW")
+  (set_attr "length"	"1")])
+
+(define_insn "sgt_df"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(gt:CC (match_operand:DF 1 "register_operand" "f")
+	       (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
+}"
+ [(set_attr "type"	"fcmp")
+  (set_attr "mode"	"FPSW")
+  (set_attr "length"	"1")])
+
+(define_insn "sge_df"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(ge:CC (match_operand:DF 1 "register_operand" "f")
+	       (match_operand:DF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "*
+{
+  return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
+}"
+ [(set_attr "type"	"fcmp")
+  (set_attr "mode"	"FPSW")
+  (set_attr "length"	"1")])
+
+(define_insn "seq_sf"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(eq:CC (match_operand:SF 1 "register_operand" "f")
+	       (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "*
+{
+  return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
+}"
+ [(set_attr "type"	"fcmp")
+  (set_attr "mode"	"FPSW")
+  (set_attr "length"	"1")])
+
+(define_insn "slt_sf"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(lt:CC (match_operand:SF 1 "register_operand" "f")
+	       (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "*
+{
+  return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
+}"
+ [(set_attr "type"	"fcmp")
+  (set_attr "mode"	"FPSW")
+  (set_attr "length"	"1")])
+
+(define_insn "sle_sf"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(le:CC (match_operand:SF 1 "register_operand" "f")
+	       (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "*
+{
+  return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
+}"
+ [(set_attr "type"	"fcmp")
+  (set_attr "mode"	"FPSW")
+  (set_attr "length"	"1")])
+
+(define_insn "sgt_sf"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(gt:CC (match_operand:SF 1 "register_operand" "f")
+	       (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "*
+{
+  return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
+}"
+ [(set_attr "type"	"fcmp")
+  (set_attr "mode"	"FPSW")
+  (set_attr "length"	"1")])
+
+(define_insn "sge_sf"
+  [(set (match_operand:CC 0 "register_operand" "=z")
+	(ge:CC (match_operand:SF 1 "register_operand" "f")
+	       (match_operand:SF 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT"
+  "*
+{
+  return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
+}"
+ [(set_attr "type"	"fcmp")
+  (set_attr "mode"	"FPSW")
+  (set_attr "length"	"1")])
+
+
+;;  ....................
+;;	UNCONDITIONAL BRANCHES
+;;  ....................
+
+;; Unconditional branches.
+
+(define_insn "jump"
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  "!TARGET_MIPS16"
+  "*
+{
+  if (GET_CODE (operands[0]) == REG)
+    return \"%*j\\t%0\";
+  /* ??? I don't know why this is necessary.  This works around an
+     assembler problem that appears when a label is defined, then referenced
+     in a switch table, then used in a `j' instruction.  */
+  else if (mips_abi != ABI_32 && mips_abi != ABI_O64)
+    return \"%*b\\t%l0\";
+  else	
+    return \"%*j\\t%l0\";
+}"
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+;; We need a different insn for the mips16, because a mips16 branch
+;; does not have a delay slot.
+
+(define_insn ""
+  [(set (pc)
+	(label_ref (match_operand 0 "" "")))]
+  "TARGET_MIPS16 && GET_CODE (operands[0]) != REG"
+  "b\\t%l0"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_expand "indirect_jump"
+  [(set (pc) (match_operand 0 "register_operand" "d"))]
+  ""
+  "
+{
+  rtx dest;
+
+  if (operands[0])		/* eliminate unused code warnings */
+    {
+      dest = operands[0];
+      if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
+	operands[0] = copy_to_mode_reg (Pmode, dest);
+
+      if (!(Pmode == DImode))
+	emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
+      else
+	emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
+
+      DONE;
+    }
+}")
+
+(define_insn "indirect_jump_internal1"
+  [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
+  "!(Pmode == DImode)"
+  "%*j\\t%0"
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "indirect_jump_internal2"
+  [(set (pc) (match_operand:DI 0 "se_register_operand" "d"))]
+  "Pmode == DImode"
+  "%*j\\t%0"
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_expand "tablejump"
+  [(set (pc)
+	(match_operand 0 "register_operand" "d"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "
+{
+  if (operands[0])		/* eliminate unused code warnings */
+    {
+      if (TARGET_MIPS16)
+	{
+	  if (GET_MODE (operands[0]) != HImode)
+	    abort ();
+	  if (!(Pmode == DImode))
+	    emit_jump_insn (gen_tablejump_mips161 (operands[0], operands[1]));
+	  else
+	    emit_jump_insn (gen_tablejump_mips162 (operands[0], operands[1]));
+	  DONE;
+	}
+
+      if (GET_MODE (operands[0]) != Pmode)
+	abort ();
+
+      if (! flag_pic)
+	{
+	  if (!(Pmode == DImode))
+	    emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
+	  else
+	    emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
+	}
+      else
+	{
+	  if (!(Pmode == DImode))
+	    emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
+	  else
+	    emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
+	}
+
+      DONE;
+    }
+}")
+
+(define_insn "tablejump_internal1"
+  [(set (pc)
+	(match_operand:SI 0 "register_operand" "d"))
+   (use (label_ref (match_operand 1 "" "")))]
+  "!(Pmode == DImode)"
+  "%*j\\t%0"
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "tablejump_internal2"
+  [(set (pc)
+	(match_operand:DI 0 "se_register_operand" "d"))
+   (use (label_ref (match_operand 1 "" "")))]
+  "Pmode == DImode"
+  "%*j\\t%0"
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_expand "tablejump_internal3"
+  [(parallel [(set (pc)
+		   (plus:SI (match_operand:SI 0 "register_operand" "d")
+			    (label_ref:SI (match_operand:SI 1 "" ""))))
+	      (use (label_ref:SI (match_dup 1)))])]
+  ""
+  "")
+
+(define_expand "tablejump_mips161"
+  [(set (pc) (plus:SI (sign_extend:SI
+		       (match_operand:HI 0 "register_operand" "d"))
+		      (label_ref:SI (match_operand:SI 1 "" ""))))]
+  "TARGET_MIPS16 && !(Pmode == DImode)"
+  "
+{
+  if (operands[0])	/* eliminate unused code warnings.  */
+    {
+      rtx t1, t2, t3;
+
+      t1 = gen_reg_rtx (SImode);
+      t2 = gen_reg_rtx (SImode);
+      t3 = gen_reg_rtx (SImode);
+      emit_insn (gen_extendhisi2 (t1, operands[0]));
+      emit_move_insn (t2, gen_rtx (LABEL_REF, SImode, operands[1]));
+      emit_insn (gen_addsi3 (t3, t1, t2));
+      emit_insn (gen_tablejump_internal1 (t3, operands[1]));
+      DONE;
+    }
+}")
+
+(define_expand "tablejump_mips162"
+  [(set (pc) (plus:DI (sign_extend:DI
+		       (match_operand:HI 0 "register_operand" "d"))
+		      (label_ref:DI (match_operand:SI 1 "" ""))))]
+  "TARGET_MIPS16 && Pmode == DImode"
+  "
+{
+  if (operands[0])	/* eliminate unused code warnings.  */
+    {
+      rtx t1, t2, t3;
+
+      t1 = gen_reg_rtx (DImode);
+      t2 = gen_reg_rtx (DImode);
+      t3 = gen_reg_rtx (DImode);
+      emit_insn (gen_extendhidi2 (t1, operands[0]));
+      emit_move_insn (t2, gen_rtx (LABEL_REF, DImode, operands[1]));
+      emit_insn (gen_adddi3 (t3, t1, t2));
+      emit_insn (gen_tablejump_internal2 (t3, operands[1]));
+      DONE;
+    }
+}")
+
+;;; Make sure that this only matches the insn before ADDR_DIFF_VEC.  Otherwise
+;;; it is not valid.  ??? With the USE, the condition tests may not be required
+;;; any longer.
+
+;;; ??? The length depends on the ABI.  It is two for o32, and one for n32.
+;;; We just use the conservative number here.
+
+(define_insn ""
+  [(set (pc)
+	(plus:SI (match_operand:SI 0 "register_operand" "d")
+		 (label_ref:SI (match_operand:SI 1 "" ""))))
+   (use (label_ref:SI (match_dup 1)))]
+  "!(Pmode == DImode) && next_active_insn (insn) != 0
+   && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
+   && PREV_INSN (next_active_insn (insn)) == operands[1]"
+  "*
+{
+  /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic.  */
+  if (mips_abi == ABI_32 || mips_abi == ABI_O64)
+    output_asm_insn (\".cpadd\\t%0\", operands);
+  return \"%*j\\t%0\";
+}"
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_expand "tablejump_internal4"
+  [(parallel [(set (pc)
+		   (plus:DI (match_operand:DI 0 "se_register_operand" "d")
+			    (label_ref:DI (match_operand:SI 1 "" ""))))
+	      (use (label_ref:DI (match_dup 1)))])]
+  ""
+  "")
+
+;;; Make sure that this only matches the insn before ADDR_DIFF_VEC.  Otherwise
+;;; it is not valid.  ??? With the USE, the condition tests may not be required
+;;; any longer.
+
+(define_insn ""
+  [(set (pc)
+	(plus:DI (match_operand:DI 0 "se_register_operand" "d")
+		 (label_ref:DI (match_operand:SI 1 "" ""))))
+   (use (label_ref:DI (match_dup 1)))]
+  "Pmode == DImode && next_active_insn (insn) != 0
+   && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
+   && PREV_INSN (next_active_insn (insn)) == operands[1]"
+  "%*j\\t%0"
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+;; Implement a switch statement when generating embedded PIC code.
+;; Switches are implemented by `tablejump' when not using -membedded-pic.
+
+(define_expand "casesi"
+  [(set (match_dup 5)
+	(minus:SI (match_operand:SI 0 "register_operand" "d")
+		  (match_operand:SI 1 "arith_operand" "dI")))
+   (set (cc0)
+	(compare:CC (match_dup 5)
+		    (match_operand:SI 2 "arith_operand" "")))
+   (set (pc)
+	(if_then_else (gtu (cc0)
+			   (const_int 0))
+		      (label_ref (match_operand 4 "" ""))
+		      (pc)))
+   (parallel
+    [(set (pc)
+	  (mem:SI (plus:SI (mult:SI (match_dup 5)
+				    (const_int 4))
+			   (label_ref (match_operand 3 "" "")))))
+     (clobber (match_scratch:SI 6 ""))
+     (clobber (reg:SI 31))])]
+  "TARGET_EMBEDDED_PIC"
+  "
+{
+  /* We need slightly different code for eight byte table entries.  */
+  if (Pmode == DImode)
+    abort ();
+
+  if (operands[0])
+    {
+      rtx reg = gen_reg_rtx (SImode);
+
+      /* If the index is too large, go to the default label.  */
+      emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
+      emit_insn (gen_cmpsi (reg, operands[2]));
+      emit_insn (gen_bgtu (operands[4]));
+
+      /* Do the PIC jump.  */
+      emit_insn (gen_casesi_internal (reg, operands[3], gen_reg_rtx (SImode)));
+
+      DONE;
+    }
+}")
+
+;; An embedded PIC switch statement looks like this:
+;;	bal	$LS1
+;;	sll	$reg,$index,2
+;; $LS1:
+;;	addu	$reg,$reg,$31
+;;	lw	$reg,$L1-$LS1($reg)
+;;	addu	$reg,$reg,$31
+;;	j	$reg
+;; $L1:
+;;	.word	case1-$LS1
+;;	.word	case2-$LS1
+;;	...
+
+(define_insn "casesi_internal"
+  [(set (pc)
+	(mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
+				  (const_int 4))
+			 (label_ref (match_operand 1 "" "")))))
+   (clobber (match_operand:SI 2 "register_operand" "d"))
+   (clobber (reg:SI 31))]
+  "TARGET_EMBEDDED_PIC"
+  "*
+{
+  output_asm_insn (\"%(bal\\t%S1\;sll\\t%0,2\\n%S1:\", operands);
+  output_asm_insn (\"addu\\t%0,%0,$31%)\", operands);
+  output_asm_insn (\"lw\\t%0,%1-%S1(%0)\;addu\\t%0,%0,$31\", operands);
+  return \"j\\t%0\";
+}"
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"6")])
+
+;; For o32/n32/n64, we save the gp in the jmp_buf as well.  While it is
+;; possible to either pull it off the stack (in the o32 case) or recalculate
+;; it given t9 and our target label, it takes 3 or 4 insns to do so, and
+;; this is easy.
+
+(define_expand "builtin_setjmp_setup"
+  [(unspec [(match_operand 0 "register_operand" "r")] 20)]
+  "TARGET_ABICALLS"
+  "
+{
+  if (Pmode == DImode)
+    emit_insn (gen_builtin_setjmp_setup_64 (operands[0]));
+  else
+    emit_insn (gen_builtin_setjmp_setup_32 (operands[0]));
+  DONE;
+}")
+
+(define_expand "builtin_setjmp_setup_32"
+  [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
+		   (const_int 12)))
+      (reg:SI 28))]
+  "TARGET_ABICALLS && ! (Pmode == DImode)"
+  "")
+
+(define_expand "builtin_setjmp_setup_64"
+  [(set (mem:DI (plus:DI (match_operand:DI 0 "register_operand" "r")
+		   (const_int 24)))
+      (reg:DI 28))]
+  "TARGET_ABICALLS && Pmode == DImode"
+  "")
+
+;; For o32/n32/n64, we need to arrange for longjmp to put the 
+;; target address in t9 so that we can use it for loading $gp.
+
+(define_expand "builtin_longjmp"
+  [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
+  "TARGET_ABICALLS"
+  "
+{
+  /* The elements of the buffer are, in order:  */
+  int W = (Pmode == DImode ? 8 : 4);
+  rtx fp = gen_rtx_MEM (Pmode, operands[0]);
+  rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
+  rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
+  rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
+  rtx pv = gen_rtx_REG (Pmode, 25);
+  rtx gp = gen_rtx_REG (Pmode, 28);
+
+  /* This bit is the same as expand_builtin_longjmp.  */
+  emit_move_insn (hard_frame_pointer_rtx, fp);
+  emit_move_insn (pv, lab);
+  emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
+  emit_move_insn (gp, gpv);
+  emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
+  emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+  emit_insn (gen_rtx_USE (VOIDmode, gp));
+  emit_indirect_jump (pv);
+  DONE;
+}")
+
+;;  ....................
+;;	Function prologue/epilogue
+;;  ....................
+
+(define_expand "prologue"
+  [(const_int 1)]
+  ""
+  "
+{
+  if (mips_isa >= 0)		/* avoid unused code warnings */
+    {
+      mips_expand_prologue ();
+      DONE;
+    }
+}")
+
+;; Block any insns from being moved before this point, since the
+;; profiling call to mcount can use various registers that aren't
+;; saved or used to pass arguments.
+
+(define_insn "blockage"
+  [(unspec_volatile [(const_int 0)] 0)]
+  ""
+  ""
+  [(set_attr "type"	"unknown")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"0")])
+
+(define_expand "epilogue"
+  [(const_int 2)]
+  ""
+  "
+{
+  if (mips_isa >= 0)            /* avoid unused code warnings */
+    {
+      mips_expand_epilogue ();
+      DONE;
+    }
+}")
+
+;; Trivial return.  Make it look like a normal return insn as that
+;; allows jump optimizations to work better .
+(define_insn "return"
+  [(return)]
+  "mips_can_use_return_insn ()"
+  "%*j\\t$31"
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+;; Normal return.
+;; We match any mode for the return address, so that this will work with
+;; both 32 bit and 64 bit targets.
+(define_insn "return_internal"
+  [(use (match_operand 0 "register_operand" ""))
+   (return)]
+  ""
+  "*
+{
+  return \"%*j\\t%0\";
+}"
+  [(set_attr "type"	"jump")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+  
+;; When generating embedded PIC code we need to get the address of the
+;; current function.  This specialized instruction does just that.
+
+(define_insn "get_fnaddr"
+  [(set (match_operand 0 "register_operand" "=d")
+	(unspec [(match_operand 1 "" "")] 1))
+   (clobber (reg:SI 31))]
+  "TARGET_EMBEDDED_PIC
+   && GET_CODE (operands[1]) == SYMBOL_REF"
+  "%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"4")])
+
+
+;;  ....................
+;;	FUNCTION CALLS
+;;  ....................
+
+;; calls.c now passes a third argument, make saber happy
+
+(define_expand "call"
+  [(parallel [(call (match_operand 0 "memory_operand" "m")
+		    (match_operand 1 "" "i"))
+	      (clobber (reg:SI 31))
+	      (use (match_operand 2 "" ""))		;; next_arg_reg
+	      (use (match_operand 3 "" ""))])]		;; struct_value_size_rtx
+  ""
+  "
+{
+  rtx addr;
+
+  if (operands[0])		/* eliminate unused code warnings */
+    {
+      addr = XEXP (operands[0], 0);
+      if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
+	  || ! call_insn_operand (addr, VOIDmode))
+	XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
+
+      /* In order to pass small structures by value in registers
+	 compatibly with the MIPS compiler, we need to shift the value
+	 into the high part of the register.  Function_arg has encoded
+	 a PARALLEL rtx, holding a vector of adjustments to be made
+	 as the next_arg_reg variable, so we split up the insns,
+	 and emit them separately.  */
+
+      if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
+	{
+	  rtvec adjust = XVEC (operands[2], 0);
+	  int num = GET_NUM_ELEM (adjust);
+	  int i;
+
+	  for (i = 0; i < num; i++)
+	    emit_insn (RTVEC_ELT (adjust, i));
+	}
+
+      if (TARGET_MIPS16
+	  && mips16_hard_float
+	  && operands[2] != 0
+	  && (int) GET_MODE (operands[2]) != 0)
+	{
+	  if (build_mips16_call_stub (NULL_RTX, operands[0], operands[1],
+				      (int) GET_MODE (operands[2])))
+	    DONE;
+	}
+
+      emit_call_insn (gen_call_internal0 (operands[0], operands[1],
+					  gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
+
+      DONE;
+    }
+}")
+
+(define_expand "call_internal0"
+  [(parallel [(call (match_operand 0 "" "")
+		    (match_operand 1 "" ""))
+	      (clobber (match_operand:SI 2 "" ""))])]
+  ""
+  "")
+
+;; We need to recognize reg:SI 31 specially for the mips16, because we
+;; don't have a constraint letter for it.
+
+(define_insn ""
+  [(call (mem (match_operand 0 "call_insn_operand" "ei"))
+	 (match_operand 1 "" "i"))
+   (clobber (match_operand:SI 2 "register_operand" "=y"))]
+  "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS
+   && GET_CODE (operands[2]) == REG && REGNO (operands[2]) == 31"
+  "%*jal\\t%0"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_insn "call_internal1"
+  [(call (mem (match_operand 0 "call_insn_operand" "ri"))
+	 (match_operand 1 "" "i"))
+   (clobber (match_operand:SI 2 "register_operand" "=d"))]
+  "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
+  "*
+{
+  register rtx target = operands[0];
+
+  if (GET_CODE (target) == SYMBOL_REF)
+    return \"%*jal\\t%0\";
+  else if (GET_CODE (target) == CONST_INT)
+    return \"%[li\\t%@,%0\\n\\t%*jal\\t%2,%@%]\";
+  else
+    return \"%*jal\\t%2,%0\";
+}"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "call_internal2"
+  [(call (mem (match_operand 0 "call_insn_operand" "ri"))
+	 (match_operand 1 "" "i"))
+   (clobber (match_operand:SI 2 "register_operand" "=d"))]
+  "TARGET_ABICALLS && !TARGET_LONG_CALLS"
+  "*
+{
+  register rtx target = operands[0];
+
+  if (GET_CODE (target) == SYMBOL_REF)
+    {
+      if (GET_MODE (target) == SImode)
+	return \"la\\t%^,%0\\n\\tjal\\t%2,%^\";
+      else
+	return \"dla\\t%^,%0\\n\\tjal\\t%2,%^\";
+    }
+  else if (GET_CODE (target) == CONST_INT)
+    return \"li\\t%^,%0\\n\\tjal\\t%2,%^\";
+  else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
+    return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
+  else
+    return \"jal\\t%2,%0\";
+}"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_insn "call_internal3a"
+  [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
+	 (match_operand 1 "" "i"))
+   (clobber (match_operand:SI 2 "register_operand" "=d"))]
+  "!(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
+  "%*jal\\t%2,%0"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "call_internal3b"
+  [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
+	 (match_operand 1 "" "i"))
+   (clobber (match_operand:SI 2 "register_operand" "=d"))]
+  "Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
+  "%*jal\\t%2,%0"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "call_internal4a"
+  [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
+	 (match_operand 1 "" "i"))
+   (clobber (match_operand:SI 2 "register_operand" "=d"))]
+  "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS"
+  "*
+{
+  if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
+    return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
+  else
+    return \"jal\\t%2,%0\";
+}"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_insn "call_internal4b"
+  [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
+	 (match_operand 1 "" "i"))
+   (clobber (match_operand:SI 2 "register_operand" "=d"))]
+  "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS"
+  "*
+{
+  if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
+    return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
+  else
+    return \"jal\\t%2,%0\";
+}"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+;; calls.c now passes a fourth argument, make saber happy
+
+(define_expand "call_value"
+  [(parallel [(set (match_operand 0 "register_operand" "=df")
+		   (call (match_operand 1 "memory_operand" "m")
+			 (match_operand 2 "" "i")))
+	      (clobber (reg:SI 31))
+	      (use (match_operand 3 "" ""))])]		;; next_arg_reg
+  ""
+  "
+{
+  rtx addr;
+
+  if (operands[0])		/* eliminate unused code warning */
+    {
+      addr = XEXP (operands[1], 0);
+      if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
+	  || ! call_insn_operand (addr, VOIDmode))
+	XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
+
+      /* In order to pass small structures by value in registers
+	 compatibly with the MIPS compiler, we need to shift the value
+	 into the high part of the register.  Function_arg has encoded
+	 a PARALLEL rtx, holding a vector of adjustments to be made
+	 as the next_arg_reg variable, so we split up the insns,
+	 and emit them separately.  */
+
+      if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
+	{
+	  rtvec adjust = XVEC (operands[3], 0);
+	  int num = GET_NUM_ELEM (adjust);
+	  int i;
+
+	  for (i = 0; i < num; i++)
+	    emit_insn (RTVEC_ELT (adjust, i));
+	}
+
+      if (TARGET_MIPS16
+	  && mips16_hard_float
+	  && ((operands[3] != 0
+	       && (int) GET_MODE (operands[3]) != 0)
+	      || GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT))
+	{
+	  if (build_mips16_call_stub (operands[0], operands[1], operands[2],
+				      (operands[3] == 0 ? 0
+				       : (int) GET_MODE (operands[3]))))
+	    DONE;
+	}
+
+      /* Handle Irix6 function calls that have multiple non-contiguous
+	 results.  */
+      if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
+	{
+	  emit_call_insn (gen_call_value_multiple_internal0
+			  (XEXP (XVECEXP (operands[0], 0, 0), 0),
+			   operands[1], operands[2],
+			   XEXP (XVECEXP (operands[0], 0, 1), 0),
+			   gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
+	  DONE;
+	}
+
+      /* We have a call returning a DImode structure in an FP reg.
+	 Strip off the now unnecessary PARALLEL.  */
+      if (GET_CODE (operands[0]) == PARALLEL)
+	operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
+
+      emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
+					        gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
+
+      DONE;
+    }
+}")
+
+(define_expand "call_value_internal0"
+  [(parallel [(set (match_operand 0 "" "")
+		   (call (match_operand 1 "" "")
+			 (match_operand 2 "" "")))
+	      (clobber (match_operand:SI 3 "" ""))])]
+  ""
+  "")
+
+;; Recognize $31 specially on the mips16, because we don't have a
+;; constraint letter for it.
+
+(define_insn ""
+  [(set (match_operand 0 "register_operand" "=d")
+        (call (mem (match_operand 1 "call_insn_operand" "ei"))
+              (match_operand 2 "" "i")))
+   (clobber (match_operand:SI 3 "register_operand" "=y"))]
+  "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS
+   && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
+  "%*jal\\t%1"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_insn "call_value_internal1"
+  [(set (match_operand 0 "register_operand" "=df")
+        (call (mem (match_operand 1 "call_insn_operand" "ri"))
+              (match_operand 2 "" "i")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
+  "*
+{
+  register rtx target = operands[1];
+
+  if (GET_CODE (target) == SYMBOL_REF)
+    return \"%*jal\\t%1\";
+  else if (GET_CODE (target) == CONST_INT)
+    return \"%[li\\t%@,%1\\n\\t%*jal\\t%3,%@%]\";
+  else
+    return \"%*jal\\t%3,%1\";
+}"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "call_value_internal2"
+  [(set (match_operand 0 "register_operand" "=df")
+        (call (mem (match_operand 1 "call_insn_operand" "ri"))
+              (match_operand 2 "" "i")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "TARGET_ABICALLS && !TARGET_LONG_CALLS"
+  "*
+{
+  register rtx target = operands[1];
+
+  if (GET_CODE (target) == SYMBOL_REF)
+    {
+      if (GET_MODE (target) == SImode)
+	return \"la\\t%^,%1\\n\\tjal\\t%3,%^\";
+      else
+	return \"dla\\t%^,%1\\n\\tjal\\t%3,%^\";
+    }
+  else if (GET_CODE (target) == CONST_INT)
+    return \"li\\t%^,%1\\n\\tjal\\t%3,%^\";
+  else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
+    return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
+  else
+    return \"jal\\t%3,%1\";
+}"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_insn "call_value_internal3a"
+  [(set (match_operand 0 "register_operand" "=df")
+        (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	      (match_operand 2 "" "i")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_MIPS16 
+   && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
+  "%*jal\\t%3,%1"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "call_value_internal3b"
+  [(set (match_operand 0 "register_operand" "=df")
+        (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
+	      (match_operand 2 "" "i")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!TARGET_MIPS16 
+   && Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
+  "%*jal\\t%3,%1"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "call_value_internal3c"
+  [(set (match_operand 0 "register_operand" "=df")
+        (call (mem:SI (match_operand:SI 1 "register_operand" "e"))
+	      (match_operand 2 "" "i")))
+   (clobber (match_operand:SI 3 "register_operand" "=y"))]
+  "TARGET_MIPS16 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS
+   && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
+  "%*jal\\t%3,%1"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+(define_insn "call_value_internal4a"
+  [(set (match_operand 0 "register_operand" "=df")
+        (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	      (match_operand 2 "" "i")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS"
+  "*
+{
+  if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
+    return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
+  else
+    return \"jal\\t%3,%1\";
+}"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_insn "call_value_internal4b"
+  [(set (match_operand 0 "register_operand" "=df")
+        (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
+	      (match_operand 2 "" "i")))
+   (clobber (match_operand:SI 3 "register_operand" "=d"))]
+  "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS"
+  "*
+{
+  if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
+    return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
+  else
+    return \"jal\\t%3,%1\";
+}"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_expand "call_value_multiple_internal0"
+  [(parallel [(set (match_operand 0 "" "")
+		   (call (match_operand 1 "" "")
+			 (match_operand 2 "" "")))
+	      (set (match_operand 3 "" "")
+		   (call (match_dup 1)
+			 (match_dup 2)))
+	      (clobber (match_operand:SI 4 "" ""))])]
+  ""
+  "")
+
+;; ??? May eventually need all 6 versions of the call patterns with multiple
+;; return values.
+
+(define_insn "call_value_multiple_internal2"
+  [(set (match_operand 0 "register_operand" "=df")
+        (call (mem (match_operand 1 "call_insn_operand" "ri"))
+              (match_operand 2 "" "i")))
+   (set (match_operand 3 "register_operand" "=df")
+        (call (mem (match_dup 1))
+              (match_dup 2)))
+   (clobber (match_operand:SI 4 "register_operand" "=d"))]
+  "TARGET_ABICALLS && !TARGET_LONG_CALLS"
+  "*
+{
+  register rtx target = operands[1];
+
+  if (GET_CODE (target) == SYMBOL_REF)
+    {
+      if (GET_MODE (target) == SImode)
+	return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
+      else
+	return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
+    }
+  else if (GET_CODE (target) == CONST_INT)
+    return \"li\\t%^,%1\\n\\tjal\\t%4,%^\";
+  else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
+    return \"move\\t%^,%1\\n\\tjal\\t%4,%^\";
+  else
+    return \"jal\\t%4,%1\";
+}"
+  [(set_attr "type"	"call")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+
+;; Call subroutine returning any type.
+
+(define_expand "untyped_call"
+  [(parallel [(call (match_operand 0 "" "")
+		    (const_int 0))
+	      (match_operand 1 "" "")
+	      (match_operand 2 "" "")])]
+  ""
+  "
+{
+  if (operands[0])		/* silence statement not reached warnings */
+    {
+      int i;
+
+      emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
+
+      for (i = 0; i < XVECLEN (operands[2], 0); i++)
+	{
+	  rtx set = XVECEXP (operands[2], 0, i);
+	  emit_move_insn (SET_DEST (set), SET_SRC (set));
+	}
+
+      emit_insn (gen_blockage ());
+      DONE;
+    }
+}")
+
+;;  ....................
+;;	MISC.
+;;  ....................
+
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "%(nop%)"
+  [(set_attr "type"	"nop")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"1")])
+
+;; The MIPS chip does not seem to require stack probes.
+;; (define_expand "probe"
+;;   [(set (match_dup 0)
+;; 	(match_dup 1))]
+;;   ""
+;;   "
+;; {
+;;   operands[0] = gen_reg_rtx (SImode);
+;;   operands[1] = gen_rtx (MEM, SImode, stack_pointer_rtx);
+;;   MEM_VOLATILE_P (operands[1]) = TRUE;
+;;   /* fall through and generate default code */
+;; }")
+
+;; MIPS4 Conditional move instructions.
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(if_then_else:SI
+	 (match_operator 4 "equality_op"
+			 [(match_operand:SI 1 "register_operand" "d,d")
+			  (const_int 0)])
+	 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
+	 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
+  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
+  "@
+    mov%B4\\t%0,%z2,%1
+    mov%b4\\t%0,%z3,%1"
+  [(set_attr "type" "move")
+   (set_attr "mode" "SI")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(if_then_else:SI
+	 (match_operator 4 "equality_op"
+			 [(match_operand:DI 1 "se_register_operand" "d,d")
+			  (const_int 0)])
+	 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
+	 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
+  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
+  "@
+    mov%B4\\t%0,%z2,%1
+    mov%b4\\t%0,%z3,%1"
+  [(set_attr "type" "move")
+   (set_attr "mode" "SI")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+	(if_then_else:SI
+	 (match_operator 3 "equality_op" [(match_operand:CC 4
+							    "register_operand"
+							    "z,z")
+					  (const_int 0)])
+	 (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
+	 (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "@
+    mov%T3\\t%0,%z1,%4
+    mov%t3\\t%0,%z2,%4"
+  [(set_attr "type" "move")
+   (set_attr "mode" "SI")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(if_then_else:DI
+	 (match_operator 4 "equality_op"
+			 [(match_operand:SI 1 "register_operand" "d,d")
+			  (const_int 0)])
+	 (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
+	 (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
+  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
+  "@
+    mov%B4\\t%0,%z2,%1
+    mov%b4\\t%0,%z3,%1"
+  [(set_attr "type" "move")
+   (set_attr "mode" "DI")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(if_then_else:DI
+	 (match_operator 4 "equality_op"
+			 [(match_operand:DI 1 "se_register_operand" "d,d")
+			  (const_int 0)])
+	 (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
+	 (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
+  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
+  "@
+    mov%B4\\t%0,%z2,%1
+    mov%b4\\t%0,%z3,%1"
+  [(set_attr "type" "move")
+   (set_attr "mode" "DI")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+	(if_then_else:DI
+	 (match_operator 3 "equality_op" [(match_operand:CC 4
+							    "register_operand"
+							    "z,z")
+					  (const_int 0)])
+	 (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
+	 (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "@
+    mov%T3\\t%0,%z1,%4
+    mov%t3\\t%0,%z2,%4"
+  [(set_attr "type" "move")
+   (set_attr "mode" "DI")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(if_then_else:SF
+	 (match_operator 4 "equality_op"
+			 [(match_operand:SI 1 "register_operand" "d,d")
+			  (const_int 0)])
+	 (match_operand:SF 2 "register_operand" "f,0")
+	 (match_operand:SF 3 "register_operand" "0,f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "@
+    mov%B4.s\\t%0,%2,%1
+    mov%b4.s\\t%0,%3,%1"
+  [(set_attr "type" "move")
+   (set_attr "mode" "SF")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(if_then_else:SF
+	 (match_operator 3 "equality_op" [(match_operand:CC 4
+							    "register_operand"
+							    "z,z")
+					  (const_int 0)])
+	 (match_operand:SF 1 "register_operand" "f,0")
+	 (match_operand:SF 2 "register_operand" "0,f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "@
+    mov%T3.s\\t%0,%1,%4
+    mov%t3.s\\t%0,%2,%4"
+  [(set_attr "type" "move")
+   (set_attr "mode" "SF")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
+	(if_then_else:DF
+	 (match_operator 4 "equality_op"
+			 [(match_operand:SI 1 "register_operand" "d,d")
+			  (const_int 0)])
+	 (match_operand:DF 2 "register_operand" "f,0")
+	 (match_operand:DF 3 "register_operand" "0,f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "@
+    mov%B4.d\\t%0,%2,%1
+    mov%b4.d\\t%0,%3,%1"
+  [(set_attr "type" "move")
+   (set_attr "mode" "DF")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
+	(if_then_else:DF
+	 (match_operator 3 "equality_op" [(match_operand:CC 4
+							    "register_operand"
+							    "z,z")
+					  (const_int 0)])
+	 (match_operand:DF 1 "register_operand" "f,0")
+	 (match_operand:DF 2 "register_operand" "0,f")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "@
+    mov%T3.d\\t%0,%1,%4
+    mov%t3.d\\t%0,%2,%4"
+  [(set_attr "type" "move")
+   (set_attr "mode" "DF")])
+
+;; These are the main define_expand's used to make conditional moves.
+
+(define_expand "movsicc"
+  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
+   (set (match_operand:SI 0 "register_operand" "")
+	(if_then_else:SI (match_dup 5)
+			 (match_operand:SI 2 "reg_or_0_operand" "")
+			 (match_operand:SI 3 "reg_or_0_operand" "")))]
+  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
+  "
+{
+
+  gen_conditional_move (operands);
+  DONE;
+}")
+
+(define_expand "movdicc"
+  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
+   (set (match_operand:DI 0 "register_operand" "")
+	(if_then_else:DI (match_dup 5)
+			 (match_operand:DI 2 "se_reg_or_0_operand" "")
+			 (match_operand:DI 3 "se_reg_or_0_operand" "")))]
+  "mips_isa >= 4 || 0" ;;  CYGNUS LOCAL law
+  "
+{
+
+  gen_conditional_move (operands);
+  DONE;
+}")
+
+(define_expand "movsfcc"
+  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
+   (set (match_operand:SF 0 "register_operand" "")
+	(if_then_else:SF (match_dup 5)
+			 (match_operand:SF 2 "register_operand" "")
+			 (match_operand:SF 3 "register_operand" "")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT"
+  "
+{
+  gen_conditional_move (operands);
+  DONE;
+}")
+
+(define_expand "movdfcc"
+  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
+   (set (match_operand:DF 0 "register_operand" "")
+	(if_then_else:DF (match_dup 5)
+			 (match_operand:DF 2 "register_operand" "")
+			 (match_operand:DF 3 "register_operand" "")))]
+  "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+  "
+{
+  gen_conditional_move (operands);
+  DONE;
+}")
+
+;;  ....................
+;;	mips16 inline constant tables
+;;  ....................
+
+(define_insn "consttable_qi"
+  [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "=g")] 10)]
+  "TARGET_MIPS16"
+  "*
+{
+  assemble_integer (operands[0], 1, 1);
+  return \"\";
+}"
+  [(set_attr "type"	"unknown")
+   (set_attr "mode"	"QI")
+   (set_attr "length"	"2")])
+
+(define_insn "consttable_hi"
+  [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")] 11)]
+  "TARGET_MIPS16"
+  "*
+{
+  assemble_integer (operands[0], 2, 1);
+  return \"\";
+}"
+  [(set_attr "type"	"unknown")
+   (set_attr "mode"	"HI")
+   (set_attr "length"	"2")])
+
+(define_insn "consttable_si"
+  [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")] 12)]
+  "TARGET_MIPS16"
+  "*
+{
+  assemble_integer (operands[0], 4, 1);
+  return \"\";
+}"
+  [(set_attr "type"	"unknown")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
+(define_insn "consttable_di"
+  [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")] 13)]
+  "TARGET_MIPS16"
+  "*
+{
+  assemble_integer (operands[0], 8, 1);
+  return \"\";
+}"
+  [(set_attr "type"	"unknown")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+
+(define_insn "consttable_sf"
+  [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")] 14)]
+  "TARGET_MIPS16"
+  "*
+{
+  union real_extract u;
+
+  if (GET_CODE (operands[0]) != CONST_DOUBLE)
+    abort ();
+  bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
+  assemble_real (u.d, SFmode);
+  return \"\";
+}"
+  [(set_attr "type"	"unknown")
+   (set_attr "mode"	"SF")
+   (set_attr "length"	"2")])
+
+(define_insn "consttable_df"
+  [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")] 15)]
+  "TARGET_MIPS16"
+  "*
+{
+  union real_extract u;
+
+  if (GET_CODE (operands[0]) != CONST_DOUBLE)
+    abort ();
+  bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
+  assemble_real (u.d, DFmode);
+  return \"\";
+}"
+  [(set_attr "type"	"unknown")
+   (set_attr "mode"	"DF")
+   (set_attr "length"	"4")])
+
+(define_insn "align_2"
+  [(unspec_volatile [(const_int 0)] 16)]
+  "TARGET_MIPS16"
+  ".align 1"
+  [(set_attr "type"	"unknown")
+   (set_attr "mode"	"HI")
+   (set_attr "length"	"2")])
+
+(define_insn "align_4"
+  [(unspec_volatile [(const_int 0)] 17)]
+  "TARGET_MIPS16"
+  ".align 2"
+  [(set_attr "type"	"unknown")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
+(define_insn "align_8"
+  [(unspec_volatile [(const_int 0)] 18)]
+  "TARGET_MIPS16"
+  ".align 3"
+  [(set_attr "type"	"unknown")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"3")])
+
+;;  ....................
+;;	mips16 peepholes
+;;  ....................
+
+;; On the mips16, reload will sometimes decide that a pseudo register
+;; should go into $24, and then later on have to reload that register.
+;; When that happens, we get a load of a general register followed by
+;; a move from the general register to $24 followed by a branch.
+;; These peepholes catch the common case, and fix it to just use the
+;; general register for the branch.
+
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=t")
+	(match_operand:SI 1 "register_operand" "d"))
+   (set (pc)
+	(if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
+							  (const_int 0)])
+		      (match_operand 3 "pc_or_label_operand" "")
+		      (match_operand 4 "pc_or_label_operand" "")))]
+  "TARGET_MIPS16
+   && GET_CODE (operands[0]) == REG
+   && REGNO (operands[0]) == 24
+   && dead_or_set_p (insn, operands[0])
+   && GET_CODE (operands[1]) == REG
+   && M16_REG_P (REGNO (operands[1]))"
+  "*
+{
+  if (operands[3] != pc_rtx)
+    return \"%*b%C2z\\t%1,%3\";
+  else
+    return \"%*b%N2z\\t%1,%4\";
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_peephole
+  [(set (match_operand:DI 0 "register_operand" "=t")
+	(match_operand:DI 1 "register_operand" "d"))
+   (set (pc)
+	(if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
+							  (const_int 0)])
+		      (match_operand 3 "pc_or_label_operand" "")
+		      (match_operand 4 "pc_or_label_operand" "")))]
+  "TARGET_MIPS16 && TARGET_64BIT
+   && GET_CODE (operands[0]) == REG
+   && REGNO (operands[0]) == 24
+   && dead_or_set_p (insn, operands[0])
+   && GET_CODE (operands[1]) == REG
+   && M16_REG_P (REGNO (operands[1]))"
+  "*
+{
+  if (operands[3] != pc_rtx)
+    return \"%*b%C2z\\t%1,%3\";
+  else
+    return \"%*b%N2z\\t%1,%4\";
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+;; We can also have the reverse reload: reload will spill $24 into
+;; another register, and then do a branch on that register when it
+;; could have just stuck with $24.
+
+(define_peephole
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(match_operand:SI 1 "register_operand" "t"))
+   (set (pc)
+	(if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
+							  (const_int 0)])
+		      (match_operand 3 "pc_or_label_operand" "")
+		      (match_operand 4 "pc_or_label_operand" "")))]
+  "TARGET_MIPS16
+   && GET_CODE (operands[1]) == REG
+   && REGNO (operands[1]) == 24
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && dead_or_set_p (insn, operands[0])"
+  "*
+{
+  if (operands[3] != pc_rtx)
+    return \"%*bt%C2z\\t%3\";
+  else
+    return \"%*bt%N2z\\t%4\";
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
+
+(define_peephole
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(match_operand:DI 1 "register_operand" "t"))
+   (set (pc)
+	(if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
+							  (const_int 0)])
+		      (match_operand 3 "pc_or_label_operand" "")
+		      (match_operand 4 "pc_or_label_operand" "")))]
+  "TARGET_MIPS16 && TARGET_64BIT
+   && GET_CODE (operands[1]) == REG
+   && REGNO (operands[1]) == 24
+   && GET_CODE (operands[0]) == REG
+   && M16_REG_P (REGNO (operands[0]))
+   && dead_or_set_p (insn, operands[0])"
+  "*
+{
+  if (operands[3] != pc_rtx)
+    return \"%*bt%C2z\\t%3\";
+  else
+    return \"%*bt%N2z\\t%4\";
+}"
+  [(set_attr "type"	"branch")
+   (set_attr "mode"	"none")
+   (set_attr "length"	"2")])
diff --git a/gcc/config/mips/mips16.S b/gcc/config/mips/mips16.S
new file mode 100755
index 0000000..f21f10f
--- /dev/null
+++ b/gcc/config/mips/mips16.S
@@ -0,0 +1,740 @@
+/* mips16 floating point support code
+   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+   Contributed by Cygnus Support
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, if you link this library with other files,
+   some of which are compiled with GCC, to produce an executable,
+   this library does not by itself cause the resulting executable
+   to be covered by the GNU General Public License.
+   This exception does not however invalidate any other reasons why
+   the executable file might be covered by the GNU General Public License.  */
+
+/* This file contains mips16 floating point support functions.  These
+   functions are called by mips16 code to handle floating point when
+   -msoft-float is not used.  They accept the arguments and return
+   values using the soft-float calling convention, but do the actual
+   operation using the hard floating point instructions.  */
+
+/* This file contains 32 bit assembly code.  */
+	.set nomips16
+
+/* Start a function. */
+
+#define STARTFN(NAME) .globl NAME; .ent NAME; NAME:
+
+/* Finish a function.  */
+
+#define ENDFN(NAME) .end NAME
+
+/* Single precision math.  */
+
+/* This macro defines a function which loads two single precision
+   values, performs an operation, and returns the single precision
+   result.  */
+
+#define SFOP(NAME, OPCODE)	\
+STARTFN (NAME);			\
+	.set	noreorder;	\
+	mtc1	$4,$f0;		\
+	mtc1	$5,$f2;		\
+	nop;			\
+	OPCODE	$f0,$f0,$f2;	\
+	mfc1	$2,$f0;		\
+	j	$31;		\
+	nop;			\
+	.set	reorder;	\
+	ENDFN (NAME)
+
+#ifdef L_m16addsf3
+SFOP(__mips16_addsf3, add.s)
+#endif
+#ifdef L_m16subsf3
+SFOP(__mips16_subsf3, sub.s)
+#endif
+#ifdef L_m16mulsf3
+SFOP(__mips16_mulsf3, mul.s)
+#endif
+#ifdef L_m16divsf3
+SFOP(__mips16_divsf3, div.s)
+#endif
+
+#define SFOP2(NAME, OPCODE)	\
+STARTFN (NAME);			\
+	.set	noreorder;	\
+	mtc1	$4,$f0;		\
+	nop;			\
+	OPCODE	$f0,$f0;	\
+	mfc1	$2,$f0;		\
+	j	$31;		\
+	nop;			\
+	.set	reorder;	\
+	ENDFN (NAME)
+	
+#ifdef L_m16negsf2
+SFOP2(__mips16_negsf2, neg.s)
+#endif
+#ifdef L_m16abssf2
+SFOP2(__mips16_abssf2, abs.s)
+#endif
+	
+/* Single precision comparisons.  */
+
+/* This macro defines a function which loads two single precision
+   values, performs a floating point comparison, and returns the
+   specified values according to whether the comparison is true or
+   false.  */
+
+#define SFCMP(NAME, OPCODE, TRUE, FALSE)	\
+STARTFN (NAME);					\
+	mtc1	$4,$f0;				\
+	mtc1	$5,$f2;				\
+	OPCODE	$f0,$f2;			\
+	li	$2,TRUE;			\
+	bc1t	1f;				\
+	li	$2,FALSE;			\
+1:;						\
+	j	$31;				\
+	ENDFN (NAME)
+
+/* This macro is like SFCMP, but it reverses the comparison.  */
+
+#define SFREVCMP(NAME, OPCODE, TRUE, FALSE)	\
+STARTFN (NAME);					\
+	mtc1	$4,$f0;				\
+	mtc1	$5,$f2;				\
+	OPCODE	$f2,$f0;			\
+	li	$2,TRUE;			\
+	bc1t	1f;				\
+	li	$2,FALSE;			\
+1:;						\
+	j	$31;				\
+	ENDFN (NAME)
+
+#ifdef L_m16eqsf2
+SFCMP(__mips16_eqsf2, c.eq.s, 0, 1)
+#endif
+#ifdef L_m16nesf2
+SFCMP(__mips16_nesf2, c.eq.s, 0, 1)
+#endif
+#ifdef L_m16gtsf2
+SFREVCMP(__mips16_gtsf2, c.lt.s, 1, 0)
+#endif
+#ifdef L_m16gesf2
+SFREVCMP(__mips16_gesf2, c.le.s, 0, -1)
+#endif
+#ifdef L_m16lesf2
+SFCMP(__mips16_lesf2, c.le.s, 0, 1)
+#endif
+#ifdef L_m16ltsf2
+SFCMP(__mips16_ltsf2, c.lt.s, -1, 0)
+#endif
+
+/* Single precision conversions.  */
+
+#ifdef L_m16fltsisf
+STARTFN (__mips16_floatsisf)
+	.set	noreorder
+	mtc1	$4,$f0
+	nop
+	cvt.s.w	$f0,$f0
+	mfc1	$2,$f0
+	j	$31
+	nop
+	.set	reorder
+	ENDFN (__mips16_floatsisf)
+#endif
+
+#ifdef L_m16fixsfsi
+STARTFN (__mips16_fixsfsi)
+	.set	noreorder
+	mtc1	$4,$f0
+	nop
+	trunc.w.s $f0,$f0,$4
+	mfc1	$2,$f0
+	j	$31
+	nop	
+	.set	reorder
+	ENDFN (__mips16_fixsfsi)
+#endif
+
+#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
+		
+/* The double precision operations.  We need to use different code
+   based on the preprocessor symbol __mips64, because the way in which
+   double precision values will change.  Without __mips64, the value
+   is passed in two 32 bit registers.  With __mips64, the value is
+   passed in a single 64 bit register.  */
+
+/* Load the first double precision operand.  */
+
+#if defined(__mips64)
+#define LDDBL1 dmtc1 $4,$f12
+#elif defined(__mipsfp64)
+#define LDDBL1 sw $4,0($29); sw $5,4($29); l.d $f12,0($29)
+#elif defined(__MIPSEB__)	
+#define LDDBL1 mtc1 $4,$f13; mtc1 $5,$f12
+#else	
+#define LDDBL1 mtc1 $4,$f12; mtc1 $5,$f13
+#endif
+
+/* Load the second double precision operand.  */
+
+#if defined(__mips64)
+/* XXX this should be $6 for Algo arg passing model */
+#define LDDBL2 dmtc1 $5,$f14
+#elif defined(__mipsfp64)
+#define LDDBL2 sw $6,8($29); sw $7,12($29); l.d $f14,8($29)
+#elif defined(__MIPSEB__)	
+#define LDDBL2 mtc1 $6,$f15; mtc1 $7,$f14
+#else	
+#define LDDBL2 mtc1 $6,$f14; mtc1 $7,$f15
+#endif
+	
+/* Move the double precision return value to the right place.  */
+
+#if defined(__mips64)
+#define RETDBL dmfc1 $2,$f0
+#elif defined(__mipsfp64)
+#define RETDBL s.d $f0,0($29); lw $2,0($29); lw $3,4($29)
+#elif defined(__MIPSEB__)	
+#define RETDBL mfc1 $2,$f1; mfc1 $3,$f0
+#else	
+#define RETDBL mfc1 $2,$f0; mfc1 $3,$f1
+#endif
+	
+/* Double precision math.  */
+
+/* This macro defines a function which loads two double precision
+   values, performs an operation, and returns the double precision
+   result.  */
+
+#define DFOP(NAME, OPCODE)	\
+STARTFN (NAME);			\
+	.set	noreorder;	\
+	LDDBL1;			\
+	LDDBL2;			\
+	nop;			\
+	OPCODE	$f0,$f12,$f14;	\
+	RETDBL;			\
+	j	$31;		\
+	nop;			\
+	.set	reorder;	\
+	ENDFN (NAME)
+
+#ifdef L_m16adddf3
+DFOP(__mips16_adddf3, add.d)
+#endif
+#ifdef L_m16subdf3
+DFOP(__mips16_subdf3, sub.d)
+#endif
+#ifdef L_m16muldf3
+DFOP(__mips16_muldf3, mul.d)
+#endif
+#ifdef L_m16divdf3
+DFOP(__mips16_divdf3, div.d)
+#endif
+
+#define DFOP2(NAME, OPCODE)	\
+STARTFN (NAME);			\
+	.set	noreorder;	\
+	LDDBL1;			\
+	nop;			\
+	OPCODE	$f0,$f12;	\
+	RETDBL;			\
+	j	$31;		\
+	nop;			\
+	.set	reorder;	\
+	ENDFN (NAME)
+	
+#ifdef L_m16negdf2
+DFOP2(__mips16_negdf2, neg.d)
+#endif
+#ifdef L_m16absdf2
+DFOP2(__mips16_absdf2, abs.d)
+#endif
+
+	
+/* Conversions between single and double precision.  */
+
+#ifdef L_m16extsfdf2
+STARTFN (__mips16_extendsfdf2)
+	.set	noreorder
+	mtc1	$4,$f12
+	nop
+	cvt.d.s	$f0,$f12
+	RETDBL
+	j	$31
+	nop
+	.set	reorder
+	ENDFN (__mips16_extendsfdf2)
+#endif
+
+#ifdef L_m16trdfsf2
+STARTFN (__mips16_truncdfsf2)
+	.set	noreorder
+	LDDBL1
+	nop
+	cvt.s.d	$f0,$f12
+	mfc1	$2,$f0
+	j	$31
+	nop
+	.set	reorder
+	ENDFN (__mips16_truncdfsf2)
+#endif
+
+/* Double precision comparisons.  */
+
+/* This macro defines a function which loads two double precision
+   values, performs a floating point comparison, and returns the
+   specified values according to whether the comparison is true or
+   false.  */
+
+#define DFCMP(NAME, OPCODE, TRUE, FALSE)	\
+STARTFN (NAME);					\
+	LDDBL1;					\
+	LDDBL2;					\
+	OPCODE	$f12,$f14;			\
+	li	$2,TRUE;			\
+	bc1t	1f;				\
+	li	$2,FALSE;			\
+1:;						\
+	j	$31;				\
+	ENDFN (NAME)
+
+/* This macro is like DFCMP, but it reverses the comparison.  */
+
+#define DFREVCMP(NAME, OPCODE, TRUE, FALSE)	\
+STARTFN (NAME);					\
+	LDDBL1;					\
+	LDDBL2;					\
+	OPCODE	$f14,$f12;			\
+	li	$2,TRUE;			\
+	bc1t	1f;				\
+	li	$2,FALSE;			\
+1:;						\
+	j	$31;				\
+	ENDFN (NAME)
+
+#ifdef L_m16eqdf2
+DFCMP(__mips16_eqdf2, c.eq.d, 0, 1)
+#endif
+#ifdef L_m16nedf2
+DFCMP(__mips16_nedf2, c.eq.d, 0, 1)
+#endif
+#ifdef L_m16gtdf2
+DFREVCMP(__mips16_gtdf2, c.lt.d, 1, 0)
+#endif
+#ifdef L_m16gedf2
+DFREVCMP(__mips16_gedf2, c.le.d, 0, -1)
+#endif
+#ifdef L_m16ledf2
+DFCMP(__mips16_ledf2, c.le.d, 0, 1)
+#endif
+#ifdef L_m16ltdf2
+DFCMP(__mips16_ltdf2, c.lt.d, -1, 0)
+#endif
+
+/* Double precision conversions.  */
+
+#ifdef L_m16fltsidf
+STARTFN (__mips16_floatsidf)
+	.set	noreorder
+	mtc1	$4,$f12
+	nop
+	cvt.d.w	$f0,$f12
+	RETDBL
+	j	$31
+	nop
+	.set	reorder
+	ENDFN (__mips16_floatsidf)
+#endif
+
+#ifdef L_m16fixdfsi
+STARTFN (__mips16_fixdfsi)
+	.set	noreorder
+	LDDBL1
+	nop
+	trunc.w.d $f0,$f12,$4
+	mfc1	$2,$f0
+	j	$31
+	nop
+	.set	reorder
+	ENDFN (__mips16_fixdfsi)
+#endif
+#endif /* !__mips_single_float */
+
+/* These functions are used to return floating point values from
+   mips16 functions which do not use -mentry.  In this case we can
+   put mtc1 in a jump delay slot, because we know that the next
+   instruction will not refer to a floating point register.  */
+
+#ifdef L_m16retsf
+STARTFN (__mips16_ret_sf)
+	.set	noreorder
+	j	$31
+	mtc1	$2,$f0
+	.set	reorder
+	ENDFN (__mips16_ret_sf)
+#endif
+
+#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
+#ifdef L_m16retdf
+STARTFN (__mips16_ret_df)
+	.set	noreorder
+#if defined(__mips64)
+	j	$31
+	dmtc1	$2,$f0
+#elif defined(__mipsfp64)
+	sw	$2,0($29)
+	sw	$3,4($29)
+	l.d	$f0,0($29) 
+#elif defined(__MIPSEB__)	
+	mtc1	$2,$f1
+	j	$31
+	mtc1	$3,$f0
+#else	
+	mtc1	$2,$f0
+	j	$31
+	mtc1	$3,$f1
+#endif
+	.set	reorder
+	ENDFN (__mips16_ret_df)
+#endif
+#endif /* !__mips_single_float */
+
+/* These functions are used by 16 bit code when calling via a function
+   pointer.  They must copy the floating point arguments from the gp
+   regs into the fp regs.  The function to call will be in $2.  The
+   exact set of floating point arguments to copy is encoded in the
+   function name; the final number is an fp_code, as described in
+   mips.h in the comment about CUMULATIVE_ARGS.  */
+
+#ifdef L_m16stub1
+/* (float) */
+STARTFN (__mips16_call_stub_1)
+	.set	noreorder
+	mtc1	$4,$f12
+	j	$2
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_1)
+#endif
+
+#ifdef L_m16stub5
+/* (float, float) */
+STARTFN (__mips16_call_stub_5)
+	.set	noreorder
+	mtc1	$4,$f12
+	mtc1	$5,$f14
+	j	$2
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_5)
+#endif
+
+#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
+
+#ifdef L_m16stub2
+/* (double) */
+STARTFN (__mips16_call_stub_2)
+	.set	noreorder
+	LDDBL1
+	j	$2
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_2)
+#endif
+
+#ifdef L_m16stub6
+/* (double, float) */
+STARTFN (__mips16_call_stub_6)
+	.set	noreorder
+	LDDBL1
+	mtc1	$6,$f14
+	j	$2
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_6)
+#endif
+
+#ifdef L_m16stub9
+/* (float, double) */
+STARTFN (__mips16_call_stub_9)
+	.set	noreorder
+	mtc1	$4,$f12
+	LDDBL2
+	j	$2
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_9)
+#endif
+
+#ifdef L_m16stub10
+/* (double, double) */
+STARTFN (__mips16_call_stub_10)
+	.set	noreorder
+	LDDBL1
+	LDDBL2
+	j	$2
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_10)
+#endif
+#endif /* !__mips_single_float */
+
+/* Now we have the same set of functions, except that this time the
+   function being called returns an SFmode value.  The calling
+   function will arrange to preserve $18, so these functions are free
+   to use it to hold the return address.
+
+   Note that we do not know whether the function we are calling is 16
+   bit or 32 bit.  However, it does not matter, because 16 bit
+   functions always return floating point values in both the gp and
+   the fp regs.  It would be possible to check whether the function
+   being called is 16 bits, in which case the copy is unnecessary;
+   however, it's faster to always do the copy.  */
+
+#ifdef L_m16stubsf0
+/* () */
+STARTFN (__mips16_call_stub_sf_0)
+	.set	noreorder
+	move	$18,$31
+	jal	$2
+	nop
+	mfc1	$2,$f0
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_sf_0)
+#endif
+
+#ifdef L_m16stubsf1
+/* (float) */
+STARTFN (__mips16_call_stub_sf_1)
+	.set	noreorder
+	mtc1	$4,$f12
+	move	$18,$31
+	jal	$2
+	nop
+	mfc1	$2,$f0
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_sf_1)
+#endif
+
+#ifdef L_m16stubsf5
+/* (float, float) */
+STARTFN (__mips16_call_stub_sf_5)
+	.set	noreorder
+	mtc1	$4,$f12
+	mtc1	$5,$f14
+	move	$18,$31
+	jal	$2
+	nop
+	mfc1	$2,$f0
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_sf_5)
+#endif
+
+#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
+#ifdef L_m16stubsf2
+/* (double) */
+STARTFN (__mips16_call_stub_sf_2)
+	.set	noreorder
+	LDDBL1
+	move	$18,$31
+	jal	$2
+	nop
+	mfc1	$2,$f0
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_sf_2)
+#endif
+
+#ifdef L_m16stubsf6
+/* (double, float) */
+STARTFN (__mips16_call_stub_sf_6)
+	.set	noreorder
+	LDDBL1
+	mtc1	$6,$f14
+	move	$18,$31
+	jal	$2
+	nop
+	mfc1	$2,$f0
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_sf_6)
+#endif
+
+#ifdef L_m16stubsf9
+/* (float, double) */
+STARTFN (__mips16_call_stub_sf_9)
+	.set	noreorder
+	mtc1	$4,$f12
+	LDDBL2
+	move	$18,$31
+	jal	$2
+	nop
+	mfc1	$2,$f0
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_sf_9)
+#endif
+
+#ifdef L_m16stubsf10
+/* (double, double) */
+STARTFN (__mips16_call_stub_sf_10)
+	.set	noreorder
+	LDDBL1
+	LDDBL2
+	move	$18,$31
+	jal	$2
+	nop
+	mfc1	$2,$f0
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_sf_10)
+#endif
+
+/* Now we have the same set of functions again, except that this time
+   the function being called returns an DFmode value.  */
+
+#ifdef L_m16stubdf0
+/* () */
+STARTFN (__mips16_call_stub_df_0)
+	.set	noreorder
+	move	$18,$31
+	jal	$2
+	nop
+	RETDBL
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_df_0)
+#endif
+
+#ifdef L_m16stubdf1
+/* (float) */
+STARTFN (__mips16_call_stub_df_1)
+	.set	noreorder
+	mtc1	$4,$f12
+	move	$18,$31
+	jal	$2
+	nop
+	RETDBL
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_df_1)
+#endif
+
+#ifdef L_m16stubdf2
+/* (double) */
+STARTFN (__mips16_call_stub_df_2)
+	.set	noreorder
+	LDDBL1
+	move	$18,$31
+	jal	$2
+	nop
+	RETDBL
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_df_2)
+#endif
+
+#ifdef L_m16stubdf5
+/* (float, float) */
+STARTFN (__mips16_call_stub_df_5)
+	.set	noreorder
+	mtc1	$4,$f12
+	mtc1	$5,$f14
+	move	$18,$31
+	jal	$2
+	nop
+	RETDBL
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_df_5)
+#endif
+
+#ifdef L_m16stubdf6
+/* (double, float) */
+STARTFN (__mips16_call_stub_df_6)
+	.set	noreorder
+	LDDBL1
+	mtc1	$6,$f14
+	move	$18,$31
+	jal	$2
+	nop
+	RETDBL
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_df_6)
+#endif
+
+#ifdef L_m16stubdf9
+/* (float, double) */
+STARTFN (__mips16_call_stub_df_9)
+	.set	noreorder
+	mtc1	$4,$f12
+	LDDBL2
+	move	$18,$31
+	jal	$2
+	nop
+	RETDBL
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_df_9)
+#endif
+
+#ifdef L_m16stubdf10
+/* (double, double) */
+STARTFN (__mips16_call_stub_df_10)
+	.set	noreorder
+	LDDBL1
+	LDDBL2
+	move	$18,$31
+	jal	$2
+	nop
+	RETDBL
+	j	$18
+	nop
+	.set	reorder
+	ENDFN (__mips16_call_stub_df_10)
+#endif
+#endif /* !__mips_single_float */
+
diff --git a/gcc/config/mips/ncd.h b/gcc/config/mips/ncd.h
new file mode 100755
index 0000000..5767d68
--- /dev/null
+++ b/gcc/config/mips/ncd.h
@@ -0,0 +1,42 @@
+/* CYGNUS LOCAL: entire file */
+
+/* Definitions of target machine for GNU compiler.
+   NCD R3000 or R4000 based X terminal.
+   Copyright (C) 1994 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#define CC1_SPEC "\
+%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
+%{g: -ggdb} \
+%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32} %{mips3:-mfp64 -mgp64} \
+%{G*} \
+%{pic-none:   -mno-half-pic} \
+%{pic-lib:    -mhalf-pic} \
+%{pic-extern: -mhalf-pic} \
+%{pic-calls:  -mhalf-pic} \
+%{save-temps: }"
+
+#define BLOCK_PROFILER_CODE
+#define DEFAULT_GDB_EXTENSIONS 1
+#define TARGET_DEFAULT MASK_GAS
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+#define MACHINE_TYPE "NCD R3000- or R4000-based X terminal"
+
+#include "mips/mips.h"
+
+#undef SDB_DEBUGGING_INFO
diff --git a/gcc/config/mips/netbsd.h b/gcc/config/mips/netbsd.h
new file mode 100755
index 0000000..3fce9fb
--- /dev/null
+++ b/gcc/config/mips/netbsd.h
@@ -0,0 +1,227 @@
+/* Definitions for DECstation running BSD as target machine for GNU compiler.
+   Copyright (C) 1993, 1995, 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define DECSTATION
+
+/* Look for the include files in the system-defined places.  */
+
+#ifndef CROSS_COMPILE
+#undef GPLUSPLUS_INCLUDE_DIR
+#define GPLUSPLUS_INCLUDE_DIR "/usr/include/g++"
+
+#undef GCC_INCLUDE_DIR
+#define GCC_INCLUDE_DIR "/usr/include"
+
+#undef INCLUDE_DEFAULTS
+#define INCLUDE_DEFAULTS			\
+  {						\
+    { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1 },	\
+    { GCC_INCLUDE_DIR, "GCC", 0, 0 },		\
+    { 0, 0, 0, 0 }				\
+  }
+
+/* Under NetBSD, the normal location of the various *crt*.o files is the
+   /usr/lib directory.  */
+
+#undef STANDARD_STARTFILE_PREFIX
+#define STANDARD_STARTFILE_PREFIX "/usr/lib/"
+#endif
+
+/* Provide a LINK_SPEC appropriate for NetBSD.  Here we provide support
+   for the special GCC options -static, -assert, and -nostdlib.  */
+
+#undef LINK_SPEC
+#define LINK_SPEC \
+  "%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+   %{!nostartfiles:%{!r*:%{!e*:-e __start}}} -dc -dp %{static:-Bstatic} %{assert*}"
+
+/* We have atexit(3).  */
+
+#define HAVE_ATEXIT
+
+/* Implicit library calls should use memcpy, not bcopy, etc.  */
+
+#define TARGET_MEM_FUNCTIONS
+
+/* Define mips-specific netbsd predefines... */
+#ifndef CPP_PREDEFINES
+#define CPP_PREDEFINES "-D__ANSI_COMPAT \
+-DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD -D__NetBSD__ -Dmips \
+-D__NO_LEADING_UNDERSCORES__ -D__GP_SUPPORT__ \
+-Dunix -D_R3000 \
+-Asystem(unix) -Asystem(NetBSD) -Amachine(mips)"
+#endif
+
+#ifndef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "%{posix:-D_POSIX_SOURCE}"
+#endif
+
+#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
+#define STARTFILE_SPEC ""
+
+#ifndef MACHINE_TYPE
+#define MACHINE_TYPE "NetBSD/pmax"
+#endif
+
+#define TARGET_DEFAULT MASK_GAS
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+
+#include "mips/mips.h"
+
+/*
+ * Some imports from svr4.h in support of shared libraries.
+ * Currently, we need the DECLARE_OBJECT_SIZE stuff.
+ */
+
+/* Define the strings used for the special svr4 .type and .size directives.
+   These strings generally do not vary from one system running svr4 to
+   another, but if a given system (e.g. m88k running svr) needs to use
+   different pseudo-op names for these, they may be overridden in the
+   file which includes this one.  */
+
+#undef TYPE_ASM_OP
+#undef SIZE_ASM_OP
+#undef WEAK_ASM_OP
+#define TYPE_ASM_OP	".type"
+#define SIZE_ASM_OP	".size"
+#define WEAK_ASM_OP	".weak"
+
+/* The following macro defines the format used to output the second
+   operand of the .type assembler directive.  Different svr4 assemblers
+   expect various different forms for this operand.  The one given here
+   is just a default.  You may need to override it in your machine-
+   specific tm.h file (depending upon the particulars of your assembler).  */
+
+#undef TYPE_OPERAND_FMT
+#define TYPE_OPERAND_FMT	"@%s"
+
+/* Write the extra assembler code needed to declare a function's result.
+   Most svr4 assemblers don't require any special declaration of the
+   result value, but there are exceptions.  */
+
+#ifndef ASM_DECLARE_RESULT
+#define ASM_DECLARE_RESULT(FILE, RESULT)
+#endif
+
+/* These macros generate the special .type and .size directives which
+   are used to set the corresponding fields of the linker symbol table
+   entries in an ELF object file under SVR4.  These macros also output
+   the starting labels for the relevant functions/objects.  */
+
+/* Write the extra assembler code needed to declare a function properly.
+   Some svr4 assemblers need to also have something extra said about the
+   function's return value.  We allow for that here.  */
+
+#undef ASM_DECLARE_FUNCTION_NAME
+#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)			\
+  do {									\
+    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
+    assemble_name (FILE, NAME);						\
+    putc (',', FILE);							\
+    fprintf (FILE, TYPE_OPERAND_FMT, "function");			\
+    putc ('\n', FILE);							\
+    ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL));			\
+  } while (0)
+
+/* Write the extra assembler code needed to declare an object properly.  */
+
+#undef ASM_DECLARE_OBJECT_NAME
+#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
+  do {									\
+    fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
+    assemble_name (FILE, NAME);						\
+    putc (',', FILE);							\
+    fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
+    putc ('\n', FILE);							\
+    size_directive_output = 0;						\
+    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
+      {									\
+	size_directive_output = 1;					\
+	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
+	assemble_name (FILE, NAME);					\
+	fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL)));	\
+      }									\
+    ASM_OUTPUT_LABEL(FILE, NAME);					\
+  } while (0)
+
+/* Output the size directive for a decl in rest_of_decl_compilation
+   in the case where we did not do so before the initializer.
+   Once we find the error_mark_node, we know that the value of
+   size_directive_output was set
+   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
+
+#undef ASM_FINISH_DECLARE_OBJECT
+#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
+do {									 \
+     char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);			 \
+     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
+         && ! AT_END && TOP_LEVEL					 \
+	 && DECL_INITIAL (DECL) == error_mark_node			 \
+	 && !size_directive_output)					 \
+       {								 \
+	 size_directive_output = 1;					 \
+	 fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			 \
+	 assemble_name (FILE, name);					 \
+	 fprintf (FILE, ",%d\n",  int_size_in_bytes (TREE_TYPE (DECL))); \
+       }								 \
+   } while (0)
+
+/* This is how to declare the size of a function.  */
+
+#undef ASM_DECLARE_FUNCTION_SIZE
+#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL)			\
+  do {									\
+    if (!flag_inhibit_size_directive)					\
+      {									\
+        char label[256];						\
+	static int labelno;						\
+	labelno++;							\
+	ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno);		\
+	ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno);		\
+	fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
+	assemble_name (FILE, (FNAME));					\
+        fprintf (FILE, ",");						\
+	assemble_name (FILE, label);					\
+        fprintf (FILE, "-");						\
+	assemble_name (FILE, (FNAME));					\
+	putc ('\n', FILE);						\
+      }									\
+  } while (0)
+
+/*
+ A C statement to output something to the assembler file to switch to section
+ NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
+ NULL_TREE.  Some target formats do not support arbitrary sections.  Do not
+ define this macro in such cases.
+*/
+#define ASM_OUTPUT_SECTION_NAME(F, DECL, NAME, RELOC)                        \
+do {                                                                         \
+  extern FILE *asm_out_text_file;                                            \
+  if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL)                           \
+    fprintf (asm_out_text_file, "\t.section %s,\"ax\",@progbits\n", (NAME)); \
+  else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC))                    \
+    fprintf (F, "\t.section %s,\"a\",@progbits\n", (NAME));                  \
+  else                                                                       \
+    fprintf (F, "\t.section %s,\"aw\",@progbits\n", (NAME));                 \
+} while (0)
+
+/* Since gas and gld are standard on NetBSD, we don't need these */
+#undef ASM_FINAL_SPEC
+#undef STARTFILE_SPEC
diff --git a/gcc/config/mips/news4.h b/gcc/config/mips/news4.h
new file mode 100755
index 0000000..502affa
--- /dev/null
+++ b/gcc/config/mips/news4.h
@@ -0,0 +1,39 @@
+/* Definitions of target machine for GNU compiler.  Sony RISC NEWS (mips)
+   Copyright (C) 1991, 1997 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_NEWS
+
+#define CPP_PREDEFINES "\
+-Dr3000 -Dnews3700 -DLANGUAGE_C -DMIPSEB -DSYSTYPE_BSD \
+-Dsony_news -Dsony -Dunix -Dmips -Dhost_mips \
+-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
+
+#define SYSTEM_INCLUDE_DIR "/usr/include2.0"
+
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
+
+#define MACHINE_TYPE "RISC NEWS-OS"
+
+/* INITIALIZE_TRAMPOLINE calls this library function to flush
+   program and data caches.  */
+#define CACHE_FLUSH_FUNC "cacheflush"
+
diff --git a/gcc/config/mips/news5.h b/gcc/config/mips/news5.h
new file mode 100755
index 0000000..a776064
--- /dev/null
+++ b/gcc/config/mips/news5.h
@@ -0,0 +1,62 @@
+/* Definitions of target machine for GNU compiler. 
+   Sony RISC NEWS (mips) System V version.
+   Copyright (C) 1992 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_SYSV
+
+#define CPP_PREDEFINES "\
+-Dmips -Dunix -Dhost_mips -Dsony -Dsonyrisc -DMIPSEB -DSYSTYPE_SYSV \
+-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)"
+
+#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
+
+#define LIB_SPEC "\
+%{ZBSD43: -L/usr/ucblib -lucb -lresolv -lsocket -lnsl} \
+-nocount %{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s values-Xt.o%s"
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:-nocount crt1.o%s -count}}"
+
+#define MACHINE_TYPE "Sony RISC NEWS (SVR4 mips)"
+
+#define NO_LIB_PROTOTYPE
+
+#define NO_DOLLAR_IN_LABEL
+
+#define NM_FLAGS "-Bp"
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
+
+/* Mips System V.4 doesn't have a getpagesize() function needed by the
+   trampoline code, so use the POSIX sysconf function to get it.
+   This is only done when compiling the trampoline code.  */
+
+#ifdef  L_trampoline
+#include <sys/param.h>
+#include <unistd.h>
+
+#ifdef _SC_PAGE_SIZE
+#define getpagesize()	sysconf(_SC_PAGE_SIZE)
+
+#else				/* older rev of OS */
+#define getpagesize()	(NBPC)
+#endif /* !_SC_PAGE_SIZE */
+#endif /*  L_trampoline */
+
diff --git a/gcc/config/mips/nws3250v4.h b/gcc/config/mips/nws3250v4.h
new file mode 100755
index 0000000..611effe
--- /dev/null
+++ b/gcc/config/mips/nws3250v4.h
@@ -0,0 +1,36 @@
+/* Definitions of target machine for GNU compiler.  Sony RISC NEWS (mips)
+   Copyright (C) 1991 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_NEWS
+
+#define CPP_PREDEFINES "\
+-Dmips -Dhost_mips -Dsony -Dsonyrisc -Dunix \
+-DLANGUAGE_C -DMIPSEB -DSYSTYPE_SYSV \
+-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)"
+
+#define MD_STARTFILE_PREFIX "/usr/ccs/lib/"
+
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s values-Xt.o%s"
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
+
+#define MACHINE_TYPE "RISC NEWS-OS SVr4"
+
+#include "mips/mips.h"
diff --git a/gcc/config/mips/osfrose.h b/gcc/config/mips/osfrose.h
new file mode 100755
index 0000000..ee76053
--- /dev/null
+++ b/gcc/config/mips/osfrose.h
@@ -0,0 +1,149 @@
+/* Definitions of target machine for GNU compiler.
+   DECstation (OSF/1 reference port with OSF/rose) version.
+   Copyright (C) 1991, 1992, 1995, 1996, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define DECSTATION
+#define OSF_OS
+
+#define HALF_PIC_DEBUG	TARGET_DEBUG_B_MODE
+#define HALF_PIC_PREFIX	"$Lp."
+
+#include "halfpic.h"
+
+#define WORD_SWITCH_TAKES_ARG(STR)					\
+ (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) || !strcmp (STR, "pic-names"))
+
+#define CPP_PREDEFINES "\
+-DOSF -DOSF1 -Dbsd4_2 -DMIPSEL -Dhost_mips -Dmips -Dunix -DR3000 -DSYSTYPE_BSD \
+-Asystem(unix) -Asystem(xpg4) -Acpu(mips) -Amachine(mips)"
+
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mlong64:-D__PTRDIFF_TYPE__=long\\ int} \
+%{!mlong64:-D__PTRDIFF_TYPE__=int}"
+
+#define SUBTARGET_CPP_SPEC "\
+%{.S:	%{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}} \
+%{.s:	%{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}}"
+
+/* ??? This assumes that GNU as is always used with GNU ld, and MIPS as is
+   always used with MIPS ld.  */
+#define LINK_SPEC "\
+%{G*} %{EL} %{EB} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} \
+%{!mmips-as: \
+ 	%{v*: -v} \
+	%{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \
+	%{nostdlib} %{noshrlib} %{glue}}"
+
+#define LIB_SPEC "-lc"
+
+/* Define this macro meaning that `gcc' should find the library
+   `libgcc.a' by hand, rather than passing the argument `-lgcc' to
+   tell the linker to do the search. */
+
+#define LINK_LIBGCC_SPECIAL 1
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
+
+#define MACHINE_TYPE "DECstation with OSF/rose objects"
+
+#ifndef MD_EXEC_PREFIX
+#define MD_EXEC_PREFIX		"/usr/ccs/gcc/"
+#endif
+
+#ifndef MD_STARTFILE_PREFIX
+#define MD_STARTFILE_PREFIX	"/usr/ccs/lib/"
+#endif
+
+/* Turn on -mpic-extern by default.  */
+#define CC1_SPEC "\
+%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
+%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32} %{mips3:-mfp64 -mgp64} \
+%{G*} \
+%{pic-none:   -mno-half-pic} \
+%{pic-lib:    -mhalf-pic} \
+%{pic-extern: -mhalf-pic} \
+%{pic-calls:  -mhalf-pic} \
+%{pic-names*: -mhalf-pic} \
+%{!pic-*:     -mhalf-pic}"
+
+/* Specify size_t and wchar_t types.  */
+#define SIZE_TYPE	"long unsigned int"
+#define WCHAR_TYPE	"unsigned int"
+#define WCHAR_TYPE_SIZE BITS_PER_WORD
+#define MAX_WCHAR_TYPE_SIZE MAX_LONG_TYPE_SIZE
+
+/* OSF/1 uses gas, not the mips assembler.  */
+#define TARGET_DEFAULT MASK_GAS
+
+/* OSF/rose uses stabs, not ECOFF.  */
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+
+/* enable dwarf debugging for testing */
+#define DWARF_DEBUGGING_INFO
+/* This is needed by dwarfout.c.  */
+#define SET_ASM_OP	".set"
+
+/* Tell collect that the object format is OSF/rose.  */
+#define OBJECT_FORMAT_ROSE
+
+/* Tell collect where the appropriate binaries are.  */
+#define REAL_LD_FILE_NAME	"/usr/ccs/gcc/gld"
+#define REAL_NM_FILE_NAME	"/usr/ccs/bin/nm"
+#define REAL_STRIP_FILE_NAME	"/usr/ccs/bin/strip"
+
+/* Default to -G 0 unless doing ecoff work.  */
+#define MIPS_DEFAULT_GVALUE ((TARGET_MIPS_AS) ? 8 : 0)
+
+/* Use atexit for static constructors/destructors, instead of defining
+   our own exit function.  */
+#define HAVE_ATEXIT
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
+
+/* A C statement to output assembler commands which will identify
+   the object file as having been compiled with GNU CC (or another
+   GNU compiler).
+
+   If you don't define this macro, the string `gcc2_compiled.:' is
+   output.  This string is calculated to define a symbol which, on
+   BSD systems, will never be defined for any other reason.  GDB
+   checks for the presence of this symbol when reading the symbol
+   table of an executable.
+
+   On non-BSD systems, you must arrange communication with GDB in
+   some other fashion.  If GDB is not used on your system, you can
+   define this macro with an empty body.
+
+   On OSF/1, gcc2_compiled. confuses the kernel debugger, so don't
+   put it out.  */
+
+#define ASM_IDENTIFY_GCC(STREAM)
+
+/* Identify the front-end which produced this file.  To keep symbol
+   space down, and not confuse kdb, only do this if the language is
+   not C.  */
+
+#define ASM_IDENTIFY_LANGUAGE(STREAM)					\
+{									\
+  if (strcmp (lang_identify (), "c") != 0)				\
+    output_lang_identify (STREAM);					\
+}
diff --git a/gcc/config/mips/r3900.h b/gcc/config/mips/r3900.h
new file mode 100755
index 0000000..3d7cac5
--- /dev/null
+++ b/gcc/config/mips/r3900.h
@@ -0,0 +1,72 @@
+/* Definitions of MIPS sub target machine for GNU compiler. 
+   Toshiba r3900.  You should include mips.h after this.
+
+   Copyright (C) 1989, 90-6, 1997 Free Software Foundation, Inc.
+   Contributed by Gavin Koch (gavin@cygnus.com).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define SUBTARGET_CPP_SPEC "\
+%{!mabi=32: %{!mabi=n32: %{!mabi=64: -D__mips_eabi}}} \
+%{!msingle-float:-D__mips_soft_float} \
+%{mhard-float:%e-mhard-float not supported.} \
+%{msingle-float:%{msoft-float: \
+  %e-msingle-float and -msoft-float can not both be specified.}}"
+
+/* The following is needed because -mips3 and -mips4 set gp64 which in
+   combination with abi=eabi, causes long64 to be set. */
+#define SUBTARGET_CPP_SIZE_SPEC "\
+%{mips3:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+%{mips4:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
+%{!mips3:%{!mips4:%{!m4650:\
+  -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}} "
+
+/* by default (if not mips-something-else) produce code for the r3900 */
+#define SUBTARGET_CC1_SPEC "\
+%{mhard-float:%e-mhard-float not supported.} \
+%{msingle-float:%{msoft-float: \
+  %e-msingle-float and -msoft-float can not both be specified.}}"
+
+#define TARGET_DEFAULT (MASK_SOFT_FLOAT | MASK_MIPS3900)
+#define MIPS_CPU_STRING_DEFAULT "R3900"
+#define MIPS_ISA_DEFAULT 1
+
+#define MULTILIB_DEFAULTS { "EB", "msoft-float" }
+
+/* We use the MIPS EABI by default.  */
+#define MIPS_ABI_DEFAULT ABI_EABI
+
+
+/* Debugging */
+
+#define DWARF2_DEBUGGING_INFO
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+
+/* For the 'preferred' cases ("gN" and "ggdbN") we need to tell the 
+   gnu assembler not to generate debugging information. */
+   
+#define SUBTARGET_ASM_DEBUGGING_SPEC "\
+%{!mmips-as: \
+  %{g:-g0} %{g0:-g0} %{g1:-g0} %{g2:-g0} %{g3:-g0} \
+  %{ggdb:-g0} %{ggdb0:-g0} %{ggdb1:-g0} %{ggdb2:-g0} %{ggdb3:-g0} \
+  %{gdwarf-2*:-g0}} \
+%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
+%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
+%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
+
+/* eof */
diff --git a/gcc/config/mips/rtems64.h b/gcc/config/mips/rtems64.h
new file mode 100755
index 0000000..cd79970
--- /dev/null
+++ b/gcc/config/mips/rtems64.h
@@ -0,0 +1,63 @@
+/* Definitions for rtems targeting a MIPS ORION using ecoff.
+   Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Joel Sherrill (joel@OARcorp.com).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Specify predefined symbols in preprocessor.  */
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000 \
+   -Drtems -D__rtems__ -Asystem(rtems)"
+
+/* Generate calls to memcpy, memcmp and memset.  */
+#ifndef TARGET_MEM_FUNCTIONS
+#define TARGET_MEM_FUNCTIONS
+#endif
+
+/* Undefine the following which were defined in elf64.h.  This will cause the rtems64
+   port to continue to use collect2 for constructors/destructors.  These may be removed
+   when .ctor/.dtor section support is desired. */
+
+#undef CTORS_SECTION_ASM_OP
+#undef DTORS_SECTION_ASM_OP
+
+#undef EXTRA_SECTIONS
+#define EXTRA_SECTIONS in_sdata, in_rdata
+
+#undef INVOKE__main
+#undef NAME__MAIN
+#undef SYMBOL__MAIN
+
+#undef EXTRA_SECTION_FUNCTIONS
+#define EXTRA_SECTION_FUNCTIONS                                         \
+  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP)
+
+#undef ASM_OUTPUT_CONSTRUCTOR
+#undef ASM_OUTPUT_DESTRUCTOR
+
+#undef CTOR_LIST_BEGIN
+#undef CTOR_LIST_END
+#undef DTOR_LIST_BEGIN
+#undef DTOR_LIST_END
+
+#undef STARTFILE_SPEC
+#undef ENDFILE_SPEC
+
+/*  End of undefines to turn off .ctor/.dtor section support */
diff --git a/gcc/config/mips/sni-gas.h b/gcc/config/mips/sni-gas.h
new file mode 100755
index 0000000..5b36998
--- /dev/null
+++ b/gcc/config/mips/sni-gas.h
@@ -0,0 +1,38 @@
+/* Enable debugging.  */
+#define DBX_DEBUGGING_INFO
+#define SDB_DEBUGGING_INFO
+#define MIPS_DEBUGGING_INFO
+
+#define DWARF_DEBUGGING_INFO
+#undef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DWARF_DEBUG
+
+/* We need to use .esize and .etype instead of .size and .type to
+   avoid conflicting with ELF directives.  These are only recognized
+   by gas, anyhow, not the native assembler.  */
+#undef PUT_SDB_SIZE
+#define PUT_SDB_SIZE(a)                                       \
+do {                                                  \
+  extern FILE *asm_out_text_file;                     \
+  fprintf (asm_out_text_file, "\t.esize\t%d;", (a));  \
+} while (0)
+
+#undef PUT_SDB_TYPE
+#define PUT_SDB_TYPE(a)                                       \
+do {                                                  \
+  extern FILE *asm_out_text_file;                     \
+  fprintf (asm_out_text_file, "\t.etype\t0x%x;", (a));        \
+} while (0)
+
+
+/* This is how to equate one symbol to another symbol.  The syntax used is
+   `SYM1=SYM2'.  Note that this is different from the way equates are done
+   with most svr4 assemblers, where the syntax is `.set SYM1,SYM2'.  */
+
+#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)				\
+ do {	fprintf ((FILE), "\t");						\
+	assemble_name (FILE, LABEL1);					\
+	fprintf (FILE, " = ");						\
+	assemble_name (FILE, LABEL2);					\
+	fprintf (FILE, "\n");						\
+  } while (0)
diff --git a/gcc/config/mips/sni-svr4.h b/gcc/config/mips/sni-svr4.h
new file mode 100755
index 0000000..cf6edbc
--- /dev/null
+++ b/gcc/config/mips/sni-svr4.h
@@ -0,0 +1,100 @@
+/* Definitions of target machine for GNU compiler.  SNI SINIX version.
+   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+   Contributed by Marco Walther (Marco.Walther@mch.sni.de).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_SVR4
+
+#define CPP_PREDEFINES "\
+-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 -Dsinix -DSNI \
+-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \
+-Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(mips)"
+
+#define SUBTARGET_CPP_SIZE_SPEC "\
+-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
+
+#define LINK_SPEC "\
+%{G*} \
+%{!mgas: \
+	%{dy} %{dn}}"
+		    
+#define LIB_SPEC "\
+	%{p:-lprof1} \
+	%{!p:%{pg:-lprof1} \
+	     %{!pg:-L/usr/ccs/lib/ -lc /usr/ccs/lib/crtn.o%s}}"
+
+#define STARTFILE_SPEC "\
+	%{pg:gcrt0.o%s} \
+	%{!pg:%{p:mcrt0.o%s} \
+	       %{!p:/usr/ccs/lib/crt1.o /usr/ccs/lib/crti.o /usr/ccs/lib/values-Xt.o%s}}"
+
+/* Mips System V.4 doesn't have a getpagesize() function needed by the
+   trampoline code, so use the POSIX sysconf function to get it.
+   This is only done when compiling the trampoline code.  */
+
+#ifdef  L_trampoline
+#include <unistd.h>
+
+#define getpagesize()	sysconf(_SC_PAGE_SIZE)
+#endif /*  L_trampoline */
+
+/* Use atexit for static constructors/destructors, instead of defining
+   our own exit function.  */
+#define HAVE_ATEXIT
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
+
+#define OBJECT_FORMAT_ELF
+
+#define	TARGET_DEFAULT	MASK_ABICALLS
+#define ABICALLS_ASM_OP ".option pic2"
+
+#define MACHINE_TYPE "SNI running SINIX 5.42"
+
+#define MIPS_DEFAULT_GVALUE	0
+
+#define NM_FLAGS	"-p"
+
+/* wir haben ein Problem, wenn in einem Assembler-File keine .text-section
+   erzeugt wird. Dann landen diese Pseudo-Labels in irgendeiner anderen
+   section, z.B. .reginfo. Das macht den ld sehr ungluecklich. */
+
+#define ASM_IDENTIFY_GCC(mw_stream) \
+	fprintf(mw_stream, "\t.ident \"gcc2_compiled.\"\n");
+
+#define ASM_IDENTIFY_LANGUAGE(STREAM)
+
+#define ASM_LONG	".word\t"
+#define ASM_GLOBAL	".rdata\n\t\t.globl\t"
+
+#include "mips/mips.h"
+
+/* We do not want to run mips-tfile!  */
+#undef ASM_FINAL_SPEC
+
+#undef OBJECT_FORMAT_COFF
+
+/* We don't support debugging info for now. */
+#undef DBX_DEBUGGING_INFO
+#undef SDB_DEBUGGING_INFO
+#undef MIPS_DEBUGGING_INFO
+#undef PREFERRED_DEBUGGING_TYPE
+
+#define DWARF2_UNWIND_INFO 0
diff --git a/gcc/config/mips/svr3-4.h b/gcc/config/mips/svr3-4.h
new file mode 100755
index 0000000..18303ac
--- /dev/null
+++ b/gcc/config/mips/svr3-4.h
@@ -0,0 +1,63 @@
+/* Definitions of target machine for GNU compiler. 
+   MIPS RISC-OS System V version.
+   Copyright (C) 1991 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_SYSV
+
+#define CPP_PREDEFINES "\
+-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SYSV \
+-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SYSV \
+-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)"
+
+#define STANDARD_INCLUDE_DIR "/sysv/usr/include"
+
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+-systype /sysv/"
+		    
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
+
+#define MACHINE_TYPE "RISC-OS System V Mips"
+
+/* Override defaults for finding the MIPS tools.  */
+#define MD_STARTFILE_PREFIX "/sysv/usr/lib/cmplrs/cc/"
+#define MD_EXEC_PREFIX "/sysv/usr/lib/cmplrs/cc/"
+
+/* Mips System V doesn't have a getpagesize() function needed by the
+   trampoline code, so use the POSIX sysconf function to get it.
+   This is only done when compiling the trampoline code.  */
+
+#ifdef  L_trampoline
+#include <sys/param.h>
+#include <unistd.h>
+
+#ifdef _SC_PAGE_SIZE
+#define getpagesize()	sysconf(_SC_PAGE_SIZE)
+
+#else				/* older rev of OS */
+#define getpagesize()	(NBPC)
+#endif /* !_SC_PAGE_SIZE */
+#endif /*  L_trampoline */
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
diff --git a/gcc/config/mips/svr3-5.h b/gcc/config/mips/svr3-5.h
new file mode 100755
index 0000000..495b389
--- /dev/null
+++ b/gcc/config/mips/svr3-5.h
@@ -0,0 +1,89 @@
+/* Definitions of target machine for GNU compiler. 
+   MIPS RISC-OS 5.0 System V version.
+   Copyright (C) 1991, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_SYSV
+
+#define CPP_PREDEFINES "\
+-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SYSV \
+-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SYSV \
+-Asystem(unix) -Asystem(svr3) -Acpu(mips) -Amachine(mips)"
+
+#define STANDARD_INCLUDE_DIR "/sysv/usr/include"
+
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+%{call_shared} %{no_archive} %{exact_version} \
+%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
+-systype /sysv/ "
+		    
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
+
+#define MACHINE_TYPE "RISC-OS System V Mips"
+
+/* Override defaults for finding the MIPS tools.  */
+#define MD_STARTFILE_PREFIX "/sysv/usr/lib/cmplrs/cc/"
+#define MD_EXEC_PREFIX "/sysv/usr/lib/cmplrs/cc/"
+
+/* Mips System V doesn't have a getpagesize() function needed by the
+   trampoline code, so use the POSIX sysconf function to get it.
+   This is only done when compiling the trampoline code.  */
+
+#ifdef  L_trampoline
+#include <sys/param.h>
+#include <unistd.h>
+
+/* In at least 5.0 and 5.01, there is no _SC_PAGE_SIZE macro, only a
+   _SC_PAGESIZE macro.  */
+#ifdef _SC_PAGESIZE
+#define _SC_PAGE_SIZE _SC_PAGESIZE
+#endif
+
+#ifdef _SC_PAGE_SIZE
+#define getpagesize()	sysconf(_SC_PAGE_SIZE)
+
+#else				/* older rev of OS */
+#define getpagesize()	(NBPC)
+#endif /* !_SC_PAGE_SIZE */
+#endif /*  L_trampoline */
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
+
+#include "mips/mips.h"
+
+/* Some assemblers have a bug that causes backslash escaped chars in .ascii
+   to be misassembled, so we just completely avoid it.  */
+#undef ASM_OUTPUT_ASCII
+#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
+do {							\
+  unsigned char *s;					\
+  int i;						\
+  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
+    {							\
+      if ((i % 8) == 0)					\
+	fputs ("\n\t.byte\t", (FILE));			\
+      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
+    }							\
+  fputs ("\n", (FILE));					\
+} while (0)
diff --git a/gcc/config/mips/svr4-4.h b/gcc/config/mips/svr4-4.h
new file mode 100755
index 0000000..d1ba64d
--- /dev/null
+++ b/gcc/config/mips/svr4-4.h
@@ -0,0 +1,61 @@
+/* Definitions of target machine for GNU compiler.
+   MIPS RISC-OS System V.4 version.
+   Copyright (C) 1992, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_SVR4
+
+#define CPP_PREDEFINES "\
+-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 \
+-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \
+-Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(mips)"
+
+#define STANDARD_INCLUDE_DIR "/svr4/usr/include"
+
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+-systype /svr4/"
+		    
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}"
+
+#define MACHINE_TYPE "RISC-OS System V.4 Mips"
+
+/* Override defaults for finding the MIPS tools.  */
+#define MD_STARTFILE_PREFIX "/svr4/usr/lib/cmplrs/cc/"
+#define MD_EXEC_PREFIX "/svr4/usr/lib/cmplrs/cc/"
+
+/* Mips System V.4 doesn't have a getpagesize() function needed by the
+   trampoline code, so use the POSIX sysconf function to get it.
+   This is only done when compiling the trampoline code.  */
+
+#ifdef  L_trampoline
+#include <unistd.h>
+
+#define getpagesize()	sysconf(_SC_PAGE_SIZE)
+#endif /*  L_trampoline */
+
+/* Use atexit for static constructors/destructors, instead of defining
+   our own exit function.  */
+#define HAVE_ATEXIT
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
diff --git a/gcc/config/mips/svr4-5.h b/gcc/config/mips/svr4-5.h
new file mode 100755
index 0000000..799e1cd
--- /dev/null
+++ b/gcc/config/mips/svr4-5.h
@@ -0,0 +1,92 @@
+/* Definitions of target machine for GNU compiler.
+   MIPS RISC-OS 5.0 System V.4 version.
+   Copyright (C) 1992 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define MIPS_SVR4
+
+#define CPP_PREDEFINES \
+"-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 \
+-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \
+-D_MIPS_SZINT=32 -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32 \
+-Asystem(unix) -Asystem(svr4) -Acpu(mips) -Amachine(mips)"
+
+#define STANDARD_INCLUDE_DIR "/svr4/usr/include"
+
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+%{call_shared} %{no_archive} %{exact_version} \
+%{!shared: %{!non_shared: %{!call_shared: -non_shared}}} \
+-systype /svr4/ "
+		    
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc crtn.o%s"
+
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}\
+	%{ansi:/svr4/usr/ccs/lib/values-Xc.o%s} \
+                          %{!ansi: \
+                           %{traditional:/svr4/usr/ccs/lib/values-Xt.o%s} \
+                           %{!traditional:/svr4/usr/ccs/lib/values-Xa.o%s}}"
+
+#define MACHINE_TYPE "RISC-OS System V.4 Mips"
+
+/* Override defaults for finding the MIPS tools.  */
+#define MD_STARTFILE_PREFIX "/svr4/usr/lib/cmplrs/cc/"
+#define MD_EXEC_PREFIX "/svr4/usr/lib/cmplrs/cc/"
+
+/* Mips System V.4 doesn't have a getpagesize() function needed by the
+   trampoline code, so use the POSIX sysconf function to get it.
+   This is only done when compiling the trampoline code.  */
+
+#ifdef  L_trampoline
+#include <unistd.h>
+
+/* In at least 5.0 and 5.01, there is no _SC_PAGE_SIZE macro, only a
+   _SC_PAGESIZE macro.  */
+#ifdef _SC_PAGESIZE
+#define _SC_PAGE_SIZE _SC_PAGESIZE
+#endif
+
+#define getpagesize()	sysconf(_SC_PAGE_SIZE)
+#endif /*  L_trampoline */
+
+/* Use atexit for static constructors/destructors, instead of defining
+   our own exit function.  */
+#define HAVE_ATEXIT
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
+
+#include "mips/mips.h"
+
+/* Some assemblers have a bug that causes backslash escaped chars in .ascii
+   to be misassembled, so we just completely avoid it.  */
+#undef ASM_OUTPUT_ASCII
+#define ASM_OUTPUT_ASCII(FILE,PTR,LEN)			\
+do {							\
+  unsigned char *s;					\
+  int i;						\
+  for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++)	\
+    {							\
+      if ((i % 8) == 0)					\
+	fputs ("\n\t.byte\t", (FILE));			\
+      fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \
+    }							\
+  fputs ("\n", (FILE));					\
+} while (0)
diff --git a/gcc/config/mips/svr4-t.h b/gcc/config/mips/svr4-t.h
new file mode 100755
index 0000000..b457aa5
--- /dev/null
+++ b/gcc/config/mips/svr4-t.h
@@ -0,0 +1,29 @@
+/* Definitions of target machine for GNU compiler.  Tandem S2 w/ NonStop UX. */
+
+/* Use the default value for this.  */
+#undef STANDARD_INCLUDE_DIR
+
+#undef MACHINE_TYPE
+#define MACHINE_TYPE "TANDEM System V.4 Mips"
+
+/* Use the default values in mips.h.  */
+#undef MD_STARTFILE_PREFIX
+#undef MD_EXEC_PREFIX
+#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
+#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
+
+/* These are the same as the ones in svr4-5.h, except that references to
+   /svr4/ have been removed.  */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt1.o%s}}\
+	%{ansi:/usr/lib/values-Xc.o%s} \
+                          %{!ansi: \
+                           %{traditional:/usr/lib/values-Xt.o%s} \
+                           %{!traditional:/usr/lib/values-Xa.o%s}}"
+
+#undef LINK_SPEC
+#define LINK_SPEC "\
+%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
+%{bestGnum} %{shared} %{non_shared} \
+%{call_shared} %{no_archive} %{exact_version} \
+%{!shared: %{!non_shared: %{!call_shared: -non_shared}}}"
diff --git a/gcc/config/mips/t-biendian b/gcc/config/mips/t-biendian
new file mode 100755
index 0000000..ada0c2e
--- /dev/null
+++ b/gcc/config/mips/t-biendian
@@ -0,0 +1,18 @@
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+MULTILIB_OPTIONS = EL/EB
+MULTILIB_DIRNAMES = el eb
+MULTILIB_MATCHES = EL=mel EB=meb
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/mips/t-bsd b/gcc/config/mips/t-bsd
new file mode 100755
index 0000000..f9c6fc8
--- /dev/null
+++ b/gcc/config/mips/t-bsd
@@ -0,0 +1,12 @@
+# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR
+# to point to the bsd43 include files.
+SYSTEM_HEADER_DIR = /bsd43/usr/include
+
+# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
+# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
+# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-bsd-gas b/gcc/config/mips/t-bsd-gas
new file mode 100755
index 0000000..bfa5a7e
--- /dev/null
+++ b/gcc/config/mips/t-bsd-gas
@@ -0,0 +1,8 @@
+# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR
+# to point to the bsd43 include files.
+SYSTEM_HEADER_DIR = /bsd43/usr/include
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-cross64 b/gcc/config/mips/t-cross64
new file mode 100755
index 0000000..bfca950
--- /dev/null
+++ b/gcc/config/mips/t-cross64
@@ -0,0 +1,17 @@
+SYSTEM_HEADER_DIR = /usr/cross64/usr/include
+
+AR = /usr/cross64/usr/bin/ar
+
+# The rest of the file is identical to t-iris6.
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 = 
+CROSS_LIBGCC1 = 
+
+MULTILIB_OPTIONS=mips1/mips2/mips3/mips4
+MULTILIB_DIRNAMES=
+MULTILIB_MATCHES=
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/mips/t-ecoff b/gcc/config/mips/t-ecoff
new file mode 100755
index 0000000..8de03ff
--- /dev/null
+++ b/gcc/config/mips/t-ecoff
@@ -0,0 +1,92 @@
+CONFIG2_H	= $(srcdir)/config/mips/ecoff.h
+
+# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
+# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
+# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+
+# When building a cross compiler, put the mips16 support functions in
+# libgcc1.a.
+CROSS_LIBGCC1 = libgcc1-asm.a
+LIB1ASMSRC = mips/mips16.S
+LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
+	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
+	_m16fltsisf _m16fixsfsi \
+	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
+	_m16extsfdf2 _m16trdfsf2 \
+	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
+	_m16fltsidf _m16fixdfsi \
+	_m16retsf _m16retdf \
+	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
+	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
+	_m16stubsf9 _m16stubsf10 \
+	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
+	_m16stubdf9 _m16stubdf10
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# fp-bit and dp-bit are really part of libgcc1, but this will cause
+# them to be built correctly, so... [taken from t-sparclite]
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __MIPSEL__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
+	echo '#endif' >> dp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __MIPSEL__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
+	echo '#endif' >> fp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3
+MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3
+MULTILIB_MATCHES = msingle-float=m4650
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+# Add additional dependencies to recompile selected modules whenever the
+# tm.h file changes.  The files compiled are:
+#
+#	gcc.c		(*_SPEC changes)
+#	toplev.c	(new switches + assembly output changes)
+#	sdbout.c	(debug format changes)
+#	dbxout.c	(debug format changes)
+#	dwarfout.c	(debug format changes)
+#	final.c		(assembly output changes)
+#	varasm.c	(assembly output changes)
+#	cse.c		(cost functions)
+#	insn-output.c	(possible ifdef changes in tm.h)
+#	regclass.c	(fixed/call used register changes)
+#	cccp.c		(new preprocessor macros, -v version #)
+#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
+#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
+#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
+
+gcc.o: $(CONFIG2_H)
+toplev.o: $(CONFIG2_H)
+sdbout.o: $(CONFIG2_H)
+dbxout.o: $(CONFIG2_H)
+dwarfout.o: $(CONFIG2_H)
+final.o: $(CONFIG2_H)
+varasm.o: $(CONFIG2_H)
+cse.o: $(CONFIG2_H)
+insn-output.o: $(CONFIG2_H)
+regclass.o: $(CONFIG2_H)
+cccp.o: $(CONFIG2_H)
+explow.o: $(CONFIG2_H)
+recog.o: $(CONFIG2_H)
+reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-elf b/gcc/config/mips/t-elf
new file mode 100755
index 0000000..dd01b7f
--- /dev/null
+++ b/gcc/config/mips/t-elf
@@ -0,0 +1,96 @@
+CONFIG2_H	= $(srcdir)/config/mips/ecoff.h
+
+# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
+# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
+# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# When building a cross compiler, put the mips16 support functions in
+# libgcc1.a.
+CROSS_LIBGCC1 = libgcc1-asm.a
+LIB1ASMSRC = mips/mips16.S
+LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
+	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
+	_m16fltsisf _m16fixsfsi \
+	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
+	_m16extsfdf2 _m16trdfsf2 \
+	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
+	_m16fltsidf _m16fixdfsi \
+	_m16retsf _m16retdf \
+	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
+	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
+	_m16stubsf9 _m16stubsf10 \
+	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
+	_m16stubdf9 _m16stubdf10
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# fp-bit and dp-bit are really part of libgcc1, but this will cause
+# them to be built correctly, so... [taken from t-sparclite]
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __MIPSEL__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
+	echo '#endif' >> dp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __MIPSEL__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
+	echo '#endif' >> fp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3
+MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3
+MULTILIB_MATCHES = msingle-float=m4650
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+# Add additional dependencies to recompile selected modules whenever the
+# tm.h file changes.  The files compiled are:
+#
+#	gcc.c		(*_SPEC changes)
+#	toplev.c	(new switches + assembly output changes)
+#	sdbout.c	(debug format changes)
+#	dbxout.c	(debug format changes)
+#	dwarfout.c	(debug format changes)
+#	final.c		(assembly output changes)
+#	varasm.c	(assembly output changes)
+#	cse.c		(cost functions)
+#	insn-output.c	(possible ifdef changes in tm.h)
+#	regclass.c	(fixed/call used register changes)
+#	cccp.c		(new preprocessor macros, -v version #)
+#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
+#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
+#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
+
+gcc.o: $(CONFIG2_H)
+toplev.o: $(CONFIG2_H)
+sdbout.o: $(CONFIG2_H)
+dbxout.o: $(CONFIG2_H)
+dwarfout.o: $(CONFIG2_H)
+final.o: $(CONFIG2_H)
+varasm.o: $(CONFIG2_H)
+cse.o: $(CONFIG2_H)
+insn-output.o: $(CONFIG2_H)
+regclass.o: $(CONFIG2_H)
+cccp.o: $(CONFIG2_H)
+explow.o: $(CONFIG2_H)
+recog.o: $(CONFIG2_H)
+reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-iris6 b/gcc/config/mips/t-iris6
new file mode 100755
index 0000000..85a63f0
--- /dev/null
+++ b/gcc/config/mips/t-iris6
@@ -0,0 +1,20 @@
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 = 
+CROSS_LIBGCC1 = 
+
+# ??? If no mabi=X option given, but a mipsX option is, then should deal
+# with that.
+# ??? mabi=32 is deliberately left off the list because it doesn't work yet.
+MULTILIB_OPTIONS=mabi=n32/mabi=64
+MULTILIB_DIRNAMES=
+MULTILIB_MATCHES=
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+# For svr4 we build crtbegin.o and crtend.o which serve to add begin and
+# end labels to the .ctors and .dtors section when we link using gcc.
+
+EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o
+CRTSTUFF_T_CFLAGS=-g1
diff --git a/gcc/config/mips/t-lsi b/gcc/config/mips/t-lsi
new file mode 100755
index 0000000..b771834
--- /dev/null
+++ b/gcc/config/mips/t-lsi
@@ -0,0 +1,100 @@
+# CYGNUS LOCAL entire file angela
+# ??? The list of multilibs is probably overkill, but is conservatively
+# correct.  We probably don't need single-float, and mips3 libs.
+
+CONFIG2_H	= $(srcdir)/config/mips/ecoff.h
+
+# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
+# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
+# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# When building a cross compiler, put the mips16 support functions in
+# libgcc1.a.
+CROSS_LIBGCC1 = libgcc1-asm.a
+LIB1ASMSRC = mips/mips16.S
+LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
+	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
+	_m16fltsisf _m16fixsfsi \
+	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
+	_m16extsfdf2 _m16trdfsf2 \
+	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
+	_m16fltsidf _m16fixdfsi \
+	_m16retsf _m16retdf \
+	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
+	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
+	_m16stubsf9 _m16stubsf10 \
+	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
+	_m16stubdf9 _m16stubdf10
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# fp-bit and dp-bit are really part of libgcc1, but this will cause
+# them to be built correctly, so... [taken from t-sparclite]
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __MIPSEL__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
+	echo '#endif' >> dp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __MIPSEL__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
+	echo '#endif' >> fp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB mips1/mips3/mips16
+MULTILIB_DIRNAMES = soft-float single el eb mips1 mips3 mips16
+MULTILIB_MATCHES = msingle-float=m4650
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+# Add additional dependencies to recompile selected modules whenever the
+# tm.h file changes.  The files compiled are:
+#
+#	gcc.c		(*_SPEC changes)
+#	toplev.c	(new switches + assembly output changes)
+#	sdbout.c	(debug format changes)
+#	dbxout.c	(debug format changes)
+#	dwarfout.c	(debug format changes)
+#	final.c		(assembly output changes)
+#	varasm.c	(assembly output changes)
+#	cse.c		(cost functions)
+#	insn-output.c	(possible ifdef changes in tm.h)
+#	regclass.c	(fixed/call used register changes)
+#	cccp.c		(new preprocessor macros, -v version #)
+#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
+#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
+#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
+
+gcc.o: $(CONFIG2_H)
+toplev.o: $(CONFIG2_H)
+sdbout.o: $(CONFIG2_H)
+dbxout.o: $(CONFIG2_H)
+dwarfout.o: $(CONFIG2_H)
+final.o: $(CONFIG2_H)
+varasm.o: $(CONFIG2_H)
+cse.o: $(CONFIG2_H)
+insn-output.o: $(CONFIG2_H)
+regclass.o: $(CONFIG2_H)
+cccp.o: $(CONFIG2_H)
+explow.o: $(CONFIG2_H)
+recog.o: $(CONFIG2_H)
+reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-mips b/gcc/config/mips/t-mips
new file mode 100755
index 0000000..e57a55a
--- /dev/null
+++ b/gcc/config/mips/t-mips
@@ -0,0 +1,8 @@
+# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
+# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
+# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-mips-gas b/gcc/config/mips/t-mips-gas
new file mode 100755
index 0000000..94f1c44
--- /dev/null
+++ b/gcc/config/mips/t-mips-gas
@@ -0,0 +1,4 @@
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-ncd b/gcc/config/mips/t-ncd
new file mode 100755
index 0000000..6160b7e
--- /dev/null
+++ b/gcc/config/mips/t-ncd
@@ -0,0 +1,2 @@
+LIBGCC1 = libgcc1.null
+CROSS_LIBGCC1 = libgcc1.null
diff --git a/gcc/config/mips/t-osfrose b/gcc/config/mips/t-osfrose
new file mode 100755
index 0000000..e57a55a
--- /dev/null
+++ b/gcc/config/mips/t-osfrose
@@ -0,0 +1,8 @@
+# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
+# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
+# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-r3900 b/gcc/config/mips/t-r3900
new file mode 100755
index 0000000..055143f
--- /dev/null
+++ b/gcc/config/mips/t-r3900
@@ -0,0 +1,95 @@
+CONFIG2_H	= $(srcdir)/config/mips/ecoff.h
+
+# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
+# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
+# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+
+# When building a cross compiler, put the mips16 support functions in
+# libgcc1.a.
+CROSS_LIBGCC1 = libgcc1-asm.a
+LIB1ASMSRC = mips/mips16.S
+LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
+	_m16eqsf2 _m16nesf2 _m16gtsf2 _m16gesf2 _m16lesf2 _m16ltsf2 \
+	_m16fltsisf _m16fixsfsi \
+	_m16adddf3 _m16subdf3 _m16muldf3 _m16divdf3 \
+	_m16extsfdf2 _m16trdfsf2 \
+	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
+	_m16fltsidf _m16fixdfsi \
+	_m16retsf _m16retdf \
+	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
+	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
+	_m16stubsf9 _m16stubsf10 \
+	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
+	_m16stubdf9 _m16stubdf10
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# fp-bit and dp-bit are really part of libgcc1, but this will cause
+# them to be built correctly, so... [taken from t-sparclite]
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __MIPSEL__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
+	echo '#endif' >> dp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __MIPSEL__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
+	echo '#endif' >> fp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS = msoft-float/msingle-float EL/EB
+MULTILIB_DIRNAMES = soft-float single el eb
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+# Add additional dependencies to recompile selected modules whenever the
+# tm.h file changes.  The files compiled are:
+#
+#	gcc.c		(*_SPEC changes)
+#	toplev.c	(new switches + assembly output changes)
+#	sdbout.c	(debug format changes)
+#	dbxout.c	(debug format changes)
+#	dwarfout.c	(debug format changes)
+#	final.c		(assembly output changes)
+#	varasm.c	(assembly output changes)
+#	cse.c		(cost functions)
+#	insn-output.c	(possible ifdef changes in tm.h)
+#	regclass.c	(fixed/call used register changes)
+#	cccp.c		(new preprocessor macros, -v version #)
+#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
+#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
+#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
+
+gcc.o: $(CONFIG2_H)
+toplev.o: $(CONFIG2_H)
+sdbout.o: $(CONFIG2_H)
+dbxout.o: $(CONFIG2_H)
+dwarfout.o: $(CONFIG2_H)
+final.o: $(CONFIG2_H)
+varasm.o: $(CONFIG2_H)
+cse.o: $(CONFIG2_H)
+insn-output.o: $(CONFIG2_H)
+regclass.o: $(CONFIG2_H)
+cccp.o: $(CONFIG2_H)
+explow.o: $(CONFIG2_H)
+recog.o: $(CONFIG2_H)
+reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-svr3 b/gcc/config/mips/t-svr3
new file mode 100755
index 0000000..273c710
--- /dev/null
+++ b/gcc/config/mips/t-svr3
@@ -0,0 +1,12 @@
+# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR
+# to point to the svr3 include files.
+SYSTEM_HEADER_DIR = /sysv/usr/include
+
+# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
+# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
+# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-svr3-gas b/gcc/config/mips/t-svr3-gas
new file mode 100755
index 0000000..99238f2
--- /dev/null
+++ b/gcc/config/mips/t-svr3-gas
@@ -0,0 +1,8 @@
+# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR
+# to point to the svr3 include files.
+SYSTEM_HEADER_DIR = /sysv/usr/include
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-svr4 b/gcc/config/mips/t-svr4
new file mode 100755
index 0000000..88029b9
--- /dev/null
+++ b/gcc/config/mips/t-svr4
@@ -0,0 +1,12 @@
+# Exactly the same as t-mips, except we must define SYSTEM_HEADER_DIR
+# to point to the svr4 include files.
+SYSTEM_HEADER_DIR = /svr4/usr/include
+
+# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
+# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
+# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-svr4-gas b/gcc/config/mips/t-svr4-gas
new file mode 100755
index 0000000..845b091
--- /dev/null
+++ b/gcc/config/mips/t-svr4-gas
@@ -0,0 +1,8 @@
+# Exactly the same as t-mips-gas, except we must define SYSTEM_HEADER_DIR
+# to point to the svr4 include files.
+SYSTEM_HEADER_DIR = /svr4/usr/include
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-ultrix b/gcc/config/mips/t-ultrix
new file mode 100755
index 0000000..7c1a845
--- /dev/null
+++ b/gcc/config/mips/t-ultrix
@@ -0,0 +1,10 @@
+CONFIG2_H	= $(srcdir)/config/mips/mips.h
+
+# We have a premade insn-attrtab.c to save the hour it takes to run genattrtab.
+# PREMADE_ATTRTAB = $(srcdir)/config/mips/mips-at.c
+# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips/mips-at.md
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
diff --git a/gcc/config/mips/t-vr4100 b/gcc/config/mips/t-vr4100
new file mode 100755
index 0000000..710c708
--- /dev/null
+++ b/gcc/config/mips/t-vr4100
@@ -0,0 +1,75 @@
+CONFIG2_H	= $(srcdir)/config/mips/elf.h
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# These are really part of libgcc1, but this will cause them to be
+# built correctly, so... [taken from t-sparclite]
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c $(srcdir)/config/mips/mips16.S
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __MIPSEL__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
+	echo '#endif' >> dp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __MIPSEL__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
+	echo '#endif' >> fp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Build the libraries for soft floating point only
+
+MULTILIB_OPTIONS = EL/EB mno-mips16/mips16
+MULTILIB_DIRNAMES = el eb nomips16 mips16
+MULTILIB_MATCHES = EL=mel EB=meb
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+# Add additional dependencies to recompile selected modules whenever the
+# tm.h file changes.  The files compiled are:
+#
+#	gcc.c		(*_SPEC changes)
+#	toplev.c	(new switches + assembly output changes)
+#	sdbout.c	(debug format changes)
+#	dbxout.c	(debug format changes)
+#	dwarfout.c	(debug format changes)
+#	final.c		(assembly output changes)
+#	varasm.c	(assembly output changes)
+#	cse.c		(cost functions)
+#	insn-output.c	(possible ifdef changes in tm.h)
+#	regclass.c	(fixed/call used register changes)
+#	cccp.c		(new preprocessor macros, -v version #)
+#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
+#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
+#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
+
+gcc.o: $(CONFIG2_H)
+toplev.o: $(CONFIG2_H)
+sdbout.o: $(CONFIG2_H)
+dbxout.o: $(CONFIG2_H)
+dwarfout.o: $(CONFIG2_H)
+final.o: $(CONFIG2_H)
+varasm.o: $(CONFIG2_H)
+cse.o: $(CONFIG2_H)
+insn-output.o: $(CONFIG2_H)
+regclass.o: $(CONFIG2_H)
+cccp.o: $(CONFIG2_H)
+explow.o: $(CONFIG2_H)
+recog.o: $(CONFIG2_H)
+reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-vr4300 b/gcc/config/mips/t-vr4300
new file mode 100755
index 0000000..d91a716
--- /dev/null
+++ b/gcc/config/mips/t-vr4300
@@ -0,0 +1,75 @@
+CONFIG2_H	= $(srcdir)/config/mips/elf.h
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# These are really part of libgcc1, but this will cause them to be
+# built correctly, so... [taken from t-sparclite]
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c $(srcdir)/config/mips/mips16.S
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __MIPSEL__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
+	echo '#endif' >> dp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __MIPSEL__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
+	echo '#endif' >> fp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+# Build the libraries for hard floating point only
+
+MULTILIB_OPTIONS = EL/EB mgp32
+MULTILIB_DIRNAMES = el eb mgp32
+MULTILIB_MATCHES = EL=mel EB=meb
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+# Add additional dependencies to recompile selected modules whenever the
+# tm.h file changes.  The files compiled are:
+#
+#	gcc.c		(*_SPEC changes)
+#	toplev.c	(new switches + assembly output changes)
+#	sdbout.c	(debug format changes)
+#	dbxout.c	(debug format changes)
+#	dwarfout.c	(debug format changes)
+#	final.c		(assembly output changes)
+#	varasm.c	(assembly output changes)
+#	cse.c		(cost functions)
+#	insn-output.c	(possible ifdef changes in tm.h)
+#	regclass.c	(fixed/call used register changes)
+#	cccp.c		(new preprocessor macros, -v version #)
+#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
+#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
+#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
+
+gcc.o: $(CONFIG2_H)
+toplev.o: $(CONFIG2_H)
+sdbout.o: $(CONFIG2_H)
+dbxout.o: $(CONFIG2_H)
+dwarfout.o: $(CONFIG2_H)
+final.o: $(CONFIG2_H)
+varasm.o: $(CONFIG2_H)
+cse.o: $(CONFIG2_H)
+insn-output.o: $(CONFIG2_H)
+regclass.o: $(CONFIG2_H)
+cccp.o: $(CONFIG2_H)
+explow.o: $(CONFIG2_H)
+recog.o: $(CONFIG2_H)
+reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/t-vr5000 b/gcc/config/mips/t-vr5000
new file mode 100755
index 0000000..6ec11d8
--- /dev/null
+++ b/gcc/config/mips/t-vr5000
@@ -0,0 +1,75 @@
+#CYGNUS LOCAL entire file law
+CONFIG2_H	= $(srcdir)/config/mips/elf.h
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# These are really part of libgcc1, but this will cause them to be
+# built correctly, so... [taken from t-sparclite]
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __MIPSEL__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
+	echo '#endif' >> dp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __MIPSEL__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
+	echo '#endif' >> fp-bit.c
+	echo '#define US_SOFTWARE_GOFAST' >> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+# Build the libraries for hard floating point only
+MULTILIB_OPTIONS = EL/EB m5400
+MULTILIB_DIRNAMES = el eb vr5400
+MULTILIB_MATCHES = EL=mel EB=meb
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
+
+# Add additional dependencies to recompile selected modules whenever the
+# tm.h file changes.  The files compiled are:
+#
+#	gcc.c		(*_SPEC changes)
+#	toplev.c	(new switches + assembly output changes)
+#	sdbout.c	(debug format changes)
+#	dbxout.c	(debug format changes)
+#	dwarfout.c	(debug format changes)
+#	final.c		(assembly output changes)
+#	varasm.c	(assembly output changes)
+#	cse.c		(cost functions)
+#	insn-output.c	(possible ifdef changes in tm.h)
+#	regclass.c	(fixed/call used register changes)
+#	cccp.c		(new preprocessor macros, -v version #)
+#	explow.c	(GO_IF_LEGITIMATE_ADDRESS)
+#	recog.c		(GO_IF_LEGITIMATE_ADDRESS)
+#	reload.c	(GO_IF_LEGITIMATE_ADDRESS)
+
+gcc.o: $(CONFIG2_H)
+toplev.o: $(CONFIG2_H)
+sdbout.o: $(CONFIG2_H)
+dbxout.o: $(CONFIG2_H)
+dwarfout.o: $(CONFIG2_H)
+final.o: $(CONFIG2_H)
+varasm.o: $(CONFIG2_H)
+cse.o: $(CONFIG2_H)
+insn-output.o: $(CONFIG2_H)
+regclass.o: $(CONFIG2_H)
+cccp.o: $(CONFIG2_H)
+explow.o: $(CONFIG2_H)
+recog.o: $(CONFIG2_H)
+reload.o: $(CONFIG2_H)
diff --git a/gcc/config/mips/ultrix.h b/gcc/config/mips/ultrix.h
new file mode 100755
index 0000000..d6da6a8
--- /dev/null
+++ b/gcc/config/mips/ultrix.h
@@ -0,0 +1,61 @@
+/* Definitions of target machine for GNU compiler; DECstation (Ultrix) version.
+   Copyright (C) 1991, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define DECSTATION
+
+#ifndef CPP_PREDEFINES
+#define CPP_PREDEFINES "\
+-D__ANSI_COMPAT -DMIPSEL -DR3000 -DSYSTYPE_BSD -D_SYSTYPE_BSD \
+-Dbsd4_2 -Dhost_mips -Dmips -Dultrix -Dunix \
+-Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
+#endif
+
+#ifndef LIB_SPEC
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} -lc"
+#endif
+
+#define SUBTARGET_CPP_SPEC "\
+%{.cc:	-D__LANGUAGE_C -D_LANGUAGE_C} \
+%{.cxx:	-D__LANGUAGE_C -D_LANGUAGE_C} \
+%{.C:	-D__LANGUAGE_C -D_LANGUAGE_C} \
+"
+
+#ifndef STARTFILE_SPEC
+#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}"
+#endif
+
+#ifndef MACHINE_TYPE
+#define MACHINE_TYPE "DECstation running ultrix"
+#endif
+
+/* Use atexit for static constructors/destructors, instead of defining
+   our own exit function.  Ultrix 4.x has this, 3.x probably does not.  */
+#define HAVE_ATEXIT
+
+/* Generate calls to memcpy, etc., not bcopy, etc.  */
+#define TARGET_MEM_FUNCTIONS
+
+/* Work around assembler forward label references generated in exception
+   handling code. */
+#define DWARF2_UNWIND_INFO 0
+
+/* INITIALIZE_TRAMPOLINE calls this library function to flush
+   program and data caches.  */
+#define CACHE_FLUSH_FUNC "cacheflush"
diff --git a/gcc/config/mips/vxworks.h b/gcc/config/mips/vxworks.h
new file mode 100755
index 0000000..0856c37
--- /dev/null
+++ b/gcc/config/mips/vxworks.h
@@ -0,0 +1,50 @@
+/* Copyright (C) 1999 Free Software Foundation, Inc. */
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Undefine the following which were defined in elf.h.  Thise will cause the mips-vxworks
+   port to continue to use collect2 for constructors/destructors.  This entire file may
+   be removed when .ctor/.dtor section support is desired. */
+
+#undef CTORS_SECTION_ASM_OP
+#undef DTORS_SECTION_ASM_OP
+
+#undef EXTRA_SECTIONS
+#define EXTRA_SECTIONS in_sdata, in_rdata
+
+#undef INVOKE__main
+#undef NAME__MAIN
+#undef SYMBOL__MAIN
+
+#undef EXTRA_SECTION_FUNCTIONS
+#define EXTRA_SECTION_FUNCTIONS                                         \
+  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(rdata_section, in_rdata, RDATA_SECTION_ASM_OP)
+
+#undef ASM_OUTPUT_CONSTRUCTOR
+#undef ASM_OUTPUT_DESTRUCTOR
+
+#undef CTOR_LIST_BEGIN
+#undef CTOR_LIST_END
+#undef DTOR_LIST_BEGIN
+#undef DTOR_LIST_END
+
+#undef STARTFILE_SPEC
+#undef ENDFILE_SPEC
+
+/*  End of undefines to turn off .ctor/.dtor section support */
diff --git a/gcc/config/mips/x-dec-osf1 b/gcc/config/mips/x-dec-osf1
new file mode 100755
index 0000000..6e46f0e
--- /dev/null
+++ b/gcc/config/mips/x-dec-osf1
@@ -0,0 +1,17 @@
+# Define CC and OLDCC as the same, so that the tests:
+#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
+#
+# will succeed (if OLDCC != CC, it is assumed that GCC is
+# being used in secondary stage builds).  We need to pass
+# the -Wf,-XNg1500 option so the compiler can compile the
+# G++ file cp-parse.c.  Otherwise it complains about
+# too many case statements.  -Olimit is so the user
+# can use -O2.  Down with fixed size tables!
+
+CC		= $(OLDCC)
+OPT		= -O1
+OLDCC		= cc -Wf,-XNg1500 -Olimit 3000 $(OPT)
+
+# The bison output files are machine-indep,
+# so different flags for a particular machine are not useful.
+#BISONFLAGS	= -l
diff --git a/gcc/config/mips/x-iris b/gcc/config/mips/x-iris
new file mode 100755
index 0000000..cf135d1
--- /dev/null
+++ b/gcc/config/mips/x-iris
@@ -0,0 +1,31 @@
+# Define CC and OLDCC as the same, so that the tests:
+#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
+#
+# will succeed (if OLDCC != CC, it is assumed that GCC is
+# being used in secondary stage builds).  We need to pass
+# the -Wf,-XNg1500 option so the compiler can compile the
+# G++ file cp-parse.c.  Otherwise it complains about
+# too many case statements.  -Olimit is so the user
+# can use -O2.  Down with fixed size tables!
+# The -cckr is to turn off strict ANSI checking.
+
+# These definitions are commented out because they cause trouble with
+# autoconf.  It is believed that they aren't needed anymore.
+#CC		= $(OLDCC)
+#OPT		= -O1
+#OLDCC		= cc -Wf,-XNh2000,-XNg1500 -Olimit 3000 -cckr $(OPT)
+
+# The bison output files are machine-indep,
+# so different flags for a particular machine are not useful.
+#BISONFLAGS	= -l
+
+# -lmld is so we can link collect2 running native.
+# -lmalloc is supposed to be faster than the normal malloc
+CLIB		= -lmld -lmalloc
+
+# Show we need to use the C version of ALLOCA
+ALLOCA		= alloca.o
+
+# Find all of the declarations from the header files
+FIXPROTO_DEFINES= -D__EXTENSIONS__ -D_SGI_SOURCE -D_LANGUAGE_C_PLUS_PLUS
+
diff --git a/gcc/config/mips/x-iris3 b/gcc/config/mips/x-iris3
new file mode 100755
index 0000000..2743ab7
--- /dev/null
+++ b/gcc/config/mips/x-iris3
@@ -0,0 +1,30 @@
+# Define CC and OLDCC as the same, so that the tests:
+#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
+#
+# will succeed (if OLDCC != CC, it is assumed that GCC is
+# being used in secondary stage builds).  We need to pass
+# the -Wf,-XNg1500 option so the compiler can compile the
+# G++ file cp-parse.c.  Otherwise it complains about
+# too many case statements.  -Olimit is so the user
+# can use -O2.  Down with fixed size tables!
+
+# In at least one version of Irix, v3.3.2, the compiler does not accept
+# the -cckr option, so, lets try without it for all versions of Irix 3.x.
+# The -cckr is to turn off strict ANSI checking.
+
+# These definitions are commented out because they cause trouble with
+# autoconf.  It is believed that they aren't needed anymore.
+#CC		= $(OLDCC)
+#OPT		= -O1
+#OLDCC		= cc -Wf,-XNh2000,-XNg1500 -Olimit 3000 $(OPT)
+
+# The bison output files are machine-indep,
+# so different flags for a particular machine are not useful.
+#BISONFLAGS	= -l
+
+# -lmld is so we can link collect2 running native.
+# -lmalloc is supposed to be faster than the normal malloc
+CLIB		= -lmld -lmalloc
+
+# Show we need to use the C version of ALLOCA
+ALLOCA		= alloca.o
diff --git a/gcc/config/mips/x-iris6 b/gcc/config/mips/x-iris6
new file mode 100755
index 0000000..88c41f4
--- /dev/null
+++ b/gcc/config/mips/x-iris6
@@ -0,0 +1,11 @@
+# We force the use of the O32 ABI for two reasons.
+# 1) For consistency, because some versions of Irix 6 default to the O32 ABI
+#    and some versions default to the N64 ABI.
+# 2) To avoid SGI compiler bugs.  The v6.x and v7.0 compilers from SGI have
+#    bugs that cause gcc to be miscompiled when the N32 or N64 ABIs are used.
+#    The O32 ABI is known to be OK.
+CC = $(OLDCC)
+OLDCC = cc -32
+
+# Find all of the declarations from the header files
+FIXPROTO_DEFINES= -D__EXTENSIONS__  -D_SGI_SOURCE -D_LANGUAGE_C_PLUS_PLUS
diff --git a/gcc/config/mips/x-mips b/gcc/config/mips/x-mips
new file mode 100755
index 0000000..7b40743
--- /dev/null
+++ b/gcc/config/mips/x-mips
@@ -0,0 +1,20 @@
+# Define CC and OLDCC as the same, so that the tests:
+#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
+#
+# will succeed (if OLDCC != CC, it is assumed that GCC is
+# being used in secondary stage builds).  We need to pass
+# the -Wf,-XNg1500 option so the compiler can compile the
+# G++ file cp-parse.c.  Otherwise it complains about
+# too many case statements.  The -Olimit is so the user
+# can use -O2.  Down with fixed size tables!
+
+CC		= $(OLDCC)
+OPT		= -O1
+OLDCC		= cc -Wf,-XNg1500,-XNh2000 -Olimit 3000 $(OPT)
+
+# The bison output files are machine-indep,
+# so different flags for a particular machine are not useful.
+#BISONFLAGS	= -l
+
+# This is so we can link collect2 running native.
+CLIB		= -lmld
diff --git a/gcc/config/mips/x-netbsd b/gcc/config/mips/x-netbsd
new file mode 100755
index 0000000..49a89f3
--- /dev/null
+++ b/gcc/config/mips/x-netbsd
@@ -0,0 +1,17 @@
+# Don't run fixproto
+STMP_FIXPROTO =
+
+# We don't need GCC's own include files.
+USER_H = $(srcdir)/ginclude/stdarg.h $(srcdir)/ginclude/varargs.h \
+	 $(srcdir)/ginclude/va-mips.h $(EXTRA_HEADERS) $(LANG_EXTRA_HEADERS)
+
+XLIMITS_H =
+
+# We don't need even the files GCC insists we need.
+GENINCLUDES = Makefile.in
+
+# A lot of stuff needs to go elsewhere.
+includedir=$(exec_prefix)/include
+infodir=$(exec_prefix)/share/info
+tooldir=$(libdir)/cross/$(target)
+mandir=$(exec_prefix)/share/man/man1
diff --git a/gcc/config/mips/x-nws3250v4 b/gcc/config/mips/x-nws3250v4
new file mode 100755
index 0000000..4f5cf26
--- /dev/null
+++ b/gcc/config/mips/x-nws3250v4
@@ -0,0 +1,19 @@
+# Define CC and OLDCC as the same, so that the tests:
+#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
+#
+# will succeed (if OLDCC != CC, it is assumed that GCC is
+# being used in secondary stage builds).  We need to pass
+# the -Wf,-XNg1500 option so the compiler can compile the
+# G++ file cp-parse.c.  Otherwise it complains about
+# too many case statements.  Down with fixed size tables!
+
+CC		= $(OLDCC)
+OLDCC		= cc -Wf,-XNg1500
+CCLIBFLAGS	= -G 0
+
+ALLOCA		= alloca.o
+
+# The bison output files are machine-indep,
+# so different flags for a particular machine are not useful.
+#BISONFLAGS	= -l
+
diff --git a/gcc/config/mips/x-osfrose b/gcc/config/mips/x-osfrose
new file mode 100755
index 0000000..825276c
--- /dev/null
+++ b/gcc/config/mips/x-osfrose
@@ -0,0 +1,32 @@
+# Define CC and OLDCC as the same, so that the tests:
+#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
+#
+# will succeed (if OLDCC != CC, it is assumed that GCC is
+# being used in secondary stage builds).
+
+BUILD		=
+CC		= $(OLDCC)
+CLIB		= -lld
+X_CFLAGS	= $(DEB_OPT) $(MSTATS) $(SHLIB) $(X_DEFINES)
+X_CFLAGS_NODEBUG = $(NO_DEBUG) $(MSTATS) $(OPT) $(PROFILE) $(SHLIB) $(X_DEFINES) $(XCFLAGS)
+CCLIBFLAGS	= -O -pic-extern
+CPP_ABORT	= # -Dabort=fancy_abort
+CPPFLAGS	= $(CPP_ABORT) $(SYSTEM_INCLUDES)
+DEB_OPT		= $(OPT) $(DEBUG) $(PROFILE)
+DEBUG		= 
+DEBUG_COLLECT	= # -DDEBUG
+CCLIBFLAGS	= -O -DNO_HALF_PIC
+GCC_CFLAGS	= $(INTERNAL_CFLAGS) $(X_CFLAGS) $(T_CFLAGS) $(CFLAGS) -B./ -DPOSIX -DNO_HALF_PIC
+LIBGCC2_CFLAGS	= -O2 $(GCC_CFLAGS) -g1 -pic-extern
+LDFLAGS		=
+MSTATS		= # -mstats
+OLDCC		= /usr/ccs/gcc/gcc
+OPT		= -O2
+PROFILE		=
+SHLIB		= -pic-none
+SYSTEM_INCLUDES	= # -I${BUILD}/usr/include
+X_DEFINES	= -Dvfork=fork
+
+libdir		= /usr/ccs
+mandir		= /usr/ccs/gcc/$(target)/$(version)
+bindir		= /usr/ccs/gcc/$(target)/$(version)
diff --git a/gcc/config/mips/x-sni-svr4 b/gcc/config/mips/x-sni-svr4
new file mode 100755
index 0000000..f986f88
--- /dev/null
+++ b/gcc/config/mips/x-sni-svr4
@@ -0,0 +1,18 @@
+# Define CC and OLDCC as the same, so that the tests:
+#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
+#
+# will succeed (if OLDCC != CC, it is assumed that GCC is
+# being used in secondary stage builds).
+# -Olimit is so the user can use -O2.  Down with fixed
+# size tables!
+
+CC		= $(OLDCC)
+OPT		=
+OLDCC		= cc -Olimit 3000 $(OPT)
+
+X_CFLAGS	= -DNO_SYS_SIGLIST
+
+# Show we need to use the C version of ALLOCA
+# The SVR3 configurations have it, but the SVR4 configurations don't.
+# For now, just try using it for all SVR* configurations.
+ALLOCA		= alloca.o
diff --git a/gcc/config/mips/x-sony b/gcc/config/mips/x-sony
new file mode 100755
index 0000000..c64593d
--- /dev/null
+++ b/gcc/config/mips/x-sony
@@ -0,0 +1,18 @@
+# Make internal tables bigger.
+OLDCC=cc -Wf,-XNg1500,-XNh2000 -Olimit 3000 $(OPT)
+
+# Define CC and OLDCC as the same, so that the tests:
+#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
+#
+# will succeed (if OLDCC != CC, it is assumed that GCC is
+# being used in secondary stage builds).  We need to pass
+# the -Wf,-XNg1500 option so the compiler can compile the
+# G++ file cp-parse.c.  Otherwise it complains about
+# too many case statements.  The -Olimit is so the user
+# can use -O2.  Down with fixed size tables!
+
+CC		= $(OLDCC)
+OPT		= -O1
+
+# This is so we can link collect2 running native.
+CLIB		= -lmld
diff --git a/gcc/config/mips/x-sysv b/gcc/config/mips/x-sysv
new file mode 100755
index 0000000..2c173b1
--- /dev/null
+++ b/gcc/config/mips/x-sysv
@@ -0,0 +1,26 @@
+# Define CC and OLDCC as the same, so that the tests:
+#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
+#
+# will succeed (if OLDCC != CC, it is assumed that GCC is
+# being used in secondary stage builds).  We need to pass
+# the -Wf,-XNg1500 option so the compiler can compile the
+# G++ file cp-parse.c.  Otherwise it complains about
+# too many case statements.  -Olimit is so the user
+# can use -O2.  Down with fixed size tables!
+
+CC		= $(OLDCC)
+OPT		= -O1
+OLDCC		= cc -Wf,-XNg1500,-XNh2000 -Olimit 3000 $(OPT)
+
+# The bison output files are machine-indep,
+# so different flags for a particular machine are not useful.
+#BISONFLAGS	= -l
+
+# This enables collect2 to link.
+# Some systems use version 2.11 of the compilers.  Some use version 3.11.
+CLIB= -L/usr/lib/cmplrs/cc2.11 -L/usr/lib/cmplrs/cc3.11 -lmld
+
+# Show we need to use the C version of ALLOCA
+# The SVR3 configurations have it, but the SVR4 configurations don't.
+# For now, just try using it for all SVR* configurations.
+ALLOCA		= alloca.o
diff --git a/gcc/config/mips/x-ultrix b/gcc/config/mips/x-ultrix
new file mode 100755
index 0000000..6e46f0e
--- /dev/null
+++ b/gcc/config/mips/x-ultrix
@@ -0,0 +1,17 @@
+# Define CC and OLDCC as the same, so that the tests:
+#	if [ x"$(OLDCC)" = x"$(CC)" ] ...
+#
+# will succeed (if OLDCC != CC, it is assumed that GCC is
+# being used in secondary stage builds).  We need to pass
+# the -Wf,-XNg1500 option so the compiler can compile the
+# G++ file cp-parse.c.  Otherwise it complains about
+# too many case statements.  -Olimit is so the user
+# can use -O2.  Down with fixed size tables!
+
+CC		= $(OLDCC)
+OPT		= -O1
+OLDCC		= cc -Wf,-XNg1500 -Olimit 3000 $(OPT)
+
+# The bison output files are machine-indep,
+# so different flags for a particular machine are not useful.
+#BISONFLAGS	= -l
diff --git a/gcc/config/mips/xm-iris3.h b/gcc/config/mips/xm-iris3.h
new file mode 100755
index 0000000..448b7ac
--- /dev/null
+++ b/gcc/config/mips/xm-iris3.h
@@ -0,0 +1,3 @@
+#include "mips/xm-mips.h"
+
+#define USG
diff --git a/gcc/config/mips/xm-iris4.h b/gcc/config/mips/xm-iris4.h
new file mode 100755
index 0000000..c01d3f4
--- /dev/null
+++ b/gcc/config/mips/xm-iris4.h
@@ -0,0 +1,13 @@
+#include "mips/xm-mips.h"
+
+#define USG
+
+#if 0
+#ifdef __GNUC__
+/* The normal irix compiler requires alloca.h or alloca doesn't work.
+   However, the IRIX compiler doesn't allow alloca to be stored in
+   something like ptr->field = alloca(), so we just use the normal
+   C alloca.  */
+#include <alloca.h>
+#endif
+#endif
diff --git a/gcc/config/mips/xm-iris5.h b/gcc/config/mips/xm-iris5.h
new file mode 100755
index 0000000..616055f
--- /dev/null
+++ b/gcc/config/mips/xm-iris5.h
@@ -0,0 +1,9 @@
+#include "mips/xm-mips.h"
+
+/* On SGI IRIX 5.3, inttypes.h clashes with sys/types.h, but the clash
+   (when compiled with GCC) is a warning, so configure.in thinks it's OK
+   to use it.  Work around this problem.  */
+
+#ifdef HAVE_INTTYPES_H
+#undef HAVE_INTTYPES_H
+#endif
diff --git a/gcc/config/mips/xm-iris6.h b/gcc/config/mips/xm-iris6.h
new file mode 100755
index 0000000..4d429c7
--- /dev/null
+++ b/gcc/config/mips/xm-iris6.h
@@ -0,0 +1,17 @@
+#define MIPS_OVERRIDE_ALLOCA
+#ifndef __GNUC__
+#include <alloca.h>
+#else
+extern void *alloca ();
+#endif
+
+#include "mips/xm-mips.h"
+
+#define USG
+
+#undef HOST_BITS_PER_LONG
+#define HOST_BITS_PER_LONG	_MIPS_SZLONG
+
+#ifndef inhibit_libc
+#include "string.h"
+#endif
diff --git a/gcc/config/mips/xm-mips.h b/gcc/config/mips/xm-mips.h
new file mode 100755
index 0000000..ad49d7f
--- /dev/null
+++ b/gcc/config/mips/xm-mips.h
@@ -0,0 +1,76 @@
+/* Configuration for GNU C-compiler for MIPS Rx000 family
+   Copyright (C) 1989, 1990, 1991, 1993, 1997 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+
+/* #defines that need visibility everywhere.  */
+#define FALSE 0
+#define TRUE 1
+
+/* This describes the machine the compiler is hosted on.  */
+#define HOST_BITS_PER_CHAR 8
+#define HOST_BITS_PER_SHORT 16
+#define HOST_BITS_PER_INT 32
+#define HOST_BITS_PER_LONG 32
+#define HOST_BITS_PER_LONGLONG 64
+
+#if !defined(MIPSEL) && !defined(__MIPSEL__)
+#define HOST_WORDS_BIG_ENDIAN
+#endif
+
+/* Enable host-conditionals for MIPS machines.  */
+#ifndef MIPS
+#define MIPS 1
+#endif
+
+/* A code distinguishing the floating point format of the host
+   machine.  There are three defined values: IEEE_FLOAT_FORMAT,
+   VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT.  */
+
+#define HOST_FLOAT_FORMAT IEEE_FLOAT_FORMAT
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.   */
+#include "tm.h"
+
+/* Arguments to use with `exit'.  */
+#define SUCCESS_EXIT_CODE 0
+#define FATAL_EXIT_CODE 33
+
+#ifndef __GNUC__
+/* The MIPS compiler gets it wrong, and treats enumerated bitfields
+   as signed quantities, making it impossible to use an 8-bit enum
+   for compiling GNU C++.  */
+#define ONLY_INT_FIELDS 1
+#endif
+
+#ifndef MIPS_OVERRIDE_ALLOCA
+#ifndef __GNUC__
+#define USE_C_ALLOCA
+
+#ifdef __STDC__
+extern void * alloca ();
+#else
+extern char * alloca ();
+#endif
+
+/* for the emacs version of alloca */
+#define STACK_DIRECTION	-1
+#endif
+#endif /* not MIPS_OVERRIDE_ALLOCA */
diff --git a/gcc/config/mips/xm-netbsd.h b/gcc/config/mips/xm-netbsd.h
new file mode 100755
index 0000000..b9d3c70
--- /dev/null
+++ b/gcc/config/mips/xm-netbsd.h
@@ -0,0 +1,2 @@
+#include "mips/xm-mips.h"
+#include "config/xm-netbsd.h"
diff --git a/gcc/config/mips/xm-news.h b/gcc/config/mips/xm-news.h
new file mode 100755
index 0000000..e3eda9d
--- /dev/null
+++ b/gcc/config/mips/xm-news.h
@@ -0,0 +1,8 @@
+/* This file is for the Sony Mips News running "NewsOS Version 5",
+   which is really System V.  */
+#include "mips/xm-sysv.h"
+
+/* Sony has a funny name for this symbol.  */
+#define sys_siglist _sys_siglist
+#undef SYS_SIGLIST_DECLARED
+#define SYS_SIGLIST_DECLARED
diff --git a/gcc/config/mips/xm-nws3250v4.h b/gcc/config/mips/xm-nws3250v4.h
new file mode 100755
index 0000000..34ab631
--- /dev/null
+++ b/gcc/config/mips/xm-nws3250v4.h
@@ -0,0 +1,9 @@
+#define USG
+
+#include "xm-mips.h"
+
+/* If compiling with mips compiler, we are probably using alloca.c,
+   so help it work right.  */
+#ifndef __GNUC__
+#define USE_C_ALLOCA
+#endif
diff --git a/gcc/config/mips/xm-sysv.h b/gcc/config/mips/xm-sysv.h
new file mode 100755
index 0000000..05a8d6c
--- /dev/null
+++ b/gcc/config/mips/xm-sysv.h
@@ -0,0 +1,30 @@
+/* Configuration for GNU C-compiler for UMIPS operating system
+   Copyright (C) 1989, 1990, 1991, 1997 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/*
+ *  Notes for compiling gcc on umips (v3.0)
+ *	- change the -g in the CFLAGS to a -g3 or take it out all together.
+ *	- do not define DBX_DEBUGGING_INFO in tm.h, it doesn't exist (unless
+ *	you get one from a bsd system)
+ */
+
+#define USG
+
+#include "mips/xm-mips.h"
diff --git a/gcc/config/mips/xm-sysv4.h b/gcc/config/mips/xm-sysv4.h
new file mode 100755
index 0000000..b79664b
--- /dev/null
+++ b/gcc/config/mips/xm-sysv4.h
@@ -0,0 +1,7 @@
+#include "mips/xm-sysv.h"
+
+/* SVR4 provides no sys_siglist,
+   but does offer the same data under another name.  */
+#define sys_siglist _sys_siglist
+#undef SYS_SIGLIST_DECLARED
+#define SYS_SIGLIST_DECLARED