diff options
Diffstat (limited to 'gcc/config/clipper')
| -rwxr-xr-x | gcc/config/clipper/clipper.c | 508 | ||||
| -rwxr-xr-x | gcc/config/clipper/clipper.h | 1125 | ||||
| -rwxr-xr-x | gcc/config/clipper/clipper.md | 1421 | ||||
| -rwxr-xr-x | gcc/config/clipper/clix.h | 162 | ||||
| -rwxr-xr-x | gcc/config/clipper/x-clix | 1 | ||||
| -rwxr-xr-x | gcc/config/clipper/xm-clix.h | 30 |
6 files changed, 3247 insertions, 0 deletions
diff --git a/gcc/config/clipper/clipper.c b/gcc/config/clipper/clipper.c new file mode 100755 index 0000000..d59d3f1 --- /dev/null +++ b/gcc/config/clipper/clipper.c @@ -0,0 +1,508 @@ +/* Subroutines for insn-output.c for Clipper + Copyright (C) 1987, 1988, 1991, 1997 Free Software Foundation, Inc. + Contributed by Holger Teutsch (holger@hotbso.rhein-main.de) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "config.h" +#include <stdio.h> +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "output.h" +#include "insn-attr.h" +#include "tree.h" +#include "c-tree.h" +#include "expr.h" +#include "flags.h" +#include "machmode.h" + +extern char regs_ever_live[]; + +extern int frame_pointer_needed; + +static int frame_size; + +/* + * compute size of a clipper stack frame where 'lsize' is the required + * space for local variables. + */ + +int +clipper_frame_size (lsize) + int lsize; +{ + int i,size; /* total size of frame */ + int save_size; + save_size = 0; /* compute size for reg saves */ + + for (i = 16; i < 32; i++) + if (regs_ever_live[i] && !call_used_regs[i]) + save_size += 8; + + for (i = 0; i < 16; i++) + if (regs_ever_live[i] && !call_used_regs[i]) + save_size += 4; + + size = lsize + save_size; + + size = (size + 7) & ~7; /* align to 64 Bit */ + return size; +} + +/* + * prologue and epilogue output + * function is entered with pc pushed, i.e. stack is 32 bit aligned + * + * current_function_args_size == 0 means that the current function's args + * are passed totally in registers i.e fp is not used as ap. + * If frame_size is also 0 the current function does not push anything and + * can run with misaligned stack -> subq $4,sp / add $4,sp on entry and exit + * can be omitted. + * + */ +void +output_function_prologue (file, lsize) + FILE *file; + int lsize; /* size for locals */ +{ + int i, offset; + int size; + + frame_size = size = clipper_frame_size (lsize); + + if (frame_pointer_needed) + { + fputs ("\tpushw fp,sp\n", file); + fputs ("\tmovw sp,fp\n", file); + } + else if (size != 0 || current_function_args_size != 0) + { + size += 4; /* keep stack aligned */ + frame_size = size; /* must push data or access args */ + } + + if (size) + { + if (size < 16) + fprintf (file, "\tsubq $%d,sp\n", size); + else + fprintf (file, "\tsubi $%d,sp\n", size); + + /* register save slots are relative to sp, because we have small positive + displacements and this works whether we have a frame pointer or not */ + + offset = 0; + for (i = 16; i < 32; i++) + if (regs_ever_live[i] && !call_used_regs[i]) + { + if (offset == 0) + fprintf (file, "\tstord f%d,(sp)\n", i-16); + else + fprintf (file, "\tstord f%d,%d(sp)\n", i-16, offset); + offset += 8; + } + + for (i = 0; i < 16; i++) + if (regs_ever_live[i] && !call_used_regs[i]) + { + if (offset == 0) + fprintf (file, "\tstorw r%d,(sp)\n", i); + else + fprintf (file, "\tstorw r%d,%d(sp)\n", i, offset); + offset += 4; + } + } +} + +void +output_function_epilogue (file, size) + FILE *file; + int size; /* ignored */ +{ + int i, offset; + + if (frame_pointer_needed) + { + offset = -frame_size; + + for (i = 16; i < 32; i++) + if (regs_ever_live[i] && !call_used_regs[i]) + { + fprintf (file, "\tloadd %d(fp),f%d\n", offset, i-16); + offset += 8; + } + + for (i = 0; i < 16; i++) + if (regs_ever_live[i] && !call_used_regs[i]) + { + fprintf (file, "\tloadw %d(fp),r%d\n", offset, i); + offset += 4; + } + + fputs ("\tmovw fp,sp\n\tpopw sp,fp\n\tret sp\n", + file); + } + + else /* no frame pointer */ + { + offset = 0; + + for (i = 16; i < 32; i++) + if (regs_ever_live[i] && !call_used_regs[i]) + { + if (offset == 0) + fprintf (file, "\tloadd (sp),f%d\n", i-16); + else + fprintf (file, "\tloadd %d(sp),f%d\n", offset, i-16); + offset += 8; + } + + for (i = 0; i < 16; i++) + if (regs_ever_live[i] && !call_used_regs[i]) + { + if (offset == 0) + fprintf (file, "\tloadw (sp),r%d\n", i); + else + fprintf (file, "\tloadw %d(sp),r%d\n", offset, i); + offset += 4; + } + + if (frame_size > 0) + { + if (frame_size < 16) + fprintf (file, "\taddq $%d,sp\n", frame_size); + else + fprintf (file, "\taddi $%d,sp\n", frame_size); + } + + fputs ("\tret sp\n", file); + } +} + +/* + * blockmove + * + * clipper_movstr () + */ +void +clipper_movstr (operands) + rtx *operands; +{ + rtx dst,src,cnt,tmp,top,bottom,xops[3]; + int align; + int fixed; + + extern FILE *asm_out_file; + + dst = operands[0]; + src = operands[1]; + /* don't change this operands[2]; gcc 2.3.3 doesn't honor clobber note */ + align = INTVAL (operands[3]); + tmp = operands[4]; + cnt = operands[5]; + + if (GET_CODE (operands[2]) == CONST_INT) /* fixed size move */ + { + if ((fixed = INTVAL (operands[2])) <= 0) + abort (); + + if (fixed <16) + output_asm_insn ("loadq %2,%5", operands); + else + output_asm_insn ("loadi %2,%5", operands); + } + else + { + fixed = 0; + bottom = (rtx)gen_label_rtx (); /* need a bottom label */ + xops[0] = cnt; xops[1] = bottom; + output_asm_insn ("movw %2,%5", operands); /* count is scratch reg 5 */ + output_asm_insn ("brle %l1", xops); + } + + + top = (rtx)gen_label_rtx (); /* top of loop label */ + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (top)); + + + xops[0] = src; xops[1] = tmp; xops[2] = dst; + + if (fixed && (align & 0x3) == 0) /* word aligned move with known size */ + { + if (fixed >= 4) + { + rtx xops1[2]; + output_asm_insn( + "loadw %a0,%1\n\taddq $4,%0\n\tstorw %1,%a2\n\taddq $4,%2", + xops); + + xops1[0] = cnt; xops1[1] = top; + output_asm_insn ("subq $4,%0\n\tbrgt %l1", xops1); + } + + if (fixed & 0x2) + { + output_asm_insn ("loadh %a0,%1\n\tstorh %1,%a2", xops); + if (fixed & 0x1) + output_asm_insn ("loadb 2%a0,%1\n\tstorb %1,2%a2", xops); + } + else + if (fixed & 0x1) + output_asm_insn ("loadb %a0,%1\n\tstorb %1,%a2", xops); + } + else + { + output_asm_insn( + "loadb %a0,%1\n\taddq $1,%0\n\tstorb %1,%a2\n\taddq $1,%2", + xops); + + xops[0] = cnt; xops[1] = top; + output_asm_insn ("subq $1,%0\n\tbrgt %l1", xops); + } + + if (fixed == 0) + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (bottom)); +} + + +print_operand_address (file, addr) + FILE *file; + register rtx addr; +{ + rtx op0,op1; + + retry: + switch (GET_CODE (addr)) + { + case REG: + fprintf (file, "(%s)", reg_names[REGNO (addr)]); + break; + + case PLUS: + /* can be 'symbol + reg' or 'reg + reg' */ + + op0 = XEXP (addr, 0); + op1 = XEXP (addr, 1); + + if (GET_CODE (op0) == REG && GET_CODE (op1) == REG) + { + fprintf (file, "[%s](%s)", + reg_names[REGNO (op0)], reg_names[REGNO (op1)]); + break; + } + + if (GET_CODE (op0) == REG && CONSTANT_ADDRESS_P (op1)) + { + output_addr_const (file, op1); + fprintf (file, "(%s)", reg_names[REGNO (op0)]); + break; + } + + if (GET_CODE (op1) == REG && CONSTANT_ADDRESS_P (op0)) + { + output_addr_const (file, op0); + fprintf (file, "(%s)", reg_names[REGNO (op1)]); + break; + } + abort (); /* Oh no */ + + default: + output_addr_const (file, addr); + } +} + + +char * +rev_cond_name (op) + rtx op; +{ + switch (GET_CODE (op)) + { + case EQ: + return "ne"; + case NE: + return "eq"; + case LT: + return "ge"; + case LE: + return "gt"; + case GT: + return "le"; + case GE: + return "lt"; + case LTU: + return "geu"; + case LEU: + return "gtu"; + case GTU: + return "leu"; + case GEU: + return "ltu"; + + default: + abort (); + } +} + + +/* Do what is necessary for `va_start'. The argument is ignored; + We fill in an initial va_list. A pointer to this constructor + is returned. */ + + +struct rtx_def * +clipper_builtin_saveregs (arglist) + tree arglist; +{ + extern int current_function_varargs; + rtx block, addr, argsize, scratch, r0_addr,r1_addr,f0_addr,f1_addr; + + /* Allocate the va_list constructor + save area for r0,r1,f0,f1 */ + + block = assign_stack_local (BLKmode, + (6 + 6) * UNITS_PER_WORD, 2 * BITS_PER_WORD); + + RTX_UNCHANGING_P (block) = 1; + RTX_UNCHANGING_P (XEXP (block, 0)) = 1; + + addr = copy_to_reg (XEXP (block, 0)); + + f0_addr = gen_rtx (PLUS, Pmode, addr, GEN_INT (24)); + f1_addr = gen_rtx (PLUS, Pmode, addr, GEN_INT (32)); + r0_addr = gen_rtx (PLUS, Pmode, addr, GEN_INT (40)); + r1_addr = gen_rtx (PLUS, Pmode, addr, GEN_INT (44)); + + + /* Store float regs */ + + emit_move_insn (gen_rtx (MEM, DFmode, f0_addr), gen_rtx (REG, DFmode, 16)); + emit_move_insn (gen_rtx (MEM, DFmode, f1_addr), gen_rtx (REG, DFmode, 17)); + + /* Store int regs */ + + emit_move_insn (gen_rtx (MEM, SImode, r0_addr), gen_rtx (REG, SImode, 0)); + emit_move_insn (gen_rtx (MEM, SImode, r1_addr), gen_rtx (REG, SImode, 1)); + + /* Store the arg pointer in the __va_stk member. */ + + emit_move_insn (gen_rtx (MEM, SImode, addr), + copy_to_reg (virtual_incoming_args_rtx)); + + + /* now move addresses of the saved regs into the pointer array */ + + scratch = gen_reg_rtx (Pmode); + + emit_move_insn (scratch, r0_addr); + emit_move_insn (gen_rtx (MEM, SImode, + gen_rtx (PLUS, Pmode, addr, + GEN_INT (4))), + scratch); + + emit_move_insn (scratch, f0_addr); + emit_move_insn (gen_rtx (MEM, SImode, + gen_rtx (PLUS, Pmode, addr, + GEN_INT (8))), + scratch); + + emit_move_insn (scratch, r1_addr); + emit_move_insn (gen_rtx (MEM, SImode, + gen_rtx (PLUS, Pmode, addr, + GEN_INT (12))), + scratch); + + emit_move_insn (scratch, f1_addr); + emit_move_insn (gen_rtx (MEM, SImode, + gen_rtx (PLUS, Pmode, addr, + GEN_INT (16))), + scratch); + + + if (current_function_check_memory_usage) + { + emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, + addr, ptr_mode, + GEN_INT (5 * GET_MODE_SIZE (SImode)), + TYPE_MODE (sizetype), + GEN_INT (MEMORY_USE_RW), + TYPE_MODE (integer_type_node)); + + emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, + f0_addr, ptr_mode, + GEN_INT (GET_MODE_SIZE (DFmode)), + TYPE_MODE (sizetype), + GEN_INT (MEMORY_USE_RW), + TYPE_MODE (integer_type_node)); + emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, + f1_addr, ptr_mode, + GEN_INT (GET_MODE_SIZE (DFmode)), + TYPE_MODE (sizetype), + GEN_INT (MEMORY_USE_RW), + TYPE_MODE (integer_type_node)); + emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, + r0_addr, ptr_mode, + GEN_INT (GET_MODE_SIZE (SImode)), + TYPE_MODE (sizetype), + GEN_INT (MEMORY_USE_RW), + TYPE_MODE (integer_type_node)); + emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3, + r1_addr, ptr_mode, + GEN_INT (GET_MODE_SIZE (SImode)), + TYPE_MODE (sizetype), + GEN_INT (MEMORY_USE_RW), + TYPE_MODE (integer_type_node)); + } + + /* Return the address of the va_list constructor, but don't put it in a + register. This fails when not optimizing and produces worse code when + optimizing. */ + return XEXP (block, 0); +} + + +/* Return truth value of whether OP can be used as an word register + operand. Reject (SUBREG:SI (REG:SF )) */ + +int +int_reg_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return (register_operand (op, mode) && + (GET_CODE (op) != SUBREG || + GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) == MODE_INT)); +} + +/* Return truth value of whether OP can be used as a float register + operand. Reject (SUBREG:SF (REG:SI )) )) */ + +int +fp_reg_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return (register_operand (op, mode) && + (GET_CODE (op) != SUBREG || + GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) == MODE_FLOAT)); +} + diff --git a/gcc/config/clipper/clipper.h b/gcc/config/clipper/clipper.h new file mode 100755 index 0000000..666e96d --- /dev/null +++ b/gcc/config/clipper/clipper.h @@ -0,0 +1,1125 @@ +/* Definitions of target machine for GNU compiler. Clipper version. + Copyright (C) 1987, 88, 91, 93-95, 1996 Free Software Foundation, Inc. + Contributed by Holger Teutsch (holger@hotbso.rhein-main.de) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +extern struct rtx_def *clipper_builtin_saveregs (); +extern int clipper_frame_size (); + +/* Print subsidiary information on the compiler version in use. */ + +#define TARGET_VERSION fprintf (stderr, " (clipper)"); + +/* Run-time compilation parameters selecting different hardware subsets. */ + +extern int target_flags; + +/* Macros used in the machine description to test the flags. */ + +/* Macro to define tables used to set the flags. + This is a list in braces of pairs in braces, + each pair being { "NAME", VALUE } + where VALUE is the bits to set or minus the bits to clear. + An empty string NAME is used to identify the default VALUE. */ + +#define TARGET_SWITCHES \ + { { "c400", 1 }, \ + { "c300", -1 }, \ + { "", TARGET_DEFAULT} } + +#define TARGET_C400 1 +#define TARGET_C300 0 + +/* Default target_flags if no switches specified. */ + +#ifndef TARGET_DEFAULT +#define TARGET_DEFAULT TARGET_C300 +#endif + +/* Show that we can debug generated code without a frame pointer. */ +#define CAN_DEBUG_WITHOUT_FP + +/* Target machine storage layout */ + +/* Define this if most significant bit is lowest numbered + in instructions that operate on numbered bit-fields. */ + +#define BITS_BIG_ENDIAN 0 + +/* Define this if most significant byte of a word is the lowest numbered. */ + +#define BYTES_BIG_ENDIAN 0 + +/* Define this if most significant word of a multiword number is the lowest + numbered. */ + +#define WORDS_BIG_ENDIAN 0 + +/* Number of bits in an addressable storage unit */ +#define BITS_PER_UNIT 8 + +/* Width in bits of a "word", which is the contents of a machine register. + Note that this is not necessarily the width of data type `int'; + if using 16-bit ints on a 68000, this would still be 32. + But on a machine with 16-bit registers, this would be 16. */ +#define BITS_PER_WORD 32 + +/* Width of a word, in units (bytes). */ +#define UNITS_PER_WORD 4 + +/* Width in bits of a pointer. + See also the macro `Pmode' defined below. */ +#define POINTER_SIZE 32 + +/* Allocation boundary (in *bits*) for storing arguments in argument list. */ +#define PARM_BOUNDARY 32 + +/* Largest alignment for stack parameters (if greater than PARM_BOUNDARY). */ +#define MAX_PARM_BOUNDARY 64 + +/* Allocation boundary (in *bits*) for the code of a function. */ +#define FUNCTION_BOUNDARY 128 + +/* Alignment of field after `int : 0' in a structure. */ +#define EMPTY_FIELD_BOUNDARY 32 + +/* Every structure's size must be a multiple of this. */ +#define STRUCTURE_SIZE_BOUNDARY 8 + +/* A bitfield declared as `int' forces `int' alignment for the struct. */ +#define PCC_BITFIELD_TYPE_MATTERS 1 + +/* No data type wants to be aligned rounder than this. */ +#define BIGGEST_ALIGNMENT 64 + +/* No structure field wants to be aligned rounder than this. */ +#define BIGGEST_FIELD_ALIGNMENT 64 + +/* Make strcpy of constants fast. */ +#define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \ + ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN)) + +/* Make arrays of chars word-aligned for the same reasons. */ +#define DATA_ALIGNMENT(TYPE, ALIGN) \ + (TREE_CODE (TYPE) == ARRAY_TYPE \ + && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ + && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) + +/* Set this nonzero if move instructions will actually fail to work + when given unaligned data. */ +#define STRICT_ALIGNMENT 1 + +/* Let's keep the stack somewhat aligned. */ +#define STACK_BOUNDARY 64 + +/* Define this macro if it is advisable to hold scalars in registers + in a wider mode than that declared by the program. In such cases, + the value is constrained to be within the bounds of the declared + type, but kept valid in the wider mode. The signedness of the + extension may differ from that of the type. + + For Clipper, we always store objects in a full register. */ + +#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ + if (GET_MODE_CLASS (MODE) == MODE_INT \ + && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ + { \ + (UNSIGNEDP) = 0; \ + (MODE) = SImode; \ + } + + +/* Define this if function arguments should also be promoted using the above + procedure. */ + +/* FIXME: do we loose compatibility to acc if we define this? */ + +/* #define PROMOTE_FUNCTION_ARGS */ + +/* Likewise, if the function return value is promoted. */ + +/* #define PROMOTE_FUNCTION_RETURN */ + + +/* Standard register usage. */ + +/* Number of actual hardware registers. + The hardware registers are assigned numbers for the compiler + from 0 to just below FIRST_PSEUDO_REGISTER. + All registers that the compiler knows about must be given numbers, + even those that are not normally considered general registers. */ +#define FIRST_PSEUDO_REGISTER 32 + +/* 1 for registers that have pervasive standard uses + and are not available for the register allocator. + On the clipper, these are the FP and SP . */ +#define FIXED_REGISTERS \ +{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,\ + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1} /* Default: C300 */ + +/* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ +#define CALL_USED_REGISTERS \ +{1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,\ + 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1} /* default: C300 */ + +/* Zero or more C statements that may conditionally modify two + variables `fixed_regs' and `call_used_regs' (both of type `char + []') after they have been initialized from the two preceding + macros. A C400 has additional floating registers f8 -> f15 */ + +#define CONDITIONAL_REGISTER_USAGE \ + if (target_flags & TARGET_C400) \ + { int i; \ + for (i = 24; i < 32; i++) fixed_regs[i] = call_used_regs[i] = 0; } + +/* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. + On the clipper, fp registers are 64 bits. */ + +#define HARD_REGNO_NREGS(REGNO, MODE) \ + ((REGNO) >= 16 ? 1 \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. + On the clipper 0-15 may hold any mode but DImode and DFmode must be even. + Registers 16-31 hold SFmode and DFmode */ + +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ + ((REGNO) < 16 \ + ? ((MODE) != DImode && (MODE) != DFmode || ((REGNO) & 1) == 0) \ + : ((MODE) == SFmode || (MODE) == DFmode)) + +/* Value is 1 if it is a good idea to tie two pseudo registers + when one has mode MODE1 and one has mode MODE2. + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, + for any hard reg, then this must be 0 for correct output. */ +#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) + +/* Specify the registers used for certain standard purposes. + The values of these macros are register numbers. */ + +/* clipper has extra PC */ +/* #define PC_REGNUM */ + +/* Register to use for pushing function arguments. */ +#define STACK_POINTER_REGNUM 15 + +/* Base register for access to local variables of the function. */ +#define FRAME_POINTER_REGNUM 14 + +/* Value should be nonzero if functions must have frame pointers. + Zero means the frame pointer need not be set up (and parms + may be accessed via the stack pointer) in functions that seem suitable. + This is computed in `reload', in reload1.c. */ +#define FRAME_POINTER_REQUIRED \ + (! leaf_function_p ()) + +/* Base register for access to arguments of the function. */ +#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM + +/* Register in which static-chain is passed to a function. */ +#define STATIC_CHAIN_REGNUM 2 + +/* Register in which address to store a structure value + is passed to a function. */ +#define STRUCT_VALUE_REGNUM 0 + +/* Define the classes of registers for register constraints in the + machine description. Also define ranges of constants. + + One of the classes must always be named ALL_REGS and include all hard regs. + If there is more than one class, another class must be named NO_REGS + and contain no registers. + + The name GENERAL_REGS must be the name of a class (or an alias for + another name such as ALL_REGS). This is the class of registers + that is allowed by "g" or "r" in a register constraint. + Also, registers outside this class are allocated only when + instructions express preferences for them. + + The classes must be numbered in nondecreasing order; that is, + a larger-numbered class must never be contained completely + in a smaller-numbered class. + + For any two classes, it is very desirable that there be another + class that represents their union. */ + +/* The clipper has general and FP regs. */ + +enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES}; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +/* Give names of register classes as strings for dump file. */ + +#define REG_CLASS_NAMES \ + {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } + +/* Define which registers fit in which classes. + This is an initializer for a vector of HARD_REG_SET + of length N_REG_CLASSES. */ + +#define REG_CLASS_CONTENTS {0, 0x0000ffff, 0xffff0000, 0xffffffff} + +/* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + +#define REGNO_REG_CLASS(REGNO) ((REGNO) >= 16 ? FLOAT_REGS : GENERAL_REGS) + +/* The class value for index registers, and the one for base regs. */ + +#define INDEX_REG_CLASS GENERAL_REGS +#define BASE_REG_CLASS GENERAL_REGS + +/* Get reg_class from a letter such as appears in the machine description. */ + +#define REG_CLASS_FROM_LETTER(C) \ + ((C) == 'r' ? GENERAL_REGS : ((C) == 'f' ? FLOAT_REGS: NO_REGS)) + +/* The letters I, J, K, L and M in a register constraint string + can be used to stand for particular ranges of immediate operands. + This macro defines what the ranges are. + C is the letter, and VALUE is a constant value. + Return 1 if VALUE is in the range specified by C. */ + +#define CONST_OK_FOR_LETTER_P(VALUE, C) 0 + +/* Similar, but for floating constants, and defining letters G and H. + Here VALUE is the CONST_DOUBLE rtx itself. */ + +#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0 + +/* Optional extra constraints for this machine. */ + +/* #define EXTRA_CONSTRAINT(OP, C) */ + + +/* Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. */ + +#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) + +/* Return the maximum number of consecutive registers + needed to represent mode MODE in a register of class CLASS. */ + +#define CLASS_MAX_NREGS(CLASS, MODE) \ + ((CLASS) == FLOAT_REGS \ + ? 1 \ + : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) + +/* Stack layout; function entry, exit and calling. */ + +/* Define this if pushing a word on the stack + makes the stack pointer a smaller address. */ +#define STACK_GROWS_DOWNWARD + +/* Define this if longjmp restores from saved registers + rather than from what setjmp saved. */ +/* #define LONGJMP_RESTORE_FROM_STACK */ + +/* Define this if the nominal address of the stack frame + is at the high-address end of the local variables; + that is, each additional local variable allocated + goes at a more negative offset in the frame. */ +#define FRAME_GROWS_DOWNWARD + +/* Offset within stack frame to start allocating local variables at. + If FRAME_GROWS_DOWNWARD, this is the offset to the END of the + first local allocated. Otherwise, it is the offset to the BEGINNING + of the first local allocated. */ +#define STARTING_FRAME_OFFSET 0 + +/* Given an rtx for the address of a frame, + return an rtx for the address of the word in the frame + that holds the dynamic chain--the previous frame's address. */ +#define DYNAMIC_CHAIN_ADDRESS(frame) (frame) + +/* If we generate an insn to push BYTES bytes, + this says how many the stack pointer really advances by. */ + +/* #define PUSH_ROUNDING(BYTES) (BYTES) */ + +/* Keep the stack pointer constant throughout the function. */ +/* we can't set this for clipper as library calls may have 3 args and we pass + only 2 args in regs. */ + +/* #define ACCUMULATE_OUTGOING_ARGS */ + + +/* Offset of first parameter from the argument pointer register value. + size of PC + FP */ + +#define FIRST_PARM_OFFSET(FNDECL) 8 + +/* Value is the number of bytes of arguments automatically + popped when returning from a subroutine call. + FUNDECL is the declaration node of the function (as a tree), + FUNTYPE is the data type of the function (as a tree), + or for a library call it is an identifier node for the subroutine name. + SIZE is the number of bytes of arguments passed on the stack. */ + +#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 + +/* Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ + +#define FUNCTION_VALUE(VALTYPE, FUNC) \ + gen_rtx (REG, TYPE_MODE (VALTYPE), ((TYPE_MODE (VALTYPE) == SFmode ||\ + TYPE_MODE (VALTYPE) == DFmode) ? \ + 16 : 0)) + +/* Define how to find the value returned by a library function + assuming the value has mode MODE. */ + +#define LIBCALL_VALUE(MODE) \ + gen_rtx (REG, (MODE), ((MODE) == SFmode || (MODE) == DFmode ? 16 : 0)) + + +/* 1 if N is a possible register number for a function value + as seen by the caller. */ + +#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16) + +/* 1 if N is a possible register number for function argument passing. */ + +#define FUNCTION_ARG_REGNO_P(N) \ + ((N) == 0 || (N) == 1 || (N) == 16 || (N) == 17) + +/* Define this if PCC uses the nonreentrant convention for returning + structure and union values. Old Green Hills C-Clipper returns static + structs but the newer Apogee compiler passes structs as hidden arg 0. + Structs etc are always passed in memory */ + +/* #define PCC_STATIC_STRUCT_RETURN */ + + +/* Define a data type for recording info about an argument list + during the scan of that argument list. This data type should + hold all necessary information about the function itself + and about the args processed so far, enough to enable macros + such as FUNCTION_ARG to determine where the next arg should go. + + Clipper uses 2 register 'slots' that pass arguments in r0/r1 or f0/f1. + An argument that must be passed in memory (struct... ) leaves that slot + free. + We pass 'long long' only in registers when both slots are free. + Returned structs must be allocated by the caller, the address is passed + in r0. + + struct ss {..} + + fun (i,j,k) i in r0, j in r1, k on stack + fun (s,j,k) s on stack, j in r1, k on stack + fun (i,s,k) i in r0, s on stack, k on stack + s1 = fun (i,s,k) &s1 in r0, i in r1, s on stack, k on stack + + We must keep enough information for varargs/stdargs. + + _clipper_cum_args is a struct of 2 integers, with + num = slots used + size = size of all stack args = offset to next arg without alignment + + If we use stdarg.h, size points to the first unnamed arg, + see va-clipper.h */ + +struct _clipper_cum_args { int num; int size; }; + +#define CUMULATIVE_ARGS struct _clipper_cum_args + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. + + clipper passes the address of a struct in r0, set num = 1 in this case */ + +#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ + ((CUM).num = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE (FNTYPE))), \ + (CUM).size = 0) + +/* internal helper : size of an argument */ + +#define CLIPPER_ARG_SIZE(MODE, TYPE) \ +(((MODE) != BLKmode \ + ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ + : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) \ + * UNITS_PER_WORD) + +/* Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + (TYPE is null for libcalls where that information may not be available.) */ + +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ +do \ +{ \ + int reg = 0; \ + \ + if ((CUM).num < 2 \ + && (GET_MODE_CLASS(MODE)==MODE_INT || GET_MODE_CLASS(MODE)==MODE_FLOAT) \ + && (GET_MODE_SIZE (MODE) <= 8) \ + && ((TYPE) == NULL || !AGGREGATE_TYPE_P(TYPE)) \ + && ((MODE) != DImode || (CUM).num == 0)) \ + { \ + reg = 1; \ + if ((MODE) == DImode) \ + (CUM).num = 1; \ + } \ + \ + (CUM).num++; \ + \ + if (! reg) \ + { \ + int align = FUNCTION_ARG_BOUNDARY (MODE, TYPE) / BITS_PER_UNIT; \ + (CUM).size += align - 1; \ + (CUM).size &= ~(align - 1); \ + (CUM).size += CLIPPER_ARG_SIZE (MODE, TYPE); \ + } \ +} while (0) + +/* Define where to put the arguments to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). + + 2 args may go into regs. These must be MODE_INT or MODE_FLOAT but only + if they really fit into ONE register. The exception is a DImode arg + that occupies both register slots. */ + +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ + (((CUM).num < 2 \ + && (GET_MODE_CLASS(MODE)==MODE_INT || GET_MODE_CLASS(MODE)==MODE_FLOAT) \ + && (GET_MODE_SIZE (MODE) <= 8) \ + && ((TYPE) == NULL || !AGGREGATE_TYPE_P(TYPE)) \ + && ((MODE) != DImode || (CUM).num == 0)) \ + ? gen_rtx (REG, (MODE), \ + GET_MODE_CLASS(MODE) == MODE_FLOAT ? (CUM).num+16 : (CUM).num) \ + : 0) + +/* If defined, a C expression that gives the alignment boundary, in bits, + of an argument with the specified mode and type. If it is not defined, + `PARM_BOUNDARY' is used for all arguments. */ + +#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ + (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_SIZE (MODE)) <= PARM_BOUNDARY \ + ? PARM_BOUNDARY : 2 * PARM_BOUNDARY) + +/* For an arg passed partly in registers and partly in memory, + this is the number of registers used. + For args passed entirely in registers or entirely in memory, zero. + Clipper never passed args partially in regs/mem. */ + +/* #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 */ + +/* Generate necessary RTL for __builtin_saveregs(). + ARGLIST is the argument list; see expr.c. */ + +#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) clipper_builtin_saveregs (ARGLIST) + +/* This macro generates the assembly code for function entry. + FILE is a stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. + Refer to the array `regs_ever_live' to determine which registers + to save; `regs_ever_live[I]' is nonzero if register number I + is ever used in the function. This macro is responsible for + knowing which registers should not be saved even if used. */ + +#define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue (FILE,SIZE) + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#define FUNCTION_PROFILER(FILE, LABELNO) /* FIXME */ + +/* Output assembler code to FILE to initialize this source file's + basic block profiling info, if that has not already been done. */ + +#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) /* FIXME */ + +/* Output assembler code to FILE to increment the entry-count for + the BLOCKNO'th basic block in this source file. */ + +#define BLOCK_PROFILER(FILE, BLOCKNO) /* FIXME */ + +/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, + the stack pointer does not matter. The value is tested only in + functions that have frame pointers. + No definition is equivalent to always zero. */ + +#define EXIT_IGNORE_STACK 1 + +/* This macro generates the assembly code for function exit, + on machines that need it. If FUNCTION_EPILOGUE is not defined + then individual return instructions are generated for each + return statement. Args are same as for FUNCTION_PROLOGUE. */ + +#define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue(FILE,SIZE) + +/* Store in the variable DEPTH the initial difference between the + frame pointer reg contents and the stack pointer reg contents, + as of the start of the function body. This depends on the layout + of the fixed parts of the stack frame and on how registers are saved. */ + +#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ + DEPTH = clipper_frame_size (get_frame_size ()) + + +/* Output assembler code for a block containing the constant parts + of a trampoline, leaving space for the variable parts. */ + +#define TRAMPOLINE_TEMPLATE(FILE) \ +{ \ + fputs ("\t.word 0x459F,0x0004\t# call sp,.+4\n", FILE); \ + fputs ("\tmovw (sp),r3\n", FILE); \ + fputs ("\taddq $4,sp\n", FILE); \ + fputs ("\tloadw 20(r3),r2\n", FILE); \ + fputs ("\tloadw 24(r3),r3\n", FILE); \ + fputs ("\tb (r3)\n", FILE); \ + fputs ("\t.long 0,0\n", FILE); \ +} + +/* Length in units of the trampoline for entering a nested function. */ + +#define TRAMPOLINE_SIZE 32 + +/* Alignment required for a trampoline. 128 is used to find the + beginning of a line in the instruction cache and to allow for + instruction cache lines of up to 128 bytes. */ + +#define TRAMPOLINE_ALIGNMENT 128 + +/* Section in which to place the trampoline. */ + +#define TRAMPOLINE_SECTION text_section + +/* Emit RTL insns to initialize the variable parts of a trampoline. + FNADDR is an RTX for the address of the function's pure code. + CXT is an RTX for the static chain value for the function. */ + +#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ +{ \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 24)), CXT); \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 28)), FNADDR); \ +} + +/* Addressing modes, and classification of registers for them. */ + +/* #define HAVE_POST_DECREMENT 0 */ + +/* #define HAVE_PRE_INCREMENT 0 */ + +/* Macros to check register numbers against specific register classes. */ + +/* These assume that REGNO is a hard or pseudo reg number. + They give nonzero only if REGNO is a hard reg of the suitable class + or a pseudo reg currently allocated to a suitable hard reg. + Since they use reg_renumber, they are safe only once reg_renumber + has been allocated, which happens in local-alloc.c. */ + +#define REGNO_OK_FOR_INDEX_P(regno) \ +((regno) < 16 || (unsigned)reg_renumber[regno] < 16) +#define REGNO_OK_FOR_BASE_P(regno) \ +((regno) < 16 || (unsigned)reg_renumber[regno] < 16) + +/* Maximum number of registers that can appear in a valid memory address. */ + +#define MAX_REGS_PER_ADDRESS 2 + +/* 1 if X is an rtx for a constant that is a valid address. */ + +#define CONSTANT_ADDRESS_P(X) \ + (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ + || GET_CODE (X) == HIGH) + +/* Nonzero if the constant value X is a legitimate general operand. + It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_CONSTANT_P(X) 1 + +/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx + and check its validity for a certain class. + We have two alternate definitions for each of them. + The usual definition accepts all pseudo regs; the other rejects + them unless they have been allocated suitable hard regs. + The symbol REG_OK_STRICT causes the latter definition to be used. + + Most source files want to accept pseudo regs in the hope that + they will get allocated to the class that the insn wants them to be in. + Source files for reload pass need to be strict. + After reload, it makes no difference, since pseudo regs have + been eliminated by then. */ + + /* clipper doesn't have true indexing */ + +#ifndef REG_OK_STRICT + +/* Nonzero if X is a hard reg that can be used as an index + or if it is a pseudo reg. */ + +#define REG_OK_FOR_INDEX_P(X) \ + (REGNO (X) < 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER) + +/* Nonzero if X is a hard reg that can be used as a base reg + or if it is a pseudo reg. */ + +#define REG_OK_FOR_BASE_P(X) \ + (REGNO (X) < 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER) + +#else + +/* Nonzero if X is a hard reg that can be used as an index. */ +#define REG_OK_FOR_INDEX_P(X) (REGNO(X) < 16) + +/* Nonzero if X is a hard reg that can be used as a base reg. */ +#define REG_OK_FOR_BASE_P(X) (REGNO(X) < 16) + +#endif + +/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, + except for CONSTANT_ADDRESS_P which is actually machine-independent. */ + +/* Non-zero if X is an address which can be indirected. */ + +#define INDIRECTABLE_CONSTANT_ADDRESS_P(X) 0 + +#define INDIRECTABLE_ADDRESS_P(X) \ + (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) + +/* Go to ADDR if X is a valid address not using indexing. + (This much is the easy part.) */ + +#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ +{ if (CONSTANT_ADDRESS_P (X)) goto ADDR; \ + if (INDIRECTABLE_ADDRESS_P (X)) goto ADDR; } + +#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +{ register rtx xfoo = (X); \ + GO_IF_NONINDEXED_ADDRESS (xfoo, ADDR); \ + if (GET_CODE (xfoo) == PLUS) \ + { register rtx xfoo0, xfoo1; \ + xfoo0 = XEXP (xfoo, 0); \ + xfoo1 = XEXP (xfoo, 1); \ + /* handle reg + reg -> [r1](r0) */ \ + if (INDIRECTABLE_ADDRESS_P (xfoo0) && INDIRECTABLE_ADDRESS_P (xfoo1)) \ + goto ADDR; \ + /* Handle <symbol>(reg) -> xxx(r0) */ \ + if (INDIRECTABLE_ADDRESS_P (xfoo0) && CONSTANT_ADDRESS_P (xfoo1)) \ + goto ADDR; \ + if (INDIRECTABLE_ADDRESS_P (xfoo1) && CONSTANT_ADDRESS_P (xfoo0)) \ + goto ADDR; }} + + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was called. + In some cases it is useful to look at this to decide what needs to be done. + + MODE and WIN are passed so that this macro can use + GO_IF_LEGITIMATE_ADDRESS. + + It is always safe for this macro to do nothing. It exists to recognize + opportunities to optimize the output. + + For the clipper, nothing needs to be done. */ + +#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} + +/* Go to LABEL if ADDR (a legitimate address expression) + has an effect that depends on the machine mode it is used for. */ + +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {} + + +/* Specify the machine mode that this machine uses + for the index in the tablejump instruction. */ +#define CASE_VECTOR_MODE SImode + +/* Define as C expression which evaluates to nonzero if the tablejump + instruction expects the table to contain offsets from the address of the + table. + Do not define this if the table should contain absolute addresses. */ +/* #define CASE_VECTOR_PC_RELATIVE 1 */ + +/* Define this if the case instruction drops through after the table + when the index is out of range. Don't define it if the case insn + jumps to the default label instead. */ +/* #define CASE_DROPS_THROUGH */ + +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND + +/* Specify the tree operation to be used to convert reals to integers. */ +#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR + +/* This is the kind of divide that is easiest to do in the general case. */ +#define EASY_DIV_EXPR TRUNC_DIV_EXPR + +/* Define this as 1 if `char' should by default be signed; else as 0. */ +#define DEFAULT_SIGNED_CHAR 1 + +/* This flag, if defined, says the same insns that convert to a signed fixnum + also convert validly to an unsigned one. */ +#define FIXUNS_TRUNC_LIKE_FIX_TRUNC + +/* Max number of bytes we can move from memory to memory + in one reasonably fast instruction. */ +#define MOVE_MAX 4 + +/* If a memory-to-memory move would take MOVE_RATIO or more simple + move-instruction pairs, we will do a movstr or libcall instead. + + Make this large on clipper, since the block move is very + inefficient with small blocks, and the hard register needs of the + block move require much reload work. */ + +#define MOVE_RATIO 20 + +/* Define this if zero-extension is slow (more than one real instruction). */ +/* #define SLOW_ZERO_EXTEND */ + +/* Nonzero if access to memory by bytes is slow and undesirable. */ +#define SLOW_BYTE_ACCESS 0 + +/* Define if shifts truncate the shift count + which implies one can omit a sign-extension or zero-extension + of a shift count. */ +/* #define SHIFT_COUNT_TRUNCATED */ + +/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +/* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. */ +#define Pmode SImode + +/* A function address in a call instruction + is a byte address (for indexing purposes) + so give the MEM rtx a byte's mode. */ +#define FUNCTION_MODE QImode + +/* This machine uses IEEE floats. */ + +#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT + +/* Check a `double' value for validity for a particular machine mode. + This is defined to avoid crashes outputting certain constants. + Since we output the number in hex, the assembler won't choke on it. */ +/* #define CHECK_FLOAT_VALUE(MODE,VALUE) */ + + +/* Compute the cost of computing a constant rtl expression RTX + whose rtx-code is CODE. The body of this macro is a portion + of a switch statement. If the code is computed here, + return it with a return statement. Otherwise, break from the switch. */ + +/* On a Clipper, constants from 0..15 are cheap because they can use the + 'quick' mode. */ + +#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ + case CONST_INT: \ + if (0 <= INTVAL (RTX) && INTVAL(RTX) <= 15 ) return 0; \ + return 1; \ + case CONST: \ + case LABEL_REF: \ + case SYMBOL_REF: \ + return 3; \ + case CONST_DOUBLE: \ + return 5; + +/* Provide the costs of a rtl expression. This is in the body of a + switch on CODE. */ + +#define RTX_COSTS(X,CODE,OUTER_CODE) \ + case MULT: \ + return COSTS_N_INSNS (4); \ + case DIV: \ + case UDIV: \ + case MOD: \ + case UMOD: \ + return COSTS_N_INSNS (40); \ + case ASHIFT: \ + case LSHIFTRT: \ + case ASHIFTRT: \ + return COSTS_N_INSNS (2); \ + case SIGN_EXTEND: \ + return (GET_CODE (XEXP (X,0)) == REG ? COSTS_N_INSNS (3) : 4); + +/* Specify the cost of a branch insn; roughly the number of extra insns that + should be added to avoid a branch */ + +/* #define BRANCH_COST 0 */ + + +/* Tell final.c how to eliminate redundant test instructions. */ + +/* Here we define machine-dependent flags and fields in cc_status + (see `conditions.h'). No extra ones are needed for the clipper. */ + +/* Store in cc_status the expressions + that the condition codes will describe + after execution of an instruction whose pattern is EXP. + Do not alter them if the instruction would not alter the cc's. */ + +#define NOTICE_UPDATE_CC(EXP, INSN) \ +{ \ + enum attr_cc cc = get_attr_cc (INSN); \ + rtx dest = SET_DEST (EXP); \ + switch (cc) \ + { \ + case CC_CHANGE0: \ + if (GET_CODE (EXP) == PARALLEL) abort(); \ + if (cc_status.value1 && rtx_equal_p (dest, cc_status.value1) || \ + cc_status.value2 && rtx_equal_p (dest, cc_status.value2)) \ + CC_STATUS_INIT; \ + break; \ + \ + case CC_SET1: \ + if (GET_CODE (EXP) == PARALLEL) abort(); \ + cc_status.flags = 0; \ + cc_status.value1 = dest; \ + cc_status.value2 = 0; \ + break; \ + \ + case CC_SET2: \ + if (GET_CODE (EXP) == PARALLEL) abort(); \ + cc_status.flags = 0; \ + cc_status.value1 = dest; \ + cc_status.value2 = SET_SRC (EXP); \ + break; \ + \ + case CC_UNCHANGED: \ + break; \ + \ + case CC_CLOBBER: \ + CC_STATUS_INIT; \ + break; \ + \ + default: \ + abort (); \ + } \ +} + + +/* Control the assembler format that we output. */ + +/* Output at beginning of assembler file. */ + +#define ASM_FILE_START(FILE) fprintf (FILE, "#NO_APP\n"); + +/* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + +#define ASM_APP_ON "#APP\n" + +/* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + +#define ASM_APP_OFF "#NO_APP\n" + +/* Output before read-only data. */ + +#define TEXT_SECTION_ASM_OP ".text" + +/* Output before writable data. */ + +#define DATA_SECTION_ASM_OP ".data" + +/* How to refer to registers in assembler output. + This sequence is indexed by compiler's hard-register-number (see above). */ + +#define REGISTER_NAMES \ +{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", \ + "r9", "r10", "r11", "r12", "r13", "fp", "sp", \ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", \ + "f9", "f10", "f11", "f12", "f13", "f14", "f15" } + +/* How to renumber registers for dbx and gdb. + Clipper needs no change in the numeration. */ + +#define DBX_REGISTER_NUMBER(REGNO) (REGNO) + + +/* This is how to output the definition of a user-level label named NAME, + such as the label on a static function or variable NAME. */ + +#define ASM_OUTPUT_LABEL(FILE,NAME) \ + do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) + +/* This is how to output a command to make the user-level label named NAME + defined for reference from other files. */ + +#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ + do { fputs (".globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) + +/* This is how to output an assembler line defining an `int' constant. */ + +#define ASM_OUTPUT_INT(FILE,VALUE) \ +( fprintf (FILE, "\t.long "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +/* Likewise for `char' and `short' constants. */ + +#define ASM_OUTPUT_SHORT(FILE,VALUE) \ +( fprintf (FILE, "\t.word "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +#define ASM_OUTPUT_CHAR(FILE,VALUE) \ +( fprintf (FILE, "\t.byte "), \ + output_addr_const (FILE, (VALUE)), \ + fprintf (FILE, "\n")) + +/* This is how to output an assembler line for a numeric constant byte. */ + +#define ASM_OUTPUT_BYTE(FILE,VALUE) \ + fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) + +/* This is how to output an insn to push a register on the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + fprintf (FILE, "\tsubq $8,sp\n\t%s %s,(sp)\n", \ + (REGNO) < 16 ? "storw" : "stord", reg_names[REGNO]) + +/* This is how to output an insn to pop a register from the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + fprintf (FILE, "\t%s (sp),%s\n\t\addq $8,sp\n", \ + (REGNO) < 16 ? "loadw" : "loadd", reg_names[REGNO]) +/* This is how to output an element of a case-vector that is absolute */ + +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ + fprintf (FILE, "\t.long .L%d\n", VALUE) + +/* This is how to output an element of a case-vector that is relative. */ + +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ + fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL) + +/* This is how to output an assembler line + that says to advance the location counter by SIZE bytes. */ + +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.space %u\n", (SIZE)) + +/* This says how to output an assembler line + to define a local common symbol. */ +/* ??? The use of .bss here seems odd. */ + +#define ASM_OUTPUT_ALIGNED_LOCAL(FILE,NAME,SIZE,ALIGN) \ +( data_section (), \ + fputs ("\t.bss\t", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN)/BITS_PER_UNIT)) + +/* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable named NAME. + LABELNO is an integer which is different for each call. */ + +#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ +( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ + sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) + +/* Define the parentheses used to group arithmetic operations + in assembler code. */ + +#define ASM_OPEN_PAREN "(" +#define ASM_CLOSE_PAREN ")" + +/* Define results of standard character escape sequences. */ +#define TARGET_BELL 007 +#define TARGET_BS 010 +#define TARGET_TAB 011 +#define TARGET_NEWLINE 012 +#define TARGET_VT 013 +#define TARGET_FF 014 +#define TARGET_CR 015 + +/* Print an instruction operand X on file FILE. + CODE is the code from the %-spec that requested printing this operand; + if `%z3' was used to print operand 3, then CODE is 'z'. + +Clipper operand formatting codes: + + letter print + C reverse branch condition +*/ + +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ + ((CODE) == 'C') + +#define PRINT_OPERAND(FILE, X, CODE) \ +{ extern char *rev_cond_name (); \ + if (CODE == 'C') \ + fputs (rev_cond_name (X), FILE); \ + else if (GET_CODE (X) == REG) \ + fprintf (FILE, "%s", reg_names[REGNO (X)]); \ + else if (GET_CODE (X) == MEM) \ + output_address (XEXP (X, 0)); \ + else { putc ('$', FILE); output_addr_const (FILE, X); }} + +/* Print a memory operand whose address is X, on file FILE. + This uses a function in output-clipper.c. */ + +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ + print_operand_address (FILE, ADDR) + +/* Define the codes that are matched by predicates in clipper.c */ + +#define PREDICATE_CODES \ + {"int_reg_operand", {SUBREG, REG}}, \ + {"fp_reg_operand", {SUBREG, REG}}, diff --git a/gcc/config/clipper/clipper.md b/gcc/config/clipper/clipper.md new file mode 100755 index 0000000..87f30fa --- /dev/null +++ b/gcc/config/clipper/clipper.md @@ -0,0 +1,1421 @@ +;;- Machine description for GNU compiler, Clipper Version +;; Copyright (C) 1987, 88, 91, 93, 94, 1997 Free Software Foundation, Inc. +;; Contributed by Holger Teutsch (holger@hotbso.rhein-main.de) + +;; This file is part of GNU CC. + +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. + +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + + +;;- Instruction patterns. When multiple patterns apply, +;;- the first one in the file is chosen. +;;- +;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. +;;- +;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code +;;- updates for most instructions. + +;; +;; define attributes +;; +;; instruction type +;; +;; unknown is temporary in order to generate 'cc clobber' until attribute +;; assignment is consistent +;; +(define_attr "type" "load,store,arith,fp,branch,unknown" + (const_string "unknown")) + +;; condition code setting +;; +;; clobber destroyed +;; unchanged +;; set1 set cc_status.value1, e.g. sub r0,r1 +;; set2 set value1 and value2, e.g. mov r0,r1 +;; change0 may be side effect, i.e. load mem,r0 +;; +;; note: loadi and loadq are 'arith' instructions that set the condition codes +;; mul,div,mod do NOT set the condition codes +;; +(define_attr "cc" "clobber,unchanged,set1,set2,change0" + (cond [(eq_attr "type" "load") (const_string "change0") + (eq_attr "type" "store,branch") (const_string "unchanged") + (eq_attr "type" "arith") (if_then_else (match_operand:SI 0 "" "") + (const_string "set1") + (const_string "clobber")) + ] + (const_string "clobber"))) + +;; +;; clipper seems to be a traditional risc processor +;; we define a functional unit 'memory' +;; +(define_function_unit "memory" 1 1 (eq_attr "type" "load") 4 0) + + +;; We don't want to allow a constant operand for test insns because +;; (set (cc0) (const_int foo)) has no mode information. Such insns will +;; be folded while optimizing anyway. + +(define_insn "tstsi" + [(set (cc0) + (match_operand:SI 0 "int_reg_operand" "r"))] + "" + "cmpq $0,%0") + +(define_insn "cmpsi" + [(set (cc0) + (compare (match_operand:SI 0 "nonimmediate_operand" "r,r,n") + (match_operand:SI 1 "nonmemory_operand" "r,n,r")))] + "" + "* +{ + int val; + + if (which_alternative == 0) + return \"cmpw %1,%0\"; + + if (which_alternative == 1) + { + val = INTVAL (operands[1]); + if (0 <= val && val < 16) + return \"cmpq %1,%0\"; + return \"cmpi %1,%0\"; + } + + cc_status.flags |= CC_REVERSED; /* immediate must be first */ + + val = INTVAL (operands[0]); + + if (0 <= val && val < 16) + return \"cmpq %0,%1\"; + + return \"cmpi %0,%1\"; +}") + +(define_insn "cmpdf" + [(set (cc0) + (compare (match_operand:DF 0 "fp_reg_operand" "f") + (match_operand:DF 1 "fp_reg_operand" "f")))] + "" + "cmpd %1,%0") + +(define_insn "cmpsf" + [(set (cc0) + (compare (match_operand:SF 0 "fp_reg_operand" "f") + (match_operand:SF 1 "fp_reg_operand" "f")))] + "" + "cmps %1,%0") + + +;; +;; double and single float move +;; +(define_expand "movdf" + [(set (match_operand:DF 0 "general_operand" "") + (match_operand:DF 1 "general_operand" ""))] + "" + " +{ + if (GET_CODE (operands[0]) == MEM) + { + if (GET_CODE (operands[1]) == CONST_DOUBLE) + operands[1] = force_reg (DFmode, + force_const_mem (DFmode, operands[1])); + else if (GET_CODE (operands[1]) != REG) + operands[1] = force_reg (DFmode, operands[1]); + } + + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + operands[1] = force_const_mem (DFmode, operands[1]); +}") + +;; +;; provide two patterns with different predicates as we don't want combine +;; to recombine a mem -> mem move +;; +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=*rf") + (match_operand:DF 1 "nonimmediate_operand" "*rfo"))] + "" + "* +{ +#define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16) + + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) /* f -> f */ + return \"movd %1,%0\"; + + if (GET_CODE (operands[1]) == REG) /* r -> f */ + return \"movld %1,%0\"; + + return \"loadd %1,%0\"; /* m -> f */ + } + + if (FP_REG_P (operands[1])) + { + if (GET_CODE (operands[0]) == REG) /* f -> r */ + return \"movdl %1,%0\"; + + abort (); + } + + if (GET_CODE (operands[1]) == MEM) /* m -> r */ + { + rtx xops[4]; + xops[0] = operands[0]; + xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + xops[2] = operands[1]; + xops[3] = adj_offsettable_operand (operands[1], 4); + output_asm_insn (\"loadw %2,%0\;loadw %3,%1\", xops); + return \"\"; + } + + if (GET_CODE (operands[1]) == REG) /* r -> r */ + { + rtx xops[4]; + xops[0] = operands[0]; + xops[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + xops[2] = operands[1]; + xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"movw %2,%0\;movw %3,%1\", xops); + return \"\"; + } + + abort (); +#undef FP_REG_P +}") + + +(define_insn "" + [(set (match_operand:DF 0 "memory_operand" "=o,m") + (match_operand:DF 1 "register_operand" "*rf,f"))] + "" + "* +{ + rtx xops[4]; + + if (REGNO (operands[1]) >= 16) /* f -> m */ + return \"stord %1,%0\"; + + xops[0] = operands[0]; /* r -> o */ + xops[1] = adj_offsettable_operand (operands[0], 4); + xops[2] = operands[1]; + xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops); + return \"\"; +}" +[(set_attr "type" "store,store") + (set_attr "cc" "clobber,unchanged")]) + + +(define_expand "movsf" + [(set (match_operand:SF 0 "general_operand" "") + (match_operand:SF 1 "general_operand" ""))] + "" + " +{ + if (GET_CODE (operands[0]) == MEM) + { + if (GET_CODE (operands[1]) == CONST_DOUBLE) + operands[1] = force_reg (SFmode, + force_const_mem (SFmode, operands[1])); + else if (GET_CODE (operands[1]) != REG) + operands[1] = force_reg (SFmode, operands[1]); + } + + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + operands[1] = force_const_mem (SFmode, operands[1]); +}") + +;; +;; provide two patterns with different predicates as we don't want combine +;; to recombine a mem -> mem move +;; +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=*rf") + (match_operand:SF 1 "nonimmediate_operand" "*rfm"))] + "" + "* +{ +#define FP_REG_P(X) (GET_CODE (X) == REG && REGNO (X) >= 16) + + if (FP_REG_P (operands[0])) + { + if (FP_REG_P (operands[1])) /* f -> f */ + return \"movs %1,%0\"; + if (GET_CODE (operands[1]) == REG) /* r -> f */ + return + \"subq $8,sp\;storw %1,(sp)\;loads (sp),%0\;addq $8,sp\"; + return \"loads %1,%0\"; /* m -> f */ + } + + if (FP_REG_P (operands[1])) + { + if (GET_CODE (operands[0]) == REG) /* f -> r */ + return + \"subq $8,sp\;stors %1,(sp)\;loadw (sp),%0\;addq $8,sp\"; + abort (); + } + + if (GET_CODE (operands[1]) == MEM) /* m -> r */ + return \"loadw %1,%0\"; + + if (GET_CODE (operands[1]) == REG) /* r -> r */ + return \"movw %1,%0\"; + + abort (); +#undef FP_REG_P +}") + +(define_insn "" + [(set (match_operand:SF 0 "memory_operand" "=m") + (match_operand:SF 1 "register_operand" "*rf"))] + "" + "* +{ + if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) >= 16) + return \"stors %1,%0\"; /* f-> m */ + + return \"storw %1,%0\"; /* r -> m */ +}" +[(set_attr "type" "store")]) + + +(define_expand "movdi" + [(set (match_operand:DI 0 "general_operand" "") + (match_operand:DI 1 "general_operand" ""))] + "" + " +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG) + operands[1] = force_reg (DImode, operands[1]); +}") + +;; If an operand is a MEM but not offsettable, we can't load it into +;; a register, so we must force the third alternative to be the one +;; reloaded. Hence we show the first as more expensive. +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=?r,r,r") + (match_operand:DI 1 "general_operand" "r,n,o"))] + "" + "* +{ + rtx xoperands[2],yoperands[2]; + + xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + + if (which_alternative == 0) /* r -> r */ + { + output_asm_insn (\"movw %1,%0\", operands); + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"movw %1,%0\", xoperands); + return \"\"; + } + + if (which_alternative == 1) /* n -> r */ + { + if (GET_CODE (operands[1]) == CONST_INT) + { + output_asm_insn (\"loadi %1,%0\", operands); + output_asm_insn (\"loadq $0,%0\", xoperands); + return \"\"; + } + + if (GET_CODE (operands[1]) != CONST_DOUBLE) + abort (); + + yoperands[0] = operands[0]; + yoperands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); + output_asm_insn (\"loadi %1,%0\", yoperands); + + xoperands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); + output_asm_insn (\"loadi %1,%0\", xoperands); + return \"\"; + } + /* m -> r */ + output_asm_insn (\"loadw %1,%0\", operands); + xoperands[1] = adj_offsettable_operand (operands[1], 4); + output_asm_insn (\"loadw %1,%0\", xoperands); + return \"\"; +}" +[(set_attr "type" "arith,arith,load") + (set_attr "cc" "clobber,clobber,clobber")]) + +(define_insn "" + [(set (match_operand:DI 0 "memory_operand" "=o") + (match_operand:DI 1 "register_operand" "r"))] + "" + "* +{ + rtx xops[4]; + xops[0] = operands[0]; + xops[1] = adj_offsettable_operand (operands[0], 4); + xops[2] = operands[1]; + xops[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + output_asm_insn (\"storw %2,%0\;storw %3,%1\", xops); + return \"\"; +}" +[(set_attr "type" "store") + (set_attr "cc" "clobber")]) + +(define_expand "movsi" + [(set (match_operand:SI 0 "general_operand" "") + (match_operand:SI 1 "general_operand" ""))] + "" + " +{ + if (GET_CODE (operands[0]) == MEM && + GET_CODE (operands[1]) != REG) + operands[1] = force_reg (SImode, operands[1]); +}") + +;; Reject both args with `general_operand' if not reloading because a +;; mem -> mem move that was split by 'movsi' can be recombined to +;; mem -> mem by the combiner. +;; +;; As a pseudo register can end up in a stack slot during reloading we must +;; allow a r->m move for the next pattern. +;; The first predicate must be `general_operand' because a predicate must +;; be true for each constraint. +;; +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,m") + (match_operand:SI 1 "general_operand" "r,m,n,i,r"))] + "reload_in_progress || register_operand (operands[0], SImode)" + "* +{ + int val; + + if (which_alternative == 0) + return \"movw %1,%0\"; /* reg -> reg */ + + if (which_alternative == 1) + return \"loadw %1,%0\"; /* mem -> reg */ + + if (which_alternative == 2) + { + val = INTVAL (operands[1]); /* known const ->reg */ + + if (val == -1) + return \"notq $0,%0\"; + + if (val < 0 || val >= 16) + return \"loadi %1,%0\"; + + return \"loadq %1,%0\"; + } + + if (which_alternative == 3) /* unknown const */ + return \"loada %a1,%0\"; + + return \"storw %1,%0\"; +}" +[(set_attr "type" "arith,load,arith,load,store") + (set_attr "cc" "set2,change0,set1,change0,unchanged")]) + + +(define_insn "" + [(set (match_operand:SI 0 "memory_operand" "=m") + (match_operand:SI 1 "int_reg_operand" "r"))] + "" + "storw %1,%0" +[(set_attr "type" "store")]) + +;; movhi +;; +;; loadh mem to reg +;; storh reg to mem +;; +;; +(define_expand "movhi" + [(set (match_operand:HI 0 "general_operand" "") + (match_operand:HI 1 "general_operand" ""))] + "" + " +{ + if (GET_CODE (operands[0]) == MEM + && ! register_operand (operands[1], HImode)) + operands[1] = force_reg (HImode, operands[1]); +}") + + +(define_insn "" + [(set (match_operand:HI 0 "register_operand" "=r,r,r") + (match_operand:HI 1 "general_operand" "r,m,n"))] + "" + "@ + movw %1,%0 + loadh %1,%0 + loadi %1,%0" +[(set_attr "type" "arith,load,arith")]) + +(define_insn "" + [(set (match_operand:HI 0 "memory_operand" "=m") + (match_operand:HI 1 "register_operand" "r"))] + "" + "storh %1,%0" + [(set_attr "type" "store")]) + +;; movqi +;; +;; loadb mem to reg +;; storb reg to mem +;; +(define_expand "movqi" + [(set (match_operand:QI 0 "general_operand" "") + (match_operand:QI 1 "general_operand" ""))] + "" + " +{ + if (GET_CODE (operands[0]) == MEM && + ! register_operand (operands[1], QImode)) + operands[1] = force_reg (QImode, operands[1]); +}") + + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=r,r,r") + (match_operand:QI 1 "general_operand" "r,m,n"))] + "" + "@ + movw %1,%0 + loadb %1,%0 + loadi %1,%0" +[(set_attr "type" "arith,load,arith")]) + +(define_insn "" + [(set (match_operand:QI 0 "memory_operand" "=m") + (match_operand:QI 1 "register_operand" "r"))] + "" + "storb %1,%0" +[(set_attr "type" "store")]) + + +;; +;; block move +;; +(define_expand "movstrsi" + [(parallel + [(set (match_operand:BLK 0 "memory_operand" "") + (match_operand:BLK 1 "memory_operand" "")) + (use (match_operand:SI 2 "general_operand" "")) + (use (match_operand:SI 3 "const_int_operand" "")) + (clobber (match_scratch:SI 4 "")) + (clobber (match_scratch:SI 5 "")) + (clobber (match_dup 6)) + (clobber (match_dup 7))])] + "" + " +{ + rtx addr0, addr1; + + addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); + addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); + + operands[6] = addr0; + operands[7] = addr1; + + operands[0] = change_address (operands[0], VOIDmode, addr0); + operands[1] = change_address (operands[1], VOIDmode, addr1); + + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = force_reg (SImode, operands[2]); +}") + +;; +;; there is a problem with this insn in gcc-2.2.3 +;; (clobber (match_dup 2)) does not prevent use of this operand later +;; we always use a scratch register and leave operand 2 unchanged +;; +(define_insn "" + [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) + (mem:BLK (match_operand:SI 1 "register_operand" "r"))) + (use (match_operand:SI 2 "nonmemory_operand" "rn")) + (use (match_operand:SI 3 "const_int_operand" "n")) + (clobber (match_scratch:SI 4 "=r")) + (clobber (match_scratch:SI 5 "=r")) + (clobber (match_dup 0)) + (clobber (match_dup 1))] + "" + "* +{ + extern void clipper_movstr (); + clipper_movstr (operands); + return \"\"; +}" +[(set_attr "cc" "clobber")]) + + + +;; Extension and truncation insns. +(define_insn "extendhisi2" + [(set (match_operand:SI 0 "int_reg_operand" "=r,r") + (sign_extend:SI (match_operand:HI 1 "general_operand" "0,m")))] + "" + "@ + andi $65535,%0\;xori $32768,%0\;subi $32768,%0 + loadh %1,%0" +[(set_attr "type" "arith,load")]) + + +(define_insn "extendqihi2" + [(set (match_operand:HI 0 "int_reg_operand" "=r,r") + (sign_extend:HI (match_operand:QI 1 "general_operand" "0,m")))] + "" + "@ + andi $255,%0\;xori $128,%0\;subi $128,%0 + loadb %1,%0" +[(set_attr "type" "arith,load") + (set_attr "cc" "set1,change0")]) + + +(define_insn "extendqisi2" + [(set (match_operand:SI 0 "int_reg_operand" "=r,r") + (sign_extend:SI (match_operand:QI 1 "general_operand" "0,m")))] + "" + "@ + andi $255,%0\;xori $128,%0\;subi $128,%0 + loadb %1,%0" +[(set_attr "type" "arith,load")]) + + +(define_insn "extendsfdf2" + [(set (match_operand:DF 0 "fp_reg_operand" "=f") + (float_extend:DF (match_operand:SF 1 "fp_reg_operand" "f")))] + "" + "cnvsd %1,%0") + +(define_insn "truncdfsf2" + [(set (match_operand:SF 0 "fp_reg_operand" "=f") + (float_truncate:SF (match_operand:DF 1 "fp_reg_operand" "f")))] + "" + "cnvds %1,%0") + +(define_insn "zero_extendhisi2" + [(set (match_operand:SI 0 "int_reg_operand" "=r,r") + (zero_extend:SI (match_operand:HI 1 "general_operand" "0,m")))] + "" + "@ + andi $65535,%0 + loadhu %1,%0" +[(set_attr "type" "arith,load")]) + + +(define_insn "zero_extendqihi2" + [(set (match_operand:HI 0 "int_reg_operand" "=r,r") + (zero_extend:HI (match_operand:QI 1 "general_operand" "0,m")))] + "" + "@ + andi $255,%0 + loadbu %1,%0" +[(set_attr "type" "arith,load") + (set_attr "cc" "clobber,clobber")]) + + +(define_insn "zero_extendqisi2" + [(set (match_operand:SI 0 "int_reg_operand" "=r,r") + (zero_extend:SI (match_operand:QI 1 "general_operand" "0,m")))] + "" + "@ + andi $255,%0 + loadbu %1,%0" +[(set_attr "type" "arith,load")]) + + + +;; Fix-to-float conversion insns. + +(define_insn "floatsisf2" + [(set (match_operand:SF 0 "fp_reg_operand" "=f") + (float:SF (match_operand:SI 1 "int_reg_operand" "r")))] + "" + "cnvws %1,%0") + +(define_insn "floatsidf2" + [(set (match_operand:DF 0 "fp_reg_operand" "=f") + (float:DF (match_operand:SI 1 "int_reg_operand" "r")))] + "" + "cnvwd %1,%0") + + +;; Float-to-fix conversion insns. + +(define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (fix:SI (fix:SF (match_operand:SF 1 "fp_reg_operand" "f"))))] + "" + "cnvtsw %1,%0") + +(define_insn "fix_truncdfsi2" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (fix:SI (fix:DF (match_operand:DF 1 "fp_reg_operand" "f"))))] + "" + "cnvtdw %1,%0") + +;;- All kinds of add instructions. + +(define_insn "adddf3" + [(set (match_operand:DF 0 "fp_reg_operand" "=f") + (plus:DF (match_operand:DF 1 "fp_reg_operand" "0") + (match_operand:DF 2 "fp_reg_operand" "f")))] + "" + "addd %2,%0" + [(set_attr "type" "fp")]) + + +(define_insn "addsf3" + [(set (match_operand:SF 0 "fp_reg_operand" "=f") + (plus:SF (match_operand:SF 1 "fp_reg_operand" "0") + (match_operand:SF 2 "fp_reg_operand" "f")))] + "" + "adds %2,%0" + [(set_attr "type" "fp")]) + +(define_insn "adddi3" + [(set (match_operand:DI 0 "int_reg_operand" "=r") + (plus:DI (match_operand:DI 1 "int_reg_operand" "%0") + (match_operand:DI 2 "int_reg_operand" "r")))] + "" + "* +{ + rtx xoperands[4]; + + xoperands[0] = operands[0]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + xoperands[2] = operands[2]; + xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1); + output_asm_insn (\"addw %2,%0\;addwc %3,%1\", xoperands); + return \"\"; +}" +[(set_attr "type" "arith") + (set_attr "cc" "clobber")]) + +(define_insn "addsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r,r,r") + (plus:SI (match_operand:SI 1 "int_reg_operand" "%0,r,r") + (match_operand:SI 2 "nonmemory_operand" "rn,0,rn")))] + "" + "* +{ + if (which_alternative == 2) /* 3 address version */ + { + if (GET_CODE (operands[2]) == CONST_INT) + return \"loada %a2(%1),%0\"; + return \"loada [%2](%1),%0\"; + } + /* 2 address version */ + if (GET_CODE (operands[2]) == CONST_INT) + { + int val = INTVAL (operands[2]); + + if (val >= 16 || val == 0x80000000) + return \"addi %2,%0\"; + + if (val < 0) /* change to sub */ + { + rtx xops[2]; + + val = -val; + + xops[0] = operands[0]; + xops[1] = GEN_INT (val); + + if (val >= 16) + output_asm_insn (\"subi %1,%0\", xops); + else + output_asm_insn (\"subq %1,%0\", xops); + + return \"\"; + } + + return \"addq %2,%0\"; + } + + if (which_alternative == 0) + return \"addw %2,%0\"; + + return \"addw %1,%0\"; +}" +[(set_attr "type" "arith,arith,arith") + (set_attr "cc" "set1,set1,change0")]) + + +;;- All kinds of subtract instructions. + +(define_insn "subdi3" + [(set (match_operand:DI 0 "int_reg_operand" "=r") + (minus:DI (match_operand:DI 1 "int_reg_operand" "0") + (match_operand:DI 2 "int_reg_operand" "r")))] + "" + "* +{ + rtx xoperands[4]; + + xoperands[0] = operands[0]; + xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + xoperands[2] = operands[2]; + xoperands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1); + output_asm_insn (\"subw %2,%0\;subwc %3,%1\", xoperands); + return \"\"; +}" +[(set_attr "type" "arith") + (set_attr "cc" "clobber")]) + +(define_insn "subsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (minus:SI (match_operand:SI 1 "int_reg_operand" "0") + (match_operand:SI 2 "nonmemory_operand" "rn")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT) + { + int val = INTVAL (operands[2]); + + if (val < 0 || val >= 16) + return \"subi %2,%0\"; + else + return \"subq %2,%0\"; + } + + return \"subw %2,%0\"; +}" +[(set_attr "type" "arith")]) + +(define_insn "subdf3" + [(set (match_operand:DF 0 "fp_reg_operand" "=f") + (minus:DF (match_operand:DF 1 "fp_reg_operand" "0") + (match_operand:DF 2 "fp_reg_operand" "f")))] + "" + "subd %2,%0" + [(set_attr "type" "fp")]) + +(define_insn "subsf3" + [(set (match_operand:SF 0 "fp_reg_operand" "=f") + (minus:SF (match_operand:SF 1 "fp_reg_operand" "0") + (match_operand:SF 2 "fp_reg_operand" "f")))] + "" + "subs %2,%0" + [(set_attr "type" "fp")]) + + +;;- Multiply instructions. + +(define_insn "muldf3" + [(set (match_operand:DF 0 "fp_reg_operand" "=f") + (mult:DF (match_operand:DF 1 "fp_reg_operand" "0") + (match_operand:DF 2 "fp_reg_operand" "f")))] + "" + "muld %2,%0" + [(set_attr "type" "fp")]) + +(define_insn "mulsf3" + [(set (match_operand:SF 0 "fp_reg_operand" "=f") + (mult:SF (match_operand:SF 1 "fp_reg_operand" "0") + (match_operand:SF 2 "fp_reg_operand" "f")))] + "" + "muls %2,%0" + [(set_attr "type" "fp")]) + +(define_insn "mulsidi3" + [(set (match_operand:DI 0 "int_reg_operand" "=r") + (mult:DI (sign_extend:DI (match_operand:SI 1 "int_reg_operand" "%0")) + (sign_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))] + "" + "mulwx %2,%0" +[(set_attr "type" "arith") + (set_attr "cc" "clobber")]) + +(define_insn "umulsidi3" + [(set (match_operand:DI 0 "int_reg_operand" "=r") + (mult:DI (zero_extend:DI (match_operand:SI 1 "int_reg_operand" "%0")) + (zero_extend:DI (match_operand:SI 2 "int_reg_operand" "r"))))] + "" + "mulwux %2,%0" +[(set_attr "type" "arith") + (set_attr "cc" "clobber")]) + +(define_insn "mulsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (mult:SI (match_operand:SI 1 "int_reg_operand" "%0") + (match_operand:SI 2 "int_reg_operand" "r")))] + "" + "mulw %2,%0" + [(set_attr "type" "arith") + (set_attr "cc" "clobber")]) + + +;;- Divide and mod instructions. + +(define_insn "divdf3" + [(set (match_operand:DF 0 "fp_reg_operand" "=f") + (div:DF (match_operand:DF 1 "fp_reg_operand" "0") + (match_operand:DF 2 "fp_reg_operand" "f")))] + "" + "divd %2,%0" + [(set_attr "type" "fp")]) + +(define_insn "divsf3" + [(set (match_operand:SF 0 "fp_reg_operand" "=f") + (div:SF (match_operand:SF 1 "fp_reg_operand" "0") + (match_operand:SF 2 "fp_reg_operand" "f")))] + "" + "divs %2,%0" + [(set_attr "type" "fp")]) + +(define_insn "divsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (div:SI (match_operand:SI 1 "int_reg_operand" "0") + (match_operand:SI 2 "int_reg_operand" "r")))] + "" + "divw %2,%0" + [(set_attr "type" "arith") + (set_attr "cc" "clobber")]) + +(define_insn "udivsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (udiv:SI (match_operand:SI 1 "int_reg_operand" "0") + (match_operand:SI 2 "int_reg_operand" "r")))] + "" + "divwu %2,%0" + [(set_attr "type" "arith") + (set_attr "cc" "clobber")]) + + +(define_insn "modsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (mod:SI (match_operand:SI 1 "int_reg_operand" "0") + (match_operand:SI 2 "int_reg_operand" "r")))] + "" + "modw %2,%0" + [(set_attr "type" "arith") + (set_attr "cc" "clobber")]) + +(define_insn "umodsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (umod:SI (match_operand:SI 1 "int_reg_operand" "0") + (match_operand:SI 2 "int_reg_operand" "r")))] + "" + "modwu %2,%0" + [(set_attr "type" "arith") + (set_attr "cc" "clobber")]) + +;; +;; bit and/or instructions +;; +(define_insn "andsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r,r") + (and:SI (match_operand:SI 1 "int_reg_operand" "%0,0") + (match_operand:SI 2 "nonmemory_operand" "r,n")))] + "" + "@ + andw %2,%0 + andi %2,%0" + [(set_attr "type" "arith")]) + +(define_insn "iorsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r,r") + (ior:SI (match_operand:SI 1 "int_reg_operand" "%0,0") + (match_operand:SI 2 "nonmemory_operand" "r,n")))] + "" + "@ + orw %2,%0 + ori %2,%0" + [(set_attr "type" "arith")]) + +(define_insn "xorsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r,r") + (xor:SI (match_operand:SI 1 "int_reg_operand" "%0,0") + (match_operand:SI 2 "nonmemory_operand" "r,n")))] + "" + "@ + xorw %2,%0 + xori %2,%0" + [(set_attr "type" "arith")]) + +(define_insn "negdf2" + [(set (match_operand:DF 0 "fp_reg_operand" "=f") + (neg:DF (match_operand:DF 1 "fp_reg_operand" "f")))] + "" + "negd %1,%0" + [(set_attr "type" "fp")]) + +(define_insn "negsf2" + [(set (match_operand:SF 0 "fp_reg_operand" "=f") + (neg:SF (match_operand:SF 1 "fp_reg_operand" "f")))] + "" + "negs %1,%0" + [(set_attr "type" "fp")]) + +(define_insn "negsi2" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (neg:SI (match_operand:SI 1 "int_reg_operand" "r")))] + "" + "negw %1,%0" + [(set_attr "type" "arith")]) + + +(define_insn "one_cmplsi2" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (not:SI (match_operand:SI 1 "int_reg_operand" "r")))] + "" + "notw %1,%0" + [(set_attr "type" "arith")]) + + + +;; Right shift on the clipper works by negating the shift count, +;; then emitting a right shift with the shift count negated. This means +;; that all actual shift counts in the RTL will be positive. + +(define_expand "ashrdi3" + [(set (match_operand:DI 0 "int_reg_operand" "") + (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:DI 0 "int_reg_operand" "=r") + (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") + (match_operand:SI 2 "const_int_operand" "n")))] + "" + "shali $%n2,%0" + [(set_attr "type" "arith")]) + +(define_insn "" + [(set (match_operand:DI 0 "int_reg_operand" "=r") + (ashiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") + (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] + "" + "shal %2,%0" + [(set_attr "type" "arith")]) + +(define_expand "ashrsi3" + [(set (match_operand:SI 0 "int_reg_operand" "") + (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") + (match_operand:SI 2 "const_int_operand" "n")))] + "" + "shai $%n2,%0" + [(set_attr "type" "arith")]) + +(define_insn "" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (ashiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") + (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] + "" + "shaw %2,%0" + [(set_attr "type" "arith")]) + +;; +;; left shift +;; + +(define_insn "ashldi3" + [(set (match_operand:DI 0 "int_reg_operand" "=r,r") + (ashift:DI (match_operand:DI 1 "int_reg_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "r,n")))] + "" + "@ + shal %2,%0 + shali %2,%0" + [(set_attr "type" "arith")]) + + +(define_insn "ashlsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r,r") + (ashift:SI (match_operand:SI 1 "int_reg_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "r,n")))] + "" + "* +{ + int val; + + if (which_alternative == 0) + return \"shaw %2,%0\"; + + val = INTVAL (operands[2]); + + if (val == 2) + return \"addw %0,%0\;addw %0,%0\"; + + if (val == 1) + return \"addw %0,%0\"; + + return \"shai %2,%0\"; +}" +[(set_attr "type" "arith")]) + +;; +;; logical shift +;; + +(define_expand "lshrdi3" + [(set (match_operand:DI 0 "int_reg_operand" "") + (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:DI 0 "int_reg_operand" "=r") + (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") + (match_operand:SI 2 "const_int_operand" "n")))] + "" + "shlli $%n2,%0" + [(set_attr "type" "arith")]) + +(define_insn "" + [(set (match_operand:DI 0 "int_reg_operand" "=r") + (lshiftrt:DI (match_operand:DI 1 "int_reg_operand" "0") + (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] + "" + "shll %2,%0" + [(set_attr "type" "arith")]) + +(define_expand "lshrsi3" + [(set (match_operand:SI 0 "int_reg_operand" "") + (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") + (match_operand:SI 2 "const_int_operand" "n")))] + "" + "shli $%n2,%0" + [(set_attr "type" "arith")]) + +(define_insn "" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (lshiftrt:SI (match_operand:SI 1 "int_reg_operand" "0") + (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] + "" + "shlw %2,%0" + [(set_attr "type" "arith")]) + + +;; +;; rotate insn +;; +(define_expand "rotrdi3" + [(set (match_operand:DI 0 "int_reg_operand" "") + (rotatert:DI (match_operand:DI 1 "int_reg_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:DI 0 "int_reg_operand" "=r") + (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0") + (match_operand:SI 2 "const_int_operand" "n")))] + "" + "rotli $%n2,%0" + [(set_attr "type" "arith")]) + +(define_insn "" + [(set (match_operand:DI 0 "int_reg_operand" "=r") + (rotatert:DI (match_operand:DI 1 "int_reg_operand" "0") + (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] + "" + "rotl %2,%0" + [(set_attr "type" "arith")]) + +(define_expand "rotrsi3" + [(set (match_operand:SI 0 "int_reg_operand" "") + (rotatert:SI (match_operand:SI 1 "int_reg_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); +}") + +(define_insn "" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0") + (match_operand:SI 2 "const_int_operand" "n")))] + "" + "roti $%n2,%0" + [(set_attr "type" "arith")]) + +(define_insn "" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (rotatert:SI (match_operand:SI 1 "int_reg_operand" "0") + (neg:SI (match_operand:SI 2 "nonmemory_operand" "r"))))] + "" + "rotw %2,%0" + [(set_attr "type" "arith")]) + +(define_insn "rotldi3" + [(set (match_operand:DI 0 "int_reg_operand" "=r,r") + (rotate:DI (match_operand:DI 1 "int_reg_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "r,n")))] + "" + "@ + rotl %2,%0 + rotli %2,%0" + [(set_attr "type" "arith")]) + +(define_insn "rotlsi3" + [(set (match_operand:SI 0 "int_reg_operand" "=r,r") + (rotate:SI (match_operand:SI 1 "int_reg_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "r,n")))] + "" + "@ + rotw %2,%0 + roti %2,%0" + [(set_attr "type" "arith")]) + + +;; +;; jump and branch insns +;; +(define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] + "" + "b %l0" + [(set_attr "type" "branch")]) + +(define_insn "tablejump" + [(set (pc) (match_operand:SI 0 "register_operand" "r")) + (use (label_ref (match_operand 1 "" "")))] + "" + "b (%0)" + [(set_attr "type" "branch")]) + +(define_insn "beq" + [(set (pc) + (if_then_else (eq (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "breq %l0" + [(set_attr "type" "branch")]) + +(define_insn "bne" + [(set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "brne %l0" + [(set_attr "type" "branch")]) + +(define_insn "bgt" + [(set (pc) + (if_then_else (gt (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "brgt %l0" + [(set_attr "type" "branch")]) + +(define_insn "bgtu" + [(set (pc) + (if_then_else (gtu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "brgtu %l0" + [(set_attr "type" "branch")]) + +(define_insn "blt" + [(set (pc) + (if_then_else (lt (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "brlt %l0" + [(set_attr "type" "branch")]) + +(define_insn "bltu" + [(set (pc) + (if_then_else (ltu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "brltu %l0" + [(set_attr "type" "branch")]) + +(define_insn "bge" + [(set (pc) + (if_then_else (ge (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "brge %l0" + [(set_attr "type" "branch")]) + +(define_insn "bgeu" + [(set (pc) + (if_then_else (geu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "brgeu %l0" + [(set_attr "type" "branch")]) + +(define_insn "ble" + [(set (pc) + (if_then_else (le (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "brle %l0" + [(set_attr "type" "branch")]) + +(define_insn "bleu" + [(set (pc) + (if_then_else (leu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "brleu %l0" + [(set_attr "type" "branch")]) + +;; Recognize reversed jumps. +(define_insn "" + [(set (pc) + (if_then_else (match_operator 0 "comparison_operator" + [(cc0) + (const_int 0)]) + (pc) + (label_ref (match_operand 1 "" ""))))] + "" + "br%C0 %l1" ; %C0 negates condition + [(set_attr "type" "branch")]) + +;; +;; call instructions +;; +(define_insn "call" + [(call (match_operand:QI 0 "general_operand" "m") + (match_operand:SI 1 "general_operand" ""))] + ;; Operand 1 not used on the clipper. + "" + "call sp,%0") + +(define_insn "call_value" + [(set (match_operand 0 "" "=rf") + (call (match_operand:QI 1 "general_operand" "m") + (match_operand:SI 2 "general_operand" "g")))] + ;; Operand 2 not used on the clipper + "" + "call sp,%1") + +;; Call subroutine returning any type. + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "" + " +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +}") + +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and +;; all of memory. This blocks insns from being moved across this point. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "") + +(define_insn "indirect_jump" + [(set (pc) (match_operand:SI 0 "register_operand" "r"))] + "" + "b (%0)" + [(set_attr "type" "branch")]) + + +(define_insn "nop" + [(const_int 0)] + "" + "noop" + [(set_attr "type" "arith") + (set_attr "cc" "unchanged")]) + + + +;; while (--foo >= 0) +;; +;; Combiners for 'decrement test and branch' do not work for clipper. +;; These patters are jump_insns that do not allow output reloads and clipper +;; can only decrement and test registers. +;; diff --git a/gcc/config/clipper/clix.h b/gcc/config/clipper/clix.h new file mode 100755 index 0000000..c36e4de --- /dev/null +++ b/gcc/config/clipper/clix.h @@ -0,0 +1,162 @@ +/* Definitions of target machine for GNU compiler. Clipper/Clix version. + Copyright (C) 1988, 1993, 1996, 1997 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Names to predefine in the preprocessor for this target machine. */ + +#define CPP_PREDEFINES "-Dclipper -Dunix -Asystem(unix) -Asystem(svr3) -Acpu(clipper) -Amachine(clipper)" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend.o%s crtn.o%s" + +#undef LIB_SPEC + +#define TARGET_MEM_FUNCTIONS + +#undef HAVE_ATEXIT +#define HAVE_ATEXIT + +#define ASM_OUTPUT_ASCII(FILE,PTR,LEN) \ +do { \ + unsigned char *s; \ + int i; \ + for (i = 0, s = (unsigned char *)(PTR); i < (LEN); s++, i++) \ + { \ + if ((i % 8) == 0) \ + fputs ("\n\t.byte\t", (FILE)); \ + fprintf ((FILE), "%s0x%x", (i%8?",":""), (unsigned)*s); \ + } \ + fputs ("\n", (FILE)); \ +} while (0) + +#undef ASM_OUTPUT_DOUBLE +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ +{ \ + union { int i[2]; double d; } _d_; \ + _d_.d = VALUE; \ + fprintf (FILE, "\t.long 0x%08x,0x%08x\n", _d_.i[0],_d_.i[1]); \ +} + +#undef ASM_OUTPUT_FLOAT +#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ +{ \ + union { int i; float f; } _f_; \ + _f_.f = VALUE; \ + fprintf (FILE, "\t.long 0x%08x\n", _f_.i); \ +} + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + fprintf(FILE, "\t.align %d\n", 1 << (LOG)) + + +#define ASM_LONG ".long" +#define BSS_SECTION_ASM_OP ".bss" +#undef INIT_SECTION_ASM_OP +#define INIT_SECTION_ASM_OP ".section .init,\"x\"" + + +/* Define a few machine-specific details of the implementation of + constructors. + + The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN + and CTOR_LIST_END to contribute to the .init section an instruction to + push a word containing 0 (or some equivalent of that). + + ASM_OUTPUT_CONSTRUCTOR should be defined to push the address of the + constructor. */ + +#define CTOR_LIST_BEGIN \ + asm (INIT_SECTION_ASM_OP); \ + asm ("subq $8,sp"); \ + asm ("loadq $0,r0"); \ + asm ("storw r0,(sp)") + +/* don't need end marker */ + +#undef CTOR_LIST_END + +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + init_section (); \ + fputs ("\tloada ", FILE); \ + assemble_name (FILE, NAME); \ + fputs (",r0\n\tsubq $8,sp\n\tstorw r0,(sp)\n", FILE); \ + } while (0) + + +/* fini psect is 8 aligned */ + +#define DTOR_LIST_BEGIN \ + asm (DTORS_SECTION_ASM_OP); \ + func_ptr __DTOR_LIST__[2] = { (func_ptr) (-1), 0 }; + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ + +#undef ASM_OUTPUT_DESTRUCTOR +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + fini_section (); \ + fprintf (FILE, "%s\t ", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",0\n"); \ + } while (0) + + +/* On clix crt1.o first calls init code and then sets environ and a valid + chrclass. Unfortunately stdio routines bomb with unset chrclass. + Therefore we set chrclass prior to calling global constructors. */ + +#undef DO_GLOBAL_CTORS_BODY +#define DO_GLOBAL_CTORS_BODY \ +do { \ + func_ptr *p, *beg = alloca (0); \ + _setchrclass (0); \ + for (p = beg; *p; p+=2) \ + ; \ + while (p != beg) \ + { p-= 2; (*p) (); } \ +} while (0) + + +#undef DO_GLOBAL_DTORS_BODY +#define DO_GLOBAL_DTORS_BODY \ + func_ptr *f = &__DTOR_LIST__[2]; /* 0,1 contains -1,0 */ \ + int n = 0; \ + while (*f) \ + { \ + f+= 2; /* skip over alignment 0 */ \ + n++; \ + } \ + f -= 2; \ + while (--n >= 0) \ + { \ + (*f) (); \ + f-= 2; /* skip over alignment 0 */ \ + } + + diff --git a/gcc/config/clipper/x-clix b/gcc/config/clipper/x-clix new file mode 100755 index 0000000..155161f --- /dev/null +++ b/gcc/config/clipper/x-clix @@ -0,0 +1 @@ +ALLOCA = alloca.o diff --git a/gcc/config/clipper/xm-clix.h b/gcc/config/clipper/xm-clix.h new file mode 100755 index 0000000..726660d --- /dev/null +++ b/gcc/config/clipper/xm-clix.h @@ -0,0 +1,30 @@ +/* Config file for Clipper running Clix, system V. 3.2 clone */ + + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ + +#include "tm.h" + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* This machine uses IEEE floats. */ +/* #define HOST_FLOAT_FORMAT IEEE_FLOAT_FORMAT */ + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +/* isinf isn't there, but finite is. */ +#define isinf(x) (!finite(x)) + +#define USG |