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authorRangi <remy.oukaour+rangi42@gmail.com>2018-06-24 21:23:51 -0400
committerRangi <remy.oukaour+rangi42@gmail.com>2018-06-24 21:23:51 -0400
commite2fb7acac0e3c1d598021b52fc2583dd983321bc (patch)
treeea5922596ce167e5b0485ea3bacd65f43339ca60 /home/sram.asm
parent1a888f22004aec967d2b6049ede7e04b1815f956 (diff)
parent364854623267a8a39242243b0cdf80144e868642 (diff)
Merge branch 'master' of https://github.com/pret/pokecrystal
# Conflicts: # engine/items/mart.asm
Diffstat (limited to 'home/sram.asm')
-rw-r--r--home/sram.asm9
1 files changed, 3 insertions, 6 deletions
diff --git a/home/sram.asm b/home/sram.asm
index 4cfe14cf9..1b1a4f318 100644
--- a/home/sram.asm
+++ b/home/sram.asm
@@ -1,12 +1,11 @@
-GetSRAMBank:: ; 2fcb
+GetSRAMBank::
; load sram bank a
; if invalid bank, sram is disabled
cp NUM_SRAM_BANKS
jr c, OpenSRAM
jr CloseSRAM
-; 2fd1
-OpenSRAM:: ; 2fd1
+OpenSRAM::
; switch to sram bank a
push af
; latch clock data
@@ -19,9 +18,8 @@ OpenSRAM:: ; 2fd1
pop af
ld [MBC3SRamBank], a
ret
-; 2fe1
-CloseSRAM:: ; 2fe1
+CloseSRAM::
push af
ld a, SRAM_DISABLE
; reset clock latch for next time
@@ -30,4 +28,3 @@ CloseSRAM:: ; 2fe1
ld [MBC3SRamEnable], a
pop af
ret
-; 2fec