1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
OpenSRAM::
; if invalid bank, sram is disabled
cp NUM_SRAM_BANKS
jr c, .valid
if DEF(_DEBUG)
push af
push bc
ld b, 1
.loop
sla b
dec a
jr nz, .loop
ld a, BANK(sOpenedInvalidSRAM)
call OpenSRAM
ld a, [sOpenedInvalidSRAM]
or b
ld [sOpenedInvalidSRAM], a
pop bc
pop af
endc
jr CloseSRAM
.valid:
; switch to sram bank a
push af
; latch clock data
ld a, 1
ld [MBC3LatchClock], a
; enable sram/clock write
ld a, SRAM_ENABLE
ld [MBC3SRamEnable], a
; select sram bank
pop af
ld [MBC3SRamBank], a
ret
CloseSRAM::
push af
ld a, SRAM_DISABLE
; reset clock latch for next time
ld [MBC3LatchClock], a
; disable sram/clock write
ld [MBC3SRamEnable], a
pop af
ret
|
