diff options
| author | red031000 <rubenru09@aol.com> | 2020-05-12 21:07:57 +0100 |
|---|---|---|
| committer | red031000 <rubenru09@aol.com> | 2020-05-12 21:07:57 +0100 |
| commit | 1adb71560d0df08263a75ed6bb5e59124ba4d1d3 (patch) | |
| tree | b25a0204df19308806f3e22ceabcdb2ae73829ff | |
| parent | 630fc59f5d016b78aa01889796e985449bb9e39b (diff) | |
gx registers
| -rw-r--r-- | arm9/lib/include/registers.h | 25 | ||||
| -rw-r--r-- | arm9/lib/src/FX_cp.c | 8 |
2 files changed, 29 insertions, 4 deletions
diff --git a/arm9/lib/include/registers.h b/arm9/lib/include/registers.h index 32c97d01..d1cc7792 100644 --- a/arm9/lib/include/registers.h +++ b/arm9/lib/include/registers.h @@ -7,10 +7,19 @@ #include "types.h" +#define reg_GX_DISPCNT (*(REGType32v *)0x4000000) +#define reg_GX_DISPSTAT (*(REGType16v *)0x4000004) #define reg_GX_VCOUNT (*(REGType16v *)0x4000006) #define reg_G3X_DISP3DCNT (*(REGType16v *)0x4000060) +#define reg_GX_DISPCAPCNT (*(REGType32v *)0x4000064) +#define reg_GX_DISP_MMEM_FIFO (*(REGType32v *)0x4000068) +#define reg_GX_DISP_MMEM_FIFO_L (*(REGType16v *)0x4000068) +#define reg_GX_DISP_MMEM_FIFO_H (*(REGType16v *)0x400006a) +#define reg_GX_MASTER_BRIGHT (*(REGType16v *)0x400006c) +#define reg_GX_TVOUTCNT (*(REGType16v *)0x4000070) + #define reg_MI_DMA0SAD (*(REGType32v *)0x40000b0) #define reg_MI_DMA0DAD (*(REGType32v *)0x40000b4) #define reg_MI_DMA0CNT (*(REGType32v *)0x40000b8) @@ -37,6 +46,20 @@ #define reg_MI_MCCMD1 (*(REGType32v *)0x40001ac) #define reg_MI_EXMEMCNT (*(REGType16v *)0x4000204) +#define reg_GX_VRAMCNT (*(REGType32v *)0x4000240) +#define reg_GX_VRAMCNT_A (*(REGType8v *)0x4000240) +#define reg_GX_VRAMCNT_B (*(REGType8v *)0x4000241) +#define reg_GX_VRAMCNT_C (*(REGType8v *)0x4000242) +#define reg_GX_VRAMCNT_D (*(REGType8v *)0x4000243) +#define reg_GX_WVRAMCNT (*(REGType32v *)0x4000244) +#define reg_GX_VRAMCNT_E (*(REGType8v *)0x4000244) +#define reg_GX_VRAMCNT_F (*(REGType8v *)0x4000245) +#define reg_GX_VRAMCNT_G (*(REGType8v *)0x4000246) +#define reg_GX_VRAMCNT_WRAM (*(REGType8v *)0x4000247) +#define reg_GX_VRAM_HI_CNT (*(REGType16v *)0x4000248) +#define reg_GX_VRAMCNT_H (*(REGType8v *)0x4000248) +#define reg_GX_VRAMCNT_I (*(REGType8v *)0x4000249) + #define reg_CP_DIVCNT (*(REGType16v *)0x4000280) #define reg_CP_DIV_NUMER (*(REGType64v *)0x4000290) #define reg_CP_DIV_DENOM (*(REGType64v *)0x4000298) @@ -46,6 +69,8 @@ #define reg_CP_SQRT_RESULT (*(REGType32v *)0x40002B4) #define reg_CP_SQRT_PARAM (*(REGType64v *)0x40002B8) +#define reg_GX_POWCNT (*(REGType16v *)0x4000304) + #define reg_G3X_RDLINES_COUNT (*(const REGType16v *)0x4000320) #define reg_G3X_EDGE_COLOR_0 (*(REGType32v *)0x4000330) #define reg_G3X_EDGE_COLOR_0_L (*(REGType16v *)0x4000330) diff --git a/arm9/lib/src/FX_cp.c b/arm9/lib/src/FX_cp.c index 0c03f673..3b6e6c96 100644 --- a/arm9/lib/src/FX_cp.c +++ b/arm9/lib/src/FX_cp.c @@ -55,16 +55,16 @@ ARM_FUNC void FX_DivAsync(fx32 numerator, fx32 denominator){ ARM_FUNC fx32 FX_DivS32(fx32 numerator, fx32 denominator){ reg_CP_DIVCNT = 0x0; - *(REGType32 *)®_CP_DIV_NUMER = (u32)numerator; //32bit write for some reason + *(REGType32v *)®_CP_DIV_NUMER = (u32)numerator; //32bit write for some reason reg_CP_DIV_DENOM = (u32)denominator; while (reg_CP_DIVCNT & 0x8000); - return *(REGType32 *)®_CP_DIV_RESULT; + return *(REGType32v *)®_CP_DIV_RESULT; } ARM_FUNC fx32 FX_ModS32(fx32 num, fx32 mod){ reg_CP_DIVCNT = 0x0; - *(REGType32 *)®_CP_DIV_NUMER = (u32)num; //32bit write for some reason + *(REGType32v *)®_CP_DIV_NUMER = (u32)num; //32bit write for some reason reg_CP_DIV_DENOM = (u32)mod; while (reg_CP_DIVCNT & 0x8000); - return *(REGType32 *)®_CP_DIVREM_RESULT; + return *(REGType32v *)®_CP_DIVREM_RESULT; } |