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authorred031000 <rubenru09@aol.com>2021-08-16 18:11:59 +0100
committerred031000 <rubenru09@aol.com>2021-08-16 18:11:59 +0100
commit5eb6b79b7f664af76802e5765dfe1a301e3f85f7 (patch)
tree664456f97d6d0c0774f0d7ec05789c2dac490409
parentffb7a81a6ed6cfc4239285157938dbc2e4446ebc (diff)
d
-rw-r--r--arm9/arm9.lsf1
-rw-r--r--arm9/global.inc1
-rw-r--r--arm9/modules/04/asm/arm_04.s139
-rw-r--r--arm9/modules/04/asm/mod04_021DD82C.s145
4 files changed, 147 insertions, 139 deletions
diff --git a/arm9/arm9.lsf b/arm9/arm9.lsf
index 2eaaeb89..c7dbe13c 100644
--- a/arm9/arm9.lsf
+++ b/arm9/arm9.lsf
@@ -666,6 +666,7 @@ Overlay MODULE_04
Object mod04_021DCCC8.o
Object mod04_021DD36C.o
Object mod04_021DD6B0.o
+ Object mod04_021DD82C.o
Object arm_04.o
}
diff --git a/arm9/global.inc b/arm9/global.inc
index f3916409..450e43b9 100644
--- a/arm9/global.inc
+++ b/arm9/global.inc
@@ -6152,6 +6152,7 @@
.extern MOD04_021DD844
.extern MOD04_021DD860
.extern MOD04_021DD904
+.extern MOD04_021DD924
.extern MOD04_021DD944
.extern MOD04_021DD968
.extern MOD04_021DD984
diff --git a/arm9/modules/04/asm/arm_04.s b/arm9/modules/04/asm/arm_04.s
index 23fd3766..714a88a0 100644
--- a/arm9/modules/04/asm/arm_04.s
+++ b/arm9/modules/04/asm/arm_04.s
@@ -3,137 +3,6 @@
.section .text
.balign 4, 0
- arm_func_start MOD04_021DD82C
-MOD04_021DD82C: ; 0x021DD82C
- ldr ip, _021DD840 ; =MOD04_021DD904
- mov r1, r0
- mov r0, #5
- mov r2, #0
- bx ip
- .align 2, 0
-_021DD840: .word MOD04_021DD904
- arm_func_end MOD04_021DD82C
-
- arm_func_start MOD04_021DD844
-MOD04_021DD844: ; 0x021DD844
- ldr ip, _021DD85C ; =MOD04_021DD8E8
- mov r2, r1
- mov r1, r0
- mov r3, r2
- mov r0, #5
- bx ip
- .align 2, 0
-_021DD85C: .word MOD04_021DD8E8
- arm_func_end MOD04_021DD844
-
- arm_func_start MOD04_021DD860
-MOD04_021DD860: ; 0x021DD860
- ldr ip, _021DD870 ; =MOD04_021DD944
- mov r1, r0
- mov r0, #5
- bx ip
- .align 2, 0
-_021DD870: .word MOD04_021DD944
- arm_func_end MOD04_021DD860
-
- arm_func_start MOD04_021DD874
-MOD04_021DD874: ; 0x021DD874
- stmdb sp!, {r4, r5, r6, r7, r8, lr}
- ldr ip, _021DD8E0 ; =UNK04_02210514
- mov r4, r2
- mov r7, r3
- mov r5, r1
- ldr r2, [sp, #0x18]
- ldr r3, [ip]
- mov r1, r7
- mov r8, r0
- blx r3
- movs r6, r0
- moveq r0, #0
- ldmeqia sp!, {r4, r5, r6, r7, r8, pc}
- cmp r5, #0
- beq _021DD8D8
- mov r0, r5
- mov r1, r6
- mov r2, r7
- bl MI_CpuCopy8
- ldr r1, _021DD8E4 ; =UNK04_02210510
- mov r0, r8
- ldr r3, [r1]
- mov r1, r5
- mov r2, r4
- blx r3
-_021DD8D8:
- mov r0, r6
- ldmia sp!, {r4, r5, r6, r7, r8, pc}
- .align 2, 0
-_021DD8E0: .word UNK04_02210514
-_021DD8E4: .word UNK04_02210510
- arm_func_end MOD04_021DD874
-
- arm_func_start MOD04_021DD8E8
-MOD04_021DD8E8: ; 0x021DD8E8
- stmdb sp!, {lr}
- sub sp, sp, #4
- mov ip, #0x20
- str ip, [sp]
- bl MOD04_021DD874
- add sp, sp, #4
- ldmfd sp!, {pc}
- arm_func_end MOD04_021DD8E8
-
- arm_func_start MOD04_021DD904
-MOD04_021DD904: ; 0x021DD904
- stmdb sp!, {lr}
- sub sp, sp, #4
- ldr r3, _021DD920 ; =UNK04_02210510
- ldr r3, [r3]
- blx r3
- add sp, sp, #4
- ldmfd sp!, {pc}
- .align 2, 0
-_021DD920: .word UNK04_02210510
- arm_func_end MOD04_021DD904
-
- arm_func_start MOD04_021DD924
-MOD04_021DD924: ; 0x021DD924
- stmdb sp!, {lr}
- sub sp, sp, #4
- ldr r3, _021DD940 ; =UNK04_02210514
- ldr r3, [r3]
- blx r3
- add sp, sp, #4
- ldmfd sp!, {pc}
- .align 2, 0
-_021DD940: .word UNK04_02210514
- arm_func_end MOD04_021DD924
-
- arm_func_start MOD04_021DD944
-MOD04_021DD944: ; 0x021DD944
- stmdb sp!, {lr}
- sub sp, sp, #4
- ldr r3, _021DD964 ; =UNK04_02210514
- mov r2, #0x20
- ldr r3, [r3]
- blx r3
- add sp, sp, #4
- ldmfd sp!, {pc}
- .align 2, 0
-_021DD964: .word UNK04_02210514
- arm_func_end MOD04_021DD944
-
- arm_func_start MOD04_021DD968
-MOD04_021DD968: ; 0x021DD968
- ldr r3, _021DD97C ; =UNK04_02210514
- ldr r2, _021DD980 ; =UNK04_02210510
- str r0, [r3]
- str r1, [r2]
- bx lr
- .align 2, 0
-_021DD97C: .word UNK04_02210514
-_021DD980: .word UNK04_02210510
- arm_func_end MOD04_021DD968
-
arm_func_start MOD04_021DD984
MOD04_021DD984: ; 0x021DD984
stmdb sp!, {lr}
@@ -57882,14 +57751,6 @@ UNK04_0220FBA4: ; 0x0220FBA4
.section .bss
- .global UNK04_02210510
-UNK04_02210510: ; 0x02210510
- .space 0x4
-
- .global UNK04_02210514
-UNK04_02210514: ; 0x02210514
- .space 0x4
-
.global UNK04_02210518
UNK04_02210518: ; 0x02210518
.space 0x4
diff --git a/arm9/modules/04/asm/mod04_021DD82C.s b/arm9/modules/04/asm/mod04_021DD82C.s
new file mode 100644
index 00000000..7c697698
--- /dev/null
+++ b/arm9/modules/04/asm/mod04_021DD82C.s
@@ -0,0 +1,145 @@
+ .include "asm/macros.inc"
+ .include "global.inc"
+ .section .text
+ .balign 4, 0
+
+ arm_func_start MOD04_021DD82C
+MOD04_021DD82C: ; 0x021DD82C
+ ldr ip, _021DD840 ; =MOD04_021DD904
+ mov r1, r0
+ mov r0, #5
+ mov r2, #0
+ bx ip
+ .align 2, 0
+_021DD840: .word MOD04_021DD904
+ arm_func_end MOD04_021DD82C
+
+ arm_func_start MOD04_021DD844
+MOD04_021DD844: ; 0x021DD844
+ ldr ip, _021DD85C ; =MOD04_021DD8E8
+ mov r2, r1
+ mov r1, r0
+ mov r3, r2
+ mov r0, #5
+ bx ip
+ .align 2, 0
+_021DD85C: .word MOD04_021DD8E8
+ arm_func_end MOD04_021DD844
+
+ arm_func_start MOD04_021DD860
+MOD04_021DD860: ; 0x021DD860
+ ldr ip, _021DD870 ; =MOD04_021DD944
+ mov r1, r0
+ mov r0, #5
+ bx ip
+ .align 2, 0
+_021DD870: .word MOD04_021DD944
+ arm_func_end MOD04_021DD860
+
+ arm_func_start MOD04_021DD874
+MOD04_021DD874: ; 0x021DD874
+ stmdb sp!, {r4, r5, r6, r7, r8, lr}
+ ldr ip, _021DD8E0 ; =UNK04_02210514
+ mov r4, r2
+ mov r7, r3
+ mov r5, r1
+ ldr r2, [sp, #0x18]
+ ldr r3, [ip]
+ mov r1, r7
+ mov r8, r0
+ blx r3
+ movs r6, r0
+ moveq r0, #0
+ ldmeqia sp!, {r4, r5, r6, r7, r8, pc}
+ cmp r5, #0
+ beq _021DD8D8
+ mov r0, r5
+ mov r1, r6
+ mov r2, r7
+ bl MI_CpuCopy8
+ ldr r1, _021DD8E4 ; =UNK04_02210510
+ mov r0, r8
+ ldr r3, [r1]
+ mov r1, r5
+ mov r2, r4
+ blx r3
+_021DD8D8:
+ mov r0, r6
+ ldmia sp!, {r4, r5, r6, r7, r8, pc}
+ .align 2, 0
+_021DD8E0: .word UNK04_02210514
+_021DD8E4: .word UNK04_02210510
+ arm_func_end MOD04_021DD874
+
+ arm_func_start MOD04_021DD8E8
+MOD04_021DD8E8: ; 0x021DD8E8
+ stmdb sp!, {lr}
+ sub sp, sp, #4
+ mov ip, #0x20
+ str ip, [sp]
+ bl MOD04_021DD874
+ add sp, sp, #4
+ ldmfd sp!, {pc}
+ arm_func_end MOD04_021DD8E8
+
+ arm_func_start MOD04_021DD904
+MOD04_021DD904: ; 0x021DD904
+ stmdb sp!, {lr}
+ sub sp, sp, #4
+ ldr r3, _021DD920 ; =UNK04_02210510
+ ldr r3, [r3]
+ blx r3
+ add sp, sp, #4
+ ldmfd sp!, {pc}
+ .align 2, 0
+_021DD920: .word UNK04_02210510
+ arm_func_end MOD04_021DD904
+
+ arm_func_start MOD04_021DD924
+MOD04_021DD924: ; 0x021DD924
+ stmdb sp!, {lr}
+ sub sp, sp, #4
+ ldr r3, _021DD940 ; =UNK04_02210514
+ ldr r3, [r3]
+ blx r3
+ add sp, sp, #4
+ ldmfd sp!, {pc}
+ .align 2, 0
+_021DD940: .word UNK04_02210514
+ arm_func_end MOD04_021DD924
+
+ arm_func_start MOD04_021DD944
+MOD04_021DD944: ; 0x021DD944
+ stmdb sp!, {lr}
+ sub sp, sp, #4
+ ldr r3, _021DD964 ; =UNK04_02210514
+ mov r2, #0x20
+ ldr r3, [r3]
+ blx r3
+ add sp, sp, #4
+ ldmfd sp!, {pc}
+ .align 2, 0
+_021DD964: .word UNK04_02210514
+ arm_func_end MOD04_021DD944
+
+ arm_func_start MOD04_021DD968
+MOD04_021DD968: ; 0x021DD968
+ ldr r3, _021DD97C ; =UNK04_02210514
+ ldr r2, _021DD980 ; =UNK04_02210510
+ str r0, [r3]
+ str r1, [r2]
+ bx lr
+ .align 2, 0
+_021DD97C: .word UNK04_02210514
+_021DD980: .word UNK04_02210510
+ arm_func_end MOD04_021DD968
+
+ .section .bss
+
+ .global UNK04_02210510
+UNK04_02210510: ; 0x02210510
+ .space 0x4
+
+ .global UNK04_02210514
+UNK04_02210514: ; 0x02210514
+ .space 0x4