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authorEgor Ananyin <ananinegor@gmail.com>2020-06-12 20:23:15 +0300
committerEgor Ananyin <ananinegor@gmail.com>2020-06-12 20:23:15 +0300
commit870046733d4b15ee55566114aad3367dbe09e37d (patch)
treee54bdb422be9e8c10e3af74d36b421fed3679721 /arm7/lib
parente508916babf251f7ed4c26f45964cdecf20f00ce (diff)
Decompile MI_dma.c
Diffstat (limited to 'arm7/lib')
-rw-r--r--arm7/lib/include/MI_dma.h30
-rw-r--r--arm7/lib/src/MI_dma.c36
2 files changed, 66 insertions, 0 deletions
diff --git a/arm7/lib/include/MI_dma.h b/arm7/lib/include/MI_dma.h
new file mode 100644
index 00000000..4bae3663
--- /dev/null
+++ b/arm7/lib/include/MI_dma.h
@@ -0,0 +1,30 @@
+#ifndef GUARD_MI_DMA_H
+#define GUARD_MI_DMA_H
+
+#include "nitro/types.h"
+
+#define REG_ADDR_DMA0SAD 0x040000b0
+
+#define DMA_DEST_INC 0x0000
+#define DMA_DEST_DEC 0x0020
+#define DMA_DEST_FIXED 0x0040
+#define DMA_DEST_RELOAD 0x0060
+#define DMA_SRC_INC 0x0000
+#define DMA_SRC_DEC 0x0080
+#define DMA_SRC_FIXED 0x0100
+#define DMA_REPEAT 0x0200
+#define DMA_16BIT 0x0000
+#define DMA_32BIT 0x0400
+#define DMA_DREQ_ON 0x0800
+#define DMA_START_NOW 0x0000
+#define DMA_START_VBLANK 0x1000
+#define DMA_START_HBLANK 0x2000
+#define DMA_START_SPECIAL 0x3000
+#define DMA_START_MASK 0x3000
+#define DMA_INTR_ENABLE 0x4000
+#define DMA_ENABLE 0x8000
+
+void MI_StopDma(u32 channel);
+void MI_WaitDma(u32 channel);
+
+#endif
diff --git a/arm7/lib/src/MI_dma.c b/arm7/lib/src/MI_dma.c
new file mode 100644
index 00000000..fc2ff0c9
--- /dev/null
+++ b/arm7/lib/src/MI_dma.c
@@ -0,0 +1,36 @@
+#include "function_target.h"
+#include "MI_dma.h"
+#include "OS_system.h"
+
+ARM_FUNC void MI_WaitDma(u32 channel) {
+ OSIntrMode mode = OS_DisableInterrupts();
+ vu32 * addr = (vu32 *)(REG_ADDR_DMA0SAD + (channel * 3 + 2) * 4);
+ while(addr[0] & 0x80000000) ;
+ if (channel == 0) {
+ addr = (vu32 *)(REG_ADDR_DMA0SAD + channel * 12);
+ addr[0] = 0;
+ addr[1] = 0;
+ addr[2] = 0x81400001;
+ }
+ mode = OS_RestoreInterrupts(mode);
+}
+
+ARM_FUNC void MI_StopDma(u32 channel) {
+ OSIntrMode mode = OS_DisableInterrupts();
+ vu16 * addr = (vu16 *)(REG_ADDR_DMA0SAD + (channel * 6 + 5) * 2);
+ addr[0] &= ~(DMA_START_MASK | DMA_REPEAT);
+ addr[0] &= ~DMA_ENABLE;
+ {
+ s32 dummy = addr[0];
+ }
+ {
+ s32 dummy = addr[0];
+ }
+ if (channel == 0) {
+ vu32 * addr32 = (vu32 *)(REG_ADDR_DMA0SAD + channel * 12);
+ addr32[0] = 0;
+ addr32[1] = 0;
+ addr32[2] = 0x81400001;
+ }
+ mode = OS_RestoreInterrupts(mode);
+}