diff options
author | red031000 <rubenru09@aol.com> | 2020-04-29 02:41:21 +0100 |
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committer | red031000 <rubenru09@aol.com> | 2020-04-29 02:41:21 +0100 |
commit | 2b7ae1f75a109553df78c9f8929e6854ea73b62e (patch) | |
tree | 59f8a3a19db20397468658b2cf03cd4f6ba17100 /arm9/asm/OS_system.s | |
parent | e56eab5ba606e2095e4565bcfab14b25f9ff655d (diff) |
split OS_arm9.s
Diffstat (limited to 'arm9/asm/OS_system.s')
-rw-r--r-- | arm9/asm/OS_system.s | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/arm9/asm/OS_system.s b/arm9/asm/OS_system.s new file mode 100644 index 00000000..3801b8e7 --- /dev/null +++ b/arm9/asm/OS_system.s @@ -0,0 +1,77 @@ + .include "asm/macros.inc" + .include "global.inc" + + .text + + arm_func_start OS_EnableInterrupts +OS_EnableInterrupts: ; 0x020CD2FC + mrs r0, cpsr + bic r1, r0, #0x80 + msr cpsr_c, r1 + and r0, r0, #0x80 + bx lr + + arm_func_start OS_DisableInterrupts +OS_DisableInterrupts: + mrs r0, cpsr + orr r1, r0, #0x80 + msr cpsr_c, r1 + and r0, r0, #0x80 + bx lr + + arm_func_start OS_RestoreInterrupts +OS_RestoreInterrupts: + mrs r1, cpsr + bic r2, r1, #0x80 + orr r2, r2, r0 + msr cpsr_c, r2 + and r0, r1, #0x80 + bx lr + + arm_func_start OS_DisableInterrupts_IrqAndFiq +OS_DisableInterrupts_IrqAndFiq: ; 0x020CD33C + mrs r0, cpsr + orr r1, r0, #0xc0 + msr cpsr_c, r1 + and r0, r0, #0xc0 + bx lr + + arm_func_start OS_RestoreInterrupts_IrqAndFiq +OS_RestoreInterrupts_IrqAndFiq: ; 0x020CD350 + mrs r1, cpsr + bic r2, r1, #0xc0 + orr r2, r2, r0 + msr cpsr_c, r2 + and r0, r1, #0xc0 + bx lr + + arm_func_start OS_GetCpsrIrq +OS_GetCpsrIrq: ; 0x020CD368 + mrs r0, cpsr + and r0, r0, #0x80 + bx lr + + arm_func_start OS_GetProcMode +OS_GetProcMode: ; 0x020CD374 + mrs r0, cpsr + and r0, r0, #0x1f + bx lr + + arm_func_start OS_SpinWait +OS_SpinWait: + subs r0, r0, #0x4 + bhs OS_SpinWait + bx lr + + arm_func_start OS_WaitVBlankIntr +OS_WaitVBlankIntr: ; 0x020CD38C + stmdb sp!, {lr} + sub sp, sp, #0x4 + mov r0, #0x1 + blx SVC_WaitByLoop + mov r0, #0x1 + mov r1, r0 + bl OS_WaitIrq + add sp, sp, #0x4 + ldmia sp!, {lr} + bx lr |