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authorPikalaxALT <pikalaxalt@gmail.com>2021-06-05 16:55:46 -0400
committerPikalaxALT <pikalaxalt@gmail.com>2021-06-05 16:55:46 -0400
commitc87b617058767519480ef2d19e233fe0e99ca01d (patch)
tree690c7ca357b58415f85c754048e90b1e693df945 /arm9/lib/include/registers.h
parent0ae4f320d929e4d8914002836055c1aad35d5ce3 (diff)
Fix GX_vramcnt symbol names
Diffstat (limited to 'arm9/lib/include/registers.h')
-rw-r--r--arm9/lib/include/registers.h71
1 files changed, 68 insertions, 3 deletions
diff --git a/arm9/lib/include/registers.h b/arm9/lib/include/registers.h
index 27796cf7..b4fd8ce7 100644
--- a/arm9/lib/include/registers.h
+++ b/arm9/lib/include/registers.h
@@ -350,12 +350,11 @@
#define REG_OS_IE_VE_SHIFT 2
#define REG_OS_IE_T0_SHIFT 3
#define REG_OS_IE_T1_SHIFT 4
+#define REG_OS_IE_T2_SHIFT 5
+#define REG_OS_IE_T3_SHIFT 6
#define REG_OS_IE_IFN_SHIFT 18
#define REG_OS_IE_MC_SHIFT 19
-#define REG_OS_TM0CNT_H_I_MASK 0x0040
-#define REG_OS_TM0CNT_H_E_MASK 0x0080
-
#define REG_PAD_KEYINPUT_L_SHIFT 9
#define REG_PAD_KEYINPUT_L_SIZE 1
#define REG_PAD_KEYINPUT_L_MASK 0x0200
@@ -1001,4 +1000,70 @@
#define REG_G2S_DB_BG3OFS_HOFFSET_SIZE 9
#define REG_G2S_DB_BG3OFS_HOFFSET_MASK 0x000001ff
+// Timer control
+
+#define REG_OS_TM0CNT_L_TIMER0CNT_SHIFT 0
+#define REG_OS_TM0CNT_L_TIMER0CNT_SIZE 16
+#define REG_OS_TM0CNT_L_TIMER0CNT_MASK 0xffff
+
+#define REG_OS_TM0CNT_H_E_SHIFT 7
+#define REG_OS_TM0CNT_H_E_SIZE 1
+#define REG_OS_TM0CNT_H_E_MASK 0x0080
+
+#define REG_OS_TM0CNT_H_I_SHIFT 6
+#define REG_OS_TM0CNT_H_I_SIZE 1
+#define REG_OS_TM0CNT_H_I_MASK 0x0040
+
+#define REG_OS_TM0CNT_H_PS_SHIFT 0
+#define REG_OS_TM0CNT_H_PS_SIZE 2
+#define REG_OS_TM0CNT_H_PS_MASK 0x0003
+
+#define REG_OS_TM1CNT_L_TIMER0CNT_SHIFT 0
+#define REG_OS_TM1CNT_L_TIMER0CNT_SIZE 16
+#define REG_OS_TM1CNT_L_TIMER0CNT_MASK 0xffff
+
+#define REG_OS_TM1CNT_H_E_SHIFT 7
+#define REG_OS_TM1CNT_H_E_SIZE 1
+#define REG_OS_TM1CNT_H_E_MASK 0x0080
+
+#define REG_OS_TM1CNT_H_I_SHIFT 6
+#define REG_OS_TM1CNT_H_I_SIZE 1
+#define REG_OS_TM1CNT_H_I_MASK 0x0040
+
+#define REG_OS_TM1CNT_H_PS_SHIFT 0
+#define REG_OS_TM1CNT_H_PS_SIZE 2
+#define REG_OS_TM1CNT_H_PS_MASK 0x0003
+
+#define REG_OS_TM2CNT_L_TIMER0CNT_SHIFT 0
+#define REG_OS_TM2CNT_L_TIMER0CNT_SIZE 16
+#define REG_OS_TM2CNT_L_TIMER0CNT_MASK 0xffff
+
+#define REG_OS_TM2CNT_H_E_SHIFT 7
+#define REG_OS_TM2CNT_H_E_SIZE 1
+#define REG_OS_TM2CNT_H_E_MASK 0x0080
+
+#define REG_OS_TM2CNT_H_I_SHIFT 6
+#define REG_OS_TM2CNT_H_I_SIZE 1
+#define REG_OS_TM2CNT_H_I_MASK 0x0040
+
+#define REG_OS_TM2CNT_H_PS_SHIFT 0
+#define REG_OS_TM2CNT_H_PS_SIZE 2
+#define REG_OS_TM2CNT_H_PS_MASK 0x0003
+
+#define REG_OS_TM3CNT_L_TIMER0CNT_SHIFT 0
+#define REG_OS_TM3CNT_L_TIMER0CNT_SIZE 16
+#define REG_OS_TM3CNT_L_TIMER0CNT_MASK 0xffff
+
+#define REG_OS_TM3CNT_H_E_SHIFT 7
+#define REG_OS_TM3CNT_H_E_SIZE 1
+#define REG_OS_TM3CNT_H_E_MASK 0x0080
+
+#define REG_OS_TM3CNT_H_I_SHIFT 6
+#define REG_OS_TM3CNT_H_I_SIZE 1
+#define REG_OS_TM3CNT_H_I_MASK 0x0040
+
+#define REG_OS_TM3CNT_H_PS_SHIFT 0
+#define REG_OS_TM3CNT_H_PS_SIZE 2
+#define REG_OS_TM3CNT_H_PS_MASK 0x0003
+
#endif //POKEDIAMOND_ARM9_REGISTERS_H