summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arm9/lib/include/consts.h14
-rw-r--r--arm9/lib/include/fx.h18
-rw-r--r--arm9/lib/include/registers.h55
-rw-r--r--arm9/lib/src/FX_cp.c48
-rw-r--r--arm9/lib/src/FX_vec.c44
5 files changed, 102 insertions, 77 deletions
diff --git a/arm9/lib/include/consts.h b/arm9/lib/include/consts.h
index c37d6269..b99b4148 100644
--- a/arm9/lib/include/consts.h
+++ b/arm9/lib/include/consts.h
@@ -6,6 +6,7 @@
#define POKEDIAMOND_CONSTS_H
#include "mmap.h"
+#include "registers.h"
#define HW_PSR_CPU_MODE_MASK 0x1f // CPU mode
@@ -13,19 +14,6 @@
#define HW_PSR_DISABLE_IRQ 0x80 // Disable IRQ
#define HW_PSR_DISABLE_IRQ_FIQ 0xc0 // Disable FIQ and IRQ
-#define HW_REG_BASE 0x04000000
-#define REG_VCOUNT_OFFSET 0x006
-#define REG_VCOUNT_ADDR (HW_REG_BASE + REG_VCOUNT_OFFSET)
-#define reg_GX_VCOUNT (*(REGType16v *)REG_VCOUNT_ADDR)
-
-#define REG_KEYINPUT_OFFSET 0x130
-#define REG_KEYINPUT_ADDR (HW_REG_BASE + REG_KEYINPUT_OFFSET)
-#define reg_PAD_KEYINPUT (*(REGType16v *)REG_KEYINPUT_ADDR)
-
-#define REG_GXSTAT_OFFSET 0x600
-#define REG_GXSTAT_ADDR (HW_REG_BASE + REG_GXSTAT_OFFSET)
-#define reg_G3X_GXSTAT (*(REGType32v *)REG_GXSTAT_ADDR)
-
#define HW_C6_PR_4KB 0x16
#define HW_C6_PR_8KB 0x18
#define HW_C6_PR_16KB 0x1a
diff --git a/arm9/lib/include/fx.h b/arm9/lib/include/fx.h
index 7e74d079..b1c3aa88 100644
--- a/arm9/lib/include/fx.h
+++ b/arm9/lib/include/fx.h
@@ -46,24 +46,6 @@ typedef s64 fx64c;
#define FX64C_INT_ABS(x) FX_INT_ABS(FX64C, x)
#define FX64C_FRAC(x) FX_FRAC(FX64C, x)
-
-#define HW_REG_DIVCNT 0x04000280
-#define HW_REG_DIV_NUMER 0x04000290
-#define HW_REG_DIV_DENOM 0x04000298
-#define HW_REG_DIV_RESULT 0x040002A0
-#define HW_REG_DIVREM_RESULT 0x040002A8
-
-#define HW_REG_SQRTCNT 0x040002B0
-#define HW_REG_SQRT_RESULT 0x040002B4
-#define HW_REG_SQRT_PARAM 0x040002B8
-
-#define SETREG16(x, y) ((*(vu16 *)x) = y)
-#define SETREG32(x, y) ((*(vu32 *)x) = y)
-#define SETREG64(x, y) ((*(vu64 *)x) = y)
-#define READREG16(x) (*(vu16 *)x)
-#define READREG32(x) (*(vu32 *)x)
-#define READREG64(x) (*(vu64 *)x)
-
#define FX32_MUL(a, b) ((fx32)(((fx64)a * b) >> FX32_INT_SHIFT))
#define FX32_MUL_ADD_MUL(a, b, c, d) ((fx32)(((fx64)a * b + (fx64)c * d) >> FX32_INT_SHIFT))
//the extra term here is for rounding
diff --git a/arm9/lib/include/registers.h b/arm9/lib/include/registers.h
new file mode 100644
index 00000000..45b36334
--- /dev/null
+++ b/arm9/lib/include/registers.h
@@ -0,0 +1,55 @@
+//
+// Created by red031000 on 2020-05-06.
+//
+
+#ifndef POKEDIAMOND_REGISTERS_H
+#define POKEDIAMOND_REGISTERS_H
+
+#include "types.h"
+
+#define HW_REG_BASE 0x04000000
+#define REG_VCOUNT_OFFSET 0x006
+#define REG_VCOUNT_ADDR (HW_REG_BASE + REG_VCOUNT_OFFSET)
+#define reg_GX_VCOUNT (*(REGType16v *)REG_VCOUNT_ADDR)
+
+#define REG_KEYINPUT_OFFSET 0x130
+#define REG_KEYINPUT_ADDR (HW_REG_BASE + REG_KEYINPUT_OFFSET)
+#define reg_PAD_KEYINPUT (*(REGType16v *)REG_KEYINPUT_ADDR)
+
+#define REG_DIVCNT_OFFSET 0x280
+#define REG_DIVCNT_ADDR (HW_REG_BASE + REG_DIVCNT_OFFSET)
+#define reg_CP_DIVCNT (*(REGType16v *)REG_DIVCNT_ADDR)
+
+#define REG_DIV_NUMER_OFFSET 0x290
+#define REG_DIV_NUMER_ADDR (HW_REG_BASE + REG_DIV_NUMER_OFFSET)
+#define reg_CP_DIV_NUMER (*(REGType64v *)REG_DIV_NUMER_ADDR)
+
+#define REG_DIV_DENOM_OFFSET 0x298
+#define REG_DIV_DENOM_ADDR (HW_REG_BASE + REG_DIV_DENOM_OFFSET)
+#define reg_CP_DIV_DENOM (*(REGType64v *)REG_DIV_DENOM_ADDR)
+
+#define REG_DIV_RESULT_OFFSET 0x2A0
+#define REG_DIV_RESULT_ADDR (HW_REG_BASE + REG_DIV_RESULT_OFFSET)
+#define reg_CP_DIV_RESULT (*(REGType64v *)REG_DIV_RESULT_ADDR)
+
+#define REG_DIVREM_RESULT_OFFSET 0x2A8
+#define REG_DIVREM_RESULT_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_OFFSET)
+#define reg_CP_DIVREM_RESULT (*(REGType64v *)REG_DIVREM_RESULT_ADDR)
+
+#define REG_SQRTCNT_OFFSET 0x2B0
+#define REG_SQRTCNT_ADDR (HW_REG_BASE + REG_SQRTCNT_OFFSET)
+#define reg_CP_SQRTCNT (*(REGType16v *)REG_SQRTCNT_ADDR)
+
+#define REG_SQRT_RESULT_OFFSET 0x2B4
+#define REG_SQRT_RESULT_ADDR (HW_REG_BASE + REG_SQRT_RESULT_OFFSET)
+#define reg_CP_SQRT_RESULT (*(REGType32v *)REG_SQRT_RESULT_ADDR)
+
+#define REG_SQRT_PARAM_OFFSET 0x2B8
+#define REG_SQRT_PARAM_ADDR (HW_REG_BASE + REG_SQRT_PARAM_OFFSET)
+#define reg_CP_SQRT_PARAM (*(REGType64v *)REG_SQRT_PARAM_ADDR)
+
+#define REG_GXSTAT_OFFSET 0x600
+#define REG_GXSTAT_ADDR (HW_REG_BASE + REG_GXSTAT_OFFSET)
+#define reg_G3X_GXSTAT (*(REGType32v *)REG_GXSTAT_ADDR)
+
+#endif //POKEDIAMOND_REGISTERS_H
diff --git a/arm9/lib/src/FX_cp.c b/arm9/lib/src/FX_cp.c
index 2ca9d720..08443dc8 100644
--- a/arm9/lib/src/FX_cp.c
+++ b/arm9/lib/src/FX_cp.c
@@ -16,8 +16,8 @@ ARM_FUNC fx32 FX_Inv(fx32 x){
ARM_FUNC fx32 FX_Sqrt(fx32 x){
if (x > 0)
{
- SETREG16(HW_REG_SQRTCNT, 0x1);
- SETREG64(HW_REG_SQRT_PARAM, (fx64)x << 32);
+ reg_CP_SQRTCNT = 0x1;
+ reg_CP_SQRT_PARAM = (fx64)x << 32;
return FX_GetSqrtResult();
}
else
@@ -27,44 +27,44 @@ ARM_FUNC fx32 FX_Sqrt(fx32 x){
}
ARM_FUNC fx64c FX_GetDivResultFx64c(){
- while (READREG16(HW_REG_DIVCNT) & 0x8000);
- return READREG64(HW_REG_DIV_RESULT);
+ while (reg_CP_DIVCNT & 0x8000);
+ return reg_CP_DIV_RESULT;
}
ARM_FUNC fx32 FX_GetDivResult(){
- while (READREG16(HW_REG_DIVCNT) & 0x8000);
- return (READREG64(HW_REG_DIV_RESULT) + (1 << (0x14 - 1))) >> 0x14;
+ while (reg_CP_DIVCNT & 0x8000);
+ return (reg_CP_DIV_RESULT + (1 << (0x14 - 1))) >> 0x14;
}
ARM_FUNC void FX_InvAsync(fx32 x){
- SETREG16(HW_REG_DIVCNT, 0x1);
- SETREG64(HW_REG_DIV_NUMER, (fx64)0x00001000 << 32);
- SETREG64(HW_REG_DIV_DENOM, (u32)x);
+ reg_CP_DIVCNT = 0x1;
+ reg_CP_DIV_NUMER = (fx64)0x00001000 << 32;
+ reg_CP_DIV_DENOM = (u32)x;
}
ARM_FUNC fx32 FX_GetSqrtResult(){
- while (READREG16(HW_REG_SQRTCNT) & 0x8000);
- return (READREG32(HW_REG_SQRT_RESULT) + (1 << (0xA - 1))) >> 0xA;
+ while (reg_CP_SQRTCNT & 0x8000);
+ return (reg_CP_SQRT_RESULT + (1 << (0xA - 1))) >> 0xA;
}
ARM_FUNC void FX_DivAsync(fx32 numerator, fx32 denominator){
- SETREG16(HW_REG_DIVCNT, 0x1);
- SETREG64(HW_REG_DIV_NUMER, (fx64)numerator << 32);
- SETREG64(HW_REG_DIV_DENOM, (u32)denominator);
+ reg_CP_DIVCNT = 0x1;
+ reg_CP_DIV_NUMER = (fx64)numerator << 32;
+ reg_CP_DIV_DENOM = (u32)denominator;
}
ARM_FUNC fx32 FX_DivS32(fx32 numerator, fx32 denominator){
- SETREG16(HW_REG_DIVCNT, 0x0);
- SETREG32(HW_REG_DIV_NUMER, (u32)numerator); //32bit write for some reason
- SETREG64(HW_REG_DIV_DENOM, (u32)denominator);
- while (READREG16(HW_REG_DIVCNT) & 0x8000);
- return READREG32(HW_REG_DIV_RESULT);
+ reg_CP_DIVCNT = 0x0;
+ *(REGType32 *)REG_DIV_NUMER_ADDR = (u32)numerator; //32bit write for some reason
+ reg_CP_DIV_DENOM = (u32)denominator;
+ while (reg_CP_DIVCNT & 0x8000);
+ return *(REGType32 *)REG_DIV_RESULT_ADDR;
}
ARM_FUNC fx32 FX_ModS32(fx32 num, fx32 mod){
- SETREG16(HW_REG_DIVCNT, 0x0);
- SETREG32(HW_REG_DIV_NUMER, (u32)num); //32bit write for some reason
- SETREG64(HW_REG_DIV_DENOM, (u32)mod);
- while (READREG16(HW_REG_DIVCNT) & 0x8000);
- return READREG32(HW_REG_DIVREM_RESULT);
+ reg_CP_DIVCNT = 0x0;
+ *(REGType32 *)REG_DIV_NUMER_ADDR = (u32)num; //32bit write for some reason
+ reg_CP_DIV_DENOM = (u32)mod;
+ while (reg_CP_DIVCNT & 0x8000);
+ return *(REGType32 *)REG_DIVREM_RESULT_ADDR;
}
diff --git a/arm9/lib/src/FX_vec.c b/arm9/lib/src/FX_vec.c
index af36fe89..95805f33 100644
--- a/arm9/lib/src/FX_vec.c
+++ b/arm9/lib/src/FX_vec.c
@@ -55,10 +55,10 @@ ARM_FUNC fx32 VEC_Mag(struct Vecx32 *a){
fx64 l2 = (fx64)a->x * a->x;
l2 += (fx64)a->y * a->y;
l2 += (fx64)a->z * a->z;
- SETREG16(HW_REG_SQRTCNT, 0x1);
- SETREG64(HW_REG_SQRT_PARAM, l2 * 4);
- while (READREG16(HW_REG_SQRTCNT) & 0x8000); //wait for coprocessor to finish
- return ((fx32)READREG32(HW_REG_SQRT_RESULT) + 1) >> 1;
+ reg_CP_SQRTCNT = 0x1;
+ reg_CP_SQRT_PARAM = l2 * 4;
+ while (reg_CP_SQRTCNT & 0x8000); //wait for coprocessor to finish
+ return ((fx32)reg_CP_SQRT_RESULT + 1) >> 1;
}
ARM_FUNC void VEC_Normalize(struct Vecx32 *a, struct Vecx32 *dst){
@@ -66,15 +66,15 @@ ARM_FUNC void VEC_Normalize(struct Vecx32 *a, struct Vecx32 *dst){
l2 += (fx64)a->y * a->y;
l2 += (fx64)a->z * a->z;
//1/sqrt(l) is computed by calculating sqrt(l)*(1/l)
- SETREG16(HW_REG_DIVCNT, 0x2);
- SETREG64(HW_REG_DIV_NUMER, 0x0100000000000000);
- SETREG64(HW_REG_DIV_DENOM, l2);
- SETREG16(HW_REG_SQRTCNT, 0x1);
- SETREG64(HW_REG_SQRT_PARAM, l2 * 4);
- while (READREG16(HW_REG_SQRTCNT) & 0x8000); //wait for sqrt to finish
- fx32 sqrtresult = READREG32(HW_REG_SQRT_RESULT);
- while (READREG16(HW_REG_DIVCNT) & 0x8000); //wait for division to finish
- l2 = READREG64(HW_REG_DIV_RESULT);
+ reg_CP_DIVCNT = 0x2;
+ reg_CP_DIV_NUMER = 0x0100000000000000;
+ reg_CP_DIV_DENOM = l2;
+ reg_CP_SQRTCNT = 0x1;
+ reg_CP_SQRT_PARAM = l2 * 4;
+ while (reg_CP_SQRTCNT & 0x8000); //wait for sqrt to finish
+ fx32 sqrtresult = reg_CP_SQRT_RESULT;
+ while (reg_CP_DIVCNT & 0x8000); //wait for division to finish
+ l2 = reg_CP_DIV_RESULT;
l2 = sqrtresult * l2;
dst->x = (l2 * a->x + (1LL << (0x2D - 1))) >> 0x2D;
dst->y = (l2 * a->y + (1LL << (0x2D - 1))) >> 0x2D;
@@ -86,15 +86,15 @@ ARM_FUNC void VEC_Fx16Normalize(struct Vecx16 *a, struct Vecx16 *dst){
l2 += a->y * a->y;
l2 += a->z * a->z;
//1/sqrt(l) is computed by calculating sqrt(l)*(1/l)
- SETREG16(HW_REG_DIVCNT, 0x2);
- SETREG64(HW_REG_DIV_NUMER, 0x0100000000000000);
- SETREG64(HW_REG_DIV_DENOM, l2);
- SETREG16(HW_REG_SQRTCNT, 0x1);
- SETREG64(HW_REG_SQRT_PARAM, l2 * 4);
- while (READREG16(HW_REG_SQRTCNT) & 0x8000); //wait for sqrt to finish
- fx32 sqrtresult = READREG32(HW_REG_SQRT_RESULT);
- while (READREG16(HW_REG_DIVCNT) & 0x8000); //wait for division to finish
- l2 = READREG64(HW_REG_DIV_RESULT);
+ reg_CP_DIVCNT = 0x2;
+ reg_CP_DIV_NUMER = 0x0100000000000000;
+ reg_CP_DIV_DENOM = l2;
+ reg_CP_SQRTCNT = 0x1;
+ reg_CP_SQRT_PARAM = l2 * 4;
+ while (reg_CP_SQRTCNT & 0x8000); //wait for sqrt to finish
+ fx32 sqrtresult = reg_CP_SQRT_RESULT;
+ while (reg_CP_DIVCNT & 0x8000); //wait for division to finish
+ l2 = reg_CP_DIV_RESULT;
l2 = sqrtresult * l2;
dst->x = (l2 * a->x + (1LL << (0x2D - 1))) >> 0x2D;
dst->y = (l2 * a->y + (1LL << (0x2D - 1))) >> 0x2D;
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-02 17:51:47 +0000