diff options
Diffstat (limited to 'arm9/lib/include')
| -rw-r--r-- | arm9/lib/include/registers.h | 137 |
1 files changed, 127 insertions, 10 deletions
diff --git a/arm9/lib/include/registers.h b/arm9/lib/include/registers.h index d1cc7792..598ba3f9 100644 --- a/arm9/lib/include/registers.h +++ b/arm9/lib/include/registers.h @@ -11,6 +11,45 @@ #define reg_GX_DISPSTAT (*(REGType16v *)0x4000004) #define reg_GX_VCOUNT (*(REGType16v *)0x4000006) +#define reg_G2_BG0CNT (*(REGType16v *)0x4000008) +#define reg_G2_BG1CNT (*(REGType16v *)0x400000a) +#define reg_G2_BG2CNT (*(REGType16v *)0x400000c) +#define reg_G2_BG3CNT (*(REGType16v *)0x400000e) +#define reg_G2_BG0OFS (*(REGType32v *)0x4000010) +#define reg_G2_BG0HOFS (*(REGType16v *)0x4000010) +#define reg_G2_BG0VOFS (*(REGType16v *)0x4000012) +#define reg_G2_BG1OFS (*(REGType32v *)0x4000014) +#define reg_G2_BG1HOFS (*(REGType16v *)0x4000014) +#define reg_G2_BG1VOFS (*(REGType16v *)0x4000016) +#define reg_G2_BG2OFS (*(REGType32v *)0x4000018) +#define reg_G2_BG2HOFS (*(REGType16v *)0x4000018) +#define reg_G2_BG2VOFS (*(REGType16v *)0x400001a) +#define reg_G2_BG3OFS (*(REGType32v *)0x400001c) +#define reg_G2_BG3HOFS (*(REGType16v *)0x400001c) +#define reg_G2_BG3VOFS (*(REGType16v *)0x400001e) +#define reg_G2_BG2PA (*(REGType16v *)0x4000020) +#define reg_G2_BG2PB (*(REGType16v *)0x4000022) +#define reg_G2_BG2PC (*(REGType16v *)0x4000024) +#define reg_G2_BG2PD (*(REGType16v *)0x4000026) +#define reg_G2_BG2X (*(REGType32v *)0x4000028) +#define reg_G2_BG2Y (*(REGType32v *)0x400002c) +#define reg_G2_BG3PA (*(REGType16v *)0x4000030) +#define reg_G2_BG3PB (*(REGType16v *)0x4000032) +#define reg_G2_BG3PC (*(REGType16v *)0x4000034) +#define reg_G2_BG3PD (*(REGType16v *)0x4000036) +#define reg_G2_BG3X (*(REGType32v *)0x4000038) +#define reg_G2_BG3Y (*(REGType32v *)0x400003c) +#define reg_G2_WIN0H (*(REGType16v *)0x4000040) +#define reg_G2_WIN1H (*(REGType16v *)0x4000042) +#define reg_G2_WIN0V (*(REGType16v *)0x4000044) +#define reg_G2_WIN1V (*(REGType16v *)0x4000046) +#define reg_G2_WININ (*(REGType16v *)0x4000048) +#define reg_G2_WINOUT (*(REGType16v *)0x400004a) +#define reg_G2_MOSAIC (*(REGType16v *)0x400004c) +#define reg_G2_BLDCNT (*(REGType16v *)0x4000050) +#define reg_G2_BLDALPHA (*(REGType16v *)0x4000052) +#define reg_G2_BLDY (*(REGType16v *)0x4000054) + #define reg_G3X_DISP3DCNT (*(REGType16v *)0x4000060) #define reg_GX_DISPCAPCNT (*(REGType32v *)0x4000064) @@ -37,7 +76,25 @@ #define reg_MI_DMA2_CLR_DATA (*(REGType32v *)0x40000e8) #define reg_MI_DMA3_CLR_DATA (*(REGType32v *)0x40000ec) +#define reg_OS_TM0CNT_L (*(REGType16v *)0x4000100) +#define reg_OS_TM0CNT_H (*(REGType16v *)0x4000102) +#define reg_OS_TM1CNT_L (*(REGType16v *)0x4000104) +#define reg_OS_TM1CNT_H (*(REGType16v *)0x4000106) +#define reg_OS_TM2CNT_L (*(REGType16v *)0x4000108) +#define reg_OS_TM2CNT_H (*(REGType16v *)0x400010a) +#define reg_OS_TM3CNT_L (*(REGType16v *)0x400010c) +#define reg_OS_TM3CNT_H (*(REGType16v *)0x400010e) + +#define reg_EXI_SIODATA32 (*(REGType32v *)0x4000120) +#define reg_EXI_SIOCNT (*(REGType16v *)0x4000128) +#define reg_EXI_SIOSEL (*(REGType32v *)0x400012c) + #define reg_PAD_KEYINPUT (*(REGType16v *)0x4000130) +#define reg_PAD_KEYCNT (*(REGType16v *)0x4000132) + +#define reg_PXI_SUBPINTF (*(REGType16v *)0x4000180) +#define reg_PXI_SUBP_FIFO_CNT (*(REGType16v *)0x4000184) +#define reg_PXI_SEND_FIFO (*(REGType32v *)0x4000188) #define reg_MI_MCCNT0 (*(REGType16v *)0x40001a0) #define reg_MI_MCD0 (*(REGType16v *)0x40001a2) @@ -46,28 +103,43 @@ #define reg_MI_MCCMD1 (*(REGType32v *)0x40001ac) #define reg_MI_EXMEMCNT (*(REGType16v *)0x4000204) +#define reg_OS_IME (*(REGType16v *)0x4000208) +#define reg_OS_IE (*(REGType32v *)0x4000210) +#define reg_OS_IF (*(REGType32v *)0x4000214) +#define reg_OS_PAUSE (*(REGType16v *)0x4000300) + #define reg_GX_VRAMCNT (*(REGType32v *)0x4000240) -#define reg_GX_VRAMCNT_A (*(REGType8v *)0x4000240) -#define reg_GX_VRAMCNT_B (*(REGType8v *)0x4000241) -#define reg_GX_VRAMCNT_C (*(REGType8v *)0x4000242) -#define reg_GX_VRAMCNT_D (*(REGType8v *)0x4000243) +#define reg_GX_VRAMCNT_A (*(REGType8v *)0x4000240) +#define reg_GX_VRAMCNT_B (*(REGType8v *)0x4000241) +#define reg_GX_VRAMCNT_C (*(REGType8v *)0x4000242) +#define reg_GX_VRAMCNT_D (*(REGType8v *)0x4000243) #define reg_GX_WVRAMCNT (*(REGType32v *)0x4000244) -#define reg_GX_VRAMCNT_E (*(REGType8v *)0x4000244) -#define reg_GX_VRAMCNT_F (*(REGType8v *)0x4000245) -#define reg_GX_VRAMCNT_G (*(REGType8v *)0x4000246) -#define reg_GX_VRAMCNT_WRAM (*(REGType8v *)0x4000247) +#define reg_GX_VRAMCNT_E (*(REGType8v *)0x4000244) +#define reg_GX_VRAMCNT_F (*(REGType8v *)0x4000245) +#define reg_GX_VRAMCNT_G (*(REGType8v *)0x4000246) +#define reg_GX_VRAMCNT_WRAM (*(REGType8v *)0x4000247) #define reg_GX_VRAM_HI_CNT (*(REGType16v *)0x4000248) -#define reg_GX_VRAMCNT_H (*(REGType8v *)0x4000248) -#define reg_GX_VRAMCNT_I (*(REGType8v *)0x4000249) +#define reg_GX_VRAMCNT_H (*(REGType8v *)0x4000248) +#define reg_GX_VRAMCNT_I (*(REGType8v *)0x4000249) #define reg_CP_DIVCNT (*(REGType16v *)0x4000280) #define reg_CP_DIV_NUMER (*(REGType64v *)0x4000290) +#define reg_CP_DIV_NUMER_L (*(REGType32v *)0x4000290) +#define reg_CP_DIV_NUMER_H (*(REGType32v *)0x4000294) #define reg_CP_DIV_DENOM (*(REGType64v *)0x4000298) +#define reg_CP_DIV_DENOM_L (*(REGType32v *)0x4000298) +#define reg_CP_DIV_DENOM_H (*(REGType32v *)0x400029c) #define reg_CP_DIV_RESULT (*(REGType64v *)0x40002A0) +#define reg_CP_DIV_RESULT_L (*(REGType32v *)0x40002A0) +#define reg_CP_DIV_RESULT_H (*(REGType32v *)0x40002A4) #define reg_CP_DIVREM_RESULT (*(REGType64v *)0x40002A8) +#define reg_CP_DIVREM_RESULT_L (*(REGType32v *)0x40002A8) +#define reg_CP_DIVREM_RESULT_H (*(REGType32v *)0x40002Ac) #define reg_CP_SQRTCNT (*(REGType16v *)0x40002B0) #define reg_CP_SQRT_RESULT (*(REGType32v *)0x40002B4) #define reg_CP_SQRT_PARAM (*(REGType64v *)0x40002B8) +#define reg_CP_SQRT_PARAM_L (*(REGType32v *)0x40002B8) +#define reg_CP_SQRT_PARAM_H (*(REGType32v *)0x40002Bc) #define reg_GX_POWCNT (*(REGType16v *)0x4000304) @@ -236,6 +308,51 @@ #define reg_G3X_VECMTX_RESULT_7 (*(const REGType32v *)0x400069c) #define reg_G3X_VECMTX_RESULT_8 (*(const REGType32v *)0x40006a0) +#define reg_GXS_DB_DISPCNT (*(REGType32v *)0x4001000) + +#define reg_G2S_DB_BG0CNT (*(REGType16v *)0x4001008) +#define reg_G2S_DB_BG1CNT (*(REGType16v *)0x400100a) +#define reg_G2S_DB_BG2CNT (*(REGType16v *)0x400100c) +#define reg_G2S_DB_BG3CNT (*(REGType16v *)0x400100e) +#define reg_G2S_DB_BG0OFS (*(REGType32v *)0x4001010) +#define reg_G2S_DB_BG0HOFS (*(REGType16v *)0x4001010) +#define reg_G2S_DB_BG0VOFS (*(REGType16v *)0x4001012) +#define reg_G2S_DB_BG1OFS (*(REGType32v *)0x4001014) +#define reg_G2S_DB_BG1HOFS (*(REGType16v *)0x4001014) +#define reg_G2S_DB_BG1VOFS (*(REGType16v *)0x4001016) +#define reg_G2S_DB_BG2OFS (*(REGType32v *)0x4001018) +#define reg_G2S_DB_BG2HOFS (*(REGType16v *)0x4001018) +#define reg_G2S_DB_BG2VOFS (*(REGType16v *)0x400101a) +#define reg_G2S_DB_BG3OFS (*(REGType32v *)0x400101c) +#define reg_G2S_DB_BG3HOFS (*(REGType16v *)0x400101c) +#define reg_G2S_DB_BG3VOFS (*(REGType16v *)0x400101e) +#define reg_G2S_DB_BG2PA (*(REGType16v *)0x4001020) +#define reg_G2S_DB_BG2PB (*(REGType16v *)0x4001022) +#define reg_G2S_DB_BG2PC (*(REGType16v *)0x4001024) +#define reg_G2S_DB_BG2PD (*(REGType16v *)0x4001026) +#define reg_G2S_DB_BG2X (*(REGType32v *)0x4001028) +#define reg_G2S_DB_BG2Y (*(REGType32v *)0x400102c) +#define reg_G2S_DB_BG3PA (*(REGType16v *)0x4001030) +#define reg_G2S_DB_BG3PB (*(REGType16v *)0x4001032) +#define reg_G2S_DB_BG3PC (*(REGType16v *)0x4001034) +#define reg_G2S_DB_BG3PD (*(REGType16v *)0x4001036) +#define reg_G2S_DB_BG3X (*(REGType32v *)0x4001038) +#define reg_G2S_DB_BG3Y (*(REGType32v *)0x400103c) +#define reg_G2S_DB_WIN0H (*(REGType16v *)0x4001040) +#define reg_G2S_DB_WIN1H (*(REGType16v *)0x4001042) +#define reg_G2S_DB_WIN0V (*(REGType16v *)0x4001044) +#define reg_G2S_DB_WIN1V (*(REGType16v *)0x4001046) +#define reg_G2S_DB_WININ (*(REGType16v *)0x4001048) +#define reg_G2S_DB_WINOUT (*(REGType16v *)0x400104a) +#define reg_G2S_DB_MOSAIC (*(REGType16v *)0x400104c) +#define reg_G2S_DB_BLDCNT (*(REGType16v *)0x4001050) +#define reg_G2S_DB_BLDALPHA (*(REGType16v *)0x4001052) +#define reg_G2S_DB_BLDY (*(REGType16v *)0x4001054) + +#define reg_GXS_DB_MASTER_BRIGHT (*(REGType16v *)0x400106c) + +#define reg_PXI_RECV_FIFO (*(REGType32v *)0x4100000) + #define reg_MI_MCD1 (*(REGType32v *)0x4100010) #define REG_PAD_KEYINPUT_L_SHIFT 9 |