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path: root/arm9/lib/src/GX_g3x.c
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Diffstat (limited to 'arm9/lib/src/GX_g3x.c')
-rw-r--r--arm9/lib/src/GX_g3x.c140
1 files changed, 70 insertions, 70 deletions
diff --git a/arm9/lib/src/GX_g3x.c b/arm9/lib/src/GX_g3x.c
index e76adce7..5a03c4ca 100644
--- a/arm9/lib/src/GX_g3x.c
+++ b/arm9/lib/src/GX_g3x.c
@@ -46,190 +46,190 @@ ARM_FUNC asm void GXi_NopClearFifo128_(void *reg){
ARM_FUNC void G3X_Init(){
G3X_ClearFifo();
- SETREG32(HW_REG_END_VTXS, 0x0);
- while (READREG32(HW_REG_GXSTAT) & 0x8000000); //wait for geometry engine to not be busy
- SETREG16(HW_REG_DISP3DCNT, 0x0);
- SETREG32(HW_REG_GXSTAT, 0x0);
- SETREG32(HW_REG_BG0HOFS, 0x0);
- SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x2000);
- SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x1000);
- SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & ~0x3002);
- SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & ~0x3000 | 0x10);
- SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & (u16)~0x3004);
- SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
- SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) & ~0xC0000000 | 0x80000000);
+ reg_G3_END_VTXS = 0x0;
+ while (reg_G3X_GXSTAT & 0x8000000); //wait for geometry engine to not be busy
+ reg_G3X_DISP3DCNT = 0x0;
+ reg_G3X_GXSTAT = 0x0;
+ reg_G2_BG0OFS = 0x0;
+ reg_G3X_DISP3DCNT |= 0x2000;
+ reg_G3X_DISP3DCNT |= 0x1000;
+ reg_G3X_DISP3DCNT &= ~0x3002;
+ reg_G3X_DISP3DCNT = reg_G3X_DISP3DCNT & ~0x3000 | 0x10;
+ reg_G3X_DISP3DCNT = reg_G3X_DISP3DCNT & (u16)~0x3004;
+ reg_G3X_GXSTAT |= 0x8000;
+ reg_G3X_GXSTAT = reg_G3X_GXSTAT & ~0xC0000000 | 0x80000000;
G3X_InitMtxStack();
- SETREG32(HW_REG_CLEAR_COLOR, 0x0);
- SETREG16(HW_REG_CLEAR_DEPTH, 0x7FFF);
- SETREG16(HW_REG_CLRIMAGE_OFFSET, 0x0);
- SETREG32(HW_REG_FOG_COLOR, 0x0);
- SETREG16(HW_REG_FOG_OFFSET, 0x0);
- SETREG16(HW_REG_BG0CNT, READREG16(HW_REG_BG0CNT) & ~0x3);
+ reg_G3X_CLEAR_COLOR = 0x0;
+ reg_G3X_CLEAR_DEPTH = 0x7FFF;
+ reg_G3X_CLRIMAGE_OFFSET = 0x0;
+ reg_G3X_FOG_COLOR = 0x0;
+ reg_G3X_FOG_OFFSET = 0x0;
+ reg_G2_BG0CNT &= ~0x3;
G3X_InitTable();
- SETREG32(HW_REG_POLYGON_ATTR, 0x1F0080);
- SETREG32(HW_REG_TEXIMAGE_PARAM, 0x0);
- SETREG32(HW_REG_PLTT_BASE, 0x0);
+ reg_G3_POLYGON_ATTR = 0x1F0080;
+ reg_G3_TEXIMAGE_PARAM = 0x0;
+ reg_G3_TEXPLTT_BASE = 0x0;
}
ARM_FUNC void G3X_ResetMtxStack(){
- while (READREG32(HW_REG_GXSTAT) & 0x8000000);
- SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
- SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x2000);
- SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x1000);
+ while (reg_G3X_GXSTAT & 0x8000000);
+ reg_G3X_GXSTAT |= 0x8000;
+ reg_G3X_DISP3DCNT |= 0x2000;
+ reg_G3X_DISP3DCNT |= 0x1000;
G3X_ResetMtxStack_2();
- SETREG32(HW_REG_POLYGON_ATTR, 0x1F0080);
- SETREG32(HW_REG_TEXIMAGE_PARAM, 0x0);
- SETREG32(HW_REG_PLTT_BASE, 0x0);
+ reg_G3_POLYGON_ATTR = 0x1F0080;
+ reg_G3_TEXIMAGE_PARAM = 0x0;
+ reg_G3_TEXPLTT_BASE = 0x0;
}
ARM_FUNC void G3X_ClearFifo(){
- GXi_NopClearFifo128_((void *)HW_REG_GXFIFO);
- while (READREG32(HW_REG_GXSTAT) & 0x8000000);
+ GXi_NopClearFifo128_((void *)&reg_G3X_GXFIFO);
+ while (reg_G3X_GXSTAT & 0x8000000);
}
ARM_FUNC void G3X_InitMtxStack(){
u32 PV_level, PJ_level;
- SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
+ reg_G3X_GXSTAT |= 0x8000;
while (G3X_GetMtxStackLevelPV(&PV_level));
while (G3X_GetMtxStackLevelPJ(&PJ_level));
- SETREG32(HW_REG_MTX_MODE, 0x3);
- SETREG32(HW_REG_MTX_IDENTITY, 0x0);
- SETREG32(HW_REG_MTX_MODE, 0x0);
+ reg_G3_MTX_MODE = 0x3;
+ reg_G3_MTX_IDENTITY = 0x0;
+ reg_G3_MTX_MODE = 0x0;
if (PJ_level)
{
- SETREG32(HW_REG_MTX_POP, PJ_level);
+ reg_G3_MTX_POP = PJ_level;
}
- SETREG32(HW_REG_MTX_IDENTITY, 0x0);
- SETREG32(HW_REG_MTX_MODE, 0x2);
- SETREG32(HW_REG_MTX_POP, PV_level);
- SETREG32(HW_REG_MTX_IDENTITY, 0x0);
+ reg_G3_MTX_IDENTITY = 0x0;
+ reg_G3_MTX_MODE = 0x2;
+ reg_G3_MTX_POP = PV_level;
+ reg_G3_MTX_IDENTITY = 0x0;
}
ARM_FUNC void G3X_ResetMtxStack_2(){
u32 PV_level, PJ_level;
- SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
+ reg_G3X_GXSTAT |= 0x8000;
while (G3X_GetMtxStackLevelPV(&PV_level));
while (G3X_GetMtxStackLevelPJ(&PJ_level));
- SETREG32(HW_REG_MTX_MODE, 0x3);
- SETREG32(HW_REG_MTX_IDENTITY, 0x0);
- SETREG32(HW_REG_MTX_MODE, 0x0);
+ reg_G3_MTX_MODE = 0x3;
+ reg_G3_MTX_IDENTITY = 0x0;
+ reg_G3_MTX_MODE = 0x0;
if (PJ_level)
{
- SETREG32(HW_REG_MTX_POP, PJ_level);
+ reg_G3_MTX_POP = PJ_level;
}
- SETREG32(HW_REG_MTX_MODE, 0x2);
- SETREG32(HW_REG_MTX_POP, PV_level);
- SETREG32(HW_REG_MTX_IDENTITY, 0x0);
+ reg_G3_MTX_MODE = 0x2;
+ reg_G3_MTX_POP = PV_level;
+ reg_G3_MTX_IDENTITY = 0x0;
}
ARM_FUNC void G3X_SetFog(u32 enable, u32 alphamode, u32 depth, s32 offset){
if (enable)
{
- SETREG16(HW_REG_FOG_OFFSET, offset);
- SETREG16(HW_REG_DISP3DCNT, (READREG16(HW_REG_DISP3DCNT) &~0x3f40) | (((depth << 0x8)| (alphamode << 0x6)|0x80 )));
+ reg_G3X_FOG_OFFSET = offset;
+ reg_G3X_DISP3DCNT = (reg_G3X_DISP3DCNT &~0x3f40) | (((depth << 0x8)| (alphamode << 0x6)|0x80 ));
}
else
{
- SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & (u16)~0x3080);
+ reg_G3X_DISP3DCNT = reg_G3X_DISP3DCNT & (u16)~0x3080;
}
}
ARM_FUNC u32 G3X_GetClipMtx(struct Mtx44 *dst){
- if (READREG32(HW_REG_GXSTAT) & 0x8000000)
+ if (reg_G3X_GXSTAT & 0x8000000)
{
return -1;
}
else
{
- MI_Copy64B((void *)HW_REG_CLIPMTX_RESULT, dst);
+ MI_Copy64B((void *)&reg_G3X_CLIPMTX_RESULT_0, dst);
return 0;
}
}
ARM_FUNC u32 G3X_GetVectorMtx(struct Mtx33 *dst){
- if (READREG32(HW_REG_GXSTAT) & 0x8000000)
+ if (reg_G3X_GXSTAT & 0x8000000)
{
return -1;
}
else
{
- MI_Copy36B((void *)HW_REG_VECMTX_RESULT, dst);
+ MI_Copy36B((void *)&reg_G3X_VECMTX_RESULT_0, dst);
return 0;
}
}
ARM_FUNC void G3X_SetEdgeColorTable(void *tbl_ptr){
- MIi_CpuCopy16(tbl_ptr, (void *)HW_REG_EDGE_COLOR, 0x10);
+ MIi_CpuCopy16(tbl_ptr, (void *)&reg_G3X_EDGE_COLOR_0, 0x10);
}
ARM_FUNC void G3X_SetFogTable(void *tbl_ptr){
- MI_Copy16B(tbl_ptr, (void *)HW_REG_FOG_TABLE);
+ MI_Copy16B(tbl_ptr, (void *)&reg_G3X_FOG_TABLE_0);
}
ARM_FUNC void G3X_SetClearColor(u32 col, u32 alpha, u32 depth, u32 polygon_id, u32 enable_fog){
u32 temp = col | (alpha << 0x10) | (polygon_id << 0x18);
if (enable_fog)
temp |= 0x8000;
- SETREG32(HW_REG_CLEAR_COLOR, temp);
- SETREG16(HW_REG_CLEAR_DEPTH, depth);
+ reg_G3X_CLEAR_COLOR = temp;
+ reg_G3X_CLEAR_DEPTH = depth;
}
ARM_FUNC void G3X_InitTable(){
if (UNK_02106814 != -1)
{
- MI_DmaFill32Async(UNK_02106814, (void *)HW_REG_EDGE_COLOR, 0x0, 0x10, 0x0, 0x0);
- MI_DmaFill32(UNK_02106814, (void *)HW_REG_FOG_TABLE, 0x0, 0x60);
+ MI_DmaFill32Async(UNK_02106814, (void *)&reg_G3X_EDGE_COLOR_0, 0x0, 0x10, 0x0, 0x0);
+ MI_DmaFill32(UNK_02106814, (void *)&reg_G3X_FOG_TABLE_0, 0x0, 0x60);
}
else
{
- MIi_CpuClear32(0x0, (void *)HW_REG_EDGE_COLOR, 0x10);
- MIi_CpuClear32(0x0, (void *)HW_REG_FOG_TABLE, 0x60);
+ MIi_CpuClear32(0x0, (void *)&reg_G3X_EDGE_COLOR_0, 0x10);
+ MIi_CpuClear32(0x0, (void *)&reg_G3X_FOG_TABLE_0, 0x60);
}
for (int i = 0; i < 0x20; i++)
{
- SETREG32(HW_REG_SHININESS, 0x0);
+ reg_G3_SHININESS = 0x0;
}
}
ARM_FUNC u32 G3X_GetMtxStackLevelPV(u32 *level){
- if (READREG32(HW_REG_GXSTAT) & 0x4000)
+ if (reg_G3X_GXSTAT & 0x4000)
{
return -1;
}
else
{
- *level = (READREG32(HW_REG_GXSTAT) & 0x1F00) >> 0x8;
+ *level = (reg_G3X_GXSTAT & 0x1F00) >> 0x8;
return 0;
}
}
ARM_FUNC u32 G3X_GetMtxStackLevelPJ(u32 *level){
- if (READREG32(HW_REG_GXSTAT) & 0x4000)
+ if (reg_G3X_GXSTAT & 0x4000)
{
return -1;
}
else
{
- *level = (READREG32(HW_REG_GXSTAT) & 0x2000) >> 0xD;
+ *level = (reg_G3X_GXSTAT & 0x2000) >> 0xD;
return 0;
}
}
ARM_FUNC u32 G3X_GetBoxTestResult(u32 *result){
- if (READREG32(HW_REG_GXSTAT) & 0x1)
+ if (reg_G3X_GXSTAT & 0x1)
{
return -1;
}
else
{
- *result = (READREG32(HW_REG_GXSTAT) & 0x2);
+ *result = (reg_G3X_GXSTAT & 0x2);
return 0;
}
}
ARM_FUNC void G3X_SetHOffset(u32 offset){
- SETREG32(HW_REG_BG0HOFS, offset);
+ reg_G2_BG0OFS = offset;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-10 18:57:41 +0000