diff options
Diffstat (limited to 'arm9/lib')
28 files changed, 1151 insertions, 36 deletions
diff --git a/arm9/lib/include/CARD_common.h b/arm9/lib/include/CARD_common.h index c8a247ee..1ae31b7a 100644 --- a/arm9/lib/include/CARD_common.h +++ b/arm9/lib/include/CARD_common.h @@ -224,8 +224,6 @@ void CARD_UnlockBackup(u16 lock_id); #define CARD_RETRY_COUNT_MAX 10 -extern BOOL PXI_SendWordByFifo(u32 param1, u32 data, u32 param2); - static inline void CARDi_SendPxi(u32 data) { while (PXI_SendWordByFifo(PXI_FIFO_TAG_FS, data, TRUE) < 0) diff --git a/arm9/lib/include/CTRDG_backup.h b/arm9/lib/include/CTRDG_backup.h new file mode 100644 index 00000000..272744ad --- /dev/null +++ b/arm9/lib/include/CTRDG_backup.h @@ -0,0 +1,45 @@ +#ifndef POKEDIAMOND_CTRDG_BACKUP_H +#define POKEDIAMOND_CTRDG_BACKUP_H + +#include "nitro/types.h" +#include "CTRDG_flash.h" +#include "CTRDG_task.h" + +#define CTRDG_BACKUP_PHASE_PROGRAM 0x0001 +#define CTRDG_BACKUP_PHASE_SECTOR_ERASE 0x0002 +#define CTRDG_BACKUP_PHASE_CHIP_ERASE 0x0003 + +typedef struct CTRDGiFlashTypePlusTag +{ + u16 (*CTRDGi_WriteAgbFlashSector)(u16 secNo, u8 *src); + u16 (*CTRDGi_EraseAgbFlashChip)(void); + u16 (*CTRDGi_EraseAgbFlashSector)(u16 secNo); + void (*CTRDGi_WriteAgbFlashSectorAsync)(u16 secNo, u8 *src, CTRDG_TASK_FUNC callback); + void (*CTRDGi_EraseAgbFlashChipAsync)(CTRDG_TASK_FUNC callback); + void (*CTRDGi_EraseAgbFlashSectorAsync)(u16 secNo, CTRDG_TASK_FUNC callback); + u16 (*CTRDGi_PollingSR)(u16 phase, u8 *adr, u16 lastData); + const u16 (*maxtime); + CTRDGFlashType type; +} CTRDGiFlashTypePlus; + +typedef enum +{ + CTRDG_BACKUP_TYPE_FLASH_512K, + CTRDG_BACKUP_TYPE_FLASH_1M, + CTRDG_BACKUP_TYPE_SRAM +} CTRDGBackupType; + +extern const u16 (*ctrdgi_fl_maxtime); + +extern u16 (*CTRDGi_PollingSR)(u16 phase, u8 *adr, u16 lastData); +extern const CTRDGFlashType *AgbFlash; +extern u16 (*CTRDGi_WriteAgbFlashSector)(u16 secNo, u8 *src); +extern u16 (*CTRDGi_EraseAgbFlashChip)(void); +extern u16 (*CTRDGi_EraseAgbFlashSector)(u16 secNo); +extern void (*CTRDGi_WriteAgbFlashSectorAsync)(u16 secNo, u8 *src, CTRDG_TASK_FUNC callback); +extern void (*CTRDGi_EraseAgbFlashChipAsync)(CTRDG_TASK_FUNC callback); +extern void (*CTRDGi_EraseAgbFlashSectorAsync)(u16 secNo, CTRDG_TASK_FUNC callback); + +u16 CTRDG_IdentifyAgbBackup(CTRDGBackupType type); + +#endif //POKEDIAMOND_CTRDG_BACKUP_H diff --git a/arm9/lib/include/CTRDG_common.h b/arm9/lib/include/CTRDG_common.h index 32049f3c..2d37c6f8 100644 --- a/arm9/lib/include/CTRDG_common.h +++ b/arm9/lib/include/CTRDG_common.h @@ -1,8 +1,137 @@ -#ifndef NITRO_CTRDG_COMMON_H_ -#define NITRO_CTRDG_COMMON_H_ +#ifndef POKEDIAMOND_CTRDG_COMMON_H +#define POKEDIAMOND_CTRDG_COMMON_H -#include "nitro/types.h" +#include "consts.h" +#include "OS_spinLock.h" +#include "OS_system.h" +#include "MI_exMemory.h" +typedef struct CTRDGWork +{ + vu16 subpInitialized; + u16 lockID; + +} CTRDGWork; + +typedef struct CTRDGModuleID +{ + union + { + struct + { + u8 bitID; + u8 numberID:5; + u8 :2; + u8 disableExLsiID:1; + }; + u16 raw; + }; +} CTRDGModuleID; + +typedef struct CTRDGModuleInfo +{ + CTRDGModuleID moduleID; + u8 exLsiID[3]; + u8 isAgbCartridge:1; + u8 detectPullOut:1; + u8 :0; //?? + u16 makerCode; + u32 gameCode; +} CTRDGModuleInfo; + +typedef struct CTRDGLockByProc +{ + BOOL locked; + OSIntrMode irq; +} CTRDGLockByProc; + +typedef struct CTRDGHeader +{ + u32 startAddress; + u8 nintendoLogo[0x9c]; + + u8 titleName[12]; + u32 gameCode; + u16 makerCode; + + u8 isRomCode; + + u8 machineCode; + u8 deviceType; + + u8 exLsiID[3]; + + u8 reserved[4]; + u8 softVersion; + u8 complement; + + u16 moduleID; +} CTRDGHeader; + +typedef struct CTRDGRomCycle +{ + MICartridgeRomCycle1st c1; + MICartridgeRomCycle2nd c2; +} CTRDGRomCycle; + +#define CTRDGi_GetModuleInfoAddr() ((CTRDGModuleInfo *)HW_CTRDG_MODULE_INFO_BUF) +#define CTRDGi_GetHeaderAddr() ((CTRDGHeader *)HW_CTRDG_ROM) +#define CTRDGi_GetModuleIDImageAddr() ((u16 *)(HW_CTRDG_ROM + 0x0001fffe)) + +#define CTRDG_IS_ROM_CODE 0x96 +#define CTRDG_LOCKED_BY_MYPROC_FLAG OS_MAINP_LOCKED_FLAG + +#define CTRDGi_FORWARD_TYPE_DMA 0x00000000 +#define CTRDGi_FORWARD_TYPE_CPU 0x00000001 +#define CTRDGi_FORWARD_TYPE_MASK 0x00000001 + +#define CTRDGi_FORWARD_WIDTH_8 0x00000000 +#define CTRDGi_FORWARD_WIDTH_16 0x00000010 +#define CTRDGi_FORWARD_WIDTH_32 0x00000020 + +#define CTRDGi_FORWARD_DMA16 (CTRDGi_FORWARD_TYPE_DMA | CTRDGi_FORWARD_WIDTH_16) +#define CTRDGi_FORWARD_DMA32 (CTRDGi_FORWARD_TYPE_DMA | CTRDGi_FORWARD_WIDTH_32) +#define CTRDGi_FORWARD_CPU8 (CTRDGi_FORWARD_TYPE_CPU | CTRDGi_FORWARD_WIDTH_8) +#define CTRDGi_FORWARD_CPU16 (CTRDGi_FORWARD_TYPE_CPU | CTRDGi_FORWARD_WIDTH_16) +#define CTRDGi_FORWARD_CPU32 (CTRDGi_FORWARD_TYPE_CPU | CTRDGi_FORWARD_WIDTH_32) + +#define CTRDGi_ACCESS_DIR_WRITE 0x00000000 +#define CTRDGi_ACCESS_DIR_READ 0x00000001 + +#define CTRDGi_ACCESS_WIDTH_8 0x00000010 +#define CTRDGi_ACCESS_WIDTH_16 0x00000020 +#define CTRDGi_ACCESS_WIDTH_32 0x00000040 + +#define CTRDGi_ACCESS_WRITE8 (CTRDGi_ACCESS_DIR_WRITE | CTRDGi_ACCESS_WIDTH_8) +#define CTRDGi_ACCESS_WRITE16 (CTRDGi_ACCESS_DIR_WRITE | CTRDGi_ACCESS_WIDTH_16) +#define CTRDGi_ACCESS_WRITE32 (CTRDGi_ACCESS_DIR_WRITE | CTRDGi_ACCESS_WIDTH_32) +#define CTRDGi_ACCESS_READ8 (CTRDGi_ACCESS_DIR_READ | CTRDGi_ACCESS_WIDTH_8) +#define CTRDGi_ACCESS_READ16 (CTRDGi_ACCESS_DIR_READ | CTRDGi_ACCESS_WIDTH_16) +#define CTRDGi_ACCESS_READ32 (CTRDGi_ACCESS_DIR_READ | CTRDGi_ACCESS_WIDTH_32) + +void CTRDGi_InitCommon(void); +BOOL CTRDG_IsAgbCartridge(void); +BOOL CTRDG_IsOptionCartridge(void); +BOOL CTRDGi_IsAgbCartridgeAtInit(void); +u32 CTRDG_GetAgbGameCode(void); +u32 CTRDGi_GetAgbGameCodeAtInit(void); +u16 CTRDG_GetAgbMakerCode(void); +u16 CTRDGi_GetAgbMakerCodeAtInit(void); BOOL CTRDG_IsPulledOut(void); +BOOL CTRDG_IsExisting(void); +void CTRDGi_ChangeLatestAccessCycle(CTRDGRomCycle *r); +void CTRDGi_RestoreAccessCycle(CTRDGRomCycle *r); +void CTRDGi_LockByProcessor(u16 lockID, CTRDGLockByProc *info); +void CTRDGi_UnlockByProcessor(u16 lockID, CTRDGLockByProc *info); +void CTRDGi_SendtoPxi(u32 data); +BOOL CTRDG_CpuCopy8(const void *src, void *dest, u32 size); +BOOL CTRDG_CpuCopy16(const void *src, void *dest, u32 size); +BOOL CTRDG_CpuCopy32(const void *src, void *dest, u32 size); +BOOL CTRDGi_CopyCommon(u32 dmaNo, const void *src, void *dest, u32 size, u32 forwardType); +BOOL CTRDG_Read32(const u32 *address, u32 *rdata); +BOOL CTRDGi_AccessCommon(void *address, u32 data, void *rdata, u32 accessType); +BOOL CTRDG_IsEnabled(void); +void CTRDG_Enable(BOOL enable); +void CTRDG_CheckEnabled(void); -#endif //NITRO_CTRDG_COMMON_H_ +#endif //POKEDIAMOND_CTRDG_COMMON_H diff --git a/arm9/lib/include/CTRDG_flash.h b/arm9/lib/include/CTRDG_flash.h new file mode 100644 index 00000000..aa02d951 --- /dev/null +++ b/arm9/lib/include/CTRDG_flash.h @@ -0,0 +1,27 @@ +#ifndef POKEDIAMOND_CTRDG_FLASH_H +#define POKEDIAMOND_CTRDG_FLASH_H + +#include "nitro/types.h" +#include "MI_exMemory.h" + +#define CTRDG_AGB_FLASH_ADR 0x0A000000 + +typedef struct CTRDGiFlashSectorTag +{ + u32 size; + u16 shift; + u16 count; + u16 top; + u8 reserved[2]; +} CTRDGiFlashSector; + +typedef struct CTRDGFlashTypeTag +{ + u32 romSize; + CTRDGiFlashSector sector; + MICartridgeRamCycle agbWait[2]; + u16 makerID; + u16 deviceID; +} CTRDGFlashType; + +#endif //POKEDIAMOND_CTRDG_FLASH_H diff --git a/arm9/lib/include/CTRDG_flash_AT29LV512.h b/arm9/lib/include/CTRDG_flash_AT29LV512.h new file mode 100644 index 00000000..908dd6cf --- /dev/null +++ b/arm9/lib/include/CTRDG_flash_AT29LV512.h @@ -0,0 +1,10 @@ +#ifndef POKEDIAMOND_CTRDG_FLASH_AT29LV512_H +#define POKEDIAMOND_CTRDG_FLASH_AT29LV512_H + +#include "nitro/types.h" +#include "CTRDG_task.h" + +u32 CTRDGi_EraseFlashChipCoreAT(CTRDGTaskInfo *arg); +u32 CTRDGi_EraseFlashSectorCoreAT(CTRDGTaskInfo *arg); + +#endif //POKEDIAMOND_CTRDG_FLASH_AT29LV512_H diff --git a/arm9/lib/include/CTRDG_task.h b/arm9/lib/include/CTRDG_task.h new file mode 100644 index 00000000..2cf7a233 --- /dev/null +++ b/arm9/lib/include/CTRDG_task.h @@ -0,0 +1,25 @@ +#ifndef POKEDIAMOND_CTRDG_TASK_H +#define POKEDIAMOND_CTRDG_TASK_H + +#include "nitro/types.h" + +struct CTRDGTaskInfo_tag; + +typedef u32 (*CTRDG_TASK_FUNC) (struct CTRDGTaskInfo_tag *); + +typedef struct CTRDGTaskInfo_tag +{ + CTRDG_TASK_FUNC task; + CTRDG_TASK_FUNC callback; + u32 result; + u8 *data; + u8 *adr; + u32 offset; + u32 size; + u8 *dst; + u16 sec_num; + u8 busy; + u8 param[1]; +} CTRDGTaskInfo; + +#endif //POKEDIAMOND_CTRDG_TASK_H diff --git a/arm9/lib/include/MI_dma.h b/arm9/lib/include/MI_dma.h index 8ce3f417..99d1cb84 100644 --- a/arm9/lib/include/MI_dma.h +++ b/arm9/lib/include/MI_dma.h @@ -21,6 +21,9 @@ typedef void (*MIDmaCallback)(void *); #define MI_DMA_SRC_FIX (2UL << 23) #define MI_DMA_SRC_INC (0UL << 23) +#define MI_DMA_16BIT_BUS (0UL << 26) +#define MI_DMA_32BIT_BUS (1UL << 26) + #define MIi_DMA_TIMING_ANY (u32)(~0) #define MI_DMA_TIMING_H_BLANK (2UL << 27) diff --git a/arm9/lib/include/MI_exMemory.h b/arm9/lib/include/MI_exMemory.h index 8bd355ac..aa90a73c 100644 --- a/arm9/lib/include/MI_exMemory.h +++ b/arm9/lib/include/MI_exMemory.h @@ -1,5 +1,5 @@ -#ifndef NITRO_MI_EXMEMORY_H_ -#define NITRO_MI_EXMEMORY_H_ +#ifndef POKEDIAMOND_MI_EXMEMORY_H +#define POKEDIAMOND_MI_EXMEMORY_H #include "consts.h" @@ -8,6 +8,28 @@ typedef enum { MI_PROCESSOR_ARM7 = 1 } MIProcessor; +typedef enum +{ + MI_CTRDG_ROMCYCLE1_10 = 0, + MI_CTRDG_ROMCYCLE1_8 = 1, + MI_CTRDG_ROMCYCLE1_6 = 2, + MI_CTRDG_ROMCYCLE1_18 = 3 +} MICartridgeRomCycle1st; + +typedef enum +{ + MI_CTRDG_ROMCYCLE2_6 = 0, + MI_CTRDG_ROMCYCLE2_4 = 1 +} MICartridgeRomCycle2nd; + +typedef enum +{ + MI_CTRDG_RAMCYCLE_10 = 0, + MI_CTRDG_RAMCYCLE_8 = 1, + MI_CTRDG_RAMCYCLE_6 = 2, + MI_CTRDG_RAMCYCLE_18 = 3 +} MICartridgeRamCycle; + static inline void MIi_SetCardProcessor(MIProcessor proc) { reg_MI_EXMEMCNT = @@ -20,4 +42,34 @@ static inline void MIi_SetCartridgeProcessor(MIProcessor proc) (u16)((reg_MI_EXMEMCNT & ~0x0080) | (proc << 7)); } -#endif //NITRO_MI_EXMEMORY_H_ +static inline MICartridgeRomCycle1st MI_GetCartridgeRomCycle1st(void) +{ + return (MICartridgeRomCycle1st)((reg_MI_EXMEMCNT & 0xc) >> 2); +} + +static inline MICartridgeRomCycle2nd MI_GetCartridgeRomCycle2nd(void) +{ + return (MICartridgeRomCycle2nd)((reg_MI_EXMEMCNT & 0x10) >> 4); +} + +static inline void MI_SetCartridgeRomCycle1st(MICartridgeRomCycle1st c1) +{ + reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~0xc) | (c1 << 2)); +} + +static inline void MI_SetCartridgeRomCycle2nd(MICartridgeRomCycle2nd c2) +{ + reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~0x10) | (c2 << 4)); +} + +static inline void MI_SetCartridgeRamCycle(MICartridgeRamCycle c) +{ + reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~3) | (c << 0)); +} + +static inline MICartridgeRamCycle MI_GetCartridgeRamCycle(void) +{ + return (MICartridgeRamCycle)((reg_MI_EXMEMCNT & 3) >> 0); +} + +#endif //POKEDIAMOND_MI_EXMEMORY_H diff --git a/arm9/lib/include/MI_memory.h b/arm9/lib/include/MI_memory.h index 450e5e58..339ff9b8 100644 --- a/arm9/lib/include/MI_memory.h +++ b/arm9/lib/include/MI_memory.h @@ -45,6 +45,11 @@ static inline void MI_CpuCopy16(const void *src, void *dest, u32 size) MIi_CpuCopy16(src, dest, size); } +static inline void MI_CpuCopy32(const void *src, void *dest, u32 size) +{ + MIi_CpuCopy32(src, dest, size); +} + static inline void MI_CpuFillFast(void *dest, u32 data, u32 size) { MIi_CpuClearFast(data, dest, size); diff --git a/arm9/lib/include/OS_interrupt.h b/arm9/lib/include/OS_interrupt.h index 3d139079..d063b817 100644 --- a/arm9/lib/include/OS_interrupt.h +++ b/arm9/lib/include/OS_interrupt.h @@ -12,6 +12,7 @@ #define OS_IE_V_COUNT (1UL << REG_OS_IE_VE_SHIFT) #define OS_IE_TIMER0 (1UL << REG_OS_IE_T0_SHIFT) #define OS_IE_TIMER1 (1UL << REG_OS_IE_T1_SHIFT) +#define OS_IE_SPFIFO_RECV (1UL << REG_OS_IE_IFN_SHIFT) #define OS_IE_CARD_DATA (1UL << REG_OS_IE_MC_SHIFT) extern OSIrqFunction OS_IRQTable[]; @@ -42,6 +43,13 @@ static inline BOOL OS_EnableIrq(void) return (BOOL)prep; } +static inline BOOL OS_RestoreIrq(BOOL enable) +{ + u16 prep = reg_OS_IME; + reg_OS_IME = (u16)enable; + return (BOOL)prep; +} + static inline OSIrqMask OS_GetIrqMask(void) { return reg_OS_IE; diff --git a/arm9/lib/include/OS_protectionRegion.h b/arm9/lib/include/OS_protectionRegion.h index 9b65258d..00b7ae63 100644 --- a/arm9/lib/include/OS_protectionRegion.h +++ b/arm9/lib/include/OS_protectionRegion.h @@ -41,4 +41,8 @@ static inline u32 OSi_CalcPRParam(u32 address, u32 size, OSiProtectionRegionBase OS_SetProtectionRegion##regionNo(OSi_CalcPRParam(address, HW_C6_PR_##sizeStr, OSi_PR_BASE_MASK_##sizeStr) \ | 1) +#define OS_PR3_ACCESS_MASK (HW_C5_PERMIT_MASK << HW_C5_PR3_SFT) +#define OS_PR3_ACCESS_RW (HW_C5_PERMIT_RW << HW_C5_PR3_SFT) +#define OS_PR3_ACCESS_RO (HW_C5_PERMIT_RO << HW_C5_PR3_SFT) + #endif //POKEDIAMOND_OS_PROTECTIONREGION_H diff --git a/arm9/lib/include/OS_spinLock.h b/arm9/lib/include/OS_spinLock.h index c26e3b9f..09c2cf2c 100644 --- a/arm9/lib/include/OS_spinLock.h +++ b/arm9/lib/include/OS_spinLock.h @@ -5,7 +5,11 @@ #include "nitro/OS_spinLock_shared.h" #include "syscall.h" -#define OS_LOCK_ID_ERROR (-3) +#define OS_ReadOwnerOfLockCartridge() OS_ReadOwnerOfLockWord( (OSLockWord *)HW_CTRDG_LOCK_BUF ) +#define OS_MAINP_LOCKED_FLAG 0x40 +#define OS_LOCK_SUCCESS 0 + +#define OS_LOCK_ID_ERROR (-3) static inline void OSi_WaitByLoop(void) { diff --git a/arm9/lib/include/PXI_fifo.h b/arm9/lib/include/PXI_fifo.h index becba32e..b1ca33f3 100644 --- a/arm9/lib/include/PXI_fifo.h +++ b/arm9/lib/include/PXI_fifo.h @@ -2,6 +2,7 @@ #define POKEDIAMOND_ARM9_PXI_FIFO_H #include "nitro/PXI_fifo_shared.h" +#include "nitro/types.h" typedef enum { @@ -13,4 +14,23 @@ typedef enum PXI_FIFO_NO_CALLBACK_ENTRY = -5 } PXIFifoStatus; +typedef void (*PXIFifoCallback) (PXIFifoTag tag, u32 data, BOOL err); + +typedef union +{ + struct + { + u32 tag:5; + u32 err:1; + u32 data:26; + } e; + u32 raw; +} PXIFifoMessage; + +void PXI_InitFifo(void); +void PXI_SetFifoRecvCallback(s32 fifotag, PXIFifoCallback callback); +BOOL PXI_IsCallbackReady(s32 fifotag, PXIProc proc); +s32 PXI_SendWordByFifo(s32 fifotag, u32 data, BOOL err); +void PXIi_HandlerRecvFifoNotEmpty(void); + #endif //POKEDIAMOND_ARM9_PXI_FIFO_H diff --git a/arm9/lib/include/consts.h b/arm9/lib/include/consts.h index 7c56a9a3..a41f22ae 100644 --- a/arm9/lib/include/consts.h +++ b/arm9/lib/include/consts.h @@ -6,6 +6,13 @@ #include "registers.h" #include "systemWork.h" +#define HW_C5_PERMIT_MASK 0xf + +#define HW_C5_PERMIT_RO 5 +#define HW_C5_PERMIT_RW 1 + +#define HW_C5_PR3_SFT 12 + #define HW_C6_PR_4KB 0x16 #define HW_C6_PR_8KB 0x18 #define HW_C6_PR_16KB 0x1a @@ -35,8 +42,6 @@ #define HW_CACHE_LINE_SIZE 32 -#define PXI_PROC_ARM7 0x01 - #define OSi_CONSOLE_NOT_DETECT 0xffffffff #define OS_CONSOLE_NITRO 0x80000000 @@ -50,4 +55,11 @@ #define HW_CPU_CLOCK_ARM9 67027964 +#define REG_PXI_SUBP_FIFO_CNT_E_MASK 0x8000 +#define REG_PXI_SUBP_FIFO_CNT_ERR_MASK 0x4000 +#define REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK 0x0400 +#define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK 0x0100 +#define REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK 0x0008 +#define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK 0x0002 + #endif //POKEDIAMOND_ARM9_CONSTS_H diff --git a/arm9/lib/include/mmap.h b/arm9/lib/include/mmap.h index de5a8057..69e9c696 100644 --- a/arm9/lib/include/mmap.h +++ b/arm9/lib/include/mmap.h @@ -34,6 +34,7 @@ extern u32 SDK_AUTOLOAD_DTCM_START[]; #define HW_BOOT_CHECK_INFO_BUF (HW_MAIN_MEM + 0x007ffc00) #define HW_RESET_PARAMETER_BUF (HW_MAIN_MEM + 0x007ffc20) #define HW_ROM_BASE_OFFSET_BUF (HW_MAIN_MEM + 0x007ffc2c) +#define HW_CTRDG_MODULE_INFO_BUF (HW_MAIN_MEM + 0x007ffc30) #define HW_ROM_HEADER_BUF (HW_MAIN_MEM + 0x007ffe00) // ROM registration area data buffer #define HW_RED_RESERVED (HW_MAIN_MEM + 0x007ff800) // Some kind of reserved data for shared memory #define HW_MAIN_MEM_EX_END (HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE) @@ -93,6 +94,8 @@ extern u32 SDK_AUTOLOAD_DTCM_START[]; #define HW_DB_OAM_END 0x07000800 #define HW_DB_OAM_SIZE (HW_DB_OAM_END-HW_DB_OAM) +#define HW_CTRDG_RAM_END 0x0a010000 + #define HW_DTCM_SYSRV_OFS_INTR_VECTOR 0x3c #define HW_RESET_VECTOR 0xffff0000 diff --git a/arm9/lib/include/registers.h b/arm9/lib/include/registers.h index 44a21bf0..d55347d5 100644 --- a/arm9/lib/include/registers.h +++ b/arm9/lib/include/registers.h @@ -350,6 +350,7 @@ #define REG_OS_IE_VE_SHIFT 2 #define REG_OS_IE_T0_SHIFT 3 #define REG_OS_IE_T1_SHIFT 4 +#define REG_OS_IE_IFN_SHIFT 18 #define REG_OS_IE_MC_SHIFT 19 #define REG_OS_TM0CNT_H_I_MASK 0x0040 diff --git a/arm9/lib/include/syscall.h b/arm9/lib/include/syscall.h index 427134a7..8e7962df 100644 --- a/arm9/lib/include/syscall.h +++ b/arm9/lib/include/syscall.h @@ -1,6 +1,19 @@ #ifndef POKEDIAMOND_ARM9_SYSCALL_H #define POKEDIAMOND_ARM9_SYSCALL_H +#include "consts.h" +#include "MI_dma.h" + +void SVC_CpuSet(const void *srcp, void *destp, u32 dmaCntData); + +#define SVC_CpuClear( data, destp, size, bit ) \ +do{ \ + vu##bit tmp = (vu##bit )(data); \ + SVC_CpuSet((u8 *)&(tmp), (u8 *)(destp), ( \ + MI_DMA_SRC_FIX | \ + MI_DMA_##bit##BIT_BUS | ((size)/((bit)/8) & 0x1fffff))); \ +} while(0) + void SVC_WaitByLoop(u32 ct); #endif //POKEDIAMOND_ARM9_SYSCALL_H diff --git a/arm9/lib/src/CARD_common.c b/arm9/lib/src/CARD_common.c index 65d92377..f820027e 100644 --- a/arm9/lib/src/CARD_common.c +++ b/arm9/lib/src/CARD_common.c @@ -14,8 +14,6 @@ static CARDiCommandArg cardi_arg ALIGN(32); u8 cardi_thread_stack[0x400] ALIGN(4); -extern void PXI_SetFifoRecvCallback(u32 param1, void* callback); - static void CARDi_LockResource(CARDiOwner owner, CARDTargetMode target); static void CARDi_UnlockResource(CARDiOwner owner, CARDTargetMode target); diff --git a/arm9/lib/src/CARD_pullOut.c b/arm9/lib/src/CARD_pullOut.c index 27293d60..3456df48 100644 --- a/arm9/lib/src/CARD_pullOut.c +++ b/arm9/lib/src/CARD_pullOut.c @@ -12,9 +12,6 @@ static CARDPulledOutCallback CARD_UserCallback; static BOOL CARDi_IsPulledOutFlag = FALSE; -extern void PXI_SetFifoRecvCallback(u32 param1, void* callback); -extern BOOL PXI_SendWordByFifo(u32 param1, u32 data, u32 param2); - static void CARDi_PulledOutCallback(PXIFifoTag tag, u32 data, BOOL err); static void CARDi_SendtoPxi(u32 data, u32 wait); diff --git a/arm9/lib/src/CARD_request.c b/arm9/lib/src/CARD_request.c index 2d728d14..098fe7a5 100644 --- a/arm9/lib/src/CARD_request.c +++ b/arm9/lib/src/CARD_request.c @@ -6,8 +6,6 @@ extern CARDiCommon cardi_common; -extern u32 PXI_IsCallbackReady(u32 param1, u32 param2); - ARM_FUNC void CARDi_OnFifoRecv(PXIFifoTag tag, u32 data, BOOL err) { #pragma unused (data) diff --git a/arm9/lib/src/CARD_spi.c b/arm9/lib/src/CARD_spi.c index 3a911333..5f02b276 100644 --- a/arm9/lib/src/CARD_spi.c +++ b/arm9/lib/src/CARD_spi.c @@ -1,6 +1,7 @@ #include "function_target.h" #include "nitro/types.h" #include "CARD_common.h" +#include "CARD_spi.h" #include "MI_memory.h" extern CARDiCommon cardi_common; diff --git a/arm9/lib/src/CTRDG_backup.c b/arm9/lib/src/CTRDG_backup.c new file mode 100644 index 00000000..dc1a3f4b --- /dev/null +++ b/arm9/lib/src/CTRDG_backup.c @@ -0,0 +1,94 @@ +#include "CTRDG_backup.h" +#include "function_target.h" +#include "OS_spinLock.h" + +extern u16 ctrdgi_flash_lock_id; +extern u16 ctrdgi_sram_lock_id; + +extern u16 CTRDGi_ReadFlashID(void); + +extern const CTRDGiFlashTypePlus defaultFlash1M; +extern const CTRDGiFlashTypePlus MX29L010; +extern const CTRDGiFlashTypePlus LE26FV10N1TS_10; + +extern const CTRDGiFlashTypePlus defaultFlash512; +extern const CTRDGiFlashTypePlus LE39FW512; +extern const CTRDGiFlashTypePlus AT29LV512_lib; +extern const CTRDGiFlashTypePlus MN63F805MNP; + +static const CTRDGiFlashTypePlus *const flash1M_list[] = { + &MX29L010, + &LE26FV10N1TS_10, + &defaultFlash1M +}; + +static const CTRDGiFlashTypePlus *const flash512_list[] = { + &LE39FW512, + &AT29LV512_lib, + &MN63F805MNP, + &defaultFlash512 +}; + +static const u16 readidtime[] = { + 20 +}; + +ARM_FUNC u16 CTRDG_IdentifyAgbBackup(CTRDGBackupType type) +{ + u16 result = 1; + u16 flashID; + const CTRDGiFlashTypePlus *const *flp; + MICartridgeRamCycle ram_cycle; + + if (type == CTRDG_BACKUP_TYPE_FLASH_512K || type == CTRDG_BACKUP_TYPE_FLASH_1M) + { + ctrdgi_flash_lock_id = (u16)OS_GetLockID(); + + (void)OS_LockCartridge(ctrdgi_flash_lock_id); + + ram_cycle = MI_GetCartridgeRamCycle(); + MI_SetCartridgeRamCycle(MI_CTRDG_RAMCYCLE_18); + + ctrdgi_fl_maxtime = readidtime; + flashID = CTRDGi_ReadFlashID(); + + if (type == CTRDG_BACKUP_TYPE_FLASH_512K) + { + flp = flash512_list; + } + + if (type == CTRDG_BACKUP_TYPE_FLASH_1M) + { + flp = flash1M_list; + } + + MI_SetCartridgeRamCycle(ram_cycle); + (void)OS_UnlockCartridge(ctrdgi_flash_lock_id); + + result = 1; + while ((*flp)->type.makerID != 0) + { + if ((flashID & 0xff) == *(u16 *)&((*flp)->type.makerID)) + { + result = 0; + break; + } + flp++; + } + CTRDGi_WriteAgbFlashSector = (*flp)->CTRDGi_WriteAgbFlashSector; + CTRDGi_EraseAgbFlashChip = (*flp)->CTRDGi_EraseAgbFlashChip; + CTRDGi_EraseAgbFlashSector = (*flp)->CTRDGi_EraseAgbFlashSector; + CTRDGi_WriteAgbFlashSectorAsync = (*flp)->CTRDGi_WriteAgbFlashSectorAsync; + CTRDGi_EraseAgbFlashChipAsync = (*flp)->CTRDGi_EraseAgbFlashChipAsync; + CTRDGi_EraseAgbFlashSectorAsync = (*flp)->CTRDGi_EraseAgbFlashSectorAsync; + CTRDGi_PollingSR = (*flp)->CTRDGi_PollingSR; + ctrdgi_fl_maxtime = (*flp)->maxtime; + AgbFlash = &(*flp)->type; + } + else if (type == CTRDG_BACKUP_TYPE_SRAM) + { + ctrdgi_sram_lock_id = (u16)OS_GetLockID(); + result = 0; + } + return result; +} diff --git a/arm9/lib/src/CTRDG_common.c b/arm9/lib/src/CTRDG_common.c new file mode 100644 index 00000000..3d80cf24 --- /dev/null +++ b/arm9/lib/src/CTRDG_common.c @@ -0,0 +1,349 @@ +#include "CTRDG_common.h" +#include "function_target.h" +#include "syscall.h" +#include "OS_cache.h" +#include "OS_protectionRegion.h" +#include "OS_terminate_proc.h" +#include "PXI_fifo.h" +#include "MI_dma.h" +#include "MI_memory.h" + +CTRDGWork CTRDGi_Work; + +static BOOL CTRDGi_EnableFlag = FALSE; + +ARM_FUNC void CTRDGi_InitCommon(void) +{ + SVC_CpuClear(0, &CTRDGi_Work, sizeof(CTRDGi_Work), 32); + + CTRDGi_Work.lockID = (u16)OS_GetLockID(); +} + +ARM_FUNC BOOL CTRDG_IsAgbCartridge(void) +{ + return (CTRDG_IsExisting() && CTRDGi_IsAgbCartridgeAtInit()); +} + +ARM_FUNC BOOL CTRDG_IsOptionCartridge(void) +{ + return (CTRDG_IsExisting() && !CTRDGi_IsAgbCartridgeAtInit()); +} + +ARM_FUNC BOOL CTRDGi_IsAgbCartridgeAtInit(void) +{ + CTRDGModuleInfo *cip = CTRDGi_GetModuleInfoAddr(); + + return cip->isAgbCartridge; +} + +ARM_FUNC u32 CTRDG_GetAgbGameCode(void) +{ + u32 ret = 0; + + if (CTRDG_IsExisting()) + { + ret = CTRDGi_GetAgbGameCodeAtInit(); + } + + return ret; +} + +ARM_FUNC u32 CTRDGi_GetAgbGameCodeAtInit(void) +{ + CTRDGModuleInfo *cip = CTRDGi_GetModuleInfoAddr(); + u32 ret = 0; + + if (CTRDGi_IsAgbCartridgeAtInit()) + { + ret = cip->gameCode; + } + + return ret; +} + +ARM_FUNC u16 CTRDG_GetAgbMakerCode(void) +{ + u16 ret = 0; + + if (CTRDG_IsExisting()) + { + ret = CTRDGi_GetAgbMakerCodeAtInit(); + } + + return ret; +} + +ARM_FUNC u16 CTRDGi_GetAgbMakerCodeAtInit(void) +{ + CTRDGModuleInfo *cip = CTRDGi_GetModuleInfoAddr(); + u16 ret = 0; + + if (CTRDGi_IsAgbCartridgeAtInit()) + { + ret = cip->makerCode; + } + + return ret; +} + +ARM_FUNC BOOL CTRDG_IsPulledOut(void) +{ + CTRDGModuleInfo *cip = CTRDGi_GetModuleInfoAddr(); + + if (cip->moduleID.raw == 0xffff) + { + return FALSE; + } + + if (!cip->detectPullOut) + { + (void)CTRDG_IsExisting(); + } + + return cip->detectPullOut; +} + +ARM_FUNC BOOL CTRDG_IsExisting(void) +{ + BOOL ret = TRUE; + CTRDGLockByProc lockInfo; + + CTRDGHeader *chp = CTRDGi_GetHeaderAddr(); + CTRDGModuleInfo *cip = CTRDGi_GetModuleInfoAddr(); + + if (cip->moduleID.raw == 0xffff) + { + return FALSE; + } + + if (cip->detectPullOut == TRUE) + { + return FALSE; + } + + CTRDGi_LockByProcessor(CTRDGi_Work.lockID, &lockInfo); + + CTRDGRomCycle rc; + + CTRDGi_ChangeLatestAccessCycle(&rc); + u8 isRomCode = chp->isRomCode; + + if ((isRomCode == CTRDG_IS_ROM_CODE && cip->moduleID.raw != chp->moduleID) + || (isRomCode != CTRDG_IS_ROM_CODE && cip->moduleID.raw != *CTRDGi_GetModuleIDImageAddr()) + || ((cip->gameCode != chp->gameCode) && cip->isAgbCartridge)) + { + cip->detectPullOut = TRUE; + ret = FALSE; + } + + CTRDGi_RestoreAccessCycle(&rc); + + CTRDGi_UnlockByProcessor(CTRDGi_Work.lockID, &lockInfo); + + return ret; +} + +ARM_FUNC void CTRDGi_ChangeLatestAccessCycle(CTRDGRomCycle *r) +{ + r->c1 = MI_GetCartridgeRomCycle1st(); + r->c2 = MI_GetCartridgeRomCycle2nd(); + + MI_SetCartridgeRomCycle1st(MI_CTRDG_ROMCYCLE1_18); + MI_SetCartridgeRomCycle2nd(MI_CTRDG_ROMCYCLE2_6); +} + +ARM_FUNC void CTRDGi_RestoreAccessCycle(CTRDGRomCycle *r) +{ + MI_SetCartridgeRomCycle1st(r->c1); + MI_SetCartridgeRomCycle2nd(r->c2); +} + +ARM_FUNC void CTRDGi_LockByProcessor(u16 lockID, CTRDGLockByProc *info) +{ + while (TRUE) + { + info->irq = OS_DisableInterrupts(); + if (((info->locked = OS_ReadOwnerOfLockCartridge() & CTRDG_LOCKED_BY_MYPROC_FLAG) != 0) + || (OS_TryLockCartridge(lockID) == OS_LOCK_SUCCESS)) + { + break; + } + (void)OS_RestoreInterrupts(info->irq); + + SVC_WaitByLoop(1); + } +} + +ARM_FUNC void CTRDGi_UnlockByProcessor(u16 lockID, CTRDGLockByProc *info) +{ + if (!info->locked) + { + (void)OS_UnLockCartridge(lockID); + } + + (void)OS_RestoreInterrupts(info->irq); +} + +ARM_FUNC void CTRDGi_SendtoPxi(u32 data) +{ + while (PXI_SendWordByFifo(PXI_FIFO_TAG_CTRDG, data, FALSE) != PXI_FIFO_SUCCESS) + { + SVC_WaitByLoop(1); + } +} + +ARM_FUNC BOOL CTRDG_CpuCopy8(const void *src, void *dest, u32 size) +{ + if (HW_CTRDG_ROM <= (u32)dest && (u32)dest < HW_CTRDG_RAM_END) + { + return CTRDGi_CopyCommon(0, (const void *)dest, (void *)src, size, CTRDGi_FORWARD_CPU8); + } + else + { + return CTRDGi_CopyCommon(0, src, dest, size, CTRDGi_FORWARD_CPU8); + } +} + +ARM_FUNC BOOL CTRDG_CpuCopy16(const void *src, void *dest, u32 size) +{ + return CTRDGi_CopyCommon(0, src, dest, size, CTRDGi_FORWARD_CPU16); +} + +ARM_FUNC BOOL CTRDG_CpuCopy32(const void *src, void *dest, u32 size) +{ + return CTRDGi_CopyCommon(0, src, dest, size, CTRDGi_FORWARD_CPU32); +} + +ARM_FUNC BOOL CTRDGi_CopyCommon(u32 dmaNo, const void *src, void *dest, u32 size, u32 forwardType) +{ + if (!CTRDG_IsExisting()) + { + return FALSE; + } + + CTRDG_CheckEnabled(); + + (void)OS_LockCartridge(CTRDGi_Work.lockID); + + if ((forwardType & CTRDGi_FORWARD_TYPE_MASK) == CTRDGi_FORWARD_TYPE_DMA) + { + MI_StopDma(dmaNo); + DC_FlushRange(dest, size); + } + + switch (forwardType) + { + case CTRDGi_FORWARD_DMA16: + MI_DmaCopy16(dmaNo, src, dest, size); + break; + case CTRDGi_FORWARD_DMA32: + MI_DmaCopy32(dmaNo, src, dest, size); + break; + case CTRDGi_FORWARD_CPU16: + MI_CpuCopy16(src, dest, size); + break; + case CTRDGi_FORWARD_CPU32: + MI_CpuCopy32(src, dest, size); + break; + + case CTRDGi_FORWARD_CPU8: + u8 *dest8 = (u8 *)dest; + u8 *src8 = (u8 *)src; + for (s32 n = 0; n < size; n++) + { + *dest8++ = *src8++; + } + break; + } + + (void)OS_UnLockCartridge(CTRDGi_Work.lockID); + + if (!CTRDG_IsExisting()) + { + return FALSE; + } + + return TRUE; +} + +ARM_FUNC BOOL CTRDG_Read32(const u32 *address, u32 *rdata) +{ + return CTRDGi_AccessCommon((void *)address, 0, rdata, CTRDGi_ACCESS_READ32); +} + +ARM_FUNC BOOL CTRDGi_AccessCommon(void *address, u32 data, void *rdata, u32 accessType) +{ + if (!CTRDG_IsExisting()) + { + return FALSE; + } + + CTRDG_CheckEnabled(); + + (void)OS_LockCartridge(CTRDGi_Work.lockID); + + switch (accessType) + { + case CTRDGi_ACCESS_READ8: + if (rdata) + { + *(u8 *)rdata = *(u8 *)address; + } + break; + case CTRDGi_ACCESS_READ16: + if (rdata) + { + *(u16 *)rdata = *(u16 *)address; + } + break; + case CTRDGi_ACCESS_READ32: + if (rdata) + { + *(u32 *)rdata = *(u32 *)address; + } + break; + case CTRDGi_ACCESS_WRITE8: + *(u8 *)address = (u8)data; + break; + case CTRDGi_ACCESS_WRITE16: + *(u16 *)address = (u16)data; + break; + case CTRDGi_ACCESS_WRITE32: + *(u32 *)address = (u32)data; + break; + } + + (void)OS_UnLockCartridge(CTRDGi_Work.lockID); + + if (!CTRDG_IsExisting()) + { + return FALSE; + } + + return TRUE; +} + +ARM_FUNC BOOL CTRDG_IsEnabled(void) +{ + return CTRDGi_EnableFlag; +} + +ARM_FUNC void CTRDG_Enable(BOOL enable) +{ + OSIntrMode bak_cpsr = OS_DisableInterrupts(); + CTRDGi_EnableFlag = enable; + if (!CTRDG_IsOptionCartridge()) + { + u32 acc = (u32)(enable ? OS_PR3_ACCESS_RW : OS_PR3_ACCESS_RO); + (void)OS_SetDPermissionsForProtectionRegion(OS_PR3_ACCESS_MASK, acc); + } + (void)OS_RestoreInterrupts(bak_cpsr); +} + +ARM_FUNC void CTRDG_CheckEnabled(void) +{ + if (!CTRDG_IsOptionCartridge() && !CTRDG_IsEnabled()) + { + OS_Terminate(); + } +} diff --git a/arm9/lib/src/CTRDG_flash_AT29LV512.c b/arm9/lib/src/CTRDG_flash_AT29LV512.c new file mode 100644 index 00000000..8cd90c31 --- /dev/null +++ b/arm9/lib/src/CTRDG_flash_AT29LV512.c @@ -0,0 +1,143 @@ +#include "CTRDG_flash_AT29LV512.h" +#include "function_target.h" +#include "CTRDG_backup.h" +#include "CTRDG_flash.h" +#include "MI_exMemory.h" +#include "OS_interrupt.h" +#include "OS_spinLock.h" + +#define CTRDG_BACKUP_COM_ADR1 (CTRDG_AGB_FLASH_ADR+0x00005555) +#define CTRDG_BACKUP_COM_ADR2 (CTRDG_AGB_FLASH_ADR+0x00002aaa) + +extern u16 ctrdgi_flash_lock_id; +extern BOOL ctrdgi_backup_irq; + +extern u16 CTRDGi_PollingSR512kCOMMON(u16 phase, u8 *adr, u16 lastData); + +extern u16 CTRDGi_EraseFlashChipAT(void); +extern u16 CTRDGi_EraseFlashSectorAT(u16 p_secNo); +extern u16 CTRDGi_EraseFlash4KBAT(u16 l_secNo); +extern u16 CTRDGi_WriteFlashSectorAT(u16 p_secNo, u8 *src); +extern u16 CTRDGi_WriteFlash4KBAT(u16 l_secNo, u8 *src); + +extern void CTRDGi_EraseFlashChipAsyncAT(CTRDG_TASK_FUNC callback); +extern void CTRDGi_EraseFlash4KBAsyncAT(u16 secNo, CTRDG_TASK_FUNC callback); +extern void CTRDGi_WriteFlash4KBAsyncAT(u16 secNo, u8 *src, CTRDG_TASK_FUNC callback); +extern void CTRDGi_EraseFlashSectorAsyncAT(u16 secNo, CTRDG_TASK_FUNC callback); +extern void CTRDGi_WriteFlashSectorAsyncAT(u16 secNo, u8 *src, CTRDG_TASK_FUNC callback); + +static const u16 atMaxTime[] = { + 10, 40, 0, 40 +}; + +const CTRDGiFlashTypePlus AT29LV512_lib = { + CTRDGi_WriteFlash4KBAT, + CTRDGi_EraseFlashChipAT, + CTRDGi_EraseFlash4KBAT, + CTRDGi_WriteFlash4KBAsyncAT, + CTRDGi_EraseFlashChipAsyncAT, + CTRDGi_EraseFlash4KBAsyncAT, + CTRDGi_PollingSR512kCOMMON, + atMaxTime, + { + 0x00010000, //ROM size + {0x00001000, 12, 16, 0}, //sector + {MI_CTRDG_RAMCYCLE_18, MI_CTRDG_RAMCYCLE_18}, //read cycle and write cycle + 0x1f, //maker ID + 0x3d, //device ID + } +}; + +const CTRDGiFlashTypePlus AT29LV512_org = { + CTRDGi_WriteFlashSectorAT, + CTRDGi_EraseFlashChipAT, + CTRDGi_EraseFlashSectorAT, + CTRDGi_WriteFlashSectorAsyncAT, + CTRDGi_EraseFlashChipAsyncAT, + CTRDGi_EraseFlashSectorAsyncAT, + CTRDGi_PollingSR512kCOMMON, + atMaxTime, + { + 0x00010000, //ROM size + {0x00000080, 7, 512, 0}, //sector + {MI_CTRDG_RAMCYCLE_18, MI_CTRDG_RAMCYCLE_18}, //read cycle and write cycle + 0x1f, //maker ID + 0x3d, //device ID + } +}; + +ARM_FUNC u32 CTRDGi_EraseFlashChipCoreAT(CTRDGTaskInfo *arg) +{ + MICartridgeRamCycle ram_cycle; + u32 result; + (void)arg; + + (void)OS_LockCartridge(ctrdgi_flash_lock_id); + + ram_cycle = MI_GetCartridgeRamCycle(); + MI_SetCartridgeRamCycle(AgbFlash->agbWait[0]); + + ctrdgi_backup_irq = OS_DisableIrq(); + + *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; + *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; + *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x80; + *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; + *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; + *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0x10; + + (void)OS_RestoreIrq(ctrdgi_backup_irq); + + result = CTRDGi_PollingSR(CTRDG_BACKUP_PHASE_CHIP_ERASE, (u8 *)CTRDG_AGB_FLASH_ADR, 0xff); + + MI_SetCartridgeRamCycle(ram_cycle); + + (void)OS_UnlockCartridge(ctrdgi_flash_lock_id); + + return result; +} + +ARM_FUNC u32 CTRDGi_EraseFlashSectorCoreAT(CTRDGTaskInfo *arg) +{ + u32 i; + u8 *dst; + BOOL shlet_ime; + MICartridgeRamCycle ram_cycle; + u32 result; + CTRDGTaskInfo p = *arg; + u16 p_secNo = p.sec_num; + + dst = (u8 *)(CTRDG_AGB_FLASH_ADR + (p_secNo << AT29LV512_org.type.sector.shift)); + + (void)OS_LockCartridge(ctrdgi_flash_lock_id); + + ram_cycle = MI_GetCartridgeRamCycle(); + MI_SetCartridgeRamCycle(AgbFlash->agbWait[0]); + + shlet_ime = OS_DisableIrq(); + + *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xaa; + *(vu8 *)CTRDG_BACKUP_COM_ADR2 = 0x55; + *(vu8 *)CTRDG_BACKUP_COM_ADR1 = 0xa0; + + for (i = AT29LV512_org.type.sector.size; i > 0; i--) + { + *dst++ = 0xff; + } + dst--; + + (void)OS_RestoreIrq(shlet_ime); + + result = CTRDGi_PollingSR(CTRDG_BACKUP_PHASE_PROGRAM, dst, 0xff); + + if (result) + { + result = (u16)((result & 0xff00) | CTRDG_BACKUP_PHASE_SECTOR_ERASE); + } + + MI_SetCartridgeRamCycle(ram_cycle); + + (void)OS_UnlockCartridge(ctrdgi_flash_lock_id); + + return result; +} diff --git a/arm9/lib/src/OS_reset.c b/arm9/lib/src/OS_reset.c index 8be8fb33..45d2bb13 100644 --- a/arm9/lib/src/OS_reset.c +++ b/arm9/lib/src/OS_reset.c @@ -10,14 +10,11 @@ #include "MI_dma.h" #include "CARD_common.h" #include "PXI_init.h" +#include "PXI_fifo.h" static u16 OSi_IsInitReset = 0; vu16 OSi_IsResetOccurred = 0; -extern u32 PXI_IsCallbackReady(u32 param1, u32 param2); -extern void PXI_SetFifoRecvCallback(u32 param1, void* callback); -extern BOOL PXI_SendWordByFifo(u32 param1, u32 data, u32 param2); - static void OSi_CommonCallback(PXIFifoTag tag, u32 data, BOOL err); static void OSi_SendToPxi(u16 data); static void OSi_DoResetSystem(void); diff --git a/arm9/lib/src/PXI_fifo.c b/arm9/lib/src/PXI_fifo.c new file mode 100644 index 00000000..35db1c7f --- /dev/null +++ b/arm9/lib/src/PXI_fifo.c @@ -0,0 +1,185 @@ +#include "function_target.h" +#include "consts.h" +#include "OS_interrupt.h" +#include "OS_system.h" +#include "PXI_fifo.h" +#include "systemWork.h" + +static u16 FifoCtrlInit = 0; +static PXIFifoCallback FifoRecvCallbackTable[PXI_MAX_FIFO_TAG]; + +static inline PXIFifoStatus PXIi_SetToFifo(u32 data); + +ARM_FUNC void PXI_InitFifo(void) +{ + OSSystemWork *p = OS_GetSystemWork(); + OSIntrMode enabled = OS_DisableInterrupts(); + s32 i; + + if (!FifoCtrlInit) + { + FifoCtrlInit = TRUE; + + p->pxiHandleChecker[PXI_PROC_ARM9] = 0UL; + + for (i = 0; i < PXI_MAX_FIFO_TAG; i++) + { + FifoRecvCallbackTable[i] = NULL; + } + + reg_PXI_SUBP_FIFO_CNT = (REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK + | REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK | REG_PXI_SUBP_FIFO_CNT_E_MASK | REG_PXI_SUBP_FIFO_CNT_ERR_MASK); + + (void)OS_ResetRequestIrqMask(OS_IE_SPFIFO_RECV); + (void)OS_SetIrqFunction(OS_IE_SPFIFO_RECV, PXIi_HandlerRecvFifoNotEmpty); + (void)OS_EnableIrqMask(OS_IE_SPFIFO_RECV); + + { + s32 timeout; + s32 c; + + for (i = 0; ; i++) + { + c = reg_PXI_SUBPINTF & 15; + reg_PXI_SUBPINTF = (u16)(c << 8); + + if (c == 0 && i > 4) + { + break; + } + + for (timeout = 1000; (reg_PXI_SUBPINTF & 15) == c; timeout--) + { + if (timeout == 0) + { + i = 0; + break; + } + } + } + } + } + (void)OS_RestoreInterrupts(enabled); +} + +ARM_FUNC void PXI_SetFifoRecvCallback(s32 fifotag, PXIFifoCallback callback) +{ + OSSystemWork *p = OS_GetSystemWork(); + OSIntrMode enabled = OS_DisableInterrupts(); + + FifoRecvCallbackTable[fifotag] = callback; + if (callback) + { + p->pxiHandleChecker[PXI_PROC_ARM9] |= (1UL << fifotag); + } + else + { + p->pxiHandleChecker[PXI_PROC_ARM9] &= ~(1UL << fifotag); + } + (void)OS_RestoreInterrupts(enabled); +} + +ARM_FUNC BOOL PXI_IsCallbackReady(s32 fifotag, PXIProc proc) +{ + OSSystemWork *p = OS_GetSystemWork(); + + return (p->pxiHandleChecker[proc] & (1UL << fifotag)) ? TRUE : FALSE; +} + +ARM_FUNC s32 PXI_SendWordByFifo(s32 fifotag, u32 data, BOOL err) +{ + PXIFifoMessage fifomsg; + + fifomsg.e.tag = (PXIFifoTag)fifotag; + fifomsg.e.err = (u32)err; + fifomsg.e.data = data; + + return PXIi_SetToFifo(fifomsg.raw); +} + +static inline PXIFifoStatus PXIi_SetToFifo(u32 data) +{ + if (reg_PXI_SUBP_FIFO_CNT & REG_PXI_SUBP_FIFO_CNT_ERR_MASK) + { + reg_PXI_SUBP_FIFO_CNT |= (REG_PXI_SUBP_FIFO_CNT_E_MASK | REG_PXI_SUBP_FIFO_CNT_ERR_MASK); + return PXI_FIFO_FAIL_SEND_ERR; + } + + OSIntrMode enabled = OS_DisableInterrupts(); + if (reg_PXI_SUBP_FIFO_CNT & REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK) + { + (void)OS_RestoreInterrupts(enabled); + return PXI_FIFO_FAIL_SEND_FULL; + } + + reg_PXI_SEND_FIFO = data; + (void)OS_RestoreInterrupts(enabled); + return PXI_FIFO_SUCCESS; +} + +static inline PXIFifoStatus PXIi_GetFromFifo(u32 *data_buf) +{ + if (reg_PXI_SUBP_FIFO_CNT & REG_PXI_SUBP_FIFO_CNT_ERR_MASK) + { + reg_PXI_SUBP_FIFO_CNT |= (REG_PXI_SUBP_FIFO_CNT_E_MASK | REG_PXI_SUBP_FIFO_CNT_ERR_MASK); + return PXI_FIFO_FAIL_RECV_ERR; + } + + OSIntrMode enabled = OS_DisableInterrupts(); + if (reg_PXI_SUBP_FIFO_CNT & REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK) + { + (void)OS_RestoreInterrupts(enabled); + return PXI_FIFO_FAIL_RECV_EMPTY; + } + + + *data_buf = reg_PXI_RECV_FIFO; + (void)OS_RestoreInterrupts(enabled); + + return PXI_FIFO_SUCCESS; +} + +ARM_FUNC void PXIi_HandlerRecvFifoNotEmpty(void) +{ + PXIFifoMessage fifomsg; + PXIFifoStatus ret_code; + PXIFifoTag tag; + + while (TRUE) + { + ret_code = PXIi_GetFromFifo(&fifomsg.raw); + + if (ret_code == PXI_FIFO_FAIL_RECV_EMPTY) + { + break; + } + if (ret_code == PXI_FIFO_FAIL_RECV_ERR) + { + continue; + } + + tag = (PXIFifoTag)fifomsg.e.tag; + + if (tag) + { + if (FifoRecvCallbackTable[tag]) + { + (FifoRecvCallbackTable[tag])(tag, fifomsg.e.data, (BOOL)fifomsg.e.err); + } + else + { + if (fifomsg.e.err) + { + } + else + { + fifomsg.e.err = TRUE; + (void)PXIi_SetToFifo(fifomsg.raw); + } + } + } + else + { + } + } +} diff --git a/arm9/lib/src/PXI_init.c b/arm9/lib/src/PXI_init.c index f079ca3d..d70ca3b0 100644 --- a/arm9/lib/src/PXI_init.c +++ b/arm9/lib/src/PXI_init.c @@ -1,8 +1,7 @@ #include "PXI_init.h" +#include "PXI_fifo.h" #include "function_target.h" -extern void PXI_InitFifo(void); - ARM_FUNC void PXI_Init(void) { PXI_InitFifo(); diff --git a/arm9/lib/src/SND_command.c b/arm9/lib/src/SND_command.c index 130a4ebc..4ad80be5 100644 --- a/arm9/lib/src/SND_command.c +++ b/arm9/lib/src/SND_command.c @@ -18,11 +18,6 @@ static u32 sCurrentTag; static u32 sFinishedTag; static struct SNDCommand *sFreeList; -// TODO remove these function declarations once they are in the headers -extern s32 PXI_SendWordByFifo(u32, u32, u32); -extern void PXI_SetFifoRecvCallback(u32, void (*)(s32, s32)); -extern BOOL PXI_IsCallbackReady(u32, u32); - static void InitPXI(void); static void RequestCommandProc(void); static struct SNDCommand *AllocCommand(void); @@ -280,25 +275,25 @@ ARM_FUNC s32 SND_CountWaitingCommand(void) { return SND_CMD_COUNT - SND_CountFreeCommand() - SND_CountReservedCommand(); } -ARM_FUNC static void PxiFifoCallback(s32 a, s32 b) { -#pragma unused (a) +ARM_FUNC static void PxiFifoCallback(PXIFifoTag tag, u32 data, BOOL) { +#pragma unused (tag) OSIntrMode oldirq = OS_DisableInterrupts(); - SNDi_CallAlarmHandler(b); + SNDi_CallAlarmHandler((s32)data); (void)OS_RestoreInterrupts(oldirq); } ARM_FUNC static void InitPXI(void) { - PXI_SetFifoRecvCallback(7, PxiFifoCallback); + PXI_SetFifoRecvCallback(PXI_FIFO_TAG_SOUND, PxiFifoCallback); if (!IsCommandAvailable()) return; - if (PXI_IsCallbackReady(7, 1)) + if (PXI_IsCallbackReady(PXI_FIFO_TAG_SOUND, PXI_PROC_ARM7)) return; do { OS_SpinWait(100); - } while (!PXI_IsCallbackReady(7, 1)); + } while (!PXI_IsCallbackReady(PXI_FIFO_TAG_SOUND, PXI_PROC_ARM7)); } ARM_FUNC static void RequestCommandProc(void) { |