summaryrefslogtreecommitdiff
path: root/arm9/lib/NitroSDK/src/FX_cp.c
blob: 0c5d4ff885fec93a184deaaf1fe59233aa39725e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
#include "fx.h"

#include "global.h"
#include "registers.h"


ARM_FUNC fx32 FX_Div(fx32 numerator, fx32 denominator){
    FX_DivAsync(numerator, denominator);
    return FX_GetDivResult();
}

ARM_FUNC fx32 FX_Inv(fx32 x){
    FX_InvAsync(x);
    return FX_GetDivResult();
}

ARM_FUNC fx32 FX_Sqrt(fx32 x){
    if (x > 0)
    {
        reg_CP_SQRTCNT = 0x1;
        reg_CP_SQRT_PARAM = (u64)((fx64)x << 32);
        return FX_GetSqrtResult();
    }
    else
    {
        return 0;
    }
}

ARM_FUNC fx64c FX_GetDivResultFx64c(){
    while (reg_CP_DIVCNT & 0x8000) {}
    return (fx64c)reg_CP_DIV_RESULT;
}

ARM_FUNC fx32 FX_GetDivResult(){
    while (reg_CP_DIVCNT & 0x8000) {}
    return (fx32)((reg_CP_DIV_RESULT + (1 << (0x14 - 1))) >> 0x14);
}

ARM_FUNC void FX_InvAsync(fx32 x){
    reg_CP_DIVCNT = 0x1;
    reg_CP_DIV_NUMER = (fx64)0x00001000 << 32;
    reg_CP_DIV_DENOM = (u32)x;
}

ARM_FUNC fx32 FX_GetSqrtResult(){
    while (reg_CP_SQRTCNT & 0x8000) {}
    return (fx32)((reg_CP_SQRT_RESULT + (1 << (0xA - 1))) >> 0xA);
}

ARM_FUNC void FX_DivAsync(fx32 numerator, fx32 denominator){
    reg_CP_DIVCNT = 0x1;
    reg_CP_DIV_NUMER = (u64)((fx64)numerator << 32);
    reg_CP_DIV_DENOM = (u32)denominator;
}

ARM_FUNC fx32 FX_DivS32(fx32 numerator, fx32 denominator){
    reg_CP_DIVCNT = 0x0;
    *(REGType32v *)&reg_CP_DIV_NUMER = (u32)numerator; //32bit write for some reason
    reg_CP_DIV_DENOM = (u32)denominator;
    while (reg_CP_DIVCNT & 0x8000) {}
    return (fx32)(*(REGType32v *)&reg_CP_DIV_RESULT);
}

ARM_FUNC fx32 FX_ModS32(fx32 num, fx32 mod){
    reg_CP_DIVCNT = 0x0;
    *(REGType32v *)&reg_CP_DIV_NUMER = (u32)num; //32bit write for some reason
    reg_CP_DIV_DENOM = (u32)mod;
    while (reg_CP_DIVCNT & 0x8000) {}
    return (fx32)(*(REGType32v *)&reg_CP_DIVREM_RESULT);
}