add I/O register constants

2 files changed, 362 insertions, 26 deletions

diff --git a/asm/crt0.s b/asm/crt0.s
index b4044495c..6173a2f1a 100644
--- a/asm/crt0.s
+++ b/asm/crt0.s
@@ -40,63 +40,63 @@ sp_irq: .4byte IWRAM_END - 0x60
 
 	arm_func_start InterruptMain
 InterruptMain:
-	mov r3, 0x4000000
+	mov r3, REG_BASE
 	add r3, r3, 0x200
-	ldr r2, [r3]
-	ldrh r1, [r3, 0x8]
+	ldr r2, [r3, OFFSET_REG_IE - 0x200]
+	ldrh r1, [r3, OFFSET_REG_IME - 0x200]
 	mrs r0, spsr
 	stmdb sp!, {r0-r3,lr}
 	mov r0, 0
-	strh r0, [r3, 0x8]
+	strh r0, [r3, OFFSET_REG_IME - 0x200]
 	and r1, r2, r2, lsr 16
 	mov r12, 0
 	ands r0, r1, INTR_FLAG_VCOUNT
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	mov r0, 0x1
-	strh r0, [r3, 0x8]
+	strh r0, [r3, OFFSET_REG_IME - 0x200]
 	ands r0, r1, INTR_FLAG_SERIAL
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_TIMER3
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_HBLANK
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_VBLANK
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_TIMER0
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_TIMER1
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_TIMER2
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_DMA0
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_DMA1
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_DMA2
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_DMA3
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_KEYPAD
-	bne _08000320
+	bne @foundInterrupt
 	add r12, r12, 0x4
 	ands r0, r1, INTR_FLAG_GAMEPAK
-	strbne r0, [r3, -0x17C]
-_0800031C:
-	bne _0800031C
-_08000320:
-	strh r0, [r3, 0x2]
+	strbne r0, [r3, OFFSET_REG_SOUNDCNT_X - 0x200]
+@loop:
+	bne @loop
+@foundInterrupt:
+	strh r0, [r3, OFFSET_REG_IF - 0x200]
 	bic r2, r2, r0
 	ldr r0, =0x03007868
 	ldr r0, [r0]
@@ -106,7 +106,7 @@ _08000320:
 	orr r0, r0, INTR_FLAG_GAMEPAK
 	orr r1, r0, INTR_FLAG_SERIAL | INTR_FLAG_TIMER3 | INTR_FLAG_VCOUNT | INTR_FLAG_HBLANK
 	and r1, r1, r2
-	strh r1, [r3]
+	strh r1, [r3, OFFSET_REG_IE - 0x200]
 	mrs r3, cpsr
 	bic r3, r3, PSR_I_BIT | PSR_F_BIT | PSR_MODE_MASK
 	orr r3, r3, PSR_SYS_MODE
@@ -123,8 +123,8 @@ _08000320:
 	orr r3, r3, PSR_I_BIT | PSR_IRQ_MODE
 	msr cpsr_cf, r3
 	ldmia sp!, {r0-r3,lr}
-	strh r2, [r3]
-	strh r1, [r3, 0x8]
+	strh r2, [r3, OFFSET_REG_IE - 0x200]
+	strh r1, [r3, OFFSET_REG_IME - 0x200]
 	msr spsr_cf, r0
 	bx lr
 
diff --git a/constants/gba_constants.s b/constants/gba_constants.s
index a4f3e3291..ae2596e94 100644
--- a/constants/gba_constants.s
+++ b/constants/gba_constants.s
@@ -31,3 +31,339 @@
 	.set INTR_FLAG_DMA3,    1 << 11
 	.set INTR_FLAG_KEYPAD,  1 << 12
 	.set INTR_FLAG_GAMEPAK, 1 << 13
+
+	.set REG_BASE, 0x4000000 ; I/O register base address
+
+; I/O register offsets
+	.set OFFSET_REG_DISPCNT,     0x0
+	.set OFFSET_REG_DISPSTAT,    0x4
+	.set OFFSET_REG_VCOUNT,      0x6
+	.set OFFSET_REG_BG0CNT,      0x8
+	.set OFFSET_REG_BG1CNT,      0xa
+	.set OFFSET_REG_BG2CNT,      0xc
+	.set OFFSET_REG_BG3CNT,      0xe
+	.set OFFSET_REG_BG0HOFS,     0x10
+	.set OFFSET_REG_BG0VOFS,     0x12
+	.set OFFSET_REG_BG1HOFS,     0x14
+	.set OFFSET_REG_BG1VOFS,     0x16
+	.set OFFSET_REG_BG2HOFS,     0x18
+	.set OFFSET_REG_BG2VOFS,     0x1a
+	.set OFFSET_REG_BG3HOFS,     0x1c
+	.set OFFSET_REG_BG3VOFS,     0x1e
+	.set OFFSET_REG_BG2PA,       0x20
+	.set OFFSET_REG_BG2PB,       0x22
+	.set OFFSET_REG_BG2PC,       0x24
+	.set OFFSET_REG_BG2PD,       0x26
+	.set OFFSET_REG_BG2X_L,      0x28
+	.set OFFSET_REG_BG2X_H,      0x2a
+	.set OFFSET_REG_BG2Y_L,      0x2c
+	.set OFFSET_REG_BG2Y_H,      0x2e
+	.set OFFSET_REG_BG3PA,       0x30
+	.set OFFSET_REG_BG3PB,       0x32
+	.set OFFSET_REG_BG3PC,       0x34
+	.set OFFSET_REG_BG3PD,       0x36
+	.set OFFSET_REG_BG3X_L,      0x38
+	.set OFFSET_REG_BG3X_H,      0x3a
+	.set OFFSET_REG_BG3Y_L,      0x3c
+	.set OFFSET_REG_BG3Y_H,      0x3e
+	.set OFFSET_REG_WIN0H,       0x40
+	.set OFFSET_REG_WIN1H,       0x42
+	.set OFFSET_REG_WIN0V,       0x44
+	.set OFFSET_REG_WIN1V,       0x46
+	.set OFFSET_REG_WININ,       0x48
+	.set OFFSET_REG_WINOUT,      0x4a
+	.set OFFSET_REG_MOSAIC,      0x4c
+	.set OFFSET_REG_BLDCNT,      0x50
+	.set OFFSET_REG_BLDALPHA,    0x52
+	.set OFFSET_REG_BLDY,        0x54
+
+	.set OFFSET_REG_SOUND1CNT,   0x60
+	.set OFFSET_REG_SOUND1CNT_L, 0x60
+	.set OFFSET_REG_SOUND1CNT_H, 0x62
+	.set OFFSET_REG_SOUND1CNT_X, 0x64
+	.set OFFSET_REG_SOUND2CNT,   0x68
+	.set OFFSET_REG_SOUND2CNT_L, 0x68
+	.set OFFSET_REG_SOUND2CNT_H, 0x6c
+	.set OFFSET_REG_SOUND3CNT,   0x70
+	.set OFFSET_REG_SOUND3CNT_L, 0x70
+	.set OFFSET_REG_SOUND3CNT_H, 0x72
+	.set OFFSET_REG_SOUND3CNT_X, 0x74
+	.set OFFSET_REG_SOUND4CNT,   0x78
+	.set OFFSET_REG_SOUND4CNT_L, 0x78
+	.set OFFSET_REG_SOUND4CNT_H, 0x7c
+	.set OFFSET_REG_SOUNDCNT,    0x80
+	.set OFFSET_REG_SOUNDCNT_L,  0x80
+	.set OFFSET_REG_SOUNDCNT_H,  0x82
+	.set OFFSET_REG_SOUNDCNT_X,  0x84
+	.set OFFSET_REG_SOUNDBIAS,   0x88
+	.set OFFSET_REG_WAVE_RAM,    0x90
+	.set OFFSET_REG_WAVE_RAM0,   0x90
+	.set OFFSET_REG_WAVE_RAM0_L, 0x90
+	.set OFFSET_REG_WAVE_RAM0_H, 0x92
+	.set OFFSET_REG_WAVE_RAM1,   0x94
+	.set OFFSET_REG_WAVE_RAM1_L, 0x94
+	.set OFFSET_REG_WAVE_RAM1_H, 0x96
+	.set OFFSET_REG_WAVE_RAM2,   0x98
+	.set OFFSET_REG_WAVE_RAM2_L, 0x98
+	.set OFFSET_REG_WAVE_RAM2_H, 0x9a
+	.set OFFSET_REG_WAVE_RAM3,   0x9c
+	.set OFFSET_REG_WAVE_RAM3_L, 0x9c
+	.set OFFSET_REG_WAVE_RAM3_H, 0x9e
+	.set OFFSET_REG_FIFO,        0xa0
+	.set OFFSET_REG_FIFO_A,      0xa0
+	.set OFFSET_REG_FIFO_A_L,    0xa0
+	.set OFFSET_REG_FIFO_A_H,    0xa2
+	.set OFFSET_REG_FIFO_B,      0xa4
+	.set OFFSET_REG_FIFO_B_L,    0xa4
+	.set OFFSET_REG_FIFO_B_H,    0xa6
+
+	.set OFFSET_REG_DMA0,        0xb0
+	.set OFFSET_REG_DMA0SAD,     0xb0
+	.set OFFSET_REG_DMA0SAD_L,   0xb0
+	.set OFFSET_REG_DMA0SAD_H,   0xb2
+	.set OFFSET_REG_DMA0DAD,     0xb4
+	.set OFFSET_REG_DMA0DAD_L,   0xb4
+	.set OFFSET_REG_DMA0DAD_H,   0xb6
+	.set OFFSET_REG_DMA0CNT,     0xb8
+	.set OFFSET_REG_DMA0CNT_L,   0xb8
+	.set OFFSET_REG_DMA0CNT_H,   0xba
+	.set OFFSET_REG_DMA1,        0xbc
+	.set OFFSET_REG_DMA1SAD,     0xbc
+	.set OFFSET_REG_DMA1SAD_L,   0xbc
+	.set OFFSET_REG_DMA1SAD_H,   0xbe
+	.set OFFSET_REG_DMA1DAD,     0xc0
+	.set OFFSET_REG_DMA1DAD_L,   0xc0
+	.set OFFSET_REG_DMA1DAD_H,   0xc2
+	.set OFFSET_REG_DMA1CNT,     0xc4
+	.set OFFSET_REG_DMA1CNT_L,   0xc4
+	.set OFFSET_REG_DMA1CNT_H,   0xc6
+	.set OFFSET_REG_DMA2,        0xc8
+	.set OFFSET_REG_DMA2SAD,     0xc8
+	.set OFFSET_REG_DMA2SAD_L,   0xc8
+	.set OFFSET_REG_DMA2SAD_H,   0xca
+	.set OFFSET_REG_DMA2DAD,     0xcc
+	.set OFFSET_REG_DMA2DAD_L,   0xcc
+	.set OFFSET_REG_DMA2DAD_H,   0xce
+	.set OFFSET_REG_DMA2CNT,     0xd0
+	.set OFFSET_REG_DMA2CNT_L,   0xd0
+	.set OFFSET_REG_DMA2CNT_H,   0xd2
+	.set OFFSET_REG_DMA3,        0xd4
+	.set OFFSET_REG_DMA3SAD,     0xd4
+	.set OFFSET_REG_DMA3SAD_L,   0xd4
+	.set OFFSET_REG_DMA3SAD_H,   0xd6
+	.set OFFSET_REG_DMA3DAD,     0xd8
+	.set OFFSET_REG_DMA3DAD_L,   0xd8
+	.set OFFSET_REG_DMA3DAD_H,   0xda
+	.set OFFSET_REG_DMA3CNT,     0xdc
+	.set OFFSET_REG_DMA3CNT_L,   0xdc
+	.set OFFSET_REG_DMA3CNT_H,   0xde
+
+	.set OFFSET_REG_TM0CNT,      0x100
+	.set OFFSET_REG_TM0CNT_L,    0x100
+	.set OFFSET_REG_TM0CNT_H,    0x102
+	.set OFFSET_REG_TM1CNT,      0x104
+	.set OFFSET_REG_TM1CNT_L,    0x104
+	.set OFFSET_REG_TM1CNT_H,    0x106
+	.set OFFSET_REG_TM2CNT,      0x108
+	.set OFFSET_REG_TM2CNT_L,    0x108
+	.set OFFSET_REG_TM2CNT_H,    0x10a
+	.set OFFSET_REG_TM3CNT,      0x10c
+	.set OFFSET_REG_TM3CNT_L,    0x10c
+	.set OFFSET_REG_TM3CNT_H,    0x10e
+
+	.set OFFSET_REG_SIOCNT,      0x128
+	.set OFFSET_REG_SIODATA8,    0x12a
+	.set OFFSET_REG_SIODATA32,   0x120
+	.set OFFSET_REG_SIOMLT_SEND, 0x12a
+	.set OFFSET_REG_SIOMLT_RECV, 0x120
+	.set OFFSET_REG_SIOMULTI0,   0x120
+	.set OFFSET_REG_SIOMULTI1,   0x122
+	.set OFFSET_REG_SIOMULTI2,   0x124
+	.set OFFSET_REG_SIOMULTI3,   0x126
+
+	.set OFFSET_REG_KEYINPUT,    0x130
+	.set OFFSET_REG_KEYCNT,      0x132
+
+	.set OFFSET_REG_RCNT,        0x134
+
+	.set OFFSET_REG_JOYCNT,      0x140
+	.set OFFSET_REG_JOYSTAT,     0x158
+	.set OFFSET_REG_JOY_RECV,    0x150
+	.set OFFSET_REG_JOY_RECV_L,  0x150
+	.set OFFSET_REG_JOY_RECV_H,  0x152
+	.set OFFSET_REG_JOY_TRANS,   0x154
+	.set OFFSET_REG_JOY_TRANS_L, 0x154
+	.set OFFSET_REG_JOY_TRANS_H, 0x156
+
+	.set OFFSET_REG_IME,         0x208
+	.set OFFSET_REG_IE,          0x200
+	.set OFFSET_REG_IF,          0x202
+
+	.set OFFSET_REG_WAITCNT,     0x204
+
+; I/O register addresses
+	.set REG_DISPCNT,     REG_BASE + OFFSET_REG_DISPCNT
+	.set REG_DISPSTAT,    REG_BASE + OFFSET_REG_DISPSTAT
+	.set REG_VCOUNT,      REG_BASE + OFFSET_REG_VCOUNT
+	.set REG_BG0CNT,      REG_BASE + OFFSET_REG_BG0CNT
+	.set REG_BG1CNT,      REG_BASE + OFFSET_REG_BG1CNT
+	.set REG_BG2CNT,      REG_BASE + OFFSET_REG_BG2CNT
+	.set REG_BG3CNT,      REG_BASE + OFFSET_REG_BG3CNT
+	.set REG_BG0HOFS,     REG_BASE + OFFSET_REG_BG0HOFS
+	.set REG_BG0VOFS,     REG_BASE + OFFSET_REG_BG0VOFS
+	.set REG_BG1HOFS,     REG_BASE + OFFSET_REG_BG1HOFS
+	.set REG_BG1VOFS,     REG_BASE + OFFSET_REG_BG1VOFS
+	.set REG_BG2HOFS,     REG_BASE + OFFSET_REG_BG2HOFS
+	.set REG_BG2VOFS,     REG_BASE + OFFSET_REG_BG2VOFS
+	.set REG_BG3HOFS,     REG_BASE + OFFSET_REG_BG3HOFS
+	.set REG_BG3VOFS,     REG_BASE + OFFSET_REG_BG3VOFS
+	.set REG_BG2PA,       REG_BASE + OFFSET_REG_BG2PA
+	.set REG_BG2PB,       REG_BASE + OFFSET_REG_BG2PB
+	.set REG_BG2PC,       REG_BASE + OFFSET_REG_BG2PC
+	.set REG_BG2PD,       REG_BASE + OFFSET_REG_BG2PD
+	.set REG_BG2X_L,      REG_BASE + OFFSET_REG_BG2X_L
+	.set REG_BG2X_H,      REG_BASE + OFFSET_REG_BG2X_H
+	.set REG_BG2Y_L,      REG_BASE + OFFSET_REG_BG2Y_L
+	.set REG_BG2Y_H,      REG_BASE + OFFSET_REG_BG2Y_H
+	.set REG_BG3PA,       REG_BASE + OFFSET_REG_BG3PA
+	.set REG_BG3PB,       REG_BASE + OFFSET_REG_BG3PB
+	.set REG_BG3PC,       REG_BASE + OFFSET_REG_BG3PC
+	.set REG_BG3PD,       REG_BASE + OFFSET_REG_BG3PD
+	.set REG_BG3X_L,      REG_BASE + OFFSET_REG_BG3X_L
+	.set REG_BG3X_H,      REG_BASE + OFFSET_REG_BG3X_H
+	.set REG_BG3Y_L,      REG_BASE + OFFSET_REG_BG3Y_L
+	.set REG_BG3Y_H,      REG_BASE + OFFSET_REG_BG3Y_H
+	.set REG_WIN0H,       REG_BASE + OFFSET_REG_WIN0H
+	.set REG_WIN1H,       REG_BASE + OFFSET_REG_WIN1H
+	.set REG_WIN0V,       REG_BASE + OFFSET_REG_WIN0V
+	.set REG_WIN1V,       REG_BASE + OFFSET_REG_WIN1V
+	.set REG_WININ,       REG_BASE + OFFSET_REG_WININ
+	.set REG_WINOUT,      REG_BASE + OFFSET_REG_WINOUT
+	.set REG_MOSAIC,      REG_BASE + OFFSET_REG_MOSAIC
+	.set REG_BLDCNT,      REG_BASE + OFFSET_REG_BLDCNT
+	.set REG_BLDALPHA,    REG_BASE + OFFSET_REG_BLDALPHA
+	.set REG_BLDY,        REG_BASE + OFFSET_REG_BLDY
+
+	.set REG_SOUND1CNT,   REG_BASE + OFFSET_REG_SOUND1CNT
+	.set REG_SOUND1CNT_L, REG_BASE + OFFSET_REG_SOUND1CNT_L
+	.set REG_SOUND1CNT_H, REG_BASE + OFFSET_REG_SOUND1CNT_H
+	.set REG_SOUND1CNT_X, REG_BASE + OFFSET_REG_SOUND1CNT_X
+	.set REG_SOUND2CNT,   REG_BASE + OFFSET_REG_SOUND2CNT
+	.set REG_SOUND2CNT_L, REG_BASE + OFFSET_REG_SOUND2CNT_L
+	.set REG_SOUND2CNT_H, REG_BASE + OFFSET_REG_SOUND2CNT_H
+	.set REG_SOUND3CNT,   REG_BASE + OFFSET_REG_SOUND3CNT
+	.set REG_SOUND3CNT_L, REG_BASE + OFFSET_REG_SOUND3CNT_L
+	.set REG_SOUND3CNT_H, REG_BASE + OFFSET_REG_SOUND3CNT_H
+	.set REG_SOUND3CNT_X, REG_BASE + OFFSET_REG_SOUND3CNT_X
+	.set REG_SOUND4CNT,   REG_BASE + OFFSET_REG_SOUND4CNT
+	.set REG_SOUND4CNT_L, REG_BASE + OFFSET_REG_SOUND4CNT_L
+	.set REG_SOUND4CNT_H, REG_BASE + OFFSET_REG_SOUND4CNT_H
+	.set REG_SOUNDCNT,    REG_BASE + OFFSET_REG_SOUNDCNT
+	.set REG_SOUNDCNT_L,  REG_BASE + OFFSET_REG_SOUNDCNT_L
+	.set REG_SOUNDCNT_H,  REG_BASE + OFFSET_REG_SOUNDCNT_H
+	.set REG_SOUNDCNT_X,  REG_BASE + OFFSET_REG_SOUNDCNT_X
+	.set REG_SOUNDBIAS,   REG_BASE + OFFSET_REG_SOUNDBIAS
+	.set REG_WAVE_RAM,    REG_BASE + OFFSET_REG_WAVE_RAM
+	.set REG_WAVE_RAM0,   REG_BASE + OFFSET_REG_WAVE_RAM0
+	.set REG_WAVE_RAM0_L, REG_BASE + OFFSET_REG_WAVE_RAM0_L
+	.set REG_WAVE_RAM0_H, REG_BASE + OFFSET_REG_WAVE_RAM0_H
+	.set REG_WAVE_RAM1,   REG_BASE + OFFSET_REG_WAVE_RAM1
+	.set REG_WAVE_RAM1_L, REG_BASE + OFFSET_REG_WAVE_RAM1_L
+	.set REG_WAVE_RAM1_H, REG_BASE + OFFSET_REG_WAVE_RAM1_H
+	.set REG_WAVE_RAM2,   REG_BASE + OFFSET_REG_WAVE_RAM2
+	.set REG_WAVE_RAM2_L, REG_BASE + OFFSET_REG_WAVE_RAM2_L
+	.set REG_WAVE_RAM2_H, REG_BASE + OFFSET_REG_WAVE_RAM2_H
+	.set REG_WAVE_RAM3,   REG_BASE + OFFSET_REG_WAVE_RAM3
+	.set REG_WAVE_RAM3_L, REG_BASE + OFFSET_REG_WAVE_RAM3_L
+	.set REG_WAVE_RAM3_H, REG_BASE + OFFSET_REG_WAVE_RAM3_H
+	.set REG_FIFO,        REG_BASE + OFFSET_REG_FIFO
+	.set REG_FIFO_A,      REG_BASE + OFFSET_REG_FIFO_A
+	.set REG_FIFO_A_L,    REG_BASE + OFFSET_REG_FIFO_A_L
+	.set REG_FIFO_A_H,    REG_BASE + OFFSET_REG_FIFO_A_H
+	.set REG_FIFO_B,      REG_BASE + OFFSET_REG_FIFO_B
+	.set REG_FIFO_B_L,    REG_BASE + OFFSET_REG_FIFO_B_L
+	.set REG_FIFO_B_H,    REG_BASE + OFFSET_REG_FIFO_B_H
+
+	.set REG_DMA0,        REG_BASE + OFFSET_REG_DMA0
+	.set REG_DMA0SAD,     REG_BASE + OFFSET_REG_DMA0SAD
+	.set REG_DMA0SAD_L,   REG_BASE + OFFSET_REG_DMA0SAD_L
+	.set REG_DMA0SAD_H,   REG_BASE + OFFSET_REG_DMA0SAD_H
+	.set REG_DMA0DAD,     REG_BASE + OFFSET_REG_DMA0DAD
+	.set REG_DMA0DAD_L,   REG_BASE + OFFSET_REG_DMA0DAD_L
+	.set REG_DMA0DAD_H,   REG_BASE + OFFSET_REG_DMA0DAD_H
+	.set REG_DMA0CNT,     REG_BASE + OFFSET_REG_DMA0CNT
+	.set REG_DMA0CNT_L,   REG_BASE + OFFSET_REG_DMA0CNT_L
+	.set REG_DMA0CNT_H,   REG_BASE + OFFSET_REG_DMA0CNT_H
+	.set REG_DMA1,        REG_BASE + OFFSET_REG_DMA1
+	.set REG_DMA1SAD,     REG_BASE + OFFSET_REG_DMA1SAD
+	.set REG_DMA1SAD_L,   REG_BASE + OFFSET_REG_DMA1SAD_L
+	.set REG_DMA1SAD_H,   REG_BASE + OFFSET_REG_DMA1SAD_H
+	.set REG_DMA1DAD,     REG_BASE + OFFSET_REG_DMA1DAD
+	.set REG_DMA1DAD_L,   REG_BASE + OFFSET_REG_DMA1DAD_L
+	.set REG_DMA1DAD_H,   REG_BASE + OFFSET_REG_DMA1DAD_H
+	.set REG_DMA1CNT,     REG_BASE + OFFSET_REG_DMA1CNT
+	.set REG_DMA1CNT_L,   REG_BASE + OFFSET_REG_DMA1CNT_L
+	.set REG_DMA1CNT_H,   REG_BASE + OFFSET_REG_DMA1CNT_H
+	.set REG_DMA2,        REG_BASE + OFFSET_REG_DMA2
+	.set REG_DMA2SAD,     REG_BASE + OFFSET_REG_DMA2SAD
+	.set REG_DMA2SAD_L,   REG_BASE + OFFSET_REG_DMA2SAD_L
+	.set REG_DMA2SAD_H,   REG_BASE + OFFSET_REG_DMA2SAD_H
+	.set REG_DMA2DAD,     REG_BASE + OFFSET_REG_DMA2DAD
+	.set REG_DMA2DAD_L,   REG_BASE + OFFSET_REG_DMA2DAD_L
+	.set REG_DMA2DAD_H,   REG_BASE + OFFSET_REG_DMA2DAD_H
+	.set REG_DMA2CNT,     REG_BASE + OFFSET_REG_DMA2CNT
+	.set REG_DMA2CNT_L,   REG_BASE + OFFSET_REG_DMA2CNT_L
+	.set REG_DMA2CNT_H,   REG_BASE + OFFSET_REG_DMA2CNT_H
+	.set REG_DMA3,        REG_BASE + OFFSET_REG_DMA3
+	.set REG_DMA3SAD,     REG_BASE + OFFSET_REG_DMA3SAD
+	.set REG_DMA3SAD_L,   REG_BASE + OFFSET_REG_DMA3SAD_L
+	.set REG_DMA3SAD_H,   REG_BASE + OFFSET_REG_DMA3SAD_H
+	.set REG_DMA3DAD,     REG_BASE + OFFSET_REG_DMA3DAD
+	.set REG_DMA3DAD_L,   REG_BASE + OFFSET_REG_DMA3DAD_L
+	.set REG_DMA3DAD_H,   REG_BASE + OFFSET_REG_DMA3DAD_H
+	.set REG_DMA3CNT,     REG_BASE + OFFSET_REG_DMA3CNT
+	.set REG_DMA3CNT_L,   REG_BASE + OFFSET_REG_DMA3CNT_L
+	.set REG_DMA3CNT_H,   REG_BASE + OFFSET_REG_DMA3CNT_H
+
+	.set REG_TM0CNT,      REG_BASE + OFFSET_REG_TM0CNT
+	.set REG_TM0CNT_L,    REG_BASE + OFFSET_REG_TM0CNT_L
+	.set REG_TM0CNT_H,    REG_BASE + OFFSET_REG_TM0CNT_H
+	.set REG_TM1CNT,      REG_BASE + OFFSET_REG_TM1CNT
+	.set REG_TM1CNT_L,    REG_BASE + OFFSET_REG_TM1CNT_L
+	.set REG_TM1CNT_H,    REG_BASE + OFFSET_REG_TM1CNT_H
+	.set REG_TM2CNT,      REG_BASE + OFFSET_REG_TM2CNT
+	.set REG_TM2CNT_L,    REG_BASE + OFFSET_REG_TM2CNT_L
+	.set REG_TM2CNT_H,    REG_BASE + OFFSET_REG_TM2CNT_H
+	.set REG_TM3CNT,      REG_BASE + OFFSET_REG_TM3CNT
+	.set REG_TM3CNT_L,    REG_BASE + OFFSET_REG_TM3CNT_L
+	.set REG_TM3CNT_H,    REG_BASE + OFFSET_REG_TM3CNT_H
+
+	.set REG_SIOCNT,      REG_BASE + OFFSET_REG_SIOCNT
+	.set REG_SIODATA8,    REG_BASE + OFFSET_REG_SIODATA8
+	.set REG_SIODATA32,   REG_BASE + OFFSET_REG_SIODATA32
+	.set REG_SIOMLT_SEND, REG_BASE + OFFSET_REG_SIOMLT_SEND
+	.set REG_SIOMLT_RECV, REG_BASE + OFFSET_REG_SIOMLT_RECV
+	.set REG_SIOMULTI0,   REG_BASE + OFFSET_REG_SIOMULTI0
+	.set REG_SIOMULTI1,   REG_BASE + OFFSET_REG_SIOMULTI1
+	.set REG_SIOMULTI2,   REG_BASE + OFFSET_REG_SIOMULTI2
+	.set REG_SIOMULTI3,   REG_BASE + OFFSET_REG_SIOMULTI3
+
+	.set REG_KEYINPUT,    REG_BASE + OFFSET_REG_KEYINPUT
+	.set REG_KEYCNT,      REG_BASE + OFFSET_REG_KEYCNT
+
+	.set REG_RCNT,        REG_BASE + OFFSET_REG_RCNT
+
+	.set REG_JOYCNT,      REG_BASE + OFFSET_REG_JOYCNT
+	.set REG_JOYSTAT,     REG_BASE + OFFSET_REG_JOYSTAT
+	.set REG_JOY_RECV,    REG_BASE + OFFSET_REG_JOY_RECV
+	.set REG_JOY_RECV_L,  REG_BASE + OFFSET_REG_JOY_RECV_L
+	.set REG_JOY_RECV_H,  REG_BASE + OFFSET_REG_JOY_RECV_H
+	.set REG_JOY_TRANS,   REG_BASE + OFFSET_REG_JOY_TRANS
+	.set REG_JOY_TRANS_L, REG_BASE + OFFSET_REG_JOY_TRANS_L
+	.set REG_JOY_TRANS_H, REG_BASE + OFFSET_REG_JOY_TRANS_H
+
+	.set REG_IME,         REG_BASE + OFFSET_REG_IME
+	.set REG_IE,          REG_BASE + OFFSET_REG_IE
+	.set REG_IF,          REG_BASE + OFFSET_REG_IF
+
+	.set REG_WAITCNT,     REG_BASE + OFFSET_REG_WAITCNT