diff options
author | Revo <projectrevotpp@hotmail.com> | 2020-09-17 20:51:45 -0400 |
---|---|---|
committer | GitHub <noreply@github.com> | 2020-09-17 20:51:45 -0400 |
commit | ba1f2d9cb6e591f3017b80d958cd384cbe4d9c4e (patch) | |
tree | c7a8685104e8e4479500622245a4a23804eb1a54 /asm/init.s | |
parent | 198be57aa4c939285a31d9f148adf7e2de290dc1 (diff) | |
parent | 52dab146835fc519e8a01de393e82950641f2c0d (diff) |
Merge pull request #47 from red031000/master
split OSError, OSExec and __mem
Diffstat (limited to 'asm/init.s')
-rw-r--r-- | asm/init.s | 103 |
1 files changed, 1 insertions, 102 deletions
@@ -1,108 +1,7 @@ .include "macros.inc" - .section .init, "ax" # 0x80004000 - 0x800064E0 -.global memcpy -memcpy: -/* 80004000 00000100 7C 04 18 40 */ cmplw r4, r3 -/* 80004004 00000104 41 80 00 28 */ blt lbl_8000402C -/* 80004008 00000108 38 84 FF FF */ addi r4, r4, -1 -/* 8000400C 0000010C 38 C3 FF FF */ addi r6, r3, -1 -/* 80004010 00000110 38 A5 00 01 */ addi r5, r5, 1 -/* 80004014 00000114 48 00 00 0C */ b lbl_80004020 -lbl_80004018: -/* 80004018 00000118 8C 04 00 01 */ lbzu r0, 1(r4) -/* 8000401C 0000011C 9C 06 00 01 */ stbu r0, 1(r6) -lbl_80004020: -/* 80004020 00000120 34 A5 FF FF */ addic. r5, r5, -1 -/* 80004024 00000124 40 82 FF F4 */ bne lbl_80004018 -/* 80004028 00000128 4E 80 00 20 */ blr -lbl_8000402C: -/* 8000402C 0000012C 7C 84 2A 14 */ add r4, r4, r5 -/* 80004030 00000130 7C C3 2A 14 */ add r6, r3, r5 -/* 80004034 00000134 38 A5 00 01 */ addi r5, r5, 1 -/* 80004038 00000138 48 00 00 0C */ b lbl_80004044 -lbl_8000403C: -/* 8000403C 0000013C 8C 04 FF FF */ lbzu r0, -1(r4) -/* 80004040 00000140 9C 06 FF FF */ stbu r0, -1(r6) -lbl_80004044: -/* 80004044 00000144 34 A5 FF FF */ addic. r5, r5, -1 -/* 80004048 00000148 40 82 FF F4 */ bne lbl_8000403C -/* 8000404C 0000014C 4E 80 00 20 */ blr - -.global func_80004050 -func_80004050: -/* 80004050 00000150 28 05 00 20 */ cmplwi r5, 0x20 -/* 80004054 00000154 54 87 06 3E */ clrlwi r7, r4, 0x18 -/* 80004058 00000158 38 C3 FF FF */ addi r6, r3, -1 -/* 8000405C 0000015C 41 80 00 90 */ blt lbl_800040EC -/* 80004060 00000160 7C C0 30 F8 */ nor r0, r6, r6 -/* 80004064 00000164 54 00 07 BF */ clrlwi. r0, r0, 0x1e -/* 80004068 00000168 41 82 00 14 */ beq lbl_8000407C -/* 8000406C 0000016C 7C A0 28 50 */ subf r5, r0, r5 -lbl_80004070: -/* 80004070 00000170 34 00 FF FF */ addic. r0, r0, -1 -/* 80004074 00000174 9C E6 00 01 */ stbu r7, 1(r6) -/* 80004078 00000178 40 82 FF F8 */ bne lbl_80004070 -lbl_8000407C: -/* 8000407C 0000017C 2C 07 00 00 */ cmpwi r7, 0 -/* 80004080 00000180 41 82 00 1C */ beq lbl_8000409C -/* 80004084 00000184 54 E4 40 2E */ slwi r4, r7, 8 -/* 80004088 00000188 54 E3 C0 0E */ slwi r3, r7, 0x18 -/* 8000408C 0000018C 54 E0 80 1E */ slwi r0, r7, 0x10 -/* 80004090 00000190 7C E4 23 78 */ or r4, r7, r4 -/* 80004094 00000194 7C 60 03 78 */ or r0, r3, r0 -/* 80004098 00000198 7C 87 03 78 */ or r7, r4, r0 -lbl_8000409C: -/* 8000409C 0000019C 54 A0 D9 7F */ rlwinm. r0, r5, 0x1b, 5, 0x1f -/* 800040A0 000001A0 38 66 FF FD */ addi r3, r6, -3 -/* 800040A4 000001A4 41 82 00 2C */ beq lbl_800040D0 -lbl_800040A8: -/* 800040A8 000001A8 90 E3 00 04 */ stw r7, 4(r3) -/* 800040AC 000001AC 34 00 FF FF */ addic. r0, r0, -1 -/* 800040B0 000001B0 90 E3 00 08 */ stw r7, 8(r3) -/* 800040B4 000001B4 90 E3 00 0C */ stw r7, 0xc(r3) -/* 800040B8 000001B8 90 E3 00 10 */ stw r7, 0x10(r3) -/* 800040BC 000001BC 90 E3 00 14 */ stw r7, 0x14(r3) -/* 800040C0 000001C0 90 E3 00 18 */ stw r7, 0x18(r3) -/* 800040C4 000001C4 90 E3 00 1C */ stw r7, 0x1c(r3) -/* 800040C8 000001C8 94 E3 00 20 */ stwu r7, 0x20(r3) -/* 800040CC 000001CC 40 82 FF DC */ bne lbl_800040A8 -lbl_800040D0: -/* 800040D0 000001D0 54 A0 F7 7F */ rlwinm. r0, r5, 0x1e, 0x1d, 0x1f -/* 800040D4 000001D4 41 82 00 10 */ beq lbl_800040E4 -lbl_800040D8: -/* 800040D8 000001D8 34 00 FF FF */ addic. r0, r0, -1 -/* 800040DC 000001DC 94 E3 00 04 */ stwu r7, 4(r3) -/* 800040E0 000001E0 40 82 FF F8 */ bne lbl_800040D8 -lbl_800040E4: -/* 800040E4 000001E4 38 C3 00 03 */ addi r6, r3, 3 -/* 800040E8 000001E8 54 A5 07 BE */ clrlwi r5, r5, 0x1e -lbl_800040EC: -/* 800040EC 000001EC 2C 05 00 00 */ cmpwi r5, 0 -/* 800040F0 000001F0 4D 82 00 20 */ beqlr -lbl_800040F4: -/* 800040F4 000001F4 34 A5 FF FF */ addic. r5, r5, -1 -/* 800040F8 000001F8 9C E6 00 01 */ stbu r7, 1(r6) -/* 800040FC 000001FC 40 82 FF F8 */ bne lbl_800040F4 -/* 80004100 00000200 4E 80 00 20 */ blr - -.global func_80004104 -func_80004104: -/* 80004104 00000204 94 21 FF F0 */ stwu r1, -0x10(r1) -/* 80004108 00000208 7C 08 02 A6 */ mflr r0 -/* 8000410C 0000020C 90 01 00 14 */ stw r0, 0x14(r1) -/* 80004110 00000210 93 E1 00 0C */ stw r31, 0xc(r1) -/* 80004114 00000214 7C 7F 1B 78 */ mr r31, r3 -/* 80004118 00000218 4B FF FF 39 */ bl func_80004050 -/* 8000411C 0000021C 7F E3 FB 78 */ mr r3, r31 -/* 80004120 00000220 83 E1 00 0C */ lwz r31, 0xc(r1) -/* 80004124 00000224 80 01 00 14 */ lwz r0, 0x14(r1) -/* 80004128 00000228 7C 08 03 A6 */ mtlr r0 -/* 8000412C 0000022C 38 21 00 10 */ addi r1, r1, 0x10 -/* 80004130 00000230 4E 80 00 20 */ blr - .global TRK_memset TRK_memset: /* 80004134 00000234 94 21 FF F0 */ stwu r1, -0x10(r1) @@ -1731,7 +1630,7 @@ lbl_80006388: /* 80006394 00002494 80 7D 00 00 */ lwz r3, 0(r29) /* 80006398 00002498 41 82 00 0C */ beq lbl_800063A4 /* 8000639C 0000249C 38 80 00 00 */ li r4, 0 -/* 800063A0 000024A0 4B FF DD 65 */ bl func_80004104 +/* 800063A0 000024A0 4B FF DD 65 */ bl memset lbl_800063A4: /* 800063A4 000024A4 3B BD 00 08 */ addi r29, r29, 8 /* 800063A8 000024A8 4B FF FF E0 */ b lbl_80006388 |