path: root/asm/MetroTRK/msgbuf.s

.include "macros.inc"

.section .text, "ax"  # 0x80006980 - 0x803E1E60

.global TRKReadBuffer_ui32
TRKReadBuffer_ui32:
/* 801D4D08 001D0968  94 21 FF D0 */	stwu r1, -0x30(r1)
/* 801D4D0C 001D096C  7C 08 02 A6 */	mflr r0
/* 801D4D10 001D0970  3C C0 80 49 */	lis r6, lbl_8048EE18@ha
/* 801D4D14 001D0974  90 01 00 34 */	stw r0, 0x34(r1)
/* 801D4D18 001D0978  BF 01 00 10 */	stmw r24, 0x10(r1)
/* 801D4D1C 001D097C  7C 7C 1B 78 */	mr r28, r3
/* 801D4D20 001D0980  7C BD 2B 78 */	mr r29, r5
/* 801D4D24 001D0984  7C 9F 23 78 */	mr r31, r4
/* 801D4D28 001D0988  3B 66 EE 18 */	addi r27, r6, lbl_8048EE18@l
/* 801D4D2C 001D098C  3B C0 00 00 */	li r30, 0
/* 801D4D30 001D0990  38 60 00 00 */	li r3, 0
/* 801D4D34 001D0994  48 00 00 A0 */	b lbl_801D4DD4
lbl_801D4D38:
/* 801D4D38 001D0998  80 1B 00 00 */	lwz r0, 0(r27)
/* 801D4D3C 001D099C  2C 00 00 00 */	cmpwi r0, 0
/* 801D4D40 001D09A0  41 82 00 0C */	beq lbl_801D4D4C
/* 801D4D44 001D09A4  7F F9 FB 78 */	mr r25, r31
/* 801D4D48 001D09A8  48 00 00 08 */	b lbl_801D4D50
lbl_801D4D4C:
/* 801D4D4C 001D09AC  3B 21 00 08 */	addi r25, r1, 8
lbl_801D4D50:
/* 801D4D50 001D09B0  80 7C 00 0C */	lwz r3, 0xc(r28)
/* 801D4D54 001D09B4  3B 00 00 04 */	li r24, 4
/* 801D4D58 001D09B8  80 1C 00 08 */	lwz r0, 8(r28)
/* 801D4D5C 001D09BC  3B 40 00 00 */	li r26, 0
/* 801D4D60 001D09C0  7C 03 00 50 */	subf r0, r3, r0
/* 801D4D64 001D09C4  7C 18 00 40 */	cmplw r24, r0
/* 801D4D68 001D09C8  40 81 00 0C */	ble lbl_801D4D74
/* 801D4D6C 001D09CC  3B 40 03 02 */	li r26, 0x302
/* 801D4D70 001D09D0  7C 18 03 78 */	mr r24, r0
lbl_801D4D74:
/* 801D4D74 001D09D4  38 83 00 10 */	addi r4, r3, 0x10
/* 801D4D78 001D09D8  7F 23 CB 78 */	mr r3, r25
/* 801D4D7C 001D09DC  7F 05 C3 78 */	mr r5, r24
/* 801D4D80 001D09E0  7C 9C 22 14 */	add r4, r28, r4
/* 801D4D84 001D09E4  4B E2 F3 E1 */	bl TRK_memcpy
/* 801D4D88 001D09E8  80 1C 00 0C */	lwz r0, 0xc(r28)
/* 801D4D8C 001D09EC  7C 00 C2 14 */	add r0, r0, r24
/* 801D4D90 001D09F0  90 1C 00 0C */	stw r0, 0xc(r28)
/* 801D4D94 001D09F4  80 1B 00 00 */	lwz r0, 0(r27)
/* 801D4D98 001D09F8  2C 00 00 00 */	cmpwi r0, 0
/* 801D4D9C 001D09FC  40 82 00 2C */	bne lbl_801D4DC8
/* 801D4DA0 001D0A00  2C 1A 00 00 */	cmpwi r26, 0
/* 801D4DA4 001D0A04  40 82 00 24 */	bne lbl_801D4DC8
/* 801D4DA8 001D0A08  88 19 00 03 */	lbz r0, 3(r25)
/* 801D4DAC 001D0A0C  98 1F 00 00 */	stb r0, 0(r31)
/* 801D4DB0 001D0A10  88 19 00 02 */	lbz r0, 2(r25)
/* 801D4DB4 001D0A14  98 1F 00 01 */	stb r0, 1(r31)
/* 801D4DB8 001D0A18  88 19 00 01 */	lbz r0, 1(r25)
/* 801D4DBC 001D0A1C  98 1F 00 02 */	stb r0, 2(r31)
/* 801D4DC0 001D0A20  88 19 00 00 */	lbz r0, 0(r25)
/* 801D4DC4 001D0A24  98 1F 00 03 */	stb r0, 3(r31)
lbl_801D4DC8:
/* 801D4DC8 001D0A28  7F 43 D3 78 */	mr r3, r26
/* 801D4DCC 001D0A2C  3B FF 00 04 */	addi r31, r31, 4
/* 801D4DD0 001D0A30  3B DE 00 01 */	addi r30, r30, 1
lbl_801D4DD4:
/* 801D4DD4 001D0A34  2C 03 00 00 */	cmpwi r3, 0
/* 801D4DD8 001D0A38  40 82 00 0C */	bne lbl_801D4DE4
/* 801D4DDC 001D0A3C  7C 1E E8 00 */	cmpw r30, r29
/* 801D4DE0 001D0A40  41 80 FF 58 */	blt lbl_801D4D38
lbl_801D4DE4:
/* 801D4DE4 001D0A44  BB 01 00 10 */	lmw r24, 0x10(r1)
/* 801D4DE8 001D0A48  80 01 00 34 */	lwz r0, 0x34(r1)
/* 801D4DEC 001D0A4C  7C 08 03 A6 */	mtlr r0
/* 801D4DF0 001D0A50  38 21 00 30 */	addi r1, r1, 0x30
/* 801D4DF4 001D0A54  4E 80 00 20 */	blr

.global TRKReadBuffer_ui8
TRKReadBuffer_ui8:
/* 801D4DF8 001D0A58  94 21 FF E0 */	stwu r1, -0x20(r1)
/* 801D4DFC 001D0A5C  7C 08 02 A6 */	mflr r0
/* 801D4E00 001D0A60  90 01 00 24 */	stw r0, 0x24(r1)
/* 801D4E04 001D0A64  BF 41 00 08 */	stmw r26, 8(r1)
/* 801D4E08 001D0A68  7C 7A 1B 78 */	mr r26, r3
/* 801D4E0C 001D0A6C  7C 9B 23 78 */	mr r27, r4
/* 801D4E10 001D0A70  7C BC 2B 78 */	mr r28, r5
/* 801D4E14 001D0A74  3B A0 00 00 */	li r29, 0
/* 801D4E18 001D0A78  38 60 00 00 */	li r3, 0
/* 801D4E1C 001D0A7C  48 00 00 50 */	b lbl_801D4E6C
lbl_801D4E20:
/* 801D4E20 001D0A80  80 7A 00 0C */	lwz r3, 0xc(r26)
/* 801D4E24 001D0A84  3B C0 00 01 */	li r30, 1
/* 801D4E28 001D0A88  80 1A 00 08 */	lwz r0, 8(r26)
/* 801D4E2C 001D0A8C  3B E0 00 00 */	li r31, 0
/* 801D4E30 001D0A90  7C 03 00 50 */	subf r0, r3, r0
/* 801D4E34 001D0A94  7C 1E 00 40 */	cmplw r30, r0
/* 801D4E38 001D0A98  40 81 00 0C */	ble lbl_801D4E44
/* 801D4E3C 001D0A9C  3B E0 03 02 */	li r31, 0x302
/* 801D4E40 001D0AA0  7C 1E 03 78 */	mr r30, r0
lbl_801D4E44:
/* 801D4E44 001D0AA4  38 83 00 10 */	addi r4, r3, 0x10
/* 801D4E48 001D0AA8  7F C5 F3 78 */	mr r5, r30
/* 801D4E4C 001D0AAC  7C 7B EA 14 */	add r3, r27, r29
/* 801D4E50 001D0AB0  7C 9A 22 14 */	add r4, r26, r4
/* 801D4E54 001D0AB4  4B E2 F3 11 */	bl TRK_memcpy
/* 801D4E58 001D0AB8  80 1A 00 0C */	lwz r0, 0xc(r26)
/* 801D4E5C 001D0ABC  7F E3 FB 78 */	mr r3, r31
/* 801D4E60 001D0AC0  3B BD 00 01 */	addi r29, r29, 1
/* 801D4E64 001D0AC4  7C 00 F2 14 */	add r0, r0, r30
/* 801D4E68 001D0AC8  90 1A 00 0C */	stw r0, 0xc(r26)
lbl_801D4E6C:
/* 801D4E6C 001D0ACC  2C 03 00 00 */	cmpwi r3, 0
/* 801D4E70 001D0AD0  40 82 00 0C */	bne lbl_801D4E7C
/* 801D4E74 001D0AD4  7C 1D E0 00 */	cmpw r29, r28
/* 801D4E78 001D0AD8  41 80 FF A8 */	blt lbl_801D4E20
lbl_801D4E7C:
/* 801D4E7C 001D0ADC  BB 41 00 08 */	lmw r26, 8(r1)
/* 801D4E80 001D0AE0  80 01 00 24 */	lwz r0, 0x24(r1)
/* 801D4E84 001D0AE4  7C 08 03 A6 */	mtlr r0
/* 801D4E88 001D0AE8  38 21 00 20 */	addi r1, r1, 0x20
/* 801D4E8C 001D0AEC  4E 80 00 20 */	blr

.global TRKReadBuffer1_ui64
TRKReadBuffer1_ui64:
/* 801D4E90 001D0AF0  94 21 FF D0 */	stwu r1, -0x30(r1)
/* 801D4E94 001D0AF4  7C 08 02 A6 */	mflr r0
/* 801D4E98 001D0AF8  3C A0 80 49 */	lis r5, lbl_8048EE18@ha
/* 801D4E9C 001D0AFC  90 01 00 34 */	stw r0, 0x34(r1)
/* 801D4EA0 001D0B00  BF 61 00 1C */	stmw r27, 0x1c(r1)
/* 801D4EA4 001D0B04  7C 7B 1B 78 */	mr r27, r3
/* 801D4EA8 001D0B08  7C 9E 23 78 */	mr r30, r4
/* 801D4EAC 001D0B0C  80 05 EE 18 */	lwz r0, lbl_8048EE18@l(r5)
/* 801D4EB0 001D0B10  2C 00 00 00 */	cmpwi r0, 0
/* 801D4EB4 001D0B14  41 82 00 0C */	beq lbl_801D4EC0
/* 801D4EB8 001D0B18  7F DF F3 78 */	mr r31, r30
/* 801D4EBC 001D0B1C  48 00 00 08 */	b lbl_801D4EC4
lbl_801D4EC0:
/* 801D4EC0 001D0B20  3B E1 00 08 */	addi r31, r1, 8
lbl_801D4EC4:
/* 801D4EC4 001D0B24  80 7B 00 0C */	lwz r3, 0xc(r27)
/* 801D4EC8 001D0B28  3B 80 00 08 */	li r28, 8
/* 801D4ECC 001D0B2C  80 1B 00 08 */	lwz r0, 8(r27)
/* 801D4ED0 001D0B30  3B A0 00 00 */	li r29, 0
/* 801D4ED4 001D0B34  7C 03 00 50 */	subf r0, r3, r0
/* 801D4ED8 001D0B38  7C 1C 00 40 */	cmplw r28, r0
/* 801D4EDC 001D0B3C  40 81 00 0C */	ble lbl_801D4EE8
/* 801D4EE0 001D0B40  3B A0 03 02 */	li r29, 0x302
/* 801D4EE4 001D0B44  7C 1C 03 78 */	mr r28, r0
lbl_801D4EE8:
/* 801D4EE8 001D0B48  38 83 00 10 */	addi r4, r3, 0x10
/* 801D4EEC 001D0B4C  7F E3 FB 78 */	mr r3, r31
/* 801D4EF0 001D0B50  7F 85 E3 78 */	mr r5, r28
/* 801D4EF4 001D0B54  7C 9B 22 14 */	add r4, r27, r4
/* 801D4EF8 001D0B58  4B E2 F2 6D */	bl TRK_memcpy
/* 801D4EFC 001D0B5C  80 1B 00 0C */	lwz r0, 0xc(r27)
/* 801D4F00 001D0B60  3C 60 80 49 */	lis r3, lbl_8048EE18@ha
/* 801D4F04 001D0B64  7C 00 E2 14 */	add r0, r0, r28
/* 801D4F08 001D0B68  90 1B 00 0C */	stw r0, 0xc(r27)
/* 801D4F0C 001D0B6C  80 03 EE 18 */	lwz r0, lbl_8048EE18@l(r3)
/* 801D4F10 001D0B70  2C 00 00 00 */	cmpwi r0, 0
/* 801D4F14 001D0B74  40 82 00 4C */	bne lbl_801D4F60
/* 801D4F18 001D0B78  2C 1D 00 00 */	cmpwi r29, 0
/* 801D4F1C 001D0B7C  40 82 00 44 */	bne lbl_801D4F60
/* 801D4F20 001D0B80  88 1F 00 07 */	lbz r0, 7(r31)
/* 801D4F24 001D0B84  98 1E 00 00 */	stb r0, 0(r30)
/* 801D4F28 001D0B88  88 1F 00 06 */	lbz r0, 6(r31)
/* 801D4F2C 001D0B8C  98 1E 00 01 */	stb r0, 1(r30)
/* 801D4F30 001D0B90  88 1F 00 05 */	lbz r0, 5(r31)
/* 801D4F34 001D0B94  98 1E 00 02 */	stb r0, 2(r30)
/* 801D4F38 001D0B98  88 1F 00 04 */	lbz r0, 4(r31)
/* 801D4F3C 001D0B9C  98 1E 00 03 */	stb r0, 3(r30)
/* 801D4F40 001D0BA0  88 1F 00 03 */	lbz r0, 3(r31)
/* 801D4F44 001D0BA4  98 1E 00 04 */	stb r0, 4(r30)
/* 801D4F48 001D0BA8  88 1F 00 02 */	lbz r0, 2(r31)
/* 801D4F4C 001D0BAC  98 1E 00 05 */	stb r0, 5(r30)
/* 801D4F50 001D0BB0  88 1F 00 01 */	lbz r0, 1(r31)
/* 801D4F54 001D0BB4  98 1E 00 06 */	stb r0, 6(r30)
/* 801D4F58 001D0BB8  88 1F 00 00 */	lbz r0, 0(r31)
/* 801D4F5C 001D0BBC  98 1E 00 07 */	stb r0, 7(r30)
lbl_801D4F60:
/* 801D4F60 001D0BC0  7F A3 EB 78 */	mr r3, r29
/* 801D4F64 001D0BC4  BB 61 00 1C */	lmw r27, 0x1c(r1)
/* 801D4F68 001D0BC8  80 01 00 34 */	lwz r0, 0x34(r1)
/* 801D4F6C 001D0BCC  7C 08 03 A6 */	mtlr r0
/* 801D4F70 001D0BD0  38 21 00 30 */	addi r1, r1, 0x30
/* 801D4F74 001D0BD4  4E 80 00 20 */	blr

.global TRKAppendBuffer_ui32
TRKAppendBuffer_ui32:
/* 801D4F78 001D0BD8  94 21 FF D0 */	stwu r1, -0x30(r1)
/* 801D4F7C 001D0BDC  7C 08 02 A6 */	mflr r0
/* 801D4F80 001D0BE0  3C C0 80 49 */	lis r6, lbl_8048EE18@ha
/* 801D4F84 001D0BE4  90 01 00 34 */	stw r0, 0x34(r1)
/* 801D4F88 001D0BE8  BF 21 00 14 */	stmw r25, 0x14(r1)
/* 801D4F8C 001D0BEC  7C 7B 1B 78 */	mr r27, r3
/* 801D4F90 001D0BF0  7C BC 2B 78 */	mr r28, r5
/* 801D4F94 001D0BF4  7C 9E 23 78 */	mr r30, r4
/* 801D4F98 001D0BF8  3B E6 EE 18 */	addi r31, r6, lbl_8048EE18@l
/* 801D4F9C 001D0BFC  3B A0 00 00 */	li r29, 0
/* 801D4FA0 001D0C00  38 60 00 00 */	li r3, 0
/* 801D4FA4 001D0C04  48 00 00 AC */	b lbl_801D5050
lbl_801D4FA8:
/* 801D4FA8 001D0C08  80 1F 00 00 */	lwz r0, 0(r31)
/* 801D4FAC 001D0C0C  80 7E 00 00 */	lwz r3, 0(r30)
/* 801D4FB0 001D0C10  2C 00 00 00 */	cmpwi r0, 0
/* 801D4FB4 001D0C14  90 61 00 08 */	stw r3, 8(r1)
/* 801D4FB8 001D0C18  41 82 00 0C */	beq lbl_801D4FC4
/* 801D4FBC 001D0C1C  38 81 00 08 */	addi r4, r1, 8
/* 801D4FC0 001D0C20  48 00 00 28 */	b lbl_801D4FE8
lbl_801D4FC4:
/* 801D4FC4 001D0C24  88 C1 00 0B */	lbz r6, 0xb(r1)
/* 801D4FC8 001D0C28  38 81 00 0C */	addi r4, r1, 0xc
/* 801D4FCC 001D0C2C  88 A1 00 0A */	lbz r5, 0xa(r1)
/* 801D4FD0 001D0C30  88 61 00 09 */	lbz r3, 9(r1)
/* 801D4FD4 001D0C34  88 01 00 08 */	lbz r0, 8(r1)
/* 801D4FD8 001D0C38  98 C1 00 0C */	stb r6, 0xc(r1)
/* 801D4FDC 001D0C3C  98 A1 00 0D */	stb r5, 0xd(r1)
/* 801D4FE0 001D0C40  98 61 00 0E */	stb r3, 0xe(r1)
/* 801D4FE4 001D0C44  98 01 00 0F */	stb r0, 0xf(r1)
lbl_801D4FE8:
/* 801D4FE8 001D0C48  80 BB 00 0C */	lwz r5, 0xc(r27)
/* 801D4FEC 001D0C4C  3B 20 00 04 */	li r25, 4
/* 801D4FF0 001D0C50  3B 40 00 00 */	li r26, 0
/* 801D4FF4 001D0C54  20 05 08 80 */	subfic r0, r5, 0x880
/* 801D4FF8 001D0C58  28 00 00 04 */	cmplwi r0, 4
/* 801D4FFC 001D0C5C  40 80 00 0C */	bge lbl_801D5008
/* 801D5000 001D0C60  3B 40 03 01 */	li r26, 0x301
/* 801D5004 001D0C64  7C 19 03 78 */	mr r25, r0
lbl_801D5008:
/* 801D5008 001D0C68  28 19 00 01 */	cmplwi r25, 1
/* 801D500C 001D0C6C  40 82 00 14 */	bne lbl_801D5020
/* 801D5010 001D0C70  88 64 00 00 */	lbz r3, 0(r4)
/* 801D5014 001D0C74  38 05 00 10 */	addi r0, r5, 0x10
/* 801D5018 001D0C78  7C 7B 01 AE */	stbx r3, r27, r0
/* 801D501C 001D0C7C  48 00 00 14 */	b lbl_801D5030
lbl_801D5020:
/* 801D5020 001D0C80  38 65 00 10 */	addi r3, r5, 0x10
/* 801D5024 001D0C84  7F 25 CB 78 */	mr r5, r25
/* 801D5028 001D0C88  7C 7B 1A 14 */	add r3, r27, r3
/* 801D502C 001D0C8C  4B E2 F1 39 */	bl TRK_memcpy
lbl_801D5030:
/* 801D5030 001D0C90  80 1B 00 0C */	lwz r0, 0xc(r27)
/* 801D5034 001D0C94  7F 43 D3 78 */	mr r3, r26
/* 801D5038 001D0C98  3B DE 00 04 */	addi r30, r30, 4
/* 801D503C 001D0C9C  3B BD 00 01 */	addi r29, r29, 1
/* 801D5040 001D0CA0  7C 00 CA 14 */	add r0, r0, r25
/* 801D5044 001D0CA4  90 1B 00 0C */	stw r0, 0xc(r27)
/* 801D5048 001D0CA8  80 1B 00 0C */	lwz r0, 0xc(r27)
/* 801D504C 001D0CAC  90 1B 00 08 */	stw r0, 8(r27)
lbl_801D5050:
/* 801D5050 001D0CB0  2C 03 00 00 */	cmpwi r3, 0
/* 801D5054 001D0CB4  40 82 00 0C */	bne lbl_801D5060
/* 801D5058 001D0CB8  7C 1D E0 00 */	cmpw r29, r28
/* 801D505C 001D0CBC  41 80 FF 4C */	blt lbl_801D4FA8
lbl_801D5060:
/* 801D5060 001D0CC0  BB 21 00 14 */	lmw r25, 0x14(r1)
/* 801D5064 001D0CC4  80 01 00 34 */	lwz r0, 0x34(r1)
/* 801D5068 001D0CC8  7C 08 03 A6 */	mtlr r0
/* 801D506C 001D0CCC  38 21 00 30 */	addi r1, r1, 0x30
/* 801D5070 001D0CD0  4E 80 00 20 */	blr

.global TRKAppendBuffer_ui8
TRKAppendBuffer_ui8:
/* 801D5074 001D0CD4  39 20 00 00 */	li r9, 0
/* 801D5078 001D0CD8  38 00 00 00 */	li r0, 0
/* 801D507C 001D0CDC  48 00 00 48 */	b lbl_801D50C4
lbl_801D5080:
/* 801D5080 001D0CE0  80 E3 00 0C */	lwz r7, 0xc(r3)
/* 801D5084 001D0CE4  89 04 00 00 */	lbz r8, 0(r4)
/* 801D5088 001D0CE8  28 07 08 80 */	cmplwi r7, 0x880
/* 801D508C 001D0CEC  41 80 00 0C */	blt lbl_801D5098
/* 801D5090 001D0CF0  38 E0 03 01 */	li r7, 0x301
/* 801D5094 001D0CF4  48 00 00 24 */	b lbl_801D50B8
lbl_801D5098:
/* 801D5098 001D0CF8  38 C7 00 01 */	addi r6, r7, 1
/* 801D509C 001D0CFC  38 07 00 10 */	addi r0, r7, 0x10
/* 801D50A0 001D0D00  90 C3 00 0C */	stw r6, 0xc(r3)
/* 801D50A4 001D0D04  38 E0 00 00 */	li r7, 0
/* 801D50A8 001D0D08  7D 03 01 AE */	stbx r8, r3, r0
/* 801D50AC 001D0D0C  80 C3 00 08 */	lwz r6, 8(r3)
/* 801D50B0 001D0D10  38 06 00 01 */	addi r0, r6, 1
/* 801D50B4 001D0D14  90 03 00 08 */	stw r0, 8(r3)
lbl_801D50B8:
/* 801D50B8 001D0D18  7C E0 3B 78 */	mr r0, r7
/* 801D50BC 001D0D1C  39 29 00 01 */	addi r9, r9, 1
/* 801D50C0 001D0D20  38 84 00 01 */	addi r4, r4, 1
lbl_801D50C4:
/* 801D50C4 001D0D24  2C 00 00 00 */	cmpwi r0, 0
/* 801D50C8 001D0D28  40 82 00 0C */	bne lbl_801D50D4
/* 801D50CC 001D0D2C  7C 09 28 00 */	cmpw r9, r5
/* 801D50D0 001D0D30  41 80 FF B0 */	blt lbl_801D5080
lbl_801D50D4:
/* 801D50D4 001D0D34  7C 03 03 78 */	mr r3, r0
/* 801D50D8 001D0D38  4E 80 00 20 */	blr

.global TRKAppendBuffer1_ui64
TRKAppendBuffer1_ui64:
/* 801D50DC 001D0D3C  94 21 FF D0 */	stwu r1, -0x30(r1)
/* 801D50E0 001D0D40  7C 08 02 A6 */	mflr r0
/* 801D50E4 001D0D44  3C 80 80 49 */	lis r4, lbl_8048EE18@ha
/* 801D50E8 001D0D48  90 01 00 34 */	stw r0, 0x34(r1)
/* 801D50EC 001D0D4C  93 E1 00 2C */	stw r31, 0x2c(r1)
/* 801D50F0 001D0D50  7C 7F 1B 78 */	mr r31, r3
/* 801D50F4 001D0D54  93 C1 00 28 */	stw r30, 0x28(r1)
/* 801D50F8 001D0D58  93 A1 00 24 */	stw r29, 0x24(r1)
/* 801D50FC 001D0D5C  80 04 EE 18 */	lwz r0, lbl_8048EE18@l(r4)
/* 801D5100 001D0D60  90 A1 00 08 */	stw r5, 8(r1)
/* 801D5104 001D0D64  2C 00 00 00 */	cmpwi r0, 0
/* 801D5108 001D0D68  90 C1 00 0C */	stw r6, 0xc(r1)
/* 801D510C 001D0D6C  41 82 00 0C */	beq lbl_801D5118
/* 801D5110 001D0D70  38 81 00 08 */	addi r4, r1, 8
/* 801D5114 001D0D74  48 00 00 48 */	b lbl_801D515C
lbl_801D5118:
/* 801D5118 001D0D78  89 41 00 0F */	lbz r10, 0xf(r1)
/* 801D511C 001D0D7C  38 81 00 10 */	addi r4, r1, 0x10
/* 801D5120 001D0D80  89 21 00 0E */	lbz r9, 0xe(r1)
/* 801D5124 001D0D84  89 01 00 0D */	lbz r8, 0xd(r1)
/* 801D5128 001D0D88  88 E1 00 0C */	lbz r7, 0xc(r1)
/* 801D512C 001D0D8C  88 C1 00 0B */	lbz r6, 0xb(r1)
/* 801D5130 001D0D90  88 A1 00 0A */	lbz r5, 0xa(r1)
/* 801D5134 001D0D94  88 61 00 09 */	lbz r3, 9(r1)
/* 801D5138 001D0D98  88 01 00 08 */	lbz r0, 8(r1)
/* 801D513C 001D0D9C  99 41 00 10 */	stb r10, 0x10(r1)
/* 801D5140 001D0DA0  99 21 00 11 */	stb r9, 0x11(r1)
/* 801D5144 001D0DA4  99 01 00 12 */	stb r8, 0x12(r1)
/* 801D5148 001D0DA8  98 E1 00 13 */	stb r7, 0x13(r1)
/* 801D514C 001D0DAC  98 C1 00 14 */	stb r6, 0x14(r1)
/* 801D5150 001D0DB0  98 A1 00 15 */	stb r5, 0x15(r1)
/* 801D5154 001D0DB4  98 61 00 16 */	stb r3, 0x16(r1)
/* 801D5158 001D0DB8  98 01 00 17 */	stb r0, 0x17(r1)
lbl_801D515C:
/* 801D515C 001D0DBC  80 7F 00 0C */	lwz r3, 0xc(r31)
/* 801D5160 001D0DC0  3B A0 00 08 */	li r29, 8
/* 801D5164 001D0DC4  3B C0 00 00 */	li r30, 0
/* 801D5168 001D0DC8  20 03 08 80 */	subfic r0, r3, 0x880
/* 801D516C 001D0DCC  28 00 00 08 */	cmplwi r0, 8
/* 801D5170 001D0DD0  40 80 00 0C */	bge lbl_801D517C
/* 801D5174 001D0DD4  3B C0 03 01 */	li r30, 0x301
/* 801D5178 001D0DD8  7C 1D 03 78 */	mr r29, r0
lbl_801D517C:
/* 801D517C 001D0DDC  28 1D 00 01 */	cmplwi r29, 1
/* 801D5180 001D0DE0  40 82 00 14 */	bne lbl_801D5194
/* 801D5184 001D0DE4  88 04 00 00 */	lbz r0, 0(r4)
/* 801D5188 001D0DE8  7C 7F 1A 14 */	add r3, r31, r3
/* 801D518C 001D0DEC  98 03 00 10 */	stb r0, 0x10(r3)
/* 801D5190 001D0DF0  48 00 00 14 */	b lbl_801D51A4
lbl_801D5194:
/* 801D5194 001D0DF4  38 63 00 10 */	addi r3, r3, 0x10
/* 801D5198 001D0DF8  7F A5 EB 78 */	mr r5, r29
/* 801D519C 001D0DFC  7C 7F 1A 14 */	add r3, r31, r3
/* 801D51A0 001D0E00  4B E2 EF C5 */	bl TRK_memcpy
lbl_801D51A4:
/* 801D51A4 001D0E04  80 1F 00 0C */	lwz r0, 0xc(r31)
/* 801D51A8 001D0E08  7F C3 F3 78 */	mr r3, r30
/* 801D51AC 001D0E0C  7C 00 EA 14 */	add r0, r0, r29
/* 801D51B0 001D0E10  90 1F 00 0C */	stw r0, 0xc(r31)
/* 801D51B4 001D0E14  80 1F 00 0C */	lwz r0, 0xc(r31)
/* 801D51B8 001D0E18  90 1F 00 08 */	stw r0, 8(r31)
/* 801D51BC 001D0E1C  83 E1 00 2C */	lwz r31, 0x2c(r1)
/* 801D51C0 001D0E20  83 C1 00 28 */	lwz r30, 0x28(r1)
/* 801D51C4 001D0E24  83 A1 00 24 */	lwz r29, 0x24(r1)
/* 801D51C8 001D0E28  80 01 00 34 */	lwz r0, 0x34(r1)
/* 801D51CC 001D0E2C  7C 08 03 A6 */	mtlr r0
/* 801D51D0 001D0E30  38 21 00 30 */	addi r1, r1, 0x30
/* 801D51D4 001D0E34  4E 80 00 20 */	blr

.global TRKReadBuffer
TRKReadBuffer:
/* 801D51D8 001D0E38  94 21 FF E0 */	stwu r1, -0x20(r1)
/* 801D51DC 001D0E3C  7C 08 02 A6 */	mflr r0
/* 801D51E0 001D0E40  90 01 00 24 */	stw r0, 0x24(r1)
/* 801D51E4 001D0E44  93 E1 00 1C */	stw r31, 0x1c(r1)
/* 801D51E8 001D0E48  3B E0 00 00 */	li r31, 0
/* 801D51EC 001D0E4C  93 C1 00 18 */	stw r30, 0x18(r1)
/* 801D51F0 001D0E50  7C BE 2B 79 */	or. r30, r5, r5
/* 801D51F4 001D0E54  93 A1 00 14 */	stw r29, 0x14(r1)
/* 801D51F8 001D0E58  7C 7D 1B 78 */	mr r29, r3
/* 801D51FC 001D0E5C  7C 83 23 78 */	mr r3, r4
/* 801D5200 001D0E60  40 82 00 0C */	bne lbl_801D520C
/* 801D5204 001D0E64  38 60 00 00 */	li r3, 0
/* 801D5208 001D0E68  48 00 00 40 */	b lbl_801D5248
lbl_801D520C:
/* 801D520C 001D0E6C  80 9D 00 0C */	lwz r4, 0xc(r29)
/* 801D5210 001D0E70  80 1D 00 08 */	lwz r0, 8(r29)
/* 801D5214 001D0E74  7C 04 00 50 */	subf r0, r4, r0
/* 801D5218 001D0E78  7C 1E 00 40 */	cmplw r30, r0
/* 801D521C 001D0E7C  40 81 00 0C */	ble lbl_801D5228
/* 801D5220 001D0E80  3B E0 03 02 */	li r31, 0x302
/* 801D5224 001D0E84  7C 1E 03 78 */	mr r30, r0
lbl_801D5228:
/* 801D5228 001D0E88  38 84 00 10 */	addi r4, r4, 0x10
/* 801D522C 001D0E8C  7F C5 F3 78 */	mr r5, r30
/* 801D5230 001D0E90  7C 9D 22 14 */	add r4, r29, r4
/* 801D5234 001D0E94  4B E2 EF 31 */	bl TRK_memcpy
/* 801D5238 001D0E98  80 1D 00 0C */	lwz r0, 0xc(r29)
/* 801D523C 001D0E9C  7F E3 FB 78 */	mr r3, r31
/* 801D5240 001D0EA0  7C 00 F2 14 */	add r0, r0, r30
/* 801D5244 001D0EA4  90 1D 00 0C */	stw r0, 0xc(r29)
lbl_801D5248:
/* 801D5248 001D0EA8  80 01 00 24 */	lwz r0, 0x24(r1)
/* 801D524C 001D0EAC  83 E1 00 1C */	lwz r31, 0x1c(r1)
/* 801D5250 001D0EB0  83 C1 00 18 */	lwz r30, 0x18(r1)
/* 801D5254 001D0EB4  83 A1 00 14 */	lwz r29, 0x14(r1)
/* 801D5258 001D0EB8  7C 08 03 A6 */	mtlr r0
/* 801D525C 001D0EBC  38 21 00 20 */	addi r1, r1, 0x20
/* 801D5260 001D0EC0  4E 80 00 20 */	blr

.global TRKAppendBuffer
TRKAppendBuffer:
/* 801D5264 001D0EC4  94 21 FF E0 */	stwu r1, -0x20(r1)
/* 801D5268 001D0EC8  7C 08 02 A6 */	mflr r0
/* 801D526C 001D0ECC  90 01 00 24 */	stw r0, 0x24(r1)
/* 801D5270 001D0ED0  93 E1 00 1C */	stw r31, 0x1c(r1)
/* 801D5274 001D0ED4  3B E0 00 00 */	li r31, 0
/* 801D5278 001D0ED8  93 C1 00 18 */	stw r30, 0x18(r1)
/* 801D527C 001D0EDC  7C BE 2B 79 */	or. r30, r5, r5
/* 801D5280 001D0EE0  93 A1 00 14 */	stw r29, 0x14(r1)
/* 801D5284 001D0EE4  7C 7D 1B 78 */	mr r29, r3
/* 801D5288 001D0EE8  40 82 00 0C */	bne lbl_801D5294
/* 801D528C 001D0EEC  38 60 00 00 */	li r3, 0
/* 801D5290 001D0EF0  48 00 00 5C */	b lbl_801D52EC
lbl_801D5294:
/* 801D5294 001D0EF4  80 7D 00 0C */	lwz r3, 0xc(r29)
/* 801D5298 001D0EF8  20 03 08 80 */	subfic r0, r3, 0x880
/* 801D529C 001D0EFC  7C 00 F0 40 */	cmplw r0, r30
/* 801D52A0 001D0F00  40 80 00 0C */	bge lbl_801D52AC
/* 801D52A4 001D0F04  3B E0 03 01 */	li r31, 0x301
/* 801D52A8 001D0F08  7C 1E 03 78 */	mr r30, r0
lbl_801D52AC:
/* 801D52AC 001D0F0C  28 1E 00 01 */	cmplwi r30, 1
/* 801D52B0 001D0F10  40 82 00 14 */	bne lbl_801D52C4
/* 801D52B4 001D0F14  88 04 00 00 */	lbz r0, 0(r4)
/* 801D52B8 001D0F18  7C 7D 1A 14 */	add r3, r29, r3
/* 801D52BC 001D0F1C  98 03 00 10 */	stb r0, 0x10(r3)
/* 801D52C0 001D0F20  48 00 00 14 */	b lbl_801D52D4
lbl_801D52C4:
/* 801D52C4 001D0F24  38 63 00 10 */	addi r3, r3, 0x10
/* 801D52C8 001D0F28  7F C5 F3 78 */	mr r5, r30
/* 801D52CC 001D0F2C  7C 7D 1A 14 */	add r3, r29, r3
/* 801D52D0 001D0F30  4B E2 EE 95 */	bl TRK_memcpy
lbl_801D52D4:
/* 801D52D4 001D0F34  80 1D 00 0C */	lwz r0, 0xc(r29)
/* 801D52D8 001D0F38  7F E3 FB 78 */	mr r3, r31
/* 801D52DC 001D0F3C  7C 00 F2 14 */	add r0, r0, r30
/* 801D52E0 001D0F40  90 1D 00 0C */	stw r0, 0xc(r29)
/* 801D52E4 001D0F44  80 1D 00 0C */	lwz r0, 0xc(r29)
/* 801D52E8 001D0F48  90 1D 00 08 */	stw r0, 8(r29)
lbl_801D52EC:
/* 801D52EC 001D0F4C  80 01 00 24 */	lwz r0, 0x24(r1)
/* 801D52F0 001D0F50  83 E1 00 1C */	lwz r31, 0x1c(r1)
/* 801D52F4 001D0F54  83 C1 00 18 */	lwz r30, 0x18(r1)
/* 801D52F8 001D0F58  83 A1 00 14 */	lwz r29, 0x14(r1)
/* 801D52FC 001D0F5C  7C 08 03 A6 */	mtlr r0
/* 801D5300 001D0F60  38 21 00 20 */	addi r1, r1, 0x20
/* 801D5304 001D0F64  4E 80 00 20 */	blr

.global TRKSetBufferPosition
TRKSetBufferPosition:
/* 801D5308 001D0F68  28 04 08 80 */	cmplwi r4, 0x880
/* 801D530C 001D0F6C  38 A0 00 00 */	li r5, 0
/* 801D5310 001D0F70  40 81 00 0C */	ble lbl_801D531C
/* 801D5314 001D0F74  38 A0 03 01 */	li r5, 0x301
/* 801D5318 001D0F78  48 00 00 18 */	b lbl_801D5330
lbl_801D531C:
/* 801D531C 001D0F7C  90 83 00 0C */	stw r4, 0xc(r3)
/* 801D5320 001D0F80  80 03 00 08 */	lwz r0, 8(r3)
/* 801D5324 001D0F84  7C 04 00 40 */	cmplw r4, r0
/* 801D5328 001D0F88  40 81 00 08 */	ble lbl_801D5330
/* 801D532C 001D0F8C  90 83 00 08 */	stw r4, 8(r3)
lbl_801D5330:
/* 801D5330 001D0F90  7C A3 2B 78 */	mr r3, r5
/* 801D5334 001D0F94  4E 80 00 20 */	blr

.global TRKResetBuffer
TRKResetBuffer:
/* 801D5338 001D0F98  94 21 FF F0 */	stwu r1, -0x10(r1)
/* 801D533C 001D0F9C  7C 08 02 A6 */	mflr r0
/* 801D5340 001D0FA0  2C 04 00 00 */	cmpwi r4, 0
/* 801D5344 001D0FA4  90 01 00 14 */	stw r0, 0x14(r1)
/* 801D5348 001D0FA8  38 00 00 00 */	li r0, 0
/* 801D534C 001D0FAC  90 03 00 08 */	stw r0, 8(r3)
/* 801D5350 001D0FB0  90 03 00 0C */	stw r0, 0xc(r3)
/* 801D5354 001D0FB4  40 82 00 14 */	bne lbl_801D5368
/* 801D5358 001D0FB8  38 63 00 10 */	addi r3, r3, 0x10
/* 801D535C 001D0FBC  38 80 00 00 */	li r4, 0
/* 801D5360 001D0FC0  38 A0 08 80 */	li r5, 0x880
/* 801D5364 001D0FC4  4B E2 ED D1 */	bl TRK_memset
lbl_801D5368:
/* 801D5368 001D0FC8  80 01 00 14 */	lwz r0, 0x14(r1)
/* 801D536C 001D0FCC  7C 08 03 A6 */	mtlr r0
/* 801D5370 001D0FD0  38 21 00 10 */	addi r1, r1, 0x10
/* 801D5374 001D0FD4  4E 80 00 20 */	blr

.global TRKReleaseBuffer
TRKReleaseBuffer:
/* 801D5378 001D0FD8  94 21 FF F0 */	stwu r1, -0x10(r1)
/* 801D537C 001D0FDC  7C 08 02 A6 */	mflr r0
/* 801D5380 001D0FE0  2C 03 FF FF */	cmpwi r3, -1
/* 801D5384 001D0FE4  90 01 00 14 */	stw r0, 0x14(r1)
/* 801D5388 001D0FE8  93 E1 00 0C */	stw r31, 0xc(r1)
/* 801D538C 001D0FEC  41 82 00 3C */	beq lbl_801D53C8
/* 801D5390 001D0FF0  2C 03 00 00 */	cmpwi r3, 0
/* 801D5394 001D0FF4  41 80 00 34 */	blt lbl_801D53C8
/* 801D5398 001D0FF8  2C 03 00 03 */	cmpwi r3, 3
/* 801D539C 001D0FFC  40 80 00 2C */	bge lbl_801D53C8
/* 801D53A0 001D1000  1C 83 08 90 */	mulli r4, r3, 0x890
/* 801D53A4 001D1004  3C 60 80 49 */	lis r3, lbl_8048EE20@ha
/* 801D53A8 001D1008  38 03 EE 20 */	addi r0, r3, lbl_8048EE20@l
/* 801D53AC 001D100C  7F E0 22 14 */	add r31, r0, r4
/* 801D53B0 001D1010  7F E3 FB 78 */	mr r3, r31
/* 801D53B4 001D1014  48 00 1C A9 */	bl TRKAcquireMutex
/* 801D53B8 001D1018  38 00 00 00 */	li r0, 0
/* 801D53BC 001D101C  7F E3 FB 78 */	mr r3, r31
/* 801D53C0 001D1020  90 1F 00 04 */	stw r0, 4(r31)
/* 801D53C4 001D1024  48 00 1C 91 */	bl TRKReleaseMutex
lbl_801D53C8:
/* 801D53C8 001D1028  80 01 00 14 */	lwz r0, 0x14(r1)
/* 801D53CC 001D102C  83 E1 00 0C */	lwz r31, 0xc(r1)
/* 801D53D0 001D1030  7C 08 03 A6 */	mtlr r0
/* 801D53D4 001D1034  38 21 00 10 */	addi r1, r1, 0x10
/* 801D53D8 001D1038  4E 80 00 20 */	blr

.global TRKGetBuffer
TRKGetBuffer:
/* 801D53DC 001D103C  2C 03 00 00 */	cmpwi r3, 0
/* 801D53E0 001D1040  38 00 00 00 */	li r0, 0
/* 801D53E4 001D1044  41 80 00 1C */	blt lbl_801D5400
/* 801D53E8 001D1048  2C 03 00 03 */	cmpwi r3, 3
/* 801D53EC 001D104C  40 80 00 14 */	bge lbl_801D5400
/* 801D53F0 001D1050  1C 83 08 90 */	mulli r4, r3, 0x890
/* 801D53F4 001D1054  3C 60 80 49 */	lis r3, lbl_8048EE20@ha
/* 801D53F8 001D1058  38 03 EE 20 */	addi r0, r3, lbl_8048EE20@l
/* 801D53FC 001D105C  7C 00 22 14 */	add r0, r0, r4
lbl_801D5400:
/* 801D5400 001D1060  7C 03 03 78 */	mr r3, r0
/* 801D5404 001D1064  4E 80 00 20 */	blr

.global TRKGetFreeBuffer
TRKGetFreeBuffer:
/* 801D5408 001D1068  94 21 FF E0 */	stwu r1, -0x20(r1)
/* 801D540C 001D106C  7C 08 02 A6 */	mflr r0
/* 801D5410 001D1070  90 01 00 24 */	stw r0, 0x24(r1)
/* 801D5414 001D1074  38 00 00 00 */	li r0, 0
/* 801D5418 001D1078  BF 61 00 0C */	stmw r27, 0xc(r1)
/* 801D541C 001D107C  7C 9C 23 78 */	mr r28, r4
/* 801D5420 001D1080  7C 7B 1B 78 */	mr r27, r3
/* 801D5424 001D1084  3B C0 03 00 */	li r30, 0x300
/* 801D5428 001D1088  3B A0 00 00 */	li r29, 0
/* 801D542C 001D108C  90 04 00 00 */	stw r0, 0(r4)
/* 801D5430 001D1090  48 00 00 6C */	b lbl_801D549C
lbl_801D5434:
/* 801D5434 001D1094  2C 1D 00 00 */	cmpwi r29, 0
/* 801D5438 001D1098  3B E0 00 00 */	li r31, 0
/* 801D543C 001D109C  41 80 00 1C */	blt lbl_801D5458
/* 801D5440 001D10A0  2C 1D 00 03 */	cmpwi r29, 3
/* 801D5444 001D10A4  40 80 00 14 */	bge lbl_801D5458
/* 801D5448 001D10A8  1C 9D 08 90 */	mulli r4, r29, 0x890
/* 801D544C 001D10AC  3C 60 80 49 */	lis r3, lbl_8048EE20@ha
/* 801D5450 001D10B0  38 03 EE 20 */	addi r0, r3, lbl_8048EE20@l
/* 801D5454 001D10B4  7F E0 22 14 */	add r31, r0, r4
lbl_801D5458:
/* 801D5458 001D10B8  7F E3 FB 78 */	mr r3, r31
/* 801D545C 001D10BC  48 00 1C 01 */	bl TRKAcquireMutex
/* 801D5460 001D10C0  80 1F 00 04 */	lwz r0, 4(r31)
/* 801D5464 001D10C4  2C 00 00 00 */	cmpwi r0, 0
/* 801D5468 001D10C8  40 82 00 28 */	bne lbl_801D5490
/* 801D546C 001D10CC  38 60 00 00 */	li r3, 0
/* 801D5470 001D10D0  38 00 00 01 */	li r0, 1
/* 801D5474 001D10D4  90 7F 00 08 */	stw r3, 8(r31)
/* 801D5478 001D10D8  3B C0 00 00 */	li r30, 0
/* 801D547C 001D10DC  90 7F 00 0C */	stw r3, 0xc(r31)
/* 801D5480 001D10E0  90 1F 00 04 */	stw r0, 4(r31)
/* 801D5484 001D10E4  93 FC 00 00 */	stw r31, 0(r28)
/* 801D5488 001D10E8  93 BB 00 00 */	stw r29, 0(r27)
/* 801D548C 001D10EC  3B A0 00 03 */	li r29, 3
lbl_801D5490:
/* 801D5490 001D10F0  7F E3 FB 78 */	mr r3, r31
/* 801D5494 001D10F4  48 00 1B C1 */	bl TRKReleaseMutex
/* 801D5498 001D10F8  3B BD 00 01 */	addi r29, r29, 1
lbl_801D549C:
/* 801D549C 001D10FC  2C 1D 00 03 */	cmpwi r29, 3
/* 801D54A0 001D1100  41 80 FF 94 */	blt lbl_801D5434
/* 801D54A4 001D1104  2C 1E 03 00 */	cmpwi r30, 0x300
/* 801D54A8 001D1108  40 82 00 10 */	bne lbl_801D54B8
/* 801D54AC 001D110C  3C 60 80 40 */	lis r3, lbl_803FD660@ha
/* 801D54B0 001D1110  38 63 D6 60 */	addi r3, r3, lbl_803FD660@l
/* 801D54B4 001D1114  48 00 02 41 */	bl usr_puts_serial
lbl_801D54B8:
/* 801D54B8 001D1118  7F C3 F3 78 */	mr r3, r30
/* 801D54BC 001D111C  BB 61 00 0C */	lmw r27, 0xc(r1)
/* 801D54C0 001D1120  80 01 00 24 */	lwz r0, 0x24(r1)
/* 801D54C4 001D1124  7C 08 03 A6 */	mtlr r0
/* 801D54C8 001D1128  38 21 00 20 */	addi r1, r1, 0x20
/* 801D54CC 001D112C  4E 80 00 20 */	blr

.global TRKInitializeMessageBuffers
TRKInitializeMessageBuffers:
/* 801D54D0 001D1130  94 21 FF E0 */	stwu r1, -0x20(r1)
/* 801D54D4 001D1134  7C 08 02 A6 */	mflr r0
/* 801D54D8 001D1138  3C 60 80 49 */	lis r3, lbl_8048EE20@ha
/* 801D54DC 001D113C  90 01 00 24 */	stw r0, 0x24(r1)
/* 801D54E0 001D1140  93 E1 00 1C */	stw r31, 0x1c(r1)
/* 801D54E4 001D1144  3B E0 00 00 */	li r31, 0
/* 801D54E8 001D1148  93 C1 00 18 */	stw r30, 0x18(r1)
/* 801D54EC 001D114C  3B C3 EE 20 */	addi r30, r3, lbl_8048EE20@l
/* 801D54F0 001D1150  93 A1 00 14 */	stw r29, 0x14(r1)
/* 801D54F4 001D1154  3B A0 00 00 */	li r29, 0
lbl_801D54F8:
/* 801D54F8 001D1158  7F C3 F3 78 */	mr r3, r30
/* 801D54FC 001D115C  48 00 1B 69 */	bl TRKInitializeMutex
/* 801D5500 001D1160  7F C3 F3 78 */	mr r3, r30
/* 801D5504 001D1164  48 00 1B 59 */	bl TRKAcquireMutex
/* 801D5508 001D1168  93 FE 00 04 */	stw r31, 4(r30)
/* 801D550C 001D116C  7F C3 F3 78 */	mr r3, r30
/* 801D5510 001D1170  48 00 1B 45 */	bl TRKReleaseMutex
/* 801D5514 001D1174  3B BD 00 01 */	addi r29, r29, 1
/* 801D5518 001D1178  3B DE 08 90 */	addi r30, r30, 0x890
/* 801D551C 001D117C  2C 1D 00 03 */	cmpwi r29, 3
/* 801D5520 001D1180  41 80 FF D8 */	blt lbl_801D54F8
/* 801D5524 001D1184  80 01 00 24 */	lwz r0, 0x24(r1)
/* 801D5528 001D1188  38 60 00 00 */	li r3, 0
/* 801D552C 001D118C  83 E1 00 1C */	lwz r31, 0x1c(r1)
/* 801D5530 001D1190  83 C1 00 18 */	lwz r30, 0x18(r1)
/* 801D5534 001D1194  83 A1 00 14 */	lwz r29, 0x14(r1)
/* 801D5538 001D1198  7C 08 03 A6 */	mtlr r0
/* 801D553C 001D119C  38 21 00 20 */	addi r1, r1, 0x20
/* 801D5540 001D11A0  4E 80 00 20 */	blr