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.include "macros.inc"
.section .text, "ax" # 0x80006980 - 0x803E1E60
.global TRKDestructEvent
TRKDestructEvent:
/* 801D4930 001D0590 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 801D4934 001D0594 7C 08 02 A6 */ mflr r0
/* 801D4938 001D0598 90 01 00 14 */ stw r0, 0x14(r1)
/* 801D493C 001D059C 80 63 00 08 */ lwz r3, 8(r3)
/* 801D4940 001D05A0 48 00 0A 39 */ bl TRKReleaseBuffer
/* 801D4944 001D05A4 80 01 00 14 */ lwz r0, 0x14(r1)
/* 801D4948 001D05A8 7C 08 03 A6 */ mtlr r0
/* 801D494C 001D05AC 38 21 00 10 */ addi r1, r1, 0x10
/* 801D4950 001D05B0 4E 80 00 20 */ blr
.global TRKConstructEvent
TRKConstructEvent:
/* 801D4954 001D05B4 90 83 00 00 */ stw r4, 0(r3)
/* 801D4958 001D05B8 38 80 00 00 */ li r4, 0
/* 801D495C 001D05BC 38 00 FF FF */ li r0, -1
/* 801D4960 001D05C0 90 83 00 04 */ stw r4, 4(r3)
/* 801D4964 001D05C4 90 03 00 08 */ stw r0, 8(r3)
/* 801D4968 001D05C8 4E 80 00 20 */ blr
.global TRKPostEvent
TRKPostEvent:
/* 801D496C 001D05CC 94 21 FF E0 */ stwu r1, -0x20(r1)
/* 801D4970 001D05D0 7C 08 02 A6 */ mflr r0
/* 801D4974 001D05D4 3C 80 80 49 */ lis r4, lbl_8048EDF0@ha
/* 801D4978 001D05D8 90 01 00 24 */ stw r0, 0x24(r1)
/* 801D497C 001D05DC 93 E1 00 1C */ stw r31, 0x1c(r1)
/* 801D4980 001D05E0 3B E0 00 00 */ li r31, 0
/* 801D4984 001D05E4 93 C1 00 18 */ stw r30, 0x18(r1)
/* 801D4988 001D05E8 93 A1 00 14 */ stw r29, 0x14(r1)
/* 801D498C 001D05EC 7C 7D 1B 78 */ mr r29, r3
/* 801D4990 001D05F0 38 64 ED F0 */ addi r3, r4, lbl_8048EDF0@l
/* 801D4994 001D05F4 48 00 26 C9 */ bl TRKAcquireMutex
/* 801D4998 001D05F8 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D499C 001D05FC 3B C3 ED F0 */ addi r30, r3, lbl_8048EDF0@l
/* 801D49A0 001D0600 80 7E 00 04 */ lwz r3, 4(r30)
/* 801D49A4 001D0604 2C 03 00 02 */ cmpwi r3, 2
/* 801D49A8 001D0608 40 82 00 0C */ bne lbl_801D49B4
/* 801D49AC 001D060C 3B E0 01 00 */ li r31, 0x100
/* 801D49B0 001D0610 48 00 00 70 */ b lbl_801D4A20
lbl_801D49B4:
/* 801D49B4 001D0614 80 1E 00 08 */ lwz r0, 8(r30)
/* 801D49B8 001D0618 7F A4 EB 78 */ mr r4, r29
/* 801D49BC 001D061C 38 A0 00 0C */ li r5, 0xc
/* 801D49C0 001D0620 7C 00 1A 14 */ add r0, r0, r3
/* 801D49C4 001D0624 54 03 0F FE */ srwi r3, r0, 0x1f
/* 801D49C8 001D0628 54 00 07 FE */ clrlwi r0, r0, 0x1f
/* 801D49CC 001D062C 7C 00 1A 78 */ xor r0, r0, r3
/* 801D49D0 001D0630 7C 03 00 50 */ subf r0, r3, r0
/* 801D49D4 001D0634 1F A0 00 0C */ mulli r29, r0, 0xc
/* 801D49D8 001D0638 7C 7E EA 14 */ add r3, r30, r29
/* 801D49DC 001D063C 38 63 00 0C */ addi r3, r3, 0xc
/* 801D49E0 001D0640 4B E2 F7 85 */ bl TRK_memcpy
/* 801D49E4 001D0644 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D49E8 001D0648 38 83 ED F0 */ addi r4, r3, lbl_8048EDF0@l
/* 801D49EC 001D064C 80 04 00 24 */ lwz r0, 0x24(r4)
/* 801D49F0 001D0650 7C 64 EA 14 */ add r3, r4, r29
/* 801D49F4 001D0654 90 03 00 10 */ stw r0, 0x10(r3)
/* 801D49F8 001D0658 80 64 00 24 */ lwz r3, 0x24(r4)
/* 801D49FC 001D065C 38 03 00 01 */ addi r0, r3, 1
/* 801D4A00 001D0660 28 00 01 00 */ cmplwi r0, 0x100
/* 801D4A04 001D0664 90 04 00 24 */ stw r0, 0x24(r4)
/* 801D4A08 001D0668 40 80 00 0C */ bge lbl_801D4A14
/* 801D4A0C 001D066C 38 00 01 00 */ li r0, 0x100
/* 801D4A10 001D0670 90 04 00 24 */ stw r0, 0x24(r4)
lbl_801D4A14:
/* 801D4A14 001D0674 80 7E 00 04 */ lwz r3, 4(r30)
/* 801D4A18 001D0678 38 03 00 01 */ addi r0, r3, 1
/* 801D4A1C 001D067C 90 1E 00 04 */ stw r0, 4(r30)
lbl_801D4A20:
/* 801D4A20 001D0680 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4A24 001D0684 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
/* 801D4A28 001D0688 48 00 26 2D */ bl TRKReleaseMutex
/* 801D4A2C 001D068C 80 01 00 24 */ lwz r0, 0x24(r1)
/* 801D4A30 001D0690 7F E3 FB 78 */ mr r3, r31
/* 801D4A34 001D0694 83 E1 00 1C */ lwz r31, 0x1c(r1)
/* 801D4A38 001D0698 83 C1 00 18 */ lwz r30, 0x18(r1)
/* 801D4A3C 001D069C 83 A1 00 14 */ lwz r29, 0x14(r1)
/* 801D4A40 001D06A0 7C 08 03 A6 */ mtlr r0
/* 801D4A44 001D06A4 38 21 00 20 */ addi r1, r1, 0x20
/* 801D4A48 001D06A8 4E 80 00 20 */ blr
.global TRKGetNextEvent
TRKGetNextEvent:
/* 801D4A4C 001D06AC 94 21 FF E0 */ stwu r1, -0x20(r1)
/* 801D4A50 001D06B0 7C 08 02 A6 */ mflr r0
/* 801D4A54 001D06B4 3C 80 80 49 */ lis r4, lbl_8048EDF0@ha
/* 801D4A58 001D06B8 90 01 00 24 */ stw r0, 0x24(r1)
/* 801D4A5C 001D06BC 93 E1 00 1C */ stw r31, 0x1c(r1)
/* 801D4A60 001D06C0 93 C1 00 18 */ stw r30, 0x18(r1)
/* 801D4A64 001D06C4 3B C0 00 00 */ li r30, 0
/* 801D4A68 001D06C8 93 A1 00 14 */ stw r29, 0x14(r1)
/* 801D4A6C 001D06CC 7C 7D 1B 78 */ mr r29, r3
/* 801D4A70 001D06D0 38 64 ED F0 */ addi r3, r4, lbl_8048EDF0@l
/* 801D4A74 001D06D4 48 00 25 E9 */ bl TRKAcquireMutex
/* 801D4A78 001D06D8 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4A7C 001D06DC 3B E3 ED F0 */ addi r31, r3, lbl_8048EDF0@l
/* 801D4A80 001D06E0 80 1F 00 04 */ lwz r0, 4(r31)
/* 801D4A84 001D06E4 2C 00 00 00 */ cmpwi r0, 0
/* 801D4A88 001D06E8 40 81 00 4C */ ble lbl_801D4AD4
/* 801D4A8C 001D06EC 80 1F 00 08 */ lwz r0, 8(r31)
/* 801D4A90 001D06F0 7F A3 EB 78 */ mr r3, r29
/* 801D4A94 001D06F4 38 A0 00 0C */ li r5, 0xc
/* 801D4A98 001D06F8 1C 00 00 0C */ mulli r0, r0, 0xc
/* 801D4A9C 001D06FC 7C 9F 02 14 */ add r4, r31, r0
/* 801D4AA0 001D0700 38 84 00 0C */ addi r4, r4, 0xc
/* 801D4AA4 001D0704 4B E2 F6 C1 */ bl TRK_memcpy
/* 801D4AA8 001D0708 80 7F 00 08 */ lwz r3, 8(r31)
/* 801D4AAC 001D070C 80 9F 00 04 */ lwz r4, 4(r31)
/* 801D4AB0 001D0710 38 03 00 01 */ addi r0, r3, 1
/* 801D4AB4 001D0714 38 64 FF FF */ addi r3, r4, -1
/* 801D4AB8 001D0718 90 1F 00 08 */ stw r0, 8(r31)
/* 801D4ABC 001D071C 2C 00 00 02 */ cmpwi r0, 2
/* 801D4AC0 001D0720 90 7F 00 04 */ stw r3, 4(r31)
/* 801D4AC4 001D0724 40 82 00 0C */ bne lbl_801D4AD0
/* 801D4AC8 001D0728 38 00 00 00 */ li r0, 0
/* 801D4ACC 001D072C 90 1F 00 08 */ stw r0, 8(r31)
lbl_801D4AD0:
/* 801D4AD0 001D0730 3B C0 00 01 */ li r30, 1
lbl_801D4AD4:
/* 801D4AD4 001D0734 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4AD8 001D0738 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
/* 801D4ADC 001D073C 48 00 25 79 */ bl TRKReleaseMutex
/* 801D4AE0 001D0740 80 01 00 24 */ lwz r0, 0x24(r1)
/* 801D4AE4 001D0744 7F C3 F3 78 */ mr r3, r30
/* 801D4AE8 001D0748 83 E1 00 1C */ lwz r31, 0x1c(r1)
/* 801D4AEC 001D074C 83 C1 00 18 */ lwz r30, 0x18(r1)
/* 801D4AF0 001D0750 83 A1 00 14 */ lwz r29, 0x14(r1)
/* 801D4AF4 001D0754 7C 08 03 A6 */ mtlr r0
/* 801D4AF8 001D0758 38 21 00 20 */ addi r1, r1, 0x20
/* 801D4AFC 001D075C 4E 80 00 20 */ blr
.global TRKInitializeEventQueue
TRKInitializeEventQueue:
/* 801D4B00 001D0760 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 801D4B04 001D0764 7C 08 02 A6 */ mflr r0
/* 801D4B08 001D0768 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4B0C 001D076C 90 01 00 14 */ stw r0, 0x14(r1)
/* 801D4B10 001D0770 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
/* 801D4B14 001D0774 48 00 25 51 */ bl TRKInitializeMutex
/* 801D4B18 001D0778 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4B1C 001D077C 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
/* 801D4B20 001D0780 48 00 25 3D */ bl TRKAcquireMutex
/* 801D4B24 001D0784 3C 60 80 49 */ lis r3, lbl_8048EDF0@ha
/* 801D4B28 001D0788 38 80 00 00 */ li r4, 0
/* 801D4B2C 001D078C 38 63 ED F0 */ addi r3, r3, lbl_8048EDF0@l
/* 801D4B30 001D0790 38 00 01 00 */ li r0, 0x100
/* 801D4B34 001D0794 90 83 00 04 */ stw r4, 4(r3)
/* 801D4B38 001D0798 90 83 00 08 */ stw r4, 8(r3)
/* 801D4B3C 001D079C 90 03 00 24 */ stw r0, 0x24(r3)
/* 801D4B40 001D07A0 48 00 25 15 */ bl TRKReleaseMutex
/* 801D4B44 001D07A4 80 01 00 14 */ lwz r0, 0x14(r1)
/* 801D4B48 001D07A8 38 60 00 00 */ li r3, 0
/* 801D4B4C 001D07AC 7C 08 03 A6 */ mtlr r0
/* 801D4B50 001D07B0 38 21 00 10 */ addi r1, r1, 0x10
/* 801D4B54 001D07B4 4E 80 00 20 */ blr
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