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.include "macros.inc"
.section .text, "ax" # 0x80006980 - 0x803E1E60
.global TRKTerminateSerialHandler
TRKTerminateSerialHandler:
/* 801D5544 001D11A4 38 60 00 00 */ li r3, 0
/* 801D5548 001D11A8 4E 80 00 20 */ blr
.global TRKInitializeSerialHandler
TRKInitializeSerialHandler:
/* 801D554C 001D11AC 3C 60 80 49 */ lis r3, lbl_804907D0@ha
/* 801D5550 001D11B0 38 A0 FF FF */ li r5, -1
/* 801D5554 001D11B4 38 83 07 D0 */ addi r4, r3, lbl_804907D0@l
/* 801D5558 001D11B8 38 00 00 00 */ li r0, 0
/* 801D555C 001D11BC 90 A4 00 00 */ stw r5, 0(r4)
/* 801D5560 001D11C0 38 60 00 00 */ li r3, 0
/* 801D5564 001D11C4 90 04 00 08 */ stw r0, 8(r4)
/* 801D5568 001D11C8 90 04 00 0C */ stw r0, 0xc(r4)
/* 801D556C 001D11CC 4E 80 00 20 */ blr
.global TRKProcessInput
TRKProcessInput:
/* 801D5570 001D11D0 94 21 FF E0 */ stwu r1, -0x20(r1)
/* 801D5574 001D11D4 7C 08 02 A6 */ mflr r0
/* 801D5578 001D11D8 38 80 00 02 */ li r4, 2
/* 801D557C 001D11DC 90 01 00 24 */ stw r0, 0x24(r1)
/* 801D5580 001D11E0 93 E1 00 1C */ stw r31, 0x1c(r1)
/* 801D5584 001D11E4 7C 7F 1B 78 */ mr r31, r3
/* 801D5588 001D11E8 38 61 00 08 */ addi r3, r1, 8
/* 801D558C 001D11EC 4B FF F3 C9 */ bl TRKConstructEvent
/* 801D5590 001D11F0 3C 60 80 49 */ lis r3, lbl_804907D0@ha
/* 801D5594 001D11F4 38 00 FF FF */ li r0, -1
/* 801D5598 001D11F8 38 83 07 D0 */ addi r4, r3, lbl_804907D0@l
/* 801D559C 001D11FC 93 E1 00 10 */ stw r31, 0x10(r1)
/* 801D55A0 001D1200 38 61 00 08 */ addi r3, r1, 8
/* 801D55A4 001D1204 90 04 00 00 */ stw r0, 0(r4)
/* 801D55A8 001D1208 4B FF F3 C5 */ bl TRKPostEvent
/* 801D55AC 001D120C 80 01 00 24 */ lwz r0, 0x24(r1)
/* 801D55B0 001D1210 83 E1 00 1C */ lwz r31, 0x1c(r1)
/* 801D55B4 001D1214 7C 08 03 A6 */ mtlr r0
/* 801D55B8 001D1218 38 21 00 20 */ addi r1, r1, 0x20
/* 801D55BC 001D121C 4E 80 00 20 */ blr
.global TRKGetInput
TRKGetInput:
/* 801D55C0 001D1220 94 21 FF E0 */ stwu r1, -0x20(r1)
/* 801D55C4 001D1224 7C 08 02 A6 */ mflr r0
/* 801D55C8 001D1228 90 01 00 24 */ stw r0, 0x24(r1)
/* 801D55CC 001D122C 93 E1 00 1C */ stw r31, 0x1c(r1)
/* 801D55D0 001D1230 48 00 00 51 */ bl TRKTestForPacket
/* 801D55D4 001D1234 7C 7F 1B 78 */ mr r31, r3
/* 801D55D8 001D1238 2C 1F FF FF */ cmpwi r31, -1
/* 801D55DC 001D123C 41 82 00 30 */ beq lbl_801D560C
/* 801D55E0 001D1240 4B FF FD FD */ bl TRKGetBuffer
/* 801D55E4 001D1244 38 61 00 08 */ addi r3, r1, 8
/* 801D55E8 001D1248 38 80 00 02 */ li r4, 2
/* 801D55EC 001D124C 4B FF F3 69 */ bl TRKConstructEvent
/* 801D55F0 001D1250 3C 60 80 49 */ lis r3, lbl_804907D0@ha
/* 801D55F4 001D1254 38 00 FF FF */ li r0, -1
/* 801D55F8 001D1258 38 83 07 D0 */ addi r4, r3, lbl_804907D0@l
/* 801D55FC 001D125C 93 E1 00 10 */ stw r31, 0x10(r1)
/* 801D5600 001D1260 38 61 00 08 */ addi r3, r1, 8
/* 801D5604 001D1264 90 04 00 00 */ stw r0, 0(r4)
/* 801D5608 001D1268 4B FF F3 65 */ bl TRKPostEvent
lbl_801D560C:
/* 801D560C 001D126C 80 01 00 24 */ lwz r0, 0x24(r1)
/* 801D5610 001D1270 83 E1 00 1C */ lwz r31, 0x1c(r1)
/* 801D5614 001D1274 7C 08 03 A6 */ mtlr r0
/* 801D5618 001D1278 38 21 00 20 */ addi r1, r1, 0x20
/* 801D561C 001D127C 4E 80 00 20 */ blr
.global TRKTestForPacket
TRKTestForPacket:
/* 801D5620 001D1280 94 21 F7 20 */ stwu r1, -0x8e0(r1)
/* 801D5624 001D1284 7C 08 02 A6 */ mflr r0
/* 801D5628 001D1288 90 01 08 E4 */ stw r0, 0x8e4(r1)
/* 801D562C 001D128C 93 E1 08 DC */ stw r31, 0x8dc(r1)
/* 801D5630 001D1290 48 00 40 55 */ bl TRKPollUART
/* 801D5634 001D1294 2C 03 00 00 */ cmpwi r3, 0
/* 801D5638 001D1298 41 81 00 0C */ bgt lbl_801D5644
/* 801D563C 001D129C 38 60 FF FF */ li r3, -1
/* 801D5640 001D12A0 48 00 00 9C */ b lbl_801D56DC
lbl_801D5644:
/* 801D5644 001D12A4 38 61 00 0C */ addi r3, r1, 0xc
/* 801D5648 001D12A8 38 81 00 08 */ addi r4, r1, 8
/* 801D564C 001D12AC 4B FF FD BD */ bl TRKGetFreeBuffer
/* 801D5650 001D12B0 7C 60 1B 78 */ mr r0, r3
/* 801D5654 001D12B4 80 61 00 08 */ lwz r3, 8(r1)
/* 801D5658 001D12B8 7C 1F 03 78 */ mr r31, r0
/* 801D565C 001D12BC 38 80 00 00 */ li r4, 0
/* 801D5660 001D12C0 4B FF FC A9 */ bl TRKSetBufferPosition
/* 801D5664 001D12C4 38 61 00 10 */ addi r3, r1, 0x10
/* 801D5668 001D12C8 38 80 00 40 */ li r4, 0x40
/* 801D566C 001D12CC 48 00 3F DD */ bl TRKReadUARTN
/* 801D5670 001D12D0 2C 03 00 00 */ cmpwi r3, 0
/* 801D5674 001D12D4 40 82 00 58 */ bne lbl_801D56CC
/* 801D5678 001D12D8 80 61 00 08 */ lwz r3, 8(r1)
/* 801D567C 001D12DC 38 81 00 10 */ addi r4, r1, 0x10
/* 801D5680 001D12E0 38 A0 00 40 */ li r5, 0x40
/* 801D5684 001D12E4 4B FF F9 F1 */ bl TRKAppendBuffer_ui8
/* 801D5688 001D12E8 80 61 00 10 */ lwz r3, 0x10(r1)
/* 801D568C 001D12EC 83 E1 00 0C */ lwz r31, 0xc(r1)
/* 801D5690 001D12F0 34 83 FF C0 */ addic. r4, r3, -64
/* 801D5694 001D12F4 40 81 00 44 */ ble lbl_801D56D8
/* 801D5698 001D12F8 38 61 00 50 */ addi r3, r1, 0x50
/* 801D569C 001D12FC 48 00 3F AD */ bl TRKReadUARTN
/* 801D56A0 001D1300 2C 03 00 00 */ cmpwi r3, 0
/* 801D56A4 001D1304 40 82 00 18 */ bne lbl_801D56BC
/* 801D56A8 001D1308 80 61 00 08 */ lwz r3, 8(r1)
/* 801D56AC 001D130C 38 81 00 50 */ addi r4, r1, 0x50
/* 801D56B0 001D1310 80 A1 00 10 */ lwz r5, 0x10(r1)
/* 801D56B4 001D1314 4B FF F9 C1 */ bl TRKAppendBuffer_ui8
/* 801D56B8 001D1318 48 00 00 20 */ b lbl_801D56D8
lbl_801D56BC:
/* 801D56BC 001D131C 7F E3 FB 78 */ mr r3, r31
/* 801D56C0 001D1320 4B FF FC B9 */ bl TRKReleaseBuffer
/* 801D56C4 001D1324 3B E0 FF FF */ li r31, -1
/* 801D56C8 001D1328 48 00 00 10 */ b lbl_801D56D8
lbl_801D56CC:
/* 801D56CC 001D132C 7F E3 FB 78 */ mr r3, r31
/* 801D56D0 001D1330 4B FF FC A9 */ bl TRKReleaseBuffer
/* 801D56D4 001D1334 3B E0 FF FF */ li r31, -1
lbl_801D56D8:
/* 801D56D8 001D1338 7F E3 FB 78 */ mr r3, r31
lbl_801D56DC:
/* 801D56DC 001D133C 80 01 08 E4 */ lwz r0, 0x8e4(r1)
/* 801D56E0 001D1340 83 E1 08 DC */ lwz r31, 0x8dc(r1)
/* 801D56E4 001D1344 7C 08 03 A6 */ mtlr r0
/* 801D56E8 001D1348 38 21 08 E0 */ addi r1, r1, 0x8e0
/* 801D56EC 001D134C 4E 80 00 20 */ blr
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