diff options
author | Raúl Peñacoba <raul.mikaop.zelda@gmail.com> | 2017-08-25 12:19:23 +0200 |
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committer | Raúl Peñacoba <raul.mikaop.zelda@gmail.com> | 2017-08-25 12:19:23 +0200 |
commit | ae56f7859fe17915d3fb33713dfef2fe31fe2a1d (patch) | |
tree | 6f626a77aa9a7ee3019e556b6fb72260d500e70e | |
parent | d844354e116e2051d601bc647d666a981725e08e (diff) |
sub_80EEF34 almost finished. just register differences
-rw-r--r-- | asm/pokenav.s | 41 | ||||
-rw-r--r-- | src/pokenav_before.c | 64 |
2 files changed, 64 insertions, 41 deletions
diff --git a/asm/pokenav.s b/asm/pokenav.s index e38c07dc6..49f9d941c 100644 --- a/asm/pokenav.s +++ b/asm/pokenav.s @@ -6,47 +6,6 @@ .text - thumb_func_start sub_80EEF34 -sub_80EEF34: @ 80EEF34 - push {r4,lr} - movs r3, 0x1 - ldr r0, _080EEF50 @ =gUnknown_083DFEC4 - ldr r0, [r0] - movs r1, 0xC3 - lsls r1, 2 - adds r2, r0, r1 - ldrh r1, [r2] - movs r4, 0 - ldrsh r0, [r2, r4] - cmp r0, 0x20 - bne _080EEF54 - movs r0, 0 - b _080EEF6E - .align 2, 0 -_080EEF50: .4byte gUnknown_083DFEC4 -_080EEF54: - adds r0, r1, 0x2 - strh r0, [r2] - lsls r0, 16 - asrs r0, 16 - cmp r0, 0x1F - ble _080EEF66 - movs r0, 0x20 - strh r0, [r2] - movs r3, 0 -_080EEF66: - ldr r1, _080EEF74 @ =REG_BG1VOFS - ldrh r0, [r2] - strh r0, [r1] - adds r0, r3, 0 -_080EEF6E: - pop {r4} - pop {r1} - bx r1 - .align 2, 0 -_080EEF74: .4byte REG_BG1VOFS - thumb_func_end sub_80EEF34 - thumb_func_start sub_80EEF78 sub_80EEF78: @ 80EEF78 push {r4,lr} diff --git a/src/pokenav_before.c b/src/pokenav_before.c index b027f2a1d..e3ea0dcc4 100644 --- a/src/pokenav_before.c +++ b/src/pokenav_before.c @@ -2930,3 +2930,67 @@ bool8 sub_80EEE54() { gUnknown_083DFEC4->unkD160++; return 1; } + +#if 0 +// not matches because of register differences +bool8 sub_80EEF34() { + bool8 ret = 0x1; + if ((s8)gUnknown_083DFEC4->unk030C == 0x20) { + return 0; + } + else { + gUnknown_083DFEC4->unk030C += 2; + if (gUnknown_083DFEC4->unk030C > 0x1F) { + gUnknown_083DFEC4->unk030C = 0x20; + ret = 0; + } + REG_BG1VOFS = gUnknown_083DFEC4->unk030C; + return ret; + } +} +#else +__attribute__((naked)) +bool8 sub_80EEF34() { + asm(".text\n" + ".include \"constants/gba_constants.inc\""); + + asm_unified( + "push {r4,lr}\n\ + movs r3, 0x1\n\ + ldr r0, _080EEF50 @ =gUnknown_083DFEC4\n\ + ldr r0, [r0]\n\ + movs r1, 0xC3\n\ + lsls r1, 2\n\ + adds r2, r0, r1\n\ + ldrh r1, [r2]\n\ + movs r4, 0\n\ + ldrsh r0, [r2, r4]\n\ + cmp r0, 0x20\n\ + bne _080EEF54\n\ + movs r0, 0\n\ + b _080EEF6E\n\ + .align 2, 0\n\ +_080EEF50: .4byte gUnknown_083DFEC4\n\ +_080EEF54:\n\ + adds r0, r1, 0x2\n\ + strh r0, [r2]\n\ + lsls r0, 16\n\ + asrs r0, 16\n\ + cmp r0, 0x1F\n\ + ble _080EEF66\n\ + movs r0, 0x20\n\ + strh r0, [r2]\n\ + movs r3, 0\n\ +_080EEF66:\n\ + ldr r1, _080EEF74 @ =REG_BG1VOFS\n\ + ldrh r0, [r2]\n\ + strh r0, [r1]\n\ + adds r0, r3, 0\n\ +_080EEF6E:\n\ + pop {r4}\n\ + pop {r1}\n\ + bx r1\n\ + .align 2, 0\n\ +_080EEF74: .4byte REG_BG1VOFS"); +} +#endif |