add sound defines

2 files changed, 113 insertions, 38 deletions

diff --git a/include/gba/gba.h b/include/gba/gba.h
index 5a9dc9b2d..10b2ffa43 100644
--- a/include/gba/gba.h
+++ b/include/gba/gba.h
@@ -31,4 +31,8 @@ typedef u32 bool32;
 #include "gba/syscall.h"
 #include "gba/macro.h"
 
+#define SOUND_INFO_PTR (*(struct SoundInfo **)0x3007FF0)
+#define INTR_CHECK     (*(u16 *)0x3007FF8)
+#define INTR_VECTOR    (*(u32 *)0x3007FFC)
+
 #endif // GUARD_GBA_GBA_H
diff --git a/include/gba/io_reg.h b/include/gba/io_reg.h
index b156ea801..92dd49a01 100644
--- a/include/gba/io_reg.h
+++ b/include/gba/io_reg.h
@@ -47,45 +47,49 @@
 #define REG_OFFSET_BLDALPHA    0x52
 #define REG_OFFSET_BLDY        0x54
 
-#define REG_OFFSET_SOUND1CNT   0x60
 #define REG_OFFSET_SOUND1CNT_L 0x60
+#define REG_OFFSET_NR10        0x60
 #define REG_OFFSET_SOUND1CNT_H 0x62
+#define REG_OFFSET_NR11        0x62
+#define REG_OFFSET_NR12        0x63
 #define REG_OFFSET_SOUND1CNT_X 0x64
-#define REG_OFFSET_SOUND2CNT   0x68
+#define REG_OFFSET_NR13        0x64
+#define REG_OFFSET_NR14        0x65
 #define REG_OFFSET_SOUND2CNT_L 0x68
+#define REG_OFFSET_NR21        0x68
+#define REG_OFFSET_NR22        0x69
 #define REG_OFFSET_SOUND2CNT_H 0x6c
-#define REG_OFFSET_SOUND3CNT   0x70
+#define REG_OFFSET_NR23        0x6c
+#define REG_OFFSET_NR24        0x6d
 #define REG_OFFSET_SOUND3CNT_L 0x70
+#define REG_OFFSET_NR30        0x70
 #define REG_OFFSET_SOUND3CNT_H 0x72
+#define REG_OFFSET_NR31        0x72
+#define REG_OFFSET_NR32        0x73
 #define REG_OFFSET_SOUND3CNT_X 0x74
-#define REG_OFFSET_SOUND4CNT   0x78
+#define REG_OFFSET_NR33        0x74
+#define REG_OFFSET_NR34        0x75
 #define REG_OFFSET_SOUND4CNT_L 0x78
+#define REG_OFFSET_NR41        0x78
+#define REG_OFFSET_NR42        0x79
 #define REG_OFFSET_SOUND4CNT_H 0x7c
-#define REG_OFFSET_SOUNDCNT    0x80
+#define REG_OFFSET_NR43        0x7c
+#define REG_OFFSET_NR44        0x7d
 #define REG_OFFSET_SOUNDCNT_L  0x80
+#define REG_OFFSET_NR50        0x80
+#define REG_OFFSET_NR51        0x81
 #define REG_OFFSET_SOUNDCNT_H  0x82
 #define REG_OFFSET_SOUNDCNT_X  0x84
+#define REG_OFFSET_NR52        0x84
 #define REG_OFFSET_SOUNDBIAS   0x88
-#define REG_OFFSET_WAVE_RAM    0x90
+#define REG_OFFSET_SOUNDBIAS_L 0x88
+#define REG_OFFSET_SOUNDBIAS_H 0x89
 #define REG_OFFSET_WAVE_RAM0   0x90
-#define REG_OFFSET_WAVE_RAM0_L 0x90
-#define REG_OFFSET_WAVE_RAM0_H 0x92
 #define REG_OFFSET_WAVE_RAM1   0x94
-#define REG_OFFSET_WAVE_RAM1_L 0x94
-#define REG_OFFSET_WAVE_RAM1_H 0x96
 #define REG_OFFSET_WAVE_RAM2   0x98
-#define REG_OFFSET_WAVE_RAM2_L 0x98
-#define REG_OFFSET_WAVE_RAM2_H 0x9a
 #define REG_OFFSET_WAVE_RAM3   0x9c
-#define REG_OFFSET_WAVE_RAM3_L 0x9c
-#define REG_OFFSET_WAVE_RAM3_H 0x9e
-#define REG_OFFSET_FIFO        0xa0
 #define REG_OFFSET_FIFO_A      0xa0
-#define REG_OFFSET_FIFO_A_L    0xa0
-#define REG_OFFSET_FIFO_A_H    0xa2
 #define REG_OFFSET_FIFO_B      0xa4
-#define REG_OFFSET_FIFO_B_L    0xa4
-#define REG_OFFSET_FIFO_B_H    0xa6
 
 #define REG_OFFSET_DMA0        0xb0
 #define REG_OFFSET_DMA0SAD     0xb0
@@ -216,45 +220,49 @@
 #define REG_ADDR_BLDALPHA    (REG_BASE + REG_OFFSET_BLDALPHA)
 #define REG_ADDR_BLDY        (REG_BASE + REG_OFFSET_BLDY)
 
-#define REG_ADDR_SOUND1CNT   (REG_BASE + REG_OFFSET_SOUND1CNT)
 #define REG_ADDR_SOUND1CNT_L (REG_BASE + REG_OFFSET_SOUND1CNT_L)
+#define REG_ADDR_NR10        (REG_BASE + REG_OFFSET_NR10)
 #define REG_ADDR_SOUND1CNT_H (REG_BASE + REG_OFFSET_SOUND1CNT_H)
+#define REG_ADDR_NR11        (REG_BASE + REG_OFFSET_NR11)
+#define REG_ADDR_NR12        (REG_BASE + REG_OFFSET_NR12)
 #define REG_ADDR_SOUND1CNT_X (REG_BASE + REG_OFFSET_SOUND1CNT_X)
-#define REG_ADDR_SOUND2CNT   (REG_BASE + REG_OFFSET_SOUND2CNT)
+#define REG_ADDR_NR13        (REG_BASE + REG_OFFSET_NR13)
+#define REG_ADDR_NR14        (REG_BASE + REG_OFFSET_NR14)
 #define REG_ADDR_SOUND2CNT_L (REG_BASE + REG_OFFSET_SOUND2CNT_L)
+#define REG_ADDR_NR21        (REG_BASE + REG_OFFSET_NR21)
+#define REG_ADDR_NR22        (REG_BASE + REG_OFFSET_NR22)
 #define REG_ADDR_SOUND2CNT_H (REG_BASE + REG_OFFSET_SOUND2CNT_H)
-#define REG_ADDR_SOUND3CNT   (REG_BASE + REG_OFFSET_SOUND3CNT)
+#define REG_ADDR_NR23        (REG_BASE + REG_OFFSET_NR23)
+#define REG_ADDR_NR24        (REG_BASE + REG_OFFSET_NR24)
 #define REG_ADDR_SOUND3CNT_L (REG_BASE + REG_OFFSET_SOUND3CNT_L)
+#define REG_ADDR_NR30        (REG_BASE + REG_OFFSET_NR30)
 #define REG_ADDR_SOUND3CNT_H (REG_BASE + REG_OFFSET_SOUND3CNT_H)
+#define REG_ADDR_NR31        (REG_BASE + REG_OFFSET_NR31)
+#define REG_ADDR_NR32        (REG_BASE + REG_OFFSET_NR32)
 #define REG_ADDR_SOUND3CNT_X (REG_BASE + REG_OFFSET_SOUND3CNT_X)
-#define REG_ADDR_SOUND4CNT   (REG_BASE + REG_OFFSET_SOUND4CNT)
+#define REG_ADDR_NR33        (REG_BASE + REG_OFFSET_NR33)
+#define REG_ADDR_NR34        (REG_BASE + REG_OFFSET_NR34)
 #define REG_ADDR_SOUND4CNT_L (REG_BASE + REG_OFFSET_SOUND4CNT_L)
+#define REG_ADDR_NR41        (REG_BASE + REG_OFFSET_NR41)
+#define REG_ADDR_NR42        (REG_BASE + REG_OFFSET_NR42)
 #define REG_ADDR_SOUND4CNT_H (REG_BASE + REG_OFFSET_SOUND4CNT_H)
-#define REG_ADDR_SOUNDCNT    (REG_BASE + REG_OFFSET_SOUNDCNT)
+#define REG_ADDR_NR43        (REG_BASE + REG_OFFSET_NR43)
+#define REG_ADDR_NR44        (REG_BASE + REG_OFFSET_NR44)
 #define REG_ADDR_SOUNDCNT_L  (REG_BASE + REG_OFFSET_SOUNDCNT_L)
+#define REG_ADDR_NR50        (REG_BASE + REG_OFFSET_NR50)
+#define REG_ADDR_NR51        (REG_BASE + REG_OFFSET_NR51)
 #define REG_ADDR_SOUNDCNT_H  (REG_BASE + REG_OFFSET_SOUNDCNT_H)
 #define REG_ADDR_SOUNDCNT_X  (REG_BASE + REG_OFFSET_SOUNDCNT_X)
+#define REG_ADDR_NR52        (REG_BASE + REG_OFFSET_NR52)
 #define REG_ADDR_SOUNDBIAS   (REG_BASE + REG_OFFSET_SOUNDBIAS)
-#define REG_ADDR_WAVE_RAM    (REG_BASE + REG_OFFSET_WAVE_RAM)
+#define REG_ADDR_SOUNDBIAS_L (REG_BASE + REG_OFFSET_SOUNDBIAS_L)
+#define REG_ADDR_SOUNDBIAS_H (REG_BASE + REG_OFFSET_SOUNDBIAS_H)
 #define REG_ADDR_WAVE_RAM0   (REG_BASE + REG_OFFSET_WAVE_RAM0)
-#define REG_ADDR_WAVE_RAM0_L (REG_BASE + REG_OFFSET_WAVE_RAM0_L)
-#define REG_ADDR_WAVE_RAM0_H (REG_BASE + REG_OFFSET_WAVE_RAM0_H)
 #define REG_ADDR_WAVE_RAM1   (REG_BASE + REG_OFFSET_WAVE_RAM1)
-#define REG_ADDR_WAVE_RAM1_L (REG_BASE + REG_OFFSET_WAVE_RAM1_L)
-#define REG_ADDR_WAVE_RAM1_H (REG_BASE + REG_OFFSET_WAVE_RAM1_H)
 #define REG_ADDR_WAVE_RAM2   (REG_BASE + REG_OFFSET_WAVE_RAM2)
-#define REG_ADDR_WAVE_RAM2_L (REG_BASE + REG_OFFSET_WAVE_RAM2_L)
-#define REG_ADDR_WAVE_RAM2_H (REG_BASE + REG_OFFSET_WAVE_RAM2_H)
 #define REG_ADDR_WAVE_RAM3   (REG_BASE + REG_OFFSET_WAVE_RAM3)
-#define REG_ADDR_WAVE_RAM3_L (REG_BASE + REG_OFFSET_WAVE_RAM3_L)
-#define REG_ADDR_WAVE_RAM3_H (REG_BASE + REG_OFFSET_WAVE_RAM3_H)
-#define REG_ADDR_FIFO        (REG_BASE + REG_OFFSET_FIFO)
 #define REG_ADDR_FIFO_A      (REG_BASE + REG_OFFSET_FIFO_A)
-#define REG_ADDR_FIFO_A_L    (REG_BASE + REG_OFFSET_FIFO_A_L)
-#define REG_ADDR_FIFO_A_H    (REG_BASE + REG_OFFSET_FIFO_A_H)
 #define REG_ADDR_FIFO_B      (REG_BASE + REG_OFFSET_FIFO_B)
-#define REG_ADDR_FIFO_B_L    (REG_BASE + REG_OFFSET_FIFO_B_L)
-#define REG_ADDR_FIFO_B_H    (REG_BASE + REG_OFFSET_FIFO_B_H)
 
 #define REG_ADDR_DMA0        (REG_BASE + REG_OFFSET_DMA0)
 #define REG_ADDR_DMA0SAD     (REG_BASE + REG_OFFSET_DMA0SAD)
@@ -331,6 +339,50 @@
 #define REG_DISPSTAT    (*(vu16 *)REG_ADDR_DISPSTAT)
 #define REG_VCOUNT      (*(vu16 *)REG_ADDR_VCOUNT)
 
+#define REG_SOUND1CNT_L (*(vu16 *)REG_ADDR_SOUND1CNT_L)
+#define REG_NR10        (*(vu8  *)REG_ADDR_NR10)
+#define REG_SOUND1CNT_H (*(vu16 *)REG_ADDR_SOUND1CNT_H)
+#define REG_NR11        (*(vu8  *)REG_ADDR_NR11)
+#define REG_NR12        (*(vu8  *)REG_ADDR_NR12)
+#define REG_SOUND1CNT_X (*(vu16 *)REG_ADDR_SOUND1CNT_X)
+#define REG_NR13        (*(vu8  *)REG_ADDR_NR13)
+#define REG_NR14        (*(vu8  *)REG_ADDR_NR14)
+#define REG_SOUND2CNT_L (*(vu16 *)REG_ADDR_SOUND2CNT_L)
+#define REG_NR21        (*(vu8  *)REG_ADDR_NR21)
+#define REG_NR22        (*(vu8  *)REG_ADDR_NR22)
+#define REG_SOUND2CNT_H (*(vu16 *)REG_ADDR_SOUND2CNT_H)
+#define REG_NR23        (*(vu8  *)REG_ADDR_NR23)
+#define REG_NR24        (*(vu8  *)REG_ADDR_NR24)
+#define REG_SOUND3CNT_L (*(vu16 *)REG_ADDR_SOUND3CNT_L)
+#define REG_NR30        (*(vu8  *)REG_ADDR_NR30)
+#define REG_SOUND3CNT_H (*(vu16 *)REG_ADDR_SOUND3CNT_H)
+#define REG_NR31        (*(vu8  *)REG_ADDR_NR31)
+#define REG_NR32        (*(vu8  *)REG_ADDR_NR32)
+#define REG_SOUND3CNT_X (*(vu16 *)REG_ADDR_SOUND3CNT_X)
+#define REG_NR33        (*(vu8  *)REG_ADDR_NR33)
+#define REG_NR34        (*(vu8  *)REG_ADDR_NR34)
+#define REG_SOUND4CNT_L (*(vu16 *)REG_ADDR_SOUND4CNT_L)
+#define REG_NR41        (*(vu8  *)REG_ADDR_NR41)
+#define REG_NR42        (*(vu8  *)REG_ADDR_NR42)
+#define REG_SOUND4CNT_H (*(vu16 *)REG_ADDR_SOUND4CNT_H)
+#define REG_NR43        (*(vu8  *)REG_ADDR_NR43)
+#define REG_NR44        (*(vu8  *)REG_ADDR_NR44)
+#define REG_SOUNDCNT_L  (*(vu16 *)REG_ADDR_SOUNDCNT_L)
+#define REG_NR50        (*(vu8  *)REG_ADDR_NR50)
+#define REG_NR51        (*(vu8  *)REG_ADDR_NR51)
+#define REG_SOUNDCNT_H  (*(vu16 *)REG_ADDR_SOUNDCNT_H)
+#define REG_SOUNDCNT_X  (*(vu16 *)REG_ADDR_SOUNDCNT_X)
+#define REG_NR52        (*(vu8  *)REG_ADDR_NR52)
+#define REG_SOUNDBIAS   (*(vu16 *)REG_ADDR_SOUNDBIAS)
+#define REG_SOUNDBIAS_L (*(vu8  *)REG_ADDR_SOUNDBIAS_L)
+#define REG_SOUNDBIAS_H (*(vu8  *)REG_ADDR_SOUNDBIAS_H)
+#define REG_WAVE_RAM0   (*(vu32 *)REG_ADDR_WAVE_RAM0)
+#define REG_WAVE_RAM1   (*(vu32 *)REG_ADDR_WAVE_RAM1)
+#define REG_WAVE_RAM2   (*(vu32 *)REG_ADDR_WAVE_RAM2)
+#define REG_WAVE_RAM3   (*(vu32 *)REG_ADDR_WAVE_RAM3)
+#define REG_FIFO_A      (*(vu32 *)REG_ADDR_FIFO_A)
+#define REG_FIFO_B      (*(vu32 *)REG_ADDR_FIFO_B)
+
 #define REG_DMA0SAD     (*(vu32 *)REG_ADDR_DMA0SAD)
 #define REG_DMA0DAD     (*(vu32 *)REG_ADDR_DMA0DAD)
 #define REG_DMA0CNT     (*(vu32 *)REG_ADDR_DMA0CNT)
@@ -356,6 +408,18 @@
 #define REG_DMA3CNT_H   (*(vu16 *)REG_ADDR_DMA3CNT_H)
 
 #define REG_TMCNT(n)    (*(vu16 *)(REG_ADDR_TMCNT + ((n) * 4)))
+#define REG_TM0CNT      (*(vu32 *)REG_ADDR_TM0CNT)
+#define REG_TM0CNT_L    (*(vu16 *)REG_ADDR_TM0CNT_L)
+#define REG_TM0CNT_H    (*(vu16 *)REG_ADDR_TM0CNT_H)
+#define REG_TM1CNT      (*(vu32 *)REG_ADDR_TM1CNT)
+#define REG_TM1CNT_L    (*(vu16 *)REG_ADDR_TM1CNT_L)
+#define REG_TM1CNT_H    (*(vu16 *)REG_ADDR_TM1CNT_H)
+#define REG_TM2CNT      (*(vu32 *)REG_ADDR_TM2CNT)
+#define REG_TM2CNT_L    (*(vu16 *)REG_ADDR_TM2CNT_L)
+#define REG_TM2CNT_H    (*(vu16 *)REG_ADDR_TM2CNT_H)
+#define REG_TM3CNT      (*(vu32 *)REG_ADDR_TM3CNT)
+#define REG_TM3CNT_L    (*(vu16 *)REG_ADDR_TM3CNT_L)
+#define REG_TM3CNT_H    (*(vu16 *)REG_ADDR_TM3CNT_H)
 
 #define REG_IME         (*(vu16 *)REG_ADDR_IME)
 #define REG_IE          (*(vu16 *)REG_ADDR_IE)
@@ -383,6 +447,13 @@
 #define DISPSTAT_HBLANK_INTR 0x0010 // H-Blank interrupt enabled
 #define DISPSTAT_VCOUNT_INTR 0x0020 // V-Count interrupt enabled
 
+// SOUNDCNT_X
+#define SOUND_1_ON          0x0001
+#define SOUND_2_ON          0x0002
+#define SOUND_3_ON          0x0004
+#define SOUND_4_ON          0x0008
+#define SOUND_MASTER_ENABLE 0x0080
+
 // DMA
 #define DMA_DEST_INC      0x0000
 #define DMA_DEST_DEC      0x0020