Replace register access macros with variables

8 files changed, 296 insertions, 387 deletions

diff --git a/arm9/lib/include/gx.h b/arm9/lib/include/gx.h
index 5abc2693..58e4c35f 100644
--- a/arm9/lib/include/gx.h
+++ b/arm9/lib/include/gx.h
@@ -20,98 +20,8 @@ void MIi_CpuCopy32(void *src, void *dst, u32 size);
 void OSi_UnlockVram(u16, u16);
 void MIi_CpuClear32(u32, void *, u32);
 
-//Todos before PR
 //TODO: Add defines for GX commands, add structs/unions for HW registers
 
-#define HW_REG_DIV_NUMER 0x04000290
-#define HW_REG_DIV_DENOM 0x04000298
-
-#define HW_REG_MTX_MODE  0x04000440
-#define HW_REG_MTX_LOAD_4x4 0x04000458
-#define HW_REG_MTX_LOAD_4x3 0x0400045C
-#define HW_REG_MTX_MULT_3x3 0x04000468
-
-#define HW_REG_END_VTXS        0x04000504
-#define HW_REG_GXSTAT          0x04000600
-#define HW_REG_DISP3DCNT       0x04000060
-#define HW_REG_BG0HOFS         0x04000010
-#define HW_REG_CLEAR_COLOR     0x04000350
-#define HW_REG_CLEAR_DEPTH     0x04000354
-#define HW_REG_CLRIMAGE_OFFSET 0x04000356
-#define HW_REG_FOG_COLOR       0x04000358
-#define HW_REG_FOG_OFFSET      0x0400035C
-#define HW_REG_BG0CNT          0x04000008
-#define HW_REG_POLYGON_ATTR    0x040004A4
-#define HW_REG_TEXIMAGE_PARAM  0x040004A8
-#define HW_REG_PLTT_BASE       0x040004AC
-
-#define HW_REG_POWCNT1         0x04000304
-
-#define HW_REG_GXFIFO          0x04000400
-#define HW_REG_MTX_IDENTITY    0x04000454
-#define HW_REG_MTX_POP         0x04000448
-#define HW_REG_MTX_MODE        0x04000440
-
-#define HW_REG_CLIPMTX_RESULT  0x04000640
-#define HW_REG_VECMTX_RESULT   0x04000680
-
-#define HW_REG_EDGE_COLOR      0x04000330
-#define HW_REG_FOG_TABLE       0x04000360
-
-#define HW_REG_SHININESS       0x040004D0
-
-#define HW_REG_MASTER_BRIGHT   0x0400006C
-
-#define HW_REG_VRAMCNT_A       0x04000240
-#define HW_REG_VRAMCNT_B       0x04000241
-#define HW_REG_VRAMCNT_C       0x04000242
-#define HW_REG_VRAMCNT_D       0x04000243
-#define HW_REG_VRAMCNT_E       0x04000244
-#define HW_REG_VRAMCNT_F       0x04000245
-#define HW_REG_VRAMCNT_G       0x04000246
-#define HW_REG_WRAMCNT         0x04000247
-#define HW_REG_VRAMCNT_H       0x04000248
-#define HW_REG_VRAMCNT_I       0x04000249
-
-#define HW_REG_DISPCNT         0x04000000
-#define HW_REG_DISPSTAT        0x04000004
-#define HW_REG_DISPCNT_2D      0x04001000
-
-#define HW_REG_DISP3DCNT       0x04000060
-
-#define HW_REG_BG2PA_A   0x04000020
-#define HW_REG_BG2PD_A   0x04000026
-#define HW_REG_BG3PA_A   0x04000030
-#define HW_REG_BG3PD_A   0x04000036
-#define HW_REG_BG2PA_B   0x04001020
-#define HW_REG_BG2PD_B   0x04001026
-#define HW_REG_BG3PA_B   0x04001030
-#define HW_REG_BG3PD_B   0x04001036
-
-#define HW_REG_BG0CNT_A 0x04000008
-#define HW_REG_BG1CNT_A 0x0400000A
-#define HW_REG_BG2CNT_A 0x0400000C
-#define HW_REG_BG3CNT_A 0x0400000E
-
-#define HW_REG_BG0CNT_B 0x04001008
-#define HW_REG_BG1CNT_B 0x0400100A
-#define HW_REG_BG2CNT_B 0x0400100C
-#define HW_REG_BG3CNT_B 0x0400100E
-
-#define HW_REG_DISPCNT_A 0x04000000
-#define HW_REG_DISPCNT_B 0x04001000
-
-//TODO: wait for register commit and replace these
-#define SETREG8(x, y) ((*(vu8 *)x) = y)
-#define SETREG16(x, y) ((*(vu16 *)x) = y)
-#define SETREG32(x, y) ((*(vu32 *)x) = y)
-#define SETREG64(x, y) ((*(vu64 *)x) = y)
-
-#define READREG8(x) (*(vu8 *)x)
-#define READREG16(x) (*(vu16 *)x)
-#define READREG32(x) (*(vu32 *)x)
-#define READREG64(x) (*(vu64 *)x)
-
 static inline void _GX_Load_16(u32 var, void *src, void *dst, u32 size){
     if (var != -1 && size > 0x1C)
     {
diff --git a/arm9/lib/src/GX.c b/arm9/lib/src/GX.c
index ca3e4604..883dfe69 100644
--- a/arm9/lib/src/GX.c
+++ b/arm9/lib/src/GX.c
@@ -8,9 +8,9 @@ extern u32 UNK_02106814;
 extern u16 UNK_02106810;
 
 ARM_FUNC void GX_Init(){
-    SETREG16(HW_REG_POWCNT1, READREG16(HW_REG_POWCNT1) | 0x8000);
-    SETREG16(HW_REG_POWCNT1, (READREG16(HW_REG_POWCNT1) & ~0x20E) | 0x20E);
-    SETREG16(HW_REG_POWCNT1, READREG16(HW_REG_POWCNT1) | 0x1);
+    reg_GX_POWCNT |= 0x8000;
+    reg_GX_POWCNT = (reg_GX_POWCNT & ~0x20E) | 0x20E;
+    reg_GX_POWCNT = reg_GX_POWCNT | 0x1;
     GX_InitGXState();
     u32 temp;
     while (UNK_021D33BC == 0)
@@ -22,88 +22,87 @@ ARM_FUNC void GX_Init(){
         }
         UNK_021D33BC = temp;
     }
-    SETREG16(HW_REG_DISPSTAT, 0x0);
-    SETREG32(HW_REG_DISPCNT, 0x0);
+    reg_GX_DISPSTAT = 0x0;
+    reg_GX_DISPCNT = 0x0;
     if (UNK_02106814 != -1)
     {
-        MI_DmaFill32(UNK_02106814, (void *)HW_REG_BG0CNT_A, 0x0, 0x60);
-        SETREG16(HW_REG_MASTER_BRIGHT, 0x0);
-        MI_DmaFill32(UNK_02106814, (void *)HW_REG_DISPCNT_2D, 0x0, 0x70);
+        MI_DmaFill32(UNK_02106814, (void *)&reg_G2_BG0CNT, 0x0, 0x60);
+        reg_GX_MASTER_BRIGHT = 0x0;
+        MI_DmaFill32(UNK_02106814, (void *)&reg_GXS_DB_DISPCNT, 0x0, 0x70);
     }
     else
     {
-        MIi_CpuClear32(0x0, (void *)HW_REG_BG0CNT_A, 0x60);
-        SETREG16(HW_REG_MASTER_BRIGHT, 0x0);
-        MIi_CpuClear32(0x0, (void *)HW_REG_DISPCNT_2D, 0x70);
+        MIi_CpuClear32(0x0, (void *)&reg_G2_BG0CNT, 0x60);
+        reg_GX_MASTER_BRIGHT = 0x0;
+        MIi_CpuClear32(0x0, (void *)&reg_GXS_DB_DISPCNT, 0x70);
     }
-    SETREG16(HW_REG_BG2PA_A, 0x100);
-    SETREG16(HW_REG_BG2PD_A, 0x100);
-    SETREG16(HW_REG_BG3PA_A, 0x100);
-    SETREG16(HW_REG_BG3PD_A, 0x100);
-    SETREG16(HW_REG_BG2PA_B, 0x100);
-    SETREG16(HW_REG_BG2PD_B, 0x100);
-    SETREG16(HW_REG_BG3PA_B, 0x100);
-    SETREG16(HW_REG_BG3PD_B, 0x100);
+    reg_G2_BG2PA = 0x100;
+    reg_G2_BG2PD = 0x100;
+    reg_G2_BG3PA = 0x100;
+    reg_G2_BG3PD = 0x100;
+    reg_G2S_DB_BG2PA = 0x100;
+    reg_G2S_DB_BG2PD = 0x100;
+    reg_G2S_DB_BG3PA = 0x100;
+    reg_G2S_DB_BG3PD = 0x100;
 }
 
 ARM_FUNC u32 GX_HBlankIntr(u32 enable){
-    u32 temp = READREG16(HW_REG_DISPSTAT) & 0x10;
+    u32 temp = reg_GX_DISPSTAT & 0x10;
     if (enable)
     {
-        SETREG16(HW_REG_DISPSTAT, READREG16(HW_REG_DISPSTAT) | 0x10);
+        reg_GX_DISPSTAT |= 0x10;
     }
     else
     {
-        SETREG16(HW_REG_DISPSTAT, READREG16(HW_REG_DISPSTAT) & ~0x10);
+        reg_GX_DISPSTAT &= ~0x10;
     }
     return temp;
 }
 
 ARM_FUNC u32 GX_VBlankIntr(u32 enable){
-    u32 temp = READREG16(HW_REG_DISPSTAT) & 0x8;
+    u32 temp = reg_GX_DISPSTAT & 0x8;
     if (enable)
     {
-        SETREG16(HW_REG_DISPSTAT, READREG16(HW_REG_DISPSTAT) | 0x8);
+        reg_GX_DISPSTAT |= 0x8;
     }
     else
     {
-        SETREG16(HW_REG_DISPSTAT, READREG16(HW_REG_DISPSTAT) & ~0x8);
+        reg_GX_DISPSTAT &= ~0x8;
     }
     return temp;
 }
 
 ARM_FUNC void GX_DispOff(){
-    u32 temp = READREG32(HW_REG_DISPCNT);
+    u32 temp = reg_GX_DISPCNT;
     UNK_02106810 = 0x0;
     UNK_021D33C0 = (temp & 0x30000) >> 0x10;
-    SETREG32(HW_REG_DISPCNT, temp & ~0x30000);
+    reg_GX_DISPCNT = temp & ~0x30000;
 }
 
 ARM_FUNC void GX_DispOn(){
     UNK_02106810 = 0x1;
     if (UNK_021D33C0)
     {
-        SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) & ~0x30000 | (UNK_021D33C0 << 0x10));
-
+        reg_GX_DISPCNT = reg_GX_DISPCNT & ~0x30000 | (UNK_021D33C0 << 0x10);
     }
     else
     {
-        SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) | 0x10000);
+        reg_GX_DISPCNT = reg_GX_DISPCNT | 0x10000;
     }
 }
 
 ARM_FUNC void GX_SetGraphicsMode(u32 mode1, u32 mode2, u32 mode3){
-    u32 temp2 = READREG32(HW_REG_DISPCNT);
+    u32 temp2 = reg_GX_DISPCNT;
     UNK_021D33C0 = mode1;
     if (!UNK_02106810)
         mode1 = 0;
-    SETREG32(HW_REG_DISPCNT, (mode2 | ((temp2 & 0xFFF0FFF0) | (mode1 << 0x10))) | (mode3 << 0x3));
+    reg_GX_DISPCNT = (mode2 | ((temp2 & 0xFFF0FFF0) | (mode1 << 0x10))) | (mode3 << 0x3);
     if (!UNK_021D33C0)
         UNK_02106810 = 0x0;
 }
 
 ARM_FUNC void GXS_SetGraphicsMode(u32 mode){
-    SETREG32(HW_REG_DISPCNT_2D, READREG32(HW_REG_DISPCNT_2D) & ~0x7 | mode);
+    reg_GXS_DB_DISPCNT = reg_GXS_DB_DISPCNT & ~0x7 | mode;
 }
 
 ARM_FUNC void GXx_SetMasterBrightness_(vu16 *dst, s32 brightness){
diff --git a/arm9/lib/src/GX_bgcnt.c b/arm9/lib/src/GX_bgcnt.c
index 1eeffab6..63fe87b1 100644
--- a/arm9/lib/src/GX_bgcnt.c
+++ b/arm9/lib/src/GX_bgcnt.c
@@ -3,27 +3,27 @@
 #include "gx.h"
 
 ARM_FUNC void *G2_GetBG0ScrPtr(){
-    u32 temp = (((READREG16(HW_REG_BG0CNT_A) & 0x1F00) >> 0x8) << 0xB);
-    return (void *)(0x6000000 + (((READREG32(HW_REG_DISPCNT_A) & 0x38000000) >> 0x1B) << 0x10) + temp);
+    u32 temp = (((reg_G2_BG0CNT & 0x1F00) >> 0x8) << 0xB);
+    return (void *)(0x6000000 + (((reg_GX_DISPCNT & 0x38000000) >> 0x1B) << 0x10) + temp);
 }
 
 ARM_FUNC void *G2S_GetBG0ScrPtr(){
-    return (void *)(0x6200000 + (((READREG16(HW_REG_BG0CNT_B) & 0x1F00) >> 0x8) << 0xB));
+    return (void *)(0x6200000 + (((reg_G2S_DB_BG0CNT & 0x1F00) >> 0x8) << 0xB));
 }
 
 ARM_FUNC void *G2_GetBG1ScrPtr(){
-    u32 temp = (((READREG16(HW_REG_BG1CNT_A) & 0x1F00) >> 0x8) << 0xB);
-    return (void *)(0x6000000 + (((READREG32(HW_REG_DISPCNT_A) & 0x38000000) >> 0x1B) << 0x10) + temp);
+    u32 temp = (((reg_G2_BG1CNT & 0x1F00) >> 0x8) << 0xB);
+    return (void *)(0x6000000 + (((reg_GX_DISPCNT & 0x38000000) >> 0x1B) << 0x10) + temp);
 }
 
 ARM_FUNC void *G2S_GetBG1ScrPtr(){
-    return (void *)(0x6200000 + (((READREG16(HW_REG_BG1CNT_B) & 0x1F00) >> 0x8) << 0xB));
+    return (void *)(0x6200000 + (((reg_G2S_DB_BG1CNT & 0x1F00) >> 0x8) << 0xB));
 }
 
 ARM_FUNC void *G2_GetBG2ScrPtr(){
-    u32 temp12 = (READREG32(HW_REG_DISPCNT_A) & 0x7);
-    u32 temp3 = READREG16(HW_REG_BG2CNT_A);
-    u32 temp2 = (((READREG32(HW_REG_DISPCNT_A) & 0x38000000) >> 0x1B) << 0x10);
+    u32 temp12 = (reg_GX_DISPCNT & 0x7);
+    u32 temp3 = reg_G2_BG2CNT;
+    u32 temp2 = (((reg_GX_DISPCNT & 0x38000000) >> 0x1B) << 0x10);
     u32 temp1 = ((temp3 & 0x1F00) >> 0x8);
     switch (temp12)
     {
@@ -46,8 +46,8 @@ ARM_FUNC void *G2_GetBG2ScrPtr(){
 }
 
 ARM_FUNC void *G2S_GetBG2ScrPtr(){
-    u32 temp12 = (READREG32(HW_REG_DISPCNT_B) & 0x7);
-    u32 temp3 = READREG16(HW_REG_BG2CNT_B);
+    u32 temp12 = (reg_GXS_DB_DISPCNT & 0x7);
+    u32 temp3 = reg_G2S_DB_BG2CNT;
     u32 temp1 = ((temp3 & 0x1F00) >> 0x8);
     switch (temp12)
     {
@@ -70,9 +70,9 @@ ARM_FUNC void *G2S_GetBG2ScrPtr(){
 }
 
 ARM_FUNC void *G2_GetBG3ScrPtr(){
-    u32 temp12 = (READREG32(HW_REG_DISPCNT_A) & 0x7);
-    u32 temp3 = READREG16(HW_REG_BG3CNT_A);
-    u32 temp2 = (((READREG32(HW_REG_DISPCNT_A) & 0x38000000) >> 0x1B) << 0x10);
+    u32 temp12 = (reg_GX_DISPCNT & 0x7);
+    u32 temp3 = reg_G2_BG3CNT;
+    u32 temp2 = (((reg_GX_DISPCNT & 0x38000000) >> 0x1B) << 0x10);
     u32 temp1 = ((temp3 & 0x1F00) >> 0x8);
     switch (temp12)
     {
@@ -95,8 +95,8 @@ ARM_FUNC void *G2_GetBG3ScrPtr(){
 }
 
 ARM_FUNC void *G2S_GetBG3ScrPtr(){
-    u32 temp12 = (READREG32(HW_REG_DISPCNT_B) & 0x7);
-    u32 temp3 = READREG16(HW_REG_BG3CNT_B);
+    u32 temp12 = (reg_GXS_DB_DISPCNT & 0x7);
+    u32 temp3 = reg_G2S_DB_BG3CNT;
     u32 temp1 = ((temp3 & 0x1F00) >> 0x8);
     switch (temp12)
     {
@@ -119,29 +119,29 @@ ARM_FUNC void *G2S_GetBG3ScrPtr(){
 }
 
 ARM_FUNC void *G2_GetBG0CharPtr(){
-    u32 temp = (((READREG16(HW_REG_BG0CNT_A) & 0x3C) >> 0x2) << 0xE);
-    return (void *)(0x6000000 + (((READREG32(HW_REG_DISPCNT_A) & 0x7000000) >> 0x18) << 0x10) + temp);
+    u32 temp = (((reg_G2_BG0CNT & 0x3C) >> 0x2) << 0xE);
+    return (void *)(0x6000000 + (((reg_GX_DISPCNT & 0x7000000) >> 0x18) << 0x10) + temp);
 }
 
 ARM_FUNC void *G2S_GetBG0CharPtr(){
-    return (void *)(0x6200000 + (((READREG16(HW_REG_BG0CNT_B) & 0x3C) >> 0x2) << 0xE));
+    return (void *)(0x6200000 + (((reg_G2S_DB_BG0CNT & 0x3C) >> 0x2) << 0xE));
 }
 
 ARM_FUNC void *G2_GetBG1CharPtr(){
-    u32 temp = (((READREG16(HW_REG_BG1CNT_A) & 0x3C) >> 0x2) << 0xE);
-    return (void *)(0x6000000 + (((READREG32(HW_REG_DISPCNT_A) & 0x7000000) >> 0x18) << 0x10) + temp);
+    u32 temp = (((reg_G2_BG1CNT & 0x3C) >> 0x2) << 0xE);
+    return (void *)(0x6000000 + (((reg_GX_DISPCNT & 0x7000000) >> 0x18) << 0x10) + temp);
 }
 
 ARM_FUNC void *G2S_GetBG1CharPtr(){
-    return (void *)(0x6200000 + (((READREG16(HW_REG_BG1CNT_B) & 0x3C) >> 0x2) << 0xE));
+    return (void *)(0x6200000 + (((reg_G2S_DB_BG1CNT & 0x3C) >> 0x2) << 0xE));
 }
 
 ARM_FUNC void *G2_GetBG2CharPtr(){
-    s32 temp1 = (READREG32(HW_REG_DISPCNT_A) & 0x7);
-    u32 temp = READREG16(HW_REG_BG2CNT_A);
+    s32 temp1 = (reg_GX_DISPCNT & 0x7);
+    u32 temp = reg_G2_BG2CNT;
     if (temp1 < 5 || !(temp & 0x80))
     {
-        u32 temp1 = (((READREG32(HW_REG_DISPCNT_A) & 0x7000000) >> 0x18) << 0x10);
+        u32 temp1 = (((reg_GX_DISPCNT & 0x7000000) >> 0x18) << 0x10);
         u32 temp2 = (temp & 0x3C) >> 2;
         return (void *)(0x6000000 + temp1 + (temp2 << 0xE));
     }
@@ -152,8 +152,8 @@ ARM_FUNC void *G2_GetBG2CharPtr(){
 }
 
 ARM_FUNC void *G2S_GetBG2CharPtr(){
-    s32 temp1 = (READREG32(HW_REG_DISPCNT_B) & 0x7);
-    u32 temp = READREG16(HW_REG_BG2CNT_B);
+    s32 temp1 = (reg_GXS_DB_DISPCNT & 0x7);
+    u32 temp = reg_G2S_DB_BG2CNT;
     if (temp1 < 5 || !(temp & 0x80))
     {
         u32 temp2 = ((temp & 0x3C) >> 2) << 0xE;
@@ -166,11 +166,11 @@ ARM_FUNC void *G2S_GetBG2CharPtr(){
 }
 
 ARM_FUNC void *G2_GetBG3CharPtr(){
-    s32 temp1 = (READREG32(HW_REG_DISPCNT_A) & 0x7);
-    u32 temp = READREG16(HW_REG_BG3CNT_A);
+    s32 temp1 = (reg_GX_DISPCNT & 0x7);
+    u32 temp = reg_G2_BG3CNT;
     if (temp1 < 3 || (temp1 < 6 && !(temp & 0x80)))
     {
-        u32 temp1 = (((READREG32(HW_REG_DISPCNT_A) & 0x7000000) >> 0x18) << 0x10);
+        u32 temp1 = (((reg_GX_DISPCNT & 0x7000000) >> 0x18) << 0x10);
         u32 temp2 = (temp & 0x3C) >> 2;
         return (void *)(0x6000000 + temp1 + (temp2 << 0xE));
     }
@@ -181,8 +181,8 @@ ARM_FUNC void *G2_GetBG3CharPtr(){
 }
 
 ARM_FUNC void *G2S_GetBG3CharPtr(){
-    s32 temp1 = (READREG32(HW_REG_DISPCNT_B) & 0x7);
-    u32 temp = READREG16(HW_REG_BG3CNT_B);
+    s32 temp1 = (reg_GXS_DB_DISPCNT & 0x7);
+    u32 temp = reg_G2S_DB_BG3CNT;
     if (temp1 < 3 || (temp1 < 6 && !(temp & 0x80)))
     {
         u32 temp2 = ((temp & 0x3C) >> 2) << 0xE;
diff --git a/arm9/lib/src/GX_g3_util.c b/arm9/lib/src/GX_g3_util.c
index 75e18589..f34e23ed 100644
--- a/arm9/lib/src/GX_g3_util.c
+++ b/arm9/lib/src/GX_g3_util.c
@@ -11,12 +11,12 @@ ARM_FUNC void G3i_PerspectiveW_(fx32 fovsin, fx32 fovcos, fx32 ratio, fx32 near,
     fovcot = FX_Div(fovcos, fovsin);
     if (scale != 0x1000) //!= 1.0
         fovcot = (fovcot * scale) / 0x1000;
-    SETREG64(HW_REG_DIV_NUMER, (s64)fovcot << 0x20);
-    SETREG64(HW_REG_DIV_DENOM, (u32)ratio);
+    reg_CP_DIV_NUMER = (s64)fovcot << 0x20;
+    reg_CP_DIV_DENOM = (u32)ratio;
     if (load)
     {
-        SETREG32(HW_REG_MTX_MODE, 0x0);
-        reg_ptr = (vu32 *)HW_REG_MTX_LOAD_4x4;
+        reg_G3_MTX_MODE =  0x0;
+        reg_ptr = (vu32 *)&reg_G3_MTX_LOAD_4x4;
     }
     if (mtx)
     {
@@ -34,8 +34,8 @@ ARM_FUNC void G3i_PerspectiveW_(fx32 fovsin, fx32 fovcos, fx32 ratio, fx32 near,
         mtx->_[15] = 0x0;
     }
     temp1 = FX_GetDivResult();
-    SETREG64(HW_REG_DIV_NUMER, (s64)0x1000 << 0x20);
-    SETREG64(HW_REG_DIV_DENOM, (u32)(near - far));
+    reg_CP_DIV_NUMER = (s64)0x1000 << 0x20;
+    reg_CP_DIV_DENOM = (u32)(near - far);
     if (load)
     {
         *reg_ptr = temp1;
@@ -83,8 +83,8 @@ ARM_FUNC void G3i_OrthoW_(fx32 top, fx32 bottom, fx32 left, fx32 right, fx32 nea
     FX_InvAsync(right - left);
     if (load)
     {
-        SETREG32(HW_REG_MTX_MODE, 0x0);
-        reg_ptr = (vu32 *)HW_REG_MTX_LOAD_4x4;
+        reg_G3_MTX_MODE = 0x0;
+        reg_ptr = (vu32 *)&reg_G3_MTX_LOAD_4x4;
     }
     if (mtx)
     {
@@ -100,8 +100,8 @@ ARM_FUNC void G3i_OrthoW_(fx32 top, fx32 bottom, fx32 left, fx32 right, fx32 nea
         mtx->_[15] = scale;
     }
     temp1 = FX_GetDivResultFx64c();
-    SETREG64(HW_REG_DIV_NUMER, (s64)0x1000 << 0x20);
-    SETREG64(HW_REG_DIV_DENOM, (u32)(top - bottom));
+    reg_CP_DIV_NUMER = (s64)0x1000 << 0x20;
+    reg_CP_DIV_DENOM = (u32)(top - bottom);
     if (scale != 0x1000)
         temp1 = (temp1 * scale) / 0x1000;
     temp0 = (0x2000 * temp1 + ((fx64)1 << (FX64C_INT_SHIFT - 1))) >> FX64C_INT_SHIFT;
@@ -118,8 +118,8 @@ ARM_FUNC void G3i_OrthoW_(fx32 top, fx32 bottom, fx32 left, fx32 right, fx32 nea
         mtx->_[0] = temp0;
     }
     temp2 = FX_GetDivResultFx64c();
-    SETREG64(HW_REG_DIV_NUMER, (s64)0x1000 << 0x20);
-    SETREG64(HW_REG_DIV_DENOM, (u32)(near - far));
+    reg_CP_DIV_NUMER = (s64)0x1000 << 0x20;
+    reg_CP_DIV_DENOM = (u32)(near - far);
     if (scale != 0x1000)
         temp2 = (temp2 * scale) / 0x1000;
     temp0 = (0x2000 * temp2 + ((fx64)1 << (FX64C_INT_SHIFT - 1))) >> FX64C_INT_SHIFT;
@@ -179,8 +179,8 @@ ARM_FUNC void G3i_LookAt_(struct Vecx32 *a, struct Vecx32 *b, struct Vecx32 *c,
     VEC_CrossProduct(&temp, &temp1, &temp2);
     if (load)
     {
-        SETREG32(HW_REG_MTX_MODE, 0x2);
-        reg_ptr = (vu32 *)HW_REG_MTX_LOAD_4x3;
+        reg_G3_MTX_MODE = 0x2;
+        reg_ptr = (vu32 *)&reg_G3_MTX_LOAD_4x3;
         *reg_ptr = temp1.x;
         *reg_ptr = temp2.x;
         *reg_ptr = temp.x;
@@ -219,7 +219,7 @@ ARM_FUNC void G3i_LookAt_(struct Vecx32 *a, struct Vecx32 *b, struct Vecx32 *c,
 
 ARM_FUNC void G3_RotX(fx32 sinphi, fx32 cosphi){
     vu32 *reg_ptr;
-    reg_ptr = (vu32 *)HW_REG_MTX_MULT_3x3;
+    reg_ptr = (vu32 *)&reg_G3_MTX_MULT_3x3;
     *reg_ptr = 0x1000;
     *reg_ptr = 0x0;
     *reg_ptr = 0x0;
@@ -233,7 +233,7 @@ ARM_FUNC void G3_RotX(fx32 sinphi, fx32 cosphi){
 
 ARM_FUNC void G3_RotY(fx32 sinphi, fx32 cosphi){
     vu32 *reg_ptr;
-    reg_ptr = (vu32 *)HW_REG_MTX_MULT_3x3;
+    reg_ptr = (vu32 *)&reg_G3_MTX_MULT_3x3;
     *reg_ptr = cosphi;
     *reg_ptr = 0x0;
     *reg_ptr = -sinphi;
@@ -247,7 +247,7 @@ ARM_FUNC void G3_RotY(fx32 sinphi, fx32 cosphi){
 
 ARM_FUNC void G3_RotZ(fx32 sinphi, fx32 cosphi){
     vu32 *reg_ptr;
-    reg_ptr = (vu32 *)HW_REG_MTX_MULT_3x3;
+    reg_ptr = (vu32 *)&reg_G3_MTX_MULT_3x3;
     *reg_ptr = cosphi;
     *reg_ptr = sinphi;
     *reg_ptr = 0x0;
diff --git a/arm9/lib/src/GX_g3imm.c b/arm9/lib/src/GX_g3imm.c
index f11e2927..a5c62c26 100644
--- a/arm9/lib/src/GX_g3imm.c
+++ b/arm9/lib/src/GX_g3imm.c
@@ -3,16 +3,16 @@
 #include "gx.h"
 
 ARM_FUNC void G3_LoadMtx43(struct Mtx43 *mtx){
-    SETREG32(HW_REG_GXFIFO, 0x17);
-    GX_SendFifo48B(mtx, (void *)HW_REG_GXFIFO);
+    reg_G3X_GXFIFO = 0x17;
+    GX_SendFifo48B(mtx, (void *)&reg_G3X_GXFIFO);
 }
 
 ARM_FUNC void G3_MultMtx43(struct Mtx43 *mtx){
-    SETREG32(HW_REG_GXFIFO, 0x19);
-    GX_SendFifo48B(mtx, (void *)HW_REG_GXFIFO);
+    reg_G3X_GXFIFO = 0x19;
+    GX_SendFifo48B(mtx, (void *)&reg_G3X_GXFIFO);
 }
 
 ARM_FUNC void G3_MultMtx33(struct Mtx33 *mtx){
-    SETREG32(HW_REG_GXFIFO, 0x1A);
-    MI_Copy36B(mtx, (void *)HW_REG_GXFIFO);
+    reg_G3X_GXFIFO = 0x1A;
+    MI_Copy36B(mtx, (void *)&reg_G3X_GXFIFO);
 }
diff --git a/arm9/lib/src/GX_g3x.c b/arm9/lib/src/GX_g3x.c
index e76adce7..5a03c4ca 100644
--- a/arm9/lib/src/GX_g3x.c
+++ b/arm9/lib/src/GX_g3x.c
@@ -46,190 +46,190 @@ ARM_FUNC asm void GXi_NopClearFifo128_(void *reg){
 
 ARM_FUNC void G3X_Init(){
     G3X_ClearFifo();
-    SETREG32(HW_REG_END_VTXS, 0x0);
-    while (READREG32(HW_REG_GXSTAT) & 0x8000000); //wait for geometry engine to not be busy
-    SETREG16(HW_REG_DISP3DCNT, 0x0);
-    SETREG32(HW_REG_GXSTAT, 0x0);
-    SETREG32(HW_REG_BG0HOFS, 0x0);
-    SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x2000);
-    SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x1000);
-    SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & ~0x3002);
-    SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & ~0x3000 | 0x10);
-    SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & (u16)~0x3004);
-    SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
-    SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) & ~0xC0000000 | 0x80000000);
+    reg_G3_END_VTXS = 0x0;
+    while (reg_G3X_GXSTAT & 0x8000000); //wait for geometry engine to not be busy
+    reg_G3X_DISP3DCNT = 0x0;
+    reg_G3X_GXSTAT = 0x0;
+    reg_G2_BG0OFS = 0x0;
+    reg_G3X_DISP3DCNT |= 0x2000;
+    reg_G3X_DISP3DCNT |= 0x1000;
+    reg_G3X_DISP3DCNT &= ~0x3002;
+    reg_G3X_DISP3DCNT = reg_G3X_DISP3DCNT & ~0x3000 | 0x10;
+    reg_G3X_DISP3DCNT = reg_G3X_DISP3DCNT & (u16)~0x3004;
+    reg_G3X_GXSTAT |= 0x8000;
+    reg_G3X_GXSTAT = reg_G3X_GXSTAT & ~0xC0000000 | 0x80000000;
     G3X_InitMtxStack();
-    SETREG32(HW_REG_CLEAR_COLOR, 0x0);
-    SETREG16(HW_REG_CLEAR_DEPTH, 0x7FFF);
-    SETREG16(HW_REG_CLRIMAGE_OFFSET, 0x0);
-    SETREG32(HW_REG_FOG_COLOR, 0x0);
-    SETREG16(HW_REG_FOG_OFFSET, 0x0);
-    SETREG16(HW_REG_BG0CNT, READREG16(HW_REG_BG0CNT) & ~0x3);
+    reg_G3X_CLEAR_COLOR = 0x0;
+    reg_G3X_CLEAR_DEPTH = 0x7FFF;
+    reg_G3X_CLRIMAGE_OFFSET = 0x0;
+    reg_G3X_FOG_COLOR = 0x0;
+    reg_G3X_FOG_OFFSET = 0x0;
+    reg_G2_BG0CNT &= ~0x3;
     G3X_InitTable();
-    SETREG32(HW_REG_POLYGON_ATTR, 0x1F0080);
-    SETREG32(HW_REG_TEXIMAGE_PARAM, 0x0);
-    SETREG32(HW_REG_PLTT_BASE, 0x0);
+    reg_G3_POLYGON_ATTR = 0x1F0080;
+    reg_G3_TEXIMAGE_PARAM = 0x0;
+    reg_G3_TEXPLTT_BASE = 0x0;
 }
 
 ARM_FUNC void G3X_ResetMtxStack(){
-    while (READREG32(HW_REG_GXSTAT) & 0x8000000);
-    SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
-    SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x2000);
-    SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x1000);
+    while (reg_G3X_GXSTAT & 0x8000000);
+    reg_G3X_GXSTAT |= 0x8000;
+    reg_G3X_DISP3DCNT |= 0x2000;
+    reg_G3X_DISP3DCNT |= 0x1000;
     G3X_ResetMtxStack_2();
-    SETREG32(HW_REG_POLYGON_ATTR, 0x1F0080);
-    SETREG32(HW_REG_TEXIMAGE_PARAM, 0x0);
-    SETREG32(HW_REG_PLTT_BASE, 0x0);
+    reg_G3_POLYGON_ATTR = 0x1F0080;
+    reg_G3_TEXIMAGE_PARAM = 0x0;
+    reg_G3_TEXPLTT_BASE = 0x0;
 }
 
 ARM_FUNC void G3X_ClearFifo(){
-    GXi_NopClearFifo128_((void *)HW_REG_GXFIFO);
-    while (READREG32(HW_REG_GXSTAT) & 0x8000000);
+    GXi_NopClearFifo128_((void *)&reg_G3X_GXFIFO);
+    while (reg_G3X_GXSTAT & 0x8000000);
 }
 
 ARM_FUNC void G3X_InitMtxStack(){
     u32 PV_level, PJ_level;
-    SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
+    reg_G3X_GXSTAT |= 0x8000;
     while (G3X_GetMtxStackLevelPV(&PV_level));
     while (G3X_GetMtxStackLevelPJ(&PJ_level));
-    SETREG32(HW_REG_MTX_MODE, 0x3);
-    SETREG32(HW_REG_MTX_IDENTITY, 0x0);
-    SETREG32(HW_REG_MTX_MODE, 0x0);
+    reg_G3_MTX_MODE = 0x3;
+    reg_G3_MTX_IDENTITY = 0x0;
+    reg_G3_MTX_MODE = 0x0;
     if (PJ_level)
     {
-        SETREG32(HW_REG_MTX_POP, PJ_level);
+        reg_G3_MTX_POP = PJ_level;
     }
-    SETREG32(HW_REG_MTX_IDENTITY, 0x0);
-    SETREG32(HW_REG_MTX_MODE, 0x2);
-    SETREG32(HW_REG_MTX_POP, PV_level);
-    SETREG32(HW_REG_MTX_IDENTITY, 0x0);
+    reg_G3_MTX_IDENTITY = 0x0;
+    reg_G3_MTX_MODE = 0x2;
+    reg_G3_MTX_POP = PV_level;
+    reg_G3_MTX_IDENTITY = 0x0;
 }
 
 ARM_FUNC void G3X_ResetMtxStack_2(){
     u32 PV_level, PJ_level;
-    SETREG32(HW_REG_GXSTAT, READREG32(HW_REG_GXSTAT) | 0x8000);
+    reg_G3X_GXSTAT |= 0x8000;
     while (G3X_GetMtxStackLevelPV(&PV_level));
     while (G3X_GetMtxStackLevelPJ(&PJ_level));
-    SETREG32(HW_REG_MTX_MODE, 0x3);
-    SETREG32(HW_REG_MTX_IDENTITY, 0x0);
-    SETREG32(HW_REG_MTX_MODE, 0x0);
+    reg_G3_MTX_MODE = 0x3;
+    reg_G3_MTX_IDENTITY = 0x0;
+    reg_G3_MTX_MODE = 0x0;
     if (PJ_level)
     {
-        SETREG32(HW_REG_MTX_POP, PJ_level);
+        reg_G3_MTX_POP = PJ_level;
     }
 
-    SETREG32(HW_REG_MTX_MODE, 0x2);
-    SETREG32(HW_REG_MTX_POP, PV_level);
-    SETREG32(HW_REG_MTX_IDENTITY, 0x0);
+    reg_G3_MTX_MODE = 0x2;
+    reg_G3_MTX_POP = PV_level;
+    reg_G3_MTX_IDENTITY = 0x0;
 
 }
 
 ARM_FUNC void G3X_SetFog(u32 enable, u32 alphamode, u32 depth, s32 offset){
     if (enable)
     {
-        SETREG16(HW_REG_FOG_OFFSET, offset);
-        SETREG16(HW_REG_DISP3DCNT,  (READREG16(HW_REG_DISP3DCNT) &~0x3f40) | (((depth << 0x8)|  (alphamode << 0x6)|0x80 )));
+        reg_G3X_FOG_OFFSET = offset;
+        reg_G3X_DISP3DCNT = (reg_G3X_DISP3DCNT &~0x3f40) | (((depth << 0x8)|  (alphamode << 0x6)|0x80 ));
 
     }
     else
     {
-        SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & (u16)~0x3080);
+        reg_G3X_DISP3DCNT = reg_G3X_DISP3DCNT & (u16)~0x3080;
     }
 }
 
 ARM_FUNC u32 G3X_GetClipMtx(struct Mtx44 *dst){
-    if (READREG32(HW_REG_GXSTAT) & 0x8000000)
+    if (reg_G3X_GXSTAT & 0x8000000)
     {
         return -1;
     }
     else
     {
-        MI_Copy64B((void *)HW_REG_CLIPMTX_RESULT, dst);
+        MI_Copy64B((void *)&reg_G3X_CLIPMTX_RESULT_0, dst);
         return 0;
     }
 }
 
 ARM_FUNC u32 G3X_GetVectorMtx(struct Mtx33 *dst){
-    if (READREG32(HW_REG_GXSTAT) & 0x8000000)
+    if (reg_G3X_GXSTAT & 0x8000000)
     {
         return -1;
     }
     else
     {
-        MI_Copy36B((void *)HW_REG_VECMTX_RESULT, dst);
+        MI_Copy36B((void *)&reg_G3X_VECMTX_RESULT_0, dst);
         return 0;
     }
 }
 
 ARM_FUNC void G3X_SetEdgeColorTable(void *tbl_ptr){
-    MIi_CpuCopy16(tbl_ptr, (void *)HW_REG_EDGE_COLOR, 0x10);
+    MIi_CpuCopy16(tbl_ptr, (void *)&reg_G3X_EDGE_COLOR_0, 0x10);
 }
 
 ARM_FUNC void G3X_SetFogTable(void *tbl_ptr){
-    MI_Copy16B(tbl_ptr, (void *)HW_REG_FOG_TABLE);
+    MI_Copy16B(tbl_ptr, (void *)&reg_G3X_FOG_TABLE_0);
 }
 
 ARM_FUNC void G3X_SetClearColor(u32 col, u32 alpha, u32 depth, u32 polygon_id, u32 enable_fog){
     u32 temp = col | (alpha << 0x10) | (polygon_id << 0x18);
     if (enable_fog)
         temp |= 0x8000;
-    SETREG32(HW_REG_CLEAR_COLOR, temp);
-    SETREG16(HW_REG_CLEAR_DEPTH, depth);
+    reg_G3X_CLEAR_COLOR = temp;
+    reg_G3X_CLEAR_DEPTH = depth;
 }
 
 ARM_FUNC void G3X_InitTable(){
     if (UNK_02106814 != -1)
     {
-        MI_DmaFill32Async(UNK_02106814, (void *)HW_REG_EDGE_COLOR, 0x0, 0x10, 0x0, 0x0);
-        MI_DmaFill32(UNK_02106814, (void *)HW_REG_FOG_TABLE, 0x0, 0x60);
+        MI_DmaFill32Async(UNK_02106814, (void *)&reg_G3X_EDGE_COLOR_0, 0x0, 0x10, 0x0, 0x0);
+        MI_DmaFill32(UNK_02106814, (void *)&reg_G3X_FOG_TABLE_0, 0x0, 0x60);
     }
     else
     {
-        MIi_CpuClear32(0x0, (void *)HW_REG_EDGE_COLOR, 0x10);
-        MIi_CpuClear32(0x0, (void *)HW_REG_FOG_TABLE, 0x60);
+        MIi_CpuClear32(0x0, (void *)&reg_G3X_EDGE_COLOR_0, 0x10);
+        MIi_CpuClear32(0x0, (void *)&reg_G3X_FOG_TABLE_0, 0x60);
     }
     for (int i = 0; i < 0x20; i++)
     {
-        SETREG32(HW_REG_SHININESS, 0x0);
+        reg_G3_SHININESS = 0x0;
     }
 }
 
 ARM_FUNC u32 G3X_GetMtxStackLevelPV(u32 *level){
-    if (READREG32(HW_REG_GXSTAT) & 0x4000)
+    if (reg_G3X_GXSTAT & 0x4000)
     {
         return -1;
     }
     else
     {
-        *level = (READREG32(HW_REG_GXSTAT) & 0x1F00) >> 0x8;
+        *level = (reg_G3X_GXSTAT & 0x1F00) >> 0x8;
         return 0;
     }
 }
 
 ARM_FUNC u32 G3X_GetMtxStackLevelPJ(u32 *level){
-    if (READREG32(HW_REG_GXSTAT) & 0x4000)
+    if (reg_G3X_GXSTAT & 0x4000)
     {
         return -1;
     }
     else
     {
-        *level = (READREG32(HW_REG_GXSTAT) & 0x2000) >> 0xD;
+        *level = (reg_G3X_GXSTAT & 0x2000) >> 0xD;
         return 0;
     }
 }
 
 ARM_FUNC u32 G3X_GetBoxTestResult(u32 *result){
-    if (READREG32(HW_REG_GXSTAT) & 0x1)
+    if (reg_G3X_GXSTAT & 0x1)
     {
         return -1;
     }
     else
     {
-        *result = (READREG32(HW_REG_GXSTAT) & 0x2);
+        *result = (reg_G3X_GXSTAT & 0x2);
         return 0;
     }
 }
 
 ARM_FUNC void G3X_SetHOffset(u32 offset){
-    SETREG32(HW_REG_BG0HOFS, offset);
+    reg_G2_BG0OFS = offset;
 }
diff --git a/arm9/lib/src/GX_state.c b/arm9/lib/src/GX_state.c
index 79a53ee7..7da3e1b4 100644
--- a/arm9/lib/src/GX_state.c
+++ b/arm9/lib/src/GX_state.c
@@ -18,9 +18,9 @@ ARM_FUNC void GX_InitGXState(){
     UNK_021D33C4.var14 = 0x0;
     UNK_021D33C4.var16 = 0x0;
     UNK_021D33C4.var18 = 0x0;
-    SETREG32(HW_REG_VRAMCNT_A, 0x0);
-    SETREG8(HW_REG_VRAMCNT_E, 0x0);
-    SETREG8(HW_REG_VRAMCNT_F, 0x0);
-    SETREG8(HW_REG_VRAMCNT_G, 0x0);
-    SETREG16(HW_REG_VRAMCNT_H, 0x0);
+    reg_GX_VRAMCNT = 0x0;
+    reg_GX_VRAMCNT_E = 0x0;
+    reg_GX_VRAMCNT_F = 0x0;
+    reg_GX_VRAMCNT_G = 0x0;
+    reg_GX_VRAM_HI_CNT = 0x0;
 }
diff --git a/arm9/lib/src/GX_vramcnt.c b/arm9/lib/src/GX_vramcnt.c
index fdedca46..18507fa4 100644
--- a/arm9/lib/src/GX_vramcnt.c
+++ b/arm9/lib/src/GX_vramcnt.c
@@ -7,23 +7,23 @@ extern struct VRAM_banks UNK_021D33C4;
 
 ARM_FUNC void GX_VRAMCNT_SetLCDC_(u32 mask){
     if (mask & (0x1 << 0))
-        SETREG8(HW_REG_VRAMCNT_A, 0x80);
+        reg_GX_VRAMCNT_A = 0x80;
     if (mask & (0x1 << 1))
-        SETREG8(HW_REG_VRAMCNT_B, 0x80);
+        reg_GX_VRAMCNT_B = 0x80;
     if (mask & (0x1 << 2))
-        SETREG8(HW_REG_VRAMCNT_C, 0x80);
+        reg_GX_VRAMCNT_C = 0x80;
     if (mask & (0x1 << 3))
-        SETREG8(HW_REG_VRAMCNT_D, 0x80);
+        reg_GX_VRAMCNT_D = 0x80;
     if (mask & (0x1 << 4))
-        SETREG8(HW_REG_VRAMCNT_E, 0x80);
+        reg_GX_VRAMCNT_E = 0x80;
     if (mask & (0x1 << 5))
-        SETREG8(HW_REG_VRAMCNT_F, 0x80);
+        reg_GX_VRAMCNT_F = 0x80;
     if (mask & (0x1 << 6))
-        SETREG8(HW_REG_VRAMCNT_G, 0x80);
+        reg_GX_VRAMCNT_G = 0x80;
     if (mask & (0x1 << 7))
-        SETREG8(HW_REG_VRAMCNT_H, 0x80);
+        reg_GX_VRAMCNT_H = 0x80;
     if (mask & (0x1 << 8))
-        SETREG8(HW_REG_VRAMCNT_I, 0x80);
+        reg_GX_VRAMCNT_I = 0x80;
 }
 
 ARM_FUNC void GX_SetBankForBG(s32 bg){
@@ -32,66 +32,66 @@ ARM_FUNC void GX_SetBankForBG(s32 bg){
     switch (bg)
     {
     case 8:
-        SETREG8(HW_REG_VRAMCNT_D, 0x81);
+        reg_GX_VRAMCNT_D = 0x81;
         break;
     case 12:
-        SETREG8(HW_REG_VRAMCNT_D, 0x89);
+        reg_GX_VRAMCNT_D = 0x89;
     case 4:
-        SETREG8(HW_REG_VRAMCNT_C, 0x81);
+        reg_GX_VRAMCNT_C = 0x81;
         break;
     case 14:
-        SETREG8(HW_REG_VRAMCNT_D, 0x91);
+        reg_GX_VRAMCNT_D = 0x91;
     case 6:
-        SETREG8(HW_REG_VRAMCNT_C, 0x89);
+        reg_GX_VRAMCNT_C = 0x89;
     case 2:
-        SETREG8(HW_REG_VRAMCNT_B, 0x81);
+        reg_GX_VRAMCNT_B = 0x81;
         break;
     case 15:
-        SETREG8(HW_REG_VRAMCNT_D, 0x99);
+        reg_GX_VRAMCNT_D = 0x99;
     case 7:
-        SETREG8(HW_REG_VRAMCNT_C, 0x91);
+        reg_GX_VRAMCNT_C = 0x91;
     case 3:
-        SETREG8(HW_REG_VRAMCNT_B, 0x89);
+        reg_GX_VRAMCNT_B = 0x89;
     case 1:
-        SETREG8(HW_REG_VRAMCNT_A, 0x81);
+        reg_GX_VRAMCNT_A = 0x81;
         break;
     case 11:
-        SETREG8(HW_REG_VRAMCNT_A, 0x81);
-        SETREG8(HW_REG_VRAMCNT_B, 0x89);
-        SETREG8(HW_REG_VRAMCNT_D, 0x91);
+        reg_GX_VRAMCNT_A = 0x81;
+        reg_GX_VRAMCNT_B = 0x89;
+        reg_GX_VRAMCNT_D = 0x91;
         break;
     case 13:
-        SETREG8(HW_REG_VRAMCNT_D, 0x91);
+        reg_GX_VRAMCNT_D = 0x91;
     case 5:
-        SETREG8(HW_REG_VRAMCNT_A, 0x81);
-        SETREG8(HW_REG_VRAMCNT_C, 0x89);
+        reg_GX_VRAMCNT_A = 0x81;
+        reg_GX_VRAMCNT_C = 0x89;
         break;
     case 9:
-        SETREG8(HW_REG_VRAMCNT_A, 0x81);
-        SETREG8(HW_REG_VRAMCNT_D, 0x89);
+        reg_GX_VRAMCNT_A = 0x81;
+        reg_GX_VRAMCNT_D = 0x89;
         break;
     case 10:
-        SETREG8(HW_REG_VRAMCNT_B, 0x81);
-        SETREG8(HW_REG_VRAMCNT_D, 0x89);
+        reg_GX_VRAMCNT_B = 0x81;
+        reg_GX_VRAMCNT_D = 0x89;
         break;
     case 112:
-        SETREG8(HW_REG_VRAMCNT_G, 0x99);
+        reg_GX_VRAMCNT_G = 0x99;
     case 48:
-        SETREG8(HW_REG_VRAMCNT_F, 0x91);
+        reg_GX_VRAMCNT_F = 0x91;
     case 16:
-        SETREG8(HW_REG_VRAMCNT_E, 0x81);
+        reg_GX_VRAMCNT_E = 0x81;
         break;
     case 80:
-        SETREG8(HW_REG_VRAMCNT_G, 0x91);
-        SETREG8(HW_REG_VRAMCNT_E, 0x81);
+        reg_GX_VRAMCNT_G = 0x91;
+        reg_GX_VRAMCNT_E = 0x81;
         break;
     case 96:
-        SETREG8(HW_REG_VRAMCNT_G, 0x89);
+        reg_GX_VRAMCNT_G = 0x89;
     case 32:
-        SETREG8(HW_REG_VRAMCNT_F, 0x81);
+        reg_GX_VRAMCNT_F = 0x81;
         break;
     case 64:
-        SETREG8(HW_REG_VRAMCNT_G, 0x81);
+        reg_GX_VRAMCNT_G = 0x81;
         break;
     default:
         break;
@@ -105,32 +105,32 @@ ARM_FUNC void GX_SetBankForOBJ(s32 obj){
     switch (obj)
     {
     case 3:
-        SETREG8(HW_REG_VRAMCNT_B, 0x8A);
+        reg_GX_VRAMCNT_B = 0x8A;
     case 1:
-        SETREG8(HW_REG_VRAMCNT_A, 0x82);
+        reg_GX_VRAMCNT_A = 0x82;
     case 0:  //needed to match
         break;
     case 2:
-        SETREG8(HW_REG_VRAMCNT_B, 0x82);
+        reg_GX_VRAMCNT_B = 0x82;
         break;
     case 112:
-        SETREG8(HW_REG_VRAMCNT_G, 0x9A);
+        reg_GX_VRAMCNT_G = 0x9A;
     case 48:
-        SETREG8(HW_REG_VRAMCNT_F, 0x92);
+        reg_GX_VRAMCNT_F = 0x92;
     case 16:
-        SETREG8(HW_REG_VRAMCNT_E, 0x82);
+        reg_GX_VRAMCNT_E = 0x82;
         break;
     case 80:
-        SETREG8(HW_REG_VRAMCNT_G, 0x92);
-        SETREG8(HW_REG_VRAMCNT_E, 0x82);
+        reg_GX_VRAMCNT_G = 0x92;
+        reg_GX_VRAMCNT_E = 0x82;
         break;
     case 96:
-        SETREG8(HW_REG_VRAMCNT_G, 0x8A);
+        reg_GX_VRAMCNT_G = 0x8A;
     case 32:
-        SETREG8(HW_REG_VRAMCNT_F, 0x82);
+        reg_GX_VRAMCNT_F = 0x82;
         break;
     case 64:
-        SETREG8(HW_REG_VRAMCNT_G, 0x82);
+        reg_GX_VRAMCNT_G = 0x82;
         break;
     default:
         break;
@@ -144,21 +144,21 @@ ARM_FUNC void GX_SetBankForBGExtPltt(s32 bgextpltt){
     switch (bgextpltt)
     {
     case 0x10:
-        SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) | 0x40000000);
-        SETREG8(HW_REG_VRAMCNT_E, 0x84);
+        reg_GX_DISPCNT |= 0x40000000;
+        reg_GX_VRAMCNT_E = 0x84;
         break;
     case 0x40:
-        SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) | 0x40000000);
-        SETREG8(HW_REG_VRAMCNT_G, 0x8C);
+        reg_GX_DISPCNT |= 0x40000000;
+        reg_GX_VRAMCNT_G = 0x8C;
         break;
     case 0x60:
-        SETREG8(HW_REG_VRAMCNT_G, 0x8C);
+        reg_GX_VRAMCNT_G = 0x8C;
     case 0x20:
-        SETREG8(HW_REG_VRAMCNT_F, 0x84);
-        SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) | 0x40000000);
+        reg_GX_VRAMCNT_F = 0x84;
+        reg_GX_DISPCNT |= 0x40000000;
         break;
     case 0:
-        SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) & ~0x40000000);
+        reg_GX_DISPCNT &= ~0x40000000;
         break;
     }
     GX_VRAMCNT_SetLCDC_(UNK_021D33C4.var00);
@@ -170,15 +170,15 @@ ARM_FUNC void GX_SetBankForOBJExtPltt(s32 objextpltt){
     switch (objextpltt)
     {
     case 32:
-        SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) | 0x80000000);
-        SETREG8(HW_REG_VRAMCNT_F, 0x85);
+        reg_GX_DISPCNT |= 0x80000000;
+        reg_GX_VRAMCNT_F = 0x85;
         break;
     case 64:
-        SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) | 0x80000000);
-        SETREG8(HW_REG_VRAMCNT_G, 0x85);
+        reg_GX_DISPCNT |= 0x80000000;
+        reg_GX_VRAMCNT_G = 0x85;
         break;
     case 0:
-        SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) & ~0x80000000);
+        reg_GX_DISPCNT &= ~0x80000000;
         break;
     }
     GX_VRAMCNT_SetLCDC_(UNK_021D33C4.var00);
@@ -189,58 +189,58 @@ ARM_FUNC void GX_SetBankForTex(s32 tex){
     UNK_021D33C4.var08 = tex;
     if (tex == 0)
     {
-        SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & 0x0000CFFE);
+        reg_G3X_DISP3DCNT &= 0x0000CFFE;
     }
     else
     {
-        SETREG16(HW_REG_DISP3DCNT, (READREG16(HW_REG_DISP3DCNT) & ~0x3000) | 0x1);
+        reg_G3X_DISP3DCNT = (reg_G3X_DISP3DCNT & ~0x3000) | 0x1;
         switch (tex)
         {
         case 5:
-            SETREG8(HW_REG_VRAMCNT_A, 0x83);
-            SETREG8(HW_REG_VRAMCNT_C, 0x8B);
+            reg_GX_VRAMCNT_A = 0x83;
+            reg_GX_VRAMCNT_C = 0x8B;
             break;
         case 9:
-            SETREG8(HW_REG_VRAMCNT_A, 0x83);
-            SETREG8(HW_REG_VRAMCNT_D, 0x8B);
+            reg_GX_VRAMCNT_A = 0x83;
+            reg_GX_VRAMCNT_D = 0x8B;
             break;
         case 10:
-            SETREG8(HW_REG_VRAMCNT_B, 0x83);
-            SETREG8(HW_REG_VRAMCNT_D, 0x8B);
+            reg_GX_VRAMCNT_B = 0x83;
+            reg_GX_VRAMCNT_D = 0x8B;
             break;
         case 11:
-            SETREG8(HW_REG_VRAMCNT_A, 0x83);
-            SETREG8(HW_REG_VRAMCNT_B, 0x8B);
-            SETREG8(HW_REG_VRAMCNT_D, 0x93);
+            reg_GX_VRAMCNT_A = 0x83;
+            reg_GX_VRAMCNT_B = 0x8B;
+            reg_GX_VRAMCNT_D = 0x93;
             break;
         case 13:
-            SETREG8(HW_REG_VRAMCNT_A, 0x83);
-            SETREG8(HW_REG_VRAMCNT_C, 0x8B);
-            SETREG8(HW_REG_VRAMCNT_D, 0x93);
+            reg_GX_VRAMCNT_A = 0x83;
+            reg_GX_VRAMCNT_C = 0x8B;
+            reg_GX_VRAMCNT_D = 0x93;
             break;
         case 8:
-            SETREG8(HW_REG_VRAMCNT_D, 0x83);
+            reg_GX_VRAMCNT_D = 0x83;
             break;
         case 12:
-            SETREG8(HW_REG_VRAMCNT_D, 0x8B);
+            reg_GX_VRAMCNT_D = 0x8B;
         case 4:
-            SETREG8(HW_REG_VRAMCNT_C, 0x83);
+            reg_GX_VRAMCNT_C = 0x83;
             break;
         case 14:
-            SETREG8(HW_REG_VRAMCNT_D, 0x93);
+            reg_GX_VRAMCNT_D = 0x93;
         case 6:
-            SETREG8(HW_REG_VRAMCNT_C, 0x8B);
+            reg_GX_VRAMCNT_C = 0x8B;
         case 2:
-            SETREG8(HW_REG_VRAMCNT_B, 0x83);
+            reg_GX_VRAMCNT_B = 0x83;
             break;
         case 15:
-            SETREG8(HW_REG_VRAMCNT_D, 0x9B);
+            reg_GX_VRAMCNT_D = 0x9B;
         case 7:
-            SETREG8(HW_REG_VRAMCNT_C, 0x93);
+            reg_GX_VRAMCNT_C = 0x93;
         case 3:
-            SETREG8(HW_REG_VRAMCNT_B, 0x8B);
+            reg_GX_VRAMCNT_B = 0x8B;
         case 1:
-            SETREG8(HW_REG_VRAMCNT_A, 0x83);
+            reg_GX_VRAMCNT_A = 0x83;
             break;
         }
     }
@@ -255,19 +255,19 @@ ARM_FUNC void GX_SetBankForTexPltt(s32 texpltt){
     case 0: //needed to match
         break;
     case 96:
-        SETREG8(HW_REG_VRAMCNT_G, 0x8B);
+        reg_GX_VRAMCNT_G = 0x8B;
     case 32:
-        SETREG8(HW_REG_VRAMCNT_F, 0x83);
+        reg_GX_VRAMCNT_F = 0x83;
         break;
     case 112:
-        SETREG8(HW_REG_VRAMCNT_G, 0x9B);
+        reg_GX_VRAMCNT_G = 0x9B;
     case 48:
-        SETREG8(HW_REG_VRAMCNT_F, 0x93);
+        reg_GX_VRAMCNT_F = 0x93;
     case 16:
-        SETREG8(HW_REG_VRAMCNT_E, 0x83);
+        reg_GX_VRAMCNT_E = 0x83;
         break;
     case 64:
-        SETREG8(HW_REG_VRAMCNT_G, 0x83);
+        reg_GX_VRAMCNT_G = 0x83;
         break;
     }
     GX_VRAMCNT_SetLCDC_(UNK_021D33C4.var00);
@@ -279,27 +279,27 @@ ARM_FUNC void GX_SetBankForClearImage(s32 clearimage){
     switch (clearimage)
     {
     case 3:
-        SETREG8(HW_REG_VRAMCNT_A, 0x93);
+        reg_GX_VRAMCNT_A = 0x93;
     case 2:
-        SETREG8(HW_REG_VRAMCNT_B, 0x9B);
-        SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x4000);
+        reg_GX_VRAMCNT_B = 0x9B;
+        reg_G3X_DISP3DCNT |= 0x4000;
         break;
     case 12:
-        SETREG8(HW_REG_VRAMCNT_C, 0x93);
+        reg_GX_VRAMCNT_C = 0x93;
     case 8:
-        SETREG8(HW_REG_VRAMCNT_D, 0x9B);
-        SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x4000);
+        reg_GX_VRAMCNT_D = 0x9B;
+        reg_G3X_DISP3DCNT |= 0x4000;
         break;
     case 0:
-        SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) & ~0x4000);
+        reg_G3X_DISP3DCNT &= ~0x4000;
         break;
     case 1:
-        SETREG8(HW_REG_VRAMCNT_A, 0x9B);
-        SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x4000);
+        reg_GX_VRAMCNT_A = 0x9B;
+        reg_G3X_DISP3DCNT |= 0x4000;
         break;
     case 4:
-        SETREG8(HW_REG_VRAMCNT_C, 0x9B);
-        SETREG16(HW_REG_DISP3DCNT, READREG16(HW_REG_DISP3DCNT) | 0x4000);
+        reg_GX_VRAMCNT_C = 0x9B;
+        reg_G3X_DISP3DCNT |= 0x4000;
     }
     GX_VRAMCNT_SetLCDC_(UNK_021D33C4.var00);
 }
@@ -312,14 +312,14 @@ ARM_FUNC void GX_SetBankForARM7(s32 arm7){
     case 0: //needed to match
         break;
     case 12:
-        SETREG8(HW_REG_VRAMCNT_D, 0x8A);
-        SETREG8(HW_REG_VRAMCNT_C, 0x82);
+        reg_GX_VRAMCNT_D = 0x8A;
+        reg_GX_VRAMCNT_C = 0x82;
         break;
     case 4:
-        SETREG8(HW_REG_VRAMCNT_C, 0x82);
+        reg_GX_VRAMCNT_C = 0x82;
         break;
     case 8:
-        SETREG8(HW_REG_VRAMCNT_D, 0x82);
+        reg_GX_VRAMCNT_D = 0x82;
     }
     GX_VRAMCNT_SetLCDC_(UNK_021D33C4.var00);
 }
@@ -337,12 +337,12 @@ ARM_FUNC void GX_SetBankForSubBG(s32 subbg){
     case 0: //needed to match
         break;
     case 4:
-        SETREG8(HW_REG_VRAMCNT_C, 0x84);
+        reg_GX_VRAMCNT_C = 0x84;
         break;
     case 384:
-        SETREG8(HW_REG_VRAMCNT_I, 0x81);
+        reg_GX_VRAMCNT_I = 0x81;
     case 128:
-        SETREG8(HW_REG_VRAMCNT_H, 0x81);
+        reg_GX_VRAMCNT_H = 0x81;
     }
     GX_VRAMCNT_SetLCDC_(UNK_021D33C4.var00);
 }
@@ -354,10 +354,10 @@ ARM_FUNC void GX_SetBankForSubOBJ(s32 subobj){
     switch (subobj)
     {
     case 8:
-        SETREG8(HW_REG_VRAMCNT_D, 0x84);
+        reg_GX_VRAMCNT_D = 0x84;
         break;
     case 256:
-        SETREG8(HW_REG_VRAMCNT_I, 0x82);
+        reg_GX_VRAMCNT_I = 0x82;
         break;
     case 0: //needed to match
         break;
@@ -371,11 +371,11 @@ ARM_FUNC void GX_SetBankForSubBGExtPltt(s32 subbgextpltt){
     switch (subbgextpltt)
     {
         case 128:
-            SETREG32(HW_REG_DISPCNT_2D, READREG32(HW_REG_DISPCNT_2D) | 0x40000000);
-            SETREG8(HW_REG_VRAMCNT_H, 0x82);
+            reg_GXS_DB_DISPCNT |= 0x40000000;
+            reg_GX_VRAMCNT_H = 0x82;
             break;
         case 0:
-            SETREG32(HW_REG_DISPCNT_2D, READREG32(HW_REG_DISPCNT_2D) & ~0x40000000);
+            reg_GXS_DB_DISPCNT &= ~0x40000000;
             break;
     }
     GX_VRAMCNT_SetLCDC_(UNK_021D33C4.var00);
@@ -387,11 +387,11 @@ ARM_FUNC void GX_SetBankForSubOBJExtPltt(s32 subobjextpltt){
     switch (subobjextpltt)
     {
         case 256:
-            SETREG32(HW_REG_DISPCNT_2D, READREG32(HW_REG_DISPCNT_2D) | 0x80000000);
-            SETREG8(HW_REG_VRAMCNT_I, 0x83);
+            reg_GXS_DB_DISPCNT |= 0x80000000;
+            reg_GX_VRAMCNT_I = 0x83;
             break;
         case 0:
-            SETREG32(HW_REG_DISPCNT_2D, READREG32(HW_REG_DISPCNT_2D) & ~0x80000000);
+            reg_GXS_DB_DISPCNT &= ~0x80000000;
             break;
     }
     GX_VRAMCNT_SetLCDC_(UNK_021D33C4.var00);
@@ -414,12 +414,12 @@ ARM_FUNC u32 GX_ResetBankForOBJ(){
 }
 
 ARM_FUNC u32 GX_ResetBankForBGExtPltt(){
-    SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) & ~0x40000000);
+    reg_GX_DISPCNT &= ~0x40000000;
     return FUN_020C6130(&UNK_021D33C4.var0E);
 }
 
 ARM_FUNC u32 GX_ResetBankForOBJExtPltt(){
-    SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) & ~0x80000000);
+    reg_GX_DISPCNT &= ~0x80000000;
     return FUN_020C6130(&UNK_021D33C4.var10);
 }
 
@@ -444,12 +444,12 @@ ARM_FUNC u32 FUN_020C605C(){
 }
 
 ARM_FUNC u32 FUN_020C6034(){
-    SETREG32(HW_REG_DISPCNT_2D, READREG32(HW_REG_DISPCNT_2D) & ~0x40000000);
+    reg_GXS_DB_DISPCNT &= ~0x40000000;
     return FUN_020C6130(&UNK_021D33C4.var16);
 }
 
 ARM_FUNC u32 GX_ResetBankForSubOBJ(){
-    SETREG32(HW_REG_DISPCNT_2D, READREG32(HW_REG_DISPCNT_2D) & ~0x80000000);
+    reg_GXS_DB_DISPCNT &= ~0x80000000;
     return FUN_020C6130(&UNK_021D33C4.var18);
 }
 
@@ -457,23 +457,23 @@ ARM_FUNC u32 FUN_020C5F28(u16 *ptr){
     u32 temp = *ptr;
     *ptr = 0;
     if (temp & (0x1 << 0))
-        SETREG8(HW_REG_VRAMCNT_A, 0x0);
+        reg_GX_VRAMCNT_A = 0x0;
     if (temp & (0x1 << 1))
-        SETREG8(HW_REG_VRAMCNT_B, 0x0);
+        reg_GX_VRAMCNT_B = 0x0;
     if (temp & (0x1 << 2))
-        SETREG8(HW_REG_VRAMCNT_C, 0x0);
+        reg_GX_VRAMCNT_C = 0x0;
     if (temp & (0x1 << 3))
-        SETREG8(HW_REG_VRAMCNT_D, 0x0);
+        reg_GX_VRAMCNT_D = 0x0;
     if (temp & (0x1 << 4))
-        SETREG8(HW_REG_VRAMCNT_E, 0x0);
+        reg_GX_VRAMCNT_E = 0x0;
     if (temp & (0x1 << 5))
-        SETREG8(HW_REG_VRAMCNT_F, 0x0);
+        reg_GX_VRAMCNT_F = 0x0;
     if (temp & (0x1 << 6))
-        SETREG8(HW_REG_VRAMCNT_G, 0x0);
+        reg_GX_VRAMCNT_G = 0x0;
     if (temp & (0x1 << 7))
-        SETREG8(HW_REG_VRAMCNT_H, 0x0);
+        reg_GX_VRAMCNT_H = 0x0;
     if (temp & (0x1 << 8))
-        SETREG8(HW_REG_VRAMCNT_I, 0x0);
+        reg_GX_VRAMCNT_I = 0x0;
     OSi_UnlockVram((u16)temp, UNK_021D33BC);
     return temp;
 }
@@ -487,12 +487,12 @@ ARM_FUNC u32 GX_DisableBankForOBJExtPltt_2(){
 }
 
 ARM_FUNC u32 GX_DisableBankForBGExtPltt(){
-    SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) & ~0x40000000);
+    reg_GX_DISPCNT &= ~0x40000000;
     return FUN_020C5F28(&UNK_021D33C4.var0E);
 }
 
 ARM_FUNC u32 GX_DisableBankForOBJExtPltt(){
-    SETREG32(HW_REG_DISPCNT, READREG32(HW_REG_DISPCNT) & ~0x80000000);
+    reg_GX_DISPCNT &= ~0x80000000;
     return FUN_020C5F28(&UNK_021D33C4.var10);
 }
 
@@ -525,12 +525,12 @@ ARM_FUNC u32 GX_DisableBankForSubOBJExtPltt_2(){
 }
 
 ARM_FUNC u32 FUN_020C5E04(){
-    SETREG32(HW_REG_DISPCNT_2D, READREG32(HW_REG_DISPCNT_2D) & ~0x40000000);
+    reg_GXS_DB_DISPCNT &= ~0x40000000;
     return FUN_020C5F28(&UNK_021D33C4.var16);
 }
 
 ARM_FUNC u32 GX_DisableBankForSubOBJExtPltt(){
-    SETREG32(HW_REG_DISPCNT_2D, READREG32(HW_REG_DISPCNT_2D) & ~0x80000000);
+    reg_GXS_DB_DISPCNT &= ~0x80000000;
     return FUN_020C5F28(&UNK_021D33C4.var18);
 }