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| author | GriffinR <griffin.g.richards@gmail.com> | 2020-08-16 05:59:10 -0400 |
|---|---|---|
| committer | GriffinR <griffin.g.richards@gmail.com> | 2020-08-16 05:59:10 -0400 |
| commit | 65bd2faf9460d4e5986c30e54b283d7674d77c55 (patch) | |
| tree | 250c345d17b8d8f910d327d98f577afddfb3a64a /berry_fix/payload | |
| parent | 2749948eebe65aa8b55738d820e4a0252dd45c1a (diff) | |
| parent | 25f45ffa8441b0f0a999355c9755782ccb4809dc (diff) | |
Merge branch 'master' of https://github.com/pret/pokeemerald into doc-contest
Diffstat (limited to 'berry_fix/payload')
| -rw-r--r-- | berry_fix/payload/asm/crt0.s | 8 | ||||
| -rw-r--r-- | berry_fix/payload/asm/libagbsyscall.s | 12 |
2 files changed, 10 insertions, 10 deletions
diff --git a/berry_fix/payload/asm/crt0.s b/berry_fix/payload/asm/crt0.s index 872a63018..2bca00636 100644 --- a/berry_fix/payload/asm/crt0.s +++ b/berry_fix/payload/asm/crt0.s @@ -9,10 +9,10 @@ .align 2, 0 .global Init Init: - mov r0, PSR_IRQ_MODE + mov r0, #PSR_IRQ_MODE msr cpsr_cf, r0 ldr sp, sp_irq - mov r0, PSR_SYS_MODE + mov r0, #PSR_SYS_MODE msr cpsr_cf, r0 ldr sp, sp_sys ldr r1, =INTR_VECTOR @@ -34,8 +34,8 @@ sp_irq: .word IWRAM_END - 0x60 .align 2, 0 .global IntrMain IntrMain: @ 0x2010048 - mov ip, REG_BASE - add r3, ip, OFFSET_REG_IE + mov ip, #REG_BASE + add r3, ip, #OFFSET_REG_IE ldr r2, [r3] and r1, r2, r2, lsr #16 mov r2, #0 diff --git a/berry_fix/payload/asm/libagbsyscall.s b/berry_fix/payload/asm/libagbsyscall.s index ea8ef3e89..9548e80d2 100644 --- a/berry_fix/payload/asm/libagbsyscall.s +++ b/berry_fix/payload/asm/libagbsyscall.s @@ -7,39 +7,39 @@ thumb_func_start CpuSet CpuSet: @ 81E3B64 - swi 0xB + svc 0xB bx lr thumb_func_end CpuSet thumb_func_start Div Div: @ 81E3B68 - swi 0x6 + svc 0x6 bx lr thumb_func_end Div thumb_func_start Mod Mod: - swi 0x6 + svc 0x6 adds r0, r1, 0 bx lr thumb_func_end Mod thumb_func_start LZ77UnCompVram LZ77UnCompVram: @ 81E3B6C - swi 0x12 + svc 0x12 bx lr thumb_func_end LZ77UnCompVram thumb_func_start RegisterRamReset RegisterRamReset: @ 81E3B80 - swi 0x1 + svc 0x1 bx lr thumb_func_end RegisterRamReset thumb_func_start VBlankIntrWait VBlankIntrWait: @ 81E3BA0 movs r2, 0 - swi 0x5 + svc 0x5 bx lr thumb_func_end VBlankIntrWait |